wcd9335.c 158 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  3. // Copyright (c) 2017-2018, Linaro Limited
  4. #include <linux/module.h>
  5. #include <linux/init.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/device.h>
  8. #include <linux/wait.h>
  9. #include <linux/bitops.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slimbus.h>
  15. #include <sound/soc.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/soc-dapm.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of.h>
  20. #include <linux/of_irq.h>
  21. #include <sound/tlv.h>
  22. #include <sound/info.h>
  23. #include "wcd9335.h"
  24. #include "wcd-clsh-v2.h"
  25. #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  26. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  27. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  28. /* Fractional Rates */
  29. #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
  30. #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  31. SNDRV_PCM_FMTBIT_S24_LE)
  32. /* slave port water mark level
  33. * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  34. */
  35. #define SLAVE_PORT_WATER_MARK_6BYTES 0
  36. #define SLAVE_PORT_WATER_MARK_9BYTES 1
  37. #define SLAVE_PORT_WATER_MARK_12BYTES 2
  38. #define SLAVE_PORT_WATER_MARK_15BYTES 3
  39. #define SLAVE_PORT_WATER_MARK_SHIFT 1
  40. #define SLAVE_PORT_ENABLE 1
  41. #define SLAVE_PORT_DISABLE 0
  42. #define WCD9335_SLIM_WATER_MARK_VAL \
  43. ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  44. (SLAVE_PORT_ENABLE))
  45. #define WCD9335_SLIM_NUM_PORT_REG 3
  46. #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
  47. #define WCD9335_MCLK_CLK_12P288MHZ 12288000
  48. #define WCD9335_MCLK_CLK_9P6MHZ 9600000
  49. #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
  50. #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
  51. #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
  52. #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
  53. #define WCD9335_NUM_INTERPOLATORS 9
  54. #define WCD9335_RX_START 16
  55. #define WCD9335_SLIM_CH_START 128
  56. #define WCD9335_MAX_MICBIAS 4
  57. #define WCD9335_MAX_VALID_ADC_MUX 13
  58. #define WCD9335_INVALID_ADC_MUX 9
  59. #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
  60. #define CF_MIN_3DB_4HZ 0x0
  61. #define CF_MIN_3DB_75HZ 0x1
  62. #define CF_MIN_3DB_150HZ 0x2
  63. #define WCD9335_DMIC_CLK_DIV_2 0x0
  64. #define WCD9335_DMIC_CLK_DIV_3 0x1
  65. #define WCD9335_DMIC_CLK_DIV_4 0x2
  66. #define WCD9335_DMIC_CLK_DIV_6 0x3
  67. #define WCD9335_DMIC_CLK_DIV_8 0x4
  68. #define WCD9335_DMIC_CLK_DIV_16 0x5
  69. #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
  70. #define WCD9335_AMIC_PWR_LEVEL_LP 0
  71. #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
  72. #define WCD9335_AMIC_PWR_LEVEL_HP 2
  73. #define WCD9335_AMIC_PWR_LVL_MASK 0x60
  74. #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
  75. #define WCD9335_DEC_PWR_LVL_MASK 0x06
  76. #define WCD9335_DEC_PWR_LVL_LP 0x02
  77. #define WCD9335_DEC_PWR_LVL_HP 0x04
  78. #define WCD9335_DEC_PWR_LVL_DF 0x00
  79. #define WCD9335_SLIM_RX_CH(p) \
  80. {.port = p + WCD9335_RX_START, .shift = p,}
  81. #define WCD9335_SLIM_TX_CH(p) \
  82. {.port = p, .shift = p,}
  83. /* vout step value */
  84. #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
  85. #define WCD9335_INTERPOLATOR_PATH(id) \
  86. {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
  87. {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
  88. {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
  89. {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
  90. {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
  91. {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
  92. {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
  93. {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
  94. {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
  95. {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
  96. {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
  97. {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
  98. {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
  99. {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
  100. {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
  101. {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
  102. {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
  103. {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
  104. {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
  105. {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
  106. {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
  107. {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
  108. {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
  109. {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
  110. {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
  111. {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
  112. {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
  113. {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
  114. {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
  115. {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
  116. {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
  117. {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
  118. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
  119. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
  120. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
  121. {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
  122. {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
  123. {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
  124. {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
  125. #define WCD9335_ADC_MUX_PATH(id) \
  126. {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
  127. {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
  128. {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
  129. {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
  130. {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
  131. {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
  132. {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
  133. {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
  134. {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
  135. {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
  136. {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
  137. {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
  138. {"AMIC MUX" #id, "ADC1", "ADC1"}, \
  139. {"AMIC MUX" #id, "ADC2", "ADC2"}, \
  140. {"AMIC MUX" #id, "ADC3", "ADC3"}, \
  141. {"AMIC MUX" #id, "ADC4", "ADC4"}, \
  142. {"AMIC MUX" #id, "ADC5", "ADC5"}, \
  143. {"AMIC MUX" #id, "ADC6", "ADC6"}
  144. enum {
  145. WCD9335_RX0 = 0,
  146. WCD9335_RX1,
  147. WCD9335_RX2,
  148. WCD9335_RX3,
  149. WCD9335_RX4,
  150. WCD9335_RX5,
  151. WCD9335_RX6,
  152. WCD9335_RX7,
  153. WCD9335_RX8,
  154. WCD9335_RX9,
  155. WCD9335_RX10,
  156. WCD9335_RX11,
  157. WCD9335_RX12,
  158. WCD9335_RX_MAX,
  159. };
  160. enum {
  161. WCD9335_TX0 = 0,
  162. WCD9335_TX1,
  163. WCD9335_TX2,
  164. WCD9335_TX3,
  165. WCD9335_TX4,
  166. WCD9335_TX5,
  167. WCD9335_TX6,
  168. WCD9335_TX7,
  169. WCD9335_TX8,
  170. WCD9335_TX9,
  171. WCD9335_TX10,
  172. WCD9335_TX11,
  173. WCD9335_TX12,
  174. WCD9335_TX13,
  175. WCD9335_TX14,
  176. WCD9335_TX15,
  177. WCD9335_TX_MAX,
  178. };
  179. enum {
  180. SIDO_SOURCE_INTERNAL = 0,
  181. SIDO_SOURCE_RCO_BG,
  182. };
  183. enum wcd9335_sido_voltage {
  184. SIDO_VOLTAGE_SVS_MV = 950,
  185. SIDO_VOLTAGE_NOMINAL_MV = 1100,
  186. };
  187. enum {
  188. AIF1_PB = 0,
  189. AIF1_CAP,
  190. AIF2_PB,
  191. AIF2_CAP,
  192. AIF3_PB,
  193. AIF3_CAP,
  194. AIF4_PB,
  195. NUM_CODEC_DAIS,
  196. };
  197. enum {
  198. COMPANDER_1, /* HPH_L */
  199. COMPANDER_2, /* HPH_R */
  200. COMPANDER_3, /* LO1_DIFF */
  201. COMPANDER_4, /* LO2_DIFF */
  202. COMPANDER_5, /* LO3_SE */
  203. COMPANDER_6, /* LO4_SE */
  204. COMPANDER_7, /* SWR SPK CH1 */
  205. COMPANDER_8, /* SWR SPK CH2 */
  206. COMPANDER_MAX,
  207. };
  208. enum {
  209. INTn_2_INP_SEL_ZERO = 0,
  210. INTn_2_INP_SEL_RX0,
  211. INTn_2_INP_SEL_RX1,
  212. INTn_2_INP_SEL_RX2,
  213. INTn_2_INP_SEL_RX3,
  214. INTn_2_INP_SEL_RX4,
  215. INTn_2_INP_SEL_RX5,
  216. INTn_2_INP_SEL_RX6,
  217. INTn_2_INP_SEL_RX7,
  218. INTn_2_INP_SEL_PROXIMITY,
  219. };
  220. enum {
  221. INTn_1_MIX_INP_SEL_ZERO = 0,
  222. INTn_1_MIX_INP_SEL_DEC0,
  223. INTn_1_MIX_INP_SEL_DEC1,
  224. INTn_1_MIX_INP_SEL_IIR0,
  225. INTn_1_MIX_INP_SEL_IIR1,
  226. INTn_1_MIX_INP_SEL_RX0,
  227. INTn_1_MIX_INP_SEL_RX1,
  228. INTn_1_MIX_INP_SEL_RX2,
  229. INTn_1_MIX_INP_SEL_RX3,
  230. INTn_1_MIX_INP_SEL_RX4,
  231. INTn_1_MIX_INP_SEL_RX5,
  232. INTn_1_MIX_INP_SEL_RX6,
  233. INTn_1_MIX_INP_SEL_RX7,
  234. };
  235. enum {
  236. INTERP_EAR = 0,
  237. INTERP_HPHL,
  238. INTERP_HPHR,
  239. INTERP_LO1,
  240. INTERP_LO2,
  241. INTERP_LO3,
  242. INTERP_LO4,
  243. INTERP_SPKR1,
  244. INTERP_SPKR2,
  245. };
  246. enum wcd_clock_type {
  247. WCD_CLK_OFF,
  248. WCD_CLK_RCO,
  249. WCD_CLK_MCLK,
  250. };
  251. enum {
  252. MIC_BIAS_1 = 1,
  253. MIC_BIAS_2,
  254. MIC_BIAS_3,
  255. MIC_BIAS_4
  256. };
  257. enum {
  258. MICB_PULLUP_ENABLE,
  259. MICB_PULLUP_DISABLE,
  260. MICB_ENABLE,
  261. MICB_DISABLE,
  262. };
  263. struct wcd9335_slim_ch {
  264. u32 ch_num;
  265. u16 port;
  266. u16 shift;
  267. struct list_head list;
  268. };
  269. struct wcd_slim_codec_dai_data {
  270. struct list_head slim_ch_list;
  271. struct slim_stream_config sconfig;
  272. struct slim_stream_runtime *sruntime;
  273. };
  274. struct wcd9335_codec {
  275. struct device *dev;
  276. struct clk *mclk;
  277. struct clk *native_clk;
  278. u32 mclk_rate;
  279. u8 version;
  280. struct slim_device *slim;
  281. struct slim_device *slim_ifc_dev;
  282. struct regmap *regmap;
  283. struct regmap *if_regmap;
  284. struct regmap_irq_chip_data *irq_data;
  285. struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
  286. struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
  287. u32 num_rx_port;
  288. u32 num_tx_port;
  289. int sido_input_src;
  290. enum wcd9335_sido_voltage sido_voltage;
  291. struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
  292. struct snd_soc_component *component;
  293. int master_bias_users;
  294. int clk_mclk_users;
  295. int clk_rco_users;
  296. int sido_ccl_cnt;
  297. enum wcd_clock_type clk_type;
  298. struct wcd_clsh_ctrl *clsh_ctrl;
  299. u32 hph_mode;
  300. int prim_int_users[WCD9335_NUM_INTERPOLATORS];
  301. int comp_enabled[COMPANDER_MAX];
  302. int intr1;
  303. int reset_gpio;
  304. struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
  305. unsigned int rx_port_value;
  306. unsigned int tx_port_value;
  307. int hph_l_gain;
  308. int hph_r_gain;
  309. u32 rx_bias_count;
  310. /*TX*/
  311. int micb_ref[WCD9335_MAX_MICBIAS];
  312. int pullup_ref[WCD9335_MAX_MICBIAS];
  313. int dmic_0_1_clk_cnt;
  314. int dmic_2_3_clk_cnt;
  315. int dmic_4_5_clk_cnt;
  316. int dmic_sample_rate;
  317. int mad_dmic_sample_rate;
  318. int native_clk_users;
  319. };
  320. struct wcd9335_irq {
  321. int irq;
  322. irqreturn_t (*handler)(int irq, void *data);
  323. char *name;
  324. };
  325. static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
  326. WCD9335_SLIM_TX_CH(0),
  327. WCD9335_SLIM_TX_CH(1),
  328. WCD9335_SLIM_TX_CH(2),
  329. WCD9335_SLIM_TX_CH(3),
  330. WCD9335_SLIM_TX_CH(4),
  331. WCD9335_SLIM_TX_CH(5),
  332. WCD9335_SLIM_TX_CH(6),
  333. WCD9335_SLIM_TX_CH(7),
  334. WCD9335_SLIM_TX_CH(8),
  335. WCD9335_SLIM_TX_CH(9),
  336. WCD9335_SLIM_TX_CH(10),
  337. WCD9335_SLIM_TX_CH(11),
  338. WCD9335_SLIM_TX_CH(12),
  339. WCD9335_SLIM_TX_CH(13),
  340. WCD9335_SLIM_TX_CH(14),
  341. WCD9335_SLIM_TX_CH(15),
  342. };
  343. static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
  344. WCD9335_SLIM_RX_CH(0), /* 16 */
  345. WCD9335_SLIM_RX_CH(1), /* 17 */
  346. WCD9335_SLIM_RX_CH(2),
  347. WCD9335_SLIM_RX_CH(3),
  348. WCD9335_SLIM_RX_CH(4),
  349. WCD9335_SLIM_RX_CH(5),
  350. WCD9335_SLIM_RX_CH(6),
  351. WCD9335_SLIM_RX_CH(7),
  352. WCD9335_SLIM_RX_CH(8),
  353. WCD9335_SLIM_RX_CH(9),
  354. WCD9335_SLIM_RX_CH(10),
  355. WCD9335_SLIM_RX_CH(11),
  356. WCD9335_SLIM_RX_CH(12),
  357. };
  358. struct interp_sample_rate {
  359. int rate;
  360. int rate_val;
  361. };
  362. static struct interp_sample_rate int_mix_rate_val[] = {
  363. {48000, 0x4}, /* 48K */
  364. {96000, 0x5}, /* 96K */
  365. {192000, 0x6}, /* 192K */
  366. };
  367. static struct interp_sample_rate int_prim_rate_val[] = {
  368. {8000, 0x0}, /* 8K */
  369. {16000, 0x1}, /* 16K */
  370. {24000, -EINVAL},/* 24K */
  371. {32000, 0x3}, /* 32K */
  372. {48000, 0x4}, /* 48K */
  373. {96000, 0x5}, /* 96K */
  374. {192000, 0x6}, /* 192K */
  375. {384000, 0x7}, /* 384K */
  376. {44100, 0x8}, /* 44.1K */
  377. };
  378. struct wcd9335_reg_mask_val {
  379. u16 reg;
  380. u8 mask;
  381. u8 val;
  382. };
  383. static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
  384. /* Rbuckfly/R_EAR(32) */
  385. {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
  386. {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
  387. {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
  388. {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
  389. {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
  390. {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
  391. {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
  392. {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
  393. {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
  394. {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
  395. {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
  396. {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
  397. {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
  398. {WCD9335_EAR_CMBUFF, 0x08, 0x00},
  399. {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  400. {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  401. {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  402. {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
  403. {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
  404. {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
  405. {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
  406. {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
  407. {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
  408. {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
  409. {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
  410. {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
  411. {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
  412. {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
  413. {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
  414. {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
  415. {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
  416. {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
  417. {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
  418. {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
  419. {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
  420. {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
  421. {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
  422. {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
  423. {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
  424. {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
  425. {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
  426. {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
  427. {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
  428. {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
  429. {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
  430. {WCD9335_HPH_L_TEST, 0x01, 0x01},
  431. {WCD9335_HPH_R_TEST, 0x01, 0x01},
  432. {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
  433. {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
  434. {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
  435. {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
  436. {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
  437. {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
  438. {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
  439. {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
  440. {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
  441. {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
  442. };
  443. /* Cutoff frequency for high pass filter */
  444. static const char * const cf_text[] = {
  445. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
  446. };
  447. static const char * const rx_cf_text[] = {
  448. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
  449. "CF_NEG_3DB_0P48HZ"
  450. };
  451. static const char * const rx_int0_7_mix_mux_text[] = {
  452. "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
  453. "RX6", "RX7", "PROXIMITY"
  454. };
  455. static const char * const rx_int_mix_mux_text[] = {
  456. "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
  457. "RX6", "RX7"
  458. };
  459. static const char * const rx_prim_mix_text[] = {
  460. "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
  461. "RX3", "RX4", "RX5", "RX6", "RX7"
  462. };
  463. static const char * const rx_int_dem_inp_mux_text[] = {
  464. "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
  465. };
  466. static const char * const rx_int0_interp_mux_text[] = {
  467. "ZERO", "RX INT0 MIX2",
  468. };
  469. static const char * const rx_int1_interp_mux_text[] = {
  470. "ZERO", "RX INT1 MIX2",
  471. };
  472. static const char * const rx_int2_interp_mux_text[] = {
  473. "ZERO", "RX INT2 MIX2",
  474. };
  475. static const char * const rx_int3_interp_mux_text[] = {
  476. "ZERO", "RX INT3 MIX2",
  477. };
  478. static const char * const rx_int4_interp_mux_text[] = {
  479. "ZERO", "RX INT4 MIX2",
  480. };
  481. static const char * const rx_int5_interp_mux_text[] = {
  482. "ZERO", "RX INT5 MIX2",
  483. };
  484. static const char * const rx_int6_interp_mux_text[] = {
  485. "ZERO", "RX INT6 MIX2",
  486. };
  487. static const char * const rx_int7_interp_mux_text[] = {
  488. "ZERO", "RX INT7 MIX2",
  489. };
  490. static const char * const rx_int8_interp_mux_text[] = {
  491. "ZERO", "RX INT8 SEC MIX"
  492. };
  493. static const char * const rx_hph_mode_mux_text[] = {
  494. "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
  495. "Class-H Hi-Fi Low Power"
  496. };
  497. static const char *const slim_rx_mux_text[] = {
  498. "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
  499. };
  500. static const char * const adc_mux_text[] = {
  501. "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
  502. };
  503. static const char * const dmic_mux_text[] = {
  504. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
  505. "SMIC0", "SMIC1", "SMIC2", "SMIC3"
  506. };
  507. static const char * const dmic_mux_alt_text[] = {
  508. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
  509. };
  510. static const char * const amic_mux_text[] = {
  511. "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
  512. };
  513. static const char * const sb_tx0_mux_text[] = {
  514. "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
  515. };
  516. static const char * const sb_tx1_mux_text[] = {
  517. "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
  518. };
  519. static const char * const sb_tx2_mux_text[] = {
  520. "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
  521. };
  522. static const char * const sb_tx3_mux_text[] = {
  523. "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
  524. };
  525. static const char * const sb_tx4_mux_text[] = {
  526. "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
  527. };
  528. static const char * const sb_tx5_mux_text[] = {
  529. "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
  530. };
  531. static const char * const sb_tx6_mux_text[] = {
  532. "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
  533. };
  534. static const char * const sb_tx7_mux_text[] = {
  535. "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
  536. };
  537. static const char * const sb_tx8_mux_text[] = {
  538. "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
  539. };
  540. static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
  541. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  542. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  543. static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
  544. static const struct soc_enum cf_dec0_enum =
  545. SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
  546. static const struct soc_enum cf_dec1_enum =
  547. SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
  548. static const struct soc_enum cf_dec2_enum =
  549. SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
  550. static const struct soc_enum cf_dec3_enum =
  551. SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
  552. static const struct soc_enum cf_dec4_enum =
  553. SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
  554. static const struct soc_enum cf_dec5_enum =
  555. SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
  556. static const struct soc_enum cf_dec6_enum =
  557. SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
  558. static const struct soc_enum cf_dec7_enum =
  559. SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
  560. static const struct soc_enum cf_dec8_enum =
  561. SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
  562. static const struct soc_enum cf_int0_1_enum =
  563. SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
  564. static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
  565. rx_cf_text);
  566. static const struct soc_enum cf_int1_1_enum =
  567. SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
  568. static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
  569. rx_cf_text);
  570. static const struct soc_enum cf_int2_1_enum =
  571. SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
  572. static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
  573. rx_cf_text);
  574. static const struct soc_enum cf_int3_1_enum =
  575. SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
  576. static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
  577. rx_cf_text);
  578. static const struct soc_enum cf_int4_1_enum =
  579. SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
  580. static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
  581. rx_cf_text);
  582. static const struct soc_enum cf_int5_1_enum =
  583. SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
  584. static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
  585. rx_cf_text);
  586. static const struct soc_enum cf_int6_1_enum =
  587. SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
  588. static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
  589. rx_cf_text);
  590. static const struct soc_enum cf_int7_1_enum =
  591. SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
  592. static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
  593. rx_cf_text);
  594. static const struct soc_enum cf_int8_1_enum =
  595. SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
  596. static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
  597. rx_cf_text);
  598. static const struct soc_enum rx_hph_mode_mux_enum =
  599. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  600. rx_hph_mode_mux_text);
  601. static const struct soc_enum slim_rx_mux_enum =
  602. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
  603. static const struct soc_enum rx_int0_2_mux_chain_enum =
  604. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
  605. rx_int0_7_mix_mux_text);
  606. static const struct soc_enum rx_int1_2_mux_chain_enum =
  607. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
  608. rx_int_mix_mux_text);
  609. static const struct soc_enum rx_int2_2_mux_chain_enum =
  610. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
  611. rx_int_mix_mux_text);
  612. static const struct soc_enum rx_int3_2_mux_chain_enum =
  613. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
  614. rx_int_mix_mux_text);
  615. static const struct soc_enum rx_int4_2_mux_chain_enum =
  616. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
  617. rx_int_mix_mux_text);
  618. static const struct soc_enum rx_int5_2_mux_chain_enum =
  619. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
  620. rx_int_mix_mux_text);
  621. static const struct soc_enum rx_int6_2_mux_chain_enum =
  622. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
  623. rx_int_mix_mux_text);
  624. static const struct soc_enum rx_int7_2_mux_chain_enum =
  625. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
  626. rx_int0_7_mix_mux_text);
  627. static const struct soc_enum rx_int8_2_mux_chain_enum =
  628. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
  629. rx_int_mix_mux_text);
  630. static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
  631. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
  632. rx_prim_mix_text);
  633. static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
  634. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
  635. rx_prim_mix_text);
  636. static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
  637. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
  638. rx_prim_mix_text);
  639. static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
  640. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
  641. rx_prim_mix_text);
  642. static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
  643. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
  644. rx_prim_mix_text);
  645. static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
  646. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
  647. rx_prim_mix_text);
  648. static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
  649. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
  650. rx_prim_mix_text);
  651. static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
  652. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
  653. rx_prim_mix_text);
  654. static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
  655. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
  656. rx_prim_mix_text);
  657. static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
  658. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
  659. rx_prim_mix_text);
  660. static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
  661. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
  662. rx_prim_mix_text);
  663. static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
  664. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
  665. rx_prim_mix_text);
  666. static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
  667. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
  668. rx_prim_mix_text);
  669. static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
  670. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
  671. rx_prim_mix_text);
  672. static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
  673. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
  674. rx_prim_mix_text);
  675. static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
  676. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
  677. rx_prim_mix_text);
  678. static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
  679. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
  680. rx_prim_mix_text);
  681. static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
  682. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
  683. rx_prim_mix_text);
  684. static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
  685. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
  686. rx_prim_mix_text);
  687. static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
  688. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
  689. rx_prim_mix_text);
  690. static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
  691. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
  692. rx_prim_mix_text);
  693. static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
  694. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
  695. rx_prim_mix_text);
  696. static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
  697. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
  698. rx_prim_mix_text);
  699. static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
  700. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
  701. rx_prim_mix_text);
  702. static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
  703. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
  704. rx_prim_mix_text);
  705. static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
  706. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
  707. rx_prim_mix_text);
  708. static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
  709. SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
  710. rx_prim_mix_text);
  711. static const struct soc_enum rx_int0_dem_inp_mux_enum =
  712. SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
  713. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  714. rx_int_dem_inp_mux_text);
  715. static const struct soc_enum rx_int1_dem_inp_mux_enum =
  716. SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
  717. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  718. rx_int_dem_inp_mux_text);
  719. static const struct soc_enum rx_int2_dem_inp_mux_enum =
  720. SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
  721. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  722. rx_int_dem_inp_mux_text);
  723. static const struct soc_enum rx_int0_interp_mux_enum =
  724. SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
  725. rx_int0_interp_mux_text);
  726. static const struct soc_enum rx_int1_interp_mux_enum =
  727. SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
  728. rx_int1_interp_mux_text);
  729. static const struct soc_enum rx_int2_interp_mux_enum =
  730. SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
  731. rx_int2_interp_mux_text);
  732. static const struct soc_enum rx_int3_interp_mux_enum =
  733. SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
  734. rx_int3_interp_mux_text);
  735. static const struct soc_enum rx_int4_interp_mux_enum =
  736. SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
  737. rx_int4_interp_mux_text);
  738. static const struct soc_enum rx_int5_interp_mux_enum =
  739. SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
  740. rx_int5_interp_mux_text);
  741. static const struct soc_enum rx_int6_interp_mux_enum =
  742. SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
  743. rx_int6_interp_mux_text);
  744. static const struct soc_enum rx_int7_interp_mux_enum =
  745. SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
  746. rx_int7_interp_mux_text);
  747. static const struct soc_enum rx_int8_interp_mux_enum =
  748. SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
  749. rx_int8_interp_mux_text);
  750. static const struct soc_enum tx_adc_mux0_chain_enum =
  751. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
  752. adc_mux_text);
  753. static const struct soc_enum tx_adc_mux1_chain_enum =
  754. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
  755. adc_mux_text);
  756. static const struct soc_enum tx_adc_mux2_chain_enum =
  757. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
  758. adc_mux_text);
  759. static const struct soc_enum tx_adc_mux3_chain_enum =
  760. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
  761. adc_mux_text);
  762. static const struct soc_enum tx_adc_mux4_chain_enum =
  763. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
  764. adc_mux_text);
  765. static const struct soc_enum tx_adc_mux5_chain_enum =
  766. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
  767. adc_mux_text);
  768. static const struct soc_enum tx_adc_mux6_chain_enum =
  769. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
  770. adc_mux_text);
  771. static const struct soc_enum tx_adc_mux7_chain_enum =
  772. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
  773. adc_mux_text);
  774. static const struct soc_enum tx_adc_mux8_chain_enum =
  775. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
  776. adc_mux_text);
  777. static const struct soc_enum tx_dmic_mux0_enum =
  778. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
  779. dmic_mux_text);
  780. static const struct soc_enum tx_dmic_mux1_enum =
  781. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
  782. dmic_mux_text);
  783. static const struct soc_enum tx_dmic_mux2_enum =
  784. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
  785. dmic_mux_text);
  786. static const struct soc_enum tx_dmic_mux3_enum =
  787. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
  788. dmic_mux_text);
  789. static const struct soc_enum tx_dmic_mux4_enum =
  790. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
  791. dmic_mux_alt_text);
  792. static const struct soc_enum tx_dmic_mux5_enum =
  793. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
  794. dmic_mux_alt_text);
  795. static const struct soc_enum tx_dmic_mux6_enum =
  796. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
  797. dmic_mux_alt_text);
  798. static const struct soc_enum tx_dmic_mux7_enum =
  799. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
  800. dmic_mux_alt_text);
  801. static const struct soc_enum tx_dmic_mux8_enum =
  802. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
  803. dmic_mux_alt_text);
  804. static const struct soc_enum tx_amic_mux0_enum =
  805. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
  806. amic_mux_text);
  807. static const struct soc_enum tx_amic_mux1_enum =
  808. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
  809. amic_mux_text);
  810. static const struct soc_enum tx_amic_mux2_enum =
  811. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
  812. amic_mux_text);
  813. static const struct soc_enum tx_amic_mux3_enum =
  814. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
  815. amic_mux_text);
  816. static const struct soc_enum tx_amic_mux4_enum =
  817. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
  818. amic_mux_text);
  819. static const struct soc_enum tx_amic_mux5_enum =
  820. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
  821. amic_mux_text);
  822. static const struct soc_enum tx_amic_mux6_enum =
  823. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
  824. amic_mux_text);
  825. static const struct soc_enum tx_amic_mux7_enum =
  826. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
  827. amic_mux_text);
  828. static const struct soc_enum tx_amic_mux8_enum =
  829. SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
  830. amic_mux_text);
  831. static const struct soc_enum sb_tx0_mux_enum =
  832. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
  833. sb_tx0_mux_text);
  834. static const struct soc_enum sb_tx1_mux_enum =
  835. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
  836. sb_tx1_mux_text);
  837. static const struct soc_enum sb_tx2_mux_enum =
  838. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
  839. sb_tx2_mux_text);
  840. static const struct soc_enum sb_tx3_mux_enum =
  841. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
  842. sb_tx3_mux_text);
  843. static const struct soc_enum sb_tx4_mux_enum =
  844. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
  845. sb_tx4_mux_text);
  846. static const struct soc_enum sb_tx5_mux_enum =
  847. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
  848. sb_tx5_mux_text);
  849. static const struct soc_enum sb_tx6_mux_enum =
  850. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
  851. sb_tx6_mux_text);
  852. static const struct soc_enum sb_tx7_mux_enum =
  853. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
  854. sb_tx7_mux_text);
  855. static const struct soc_enum sb_tx8_mux_enum =
  856. SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
  857. sb_tx8_mux_text);
  858. static const struct snd_kcontrol_new rx_int0_2_mux =
  859. SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
  860. static const struct snd_kcontrol_new rx_int1_2_mux =
  861. SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
  862. static const struct snd_kcontrol_new rx_int2_2_mux =
  863. SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
  864. static const struct snd_kcontrol_new rx_int3_2_mux =
  865. SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
  866. static const struct snd_kcontrol_new rx_int4_2_mux =
  867. SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
  868. static const struct snd_kcontrol_new rx_int5_2_mux =
  869. SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
  870. static const struct snd_kcontrol_new rx_int6_2_mux =
  871. SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
  872. static const struct snd_kcontrol_new rx_int7_2_mux =
  873. SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
  874. static const struct snd_kcontrol_new rx_int8_2_mux =
  875. SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
  876. static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
  877. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
  878. static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
  879. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
  880. static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
  881. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
  882. static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
  883. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
  884. static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
  885. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
  886. static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
  887. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
  888. static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
  889. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
  890. static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
  891. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
  892. static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
  893. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
  894. static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
  895. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
  896. static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
  897. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
  898. static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
  899. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
  900. static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
  901. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
  902. static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
  903. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
  904. static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
  905. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
  906. static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
  907. SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
  908. static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
  909. SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
  910. static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
  911. SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
  912. static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
  913. SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
  914. static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
  915. SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
  916. static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
  917. SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
  918. static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
  919. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
  920. static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
  921. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
  922. static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
  923. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
  924. static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
  925. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
  926. static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
  927. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
  928. static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
  929. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
  930. static const struct snd_kcontrol_new rx_int0_interp_mux =
  931. SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
  932. static const struct snd_kcontrol_new rx_int1_interp_mux =
  933. SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
  934. static const struct snd_kcontrol_new rx_int2_interp_mux =
  935. SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
  936. static const struct snd_kcontrol_new rx_int3_interp_mux =
  937. SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
  938. static const struct snd_kcontrol_new rx_int4_interp_mux =
  939. SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
  940. static const struct snd_kcontrol_new rx_int5_interp_mux =
  941. SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
  942. static const struct snd_kcontrol_new rx_int6_interp_mux =
  943. SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
  944. static const struct snd_kcontrol_new rx_int7_interp_mux =
  945. SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
  946. static const struct snd_kcontrol_new rx_int8_interp_mux =
  947. SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
  948. static const struct snd_kcontrol_new tx_dmic_mux0 =
  949. SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
  950. static const struct snd_kcontrol_new tx_dmic_mux1 =
  951. SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
  952. static const struct snd_kcontrol_new tx_dmic_mux2 =
  953. SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
  954. static const struct snd_kcontrol_new tx_dmic_mux3 =
  955. SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
  956. static const struct snd_kcontrol_new tx_dmic_mux4 =
  957. SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
  958. static const struct snd_kcontrol_new tx_dmic_mux5 =
  959. SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
  960. static const struct snd_kcontrol_new tx_dmic_mux6 =
  961. SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
  962. static const struct snd_kcontrol_new tx_dmic_mux7 =
  963. SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
  964. static const struct snd_kcontrol_new tx_dmic_mux8 =
  965. SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
  966. static const struct snd_kcontrol_new tx_amic_mux0 =
  967. SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
  968. static const struct snd_kcontrol_new tx_amic_mux1 =
  969. SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
  970. static const struct snd_kcontrol_new tx_amic_mux2 =
  971. SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
  972. static const struct snd_kcontrol_new tx_amic_mux3 =
  973. SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
  974. static const struct snd_kcontrol_new tx_amic_mux4 =
  975. SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
  976. static const struct snd_kcontrol_new tx_amic_mux5 =
  977. SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
  978. static const struct snd_kcontrol_new tx_amic_mux6 =
  979. SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
  980. static const struct snd_kcontrol_new tx_amic_mux7 =
  981. SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
  982. static const struct snd_kcontrol_new tx_amic_mux8 =
  983. SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
  984. static const struct snd_kcontrol_new sb_tx0_mux =
  985. SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
  986. static const struct snd_kcontrol_new sb_tx1_mux =
  987. SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
  988. static const struct snd_kcontrol_new sb_tx2_mux =
  989. SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
  990. static const struct snd_kcontrol_new sb_tx3_mux =
  991. SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
  992. static const struct snd_kcontrol_new sb_tx4_mux =
  993. SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
  994. static const struct snd_kcontrol_new sb_tx5_mux =
  995. SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
  996. static const struct snd_kcontrol_new sb_tx6_mux =
  997. SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
  998. static const struct snd_kcontrol_new sb_tx7_mux =
  999. SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
  1000. static const struct snd_kcontrol_new sb_tx8_mux =
  1001. SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
  1002. static int slim_rx_mux_get(struct snd_kcontrol *kc,
  1003. struct snd_ctl_elem_value *ucontrol)
  1004. {
  1005. struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
  1006. struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
  1007. ucontrol->value.enumerated.item[0] = wcd->rx_port_value;
  1008. return 0;
  1009. }
  1010. static int slim_rx_mux_put(struct snd_kcontrol *kc,
  1011. struct snd_ctl_elem_value *ucontrol)
  1012. {
  1013. struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
  1014. struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
  1015. struct soc_enum *e = (struct soc_enum *)kc->private_value;
  1016. struct snd_soc_dapm_update *update = NULL;
  1017. u32 port_id = w->shift;
  1018. wcd->rx_port_value = ucontrol->value.enumerated.item[0];
  1019. switch (wcd->rx_port_value) {
  1020. case 0:
  1021. list_del_init(&wcd->rx_chs[port_id].list);
  1022. break;
  1023. case 1:
  1024. list_add_tail(&wcd->rx_chs[port_id].list,
  1025. &wcd->dai[AIF1_PB].slim_ch_list);
  1026. break;
  1027. case 2:
  1028. list_add_tail(&wcd->rx_chs[port_id].list,
  1029. &wcd->dai[AIF2_PB].slim_ch_list);
  1030. break;
  1031. case 3:
  1032. list_add_tail(&wcd->rx_chs[port_id].list,
  1033. &wcd->dai[AIF3_PB].slim_ch_list);
  1034. break;
  1035. case 4:
  1036. list_add_tail(&wcd->rx_chs[port_id].list,
  1037. &wcd->dai[AIF4_PB].slim_ch_list);
  1038. break;
  1039. default:
  1040. dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value);
  1041. goto err;
  1042. }
  1043. snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value,
  1044. e, update);
  1045. return 0;
  1046. err:
  1047. return -EINVAL;
  1048. }
  1049. static int slim_tx_mixer_get(struct snd_kcontrol *kc,
  1050. struct snd_ctl_elem_value *ucontrol)
  1051. {
  1052. struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
  1053. struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
  1054. ucontrol->value.integer.value[0] = wcd->tx_port_value;
  1055. return 0;
  1056. }
  1057. static int slim_tx_mixer_put(struct snd_kcontrol *kc,
  1058. struct snd_ctl_elem_value *ucontrol)
  1059. {
  1060. struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
  1061. struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
  1062. struct snd_soc_dapm_update *update = NULL;
  1063. struct soc_mixer_control *mixer =
  1064. (struct soc_mixer_control *)kc->private_value;
  1065. int enable = ucontrol->value.integer.value[0];
  1066. int dai_id = widget->shift;
  1067. int port_id = mixer->shift;
  1068. switch (dai_id) {
  1069. case AIF1_CAP:
  1070. case AIF2_CAP:
  1071. case AIF3_CAP:
  1072. /* only add to the list if value not set */
  1073. if (enable && !(wcd->tx_port_value & BIT(port_id))) {
  1074. wcd->tx_port_value |= BIT(port_id);
  1075. list_add_tail(&wcd->tx_chs[port_id].list,
  1076. &wcd->dai[dai_id].slim_ch_list);
  1077. } else if (!enable && (wcd->tx_port_value & BIT(port_id))) {
  1078. wcd->tx_port_value &= ~BIT(port_id);
  1079. list_del_init(&wcd->tx_chs[port_id].list);
  1080. }
  1081. break;
  1082. default:
  1083. dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
  1084. return -EINVAL;
  1085. }
  1086. snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
  1087. return 0;
  1088. }
  1089. static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
  1090. SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
  1091. slim_rx_mux_get, slim_rx_mux_put),
  1092. SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
  1093. slim_rx_mux_get, slim_rx_mux_put),
  1094. SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
  1095. slim_rx_mux_get, slim_rx_mux_put),
  1096. SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
  1097. slim_rx_mux_get, slim_rx_mux_put),
  1098. SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
  1099. slim_rx_mux_get, slim_rx_mux_put),
  1100. SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
  1101. slim_rx_mux_get, slim_rx_mux_put),
  1102. SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
  1103. slim_rx_mux_get, slim_rx_mux_put),
  1104. SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
  1105. slim_rx_mux_get, slim_rx_mux_put),
  1106. };
  1107. static const struct snd_kcontrol_new aif1_cap_mixer[] = {
  1108. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
  1109. slim_tx_mixer_get, slim_tx_mixer_put),
  1110. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
  1111. slim_tx_mixer_get, slim_tx_mixer_put),
  1112. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
  1113. slim_tx_mixer_get, slim_tx_mixer_put),
  1114. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
  1115. slim_tx_mixer_get, slim_tx_mixer_put),
  1116. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
  1117. slim_tx_mixer_get, slim_tx_mixer_put),
  1118. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
  1119. slim_tx_mixer_get, slim_tx_mixer_put),
  1120. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
  1121. slim_tx_mixer_get, slim_tx_mixer_put),
  1122. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
  1123. slim_tx_mixer_get, slim_tx_mixer_put),
  1124. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
  1125. slim_tx_mixer_get, slim_tx_mixer_put),
  1126. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
  1127. slim_tx_mixer_get, slim_tx_mixer_put),
  1128. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
  1129. slim_tx_mixer_get, slim_tx_mixer_put),
  1130. SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
  1131. slim_tx_mixer_get, slim_tx_mixer_put),
  1132. SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
  1133. slim_tx_mixer_get, slim_tx_mixer_put),
  1134. };
  1135. static const struct snd_kcontrol_new aif2_cap_mixer[] = {
  1136. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
  1137. slim_tx_mixer_get, slim_tx_mixer_put),
  1138. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
  1139. slim_tx_mixer_get, slim_tx_mixer_put),
  1140. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
  1141. slim_tx_mixer_get, slim_tx_mixer_put),
  1142. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
  1143. slim_tx_mixer_get, slim_tx_mixer_put),
  1144. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
  1145. slim_tx_mixer_get, slim_tx_mixer_put),
  1146. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
  1147. slim_tx_mixer_get, slim_tx_mixer_put),
  1148. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
  1149. slim_tx_mixer_get, slim_tx_mixer_put),
  1150. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
  1151. slim_tx_mixer_get, slim_tx_mixer_put),
  1152. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
  1153. slim_tx_mixer_get, slim_tx_mixer_put),
  1154. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
  1155. slim_tx_mixer_get, slim_tx_mixer_put),
  1156. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
  1157. slim_tx_mixer_get, slim_tx_mixer_put),
  1158. SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
  1159. slim_tx_mixer_get, slim_tx_mixer_put),
  1160. SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
  1161. slim_tx_mixer_get, slim_tx_mixer_put),
  1162. };
  1163. static const struct snd_kcontrol_new aif3_cap_mixer[] = {
  1164. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
  1165. slim_tx_mixer_get, slim_tx_mixer_put),
  1166. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
  1167. slim_tx_mixer_get, slim_tx_mixer_put),
  1168. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
  1169. slim_tx_mixer_get, slim_tx_mixer_put),
  1170. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
  1171. slim_tx_mixer_get, slim_tx_mixer_put),
  1172. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
  1173. slim_tx_mixer_get, slim_tx_mixer_put),
  1174. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
  1175. slim_tx_mixer_get, slim_tx_mixer_put),
  1176. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
  1177. slim_tx_mixer_get, slim_tx_mixer_put),
  1178. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
  1179. slim_tx_mixer_get, slim_tx_mixer_put),
  1180. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
  1181. slim_tx_mixer_get, slim_tx_mixer_put),
  1182. };
  1183. static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
  1184. struct snd_ctl_elem_value *ucontrol)
  1185. {
  1186. struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
  1187. struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
  1188. struct soc_enum *e = (struct soc_enum *)kc->private_value;
  1189. unsigned int val, reg, sel;
  1190. val = ucontrol->value.enumerated.item[0];
  1191. switch (e->reg) {
  1192. case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
  1193. reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
  1194. break;
  1195. case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
  1196. reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
  1197. break;
  1198. case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
  1199. reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
  1200. break;
  1201. case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
  1202. reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
  1203. break;
  1204. case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
  1205. reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
  1206. break;
  1207. case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
  1208. reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
  1209. break;
  1210. case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
  1211. reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
  1212. break;
  1213. case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
  1214. reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
  1215. break;
  1216. case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
  1217. reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
  1218. break;
  1219. default:
  1220. return -EINVAL;
  1221. }
  1222. /* AMIC: 0, DMIC: 1 */
  1223. sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
  1224. snd_soc_component_update_bits(component, reg,
  1225. WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
  1226. sel);
  1227. return snd_soc_dapm_put_enum_double(kc, ucontrol);
  1228. }
  1229. static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
  1230. struct snd_ctl_elem_value *ucontrol)
  1231. {
  1232. struct soc_enum *e = (struct soc_enum *)kc->private_value;
  1233. struct snd_soc_component *component;
  1234. int reg, val;
  1235. component = snd_soc_dapm_kcontrol_component(kc);
  1236. val = ucontrol->value.enumerated.item[0];
  1237. if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
  1238. reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
  1239. else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
  1240. reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
  1241. else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
  1242. reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
  1243. else
  1244. return -EINVAL;
  1245. /* Set Look Ahead Delay */
  1246. snd_soc_component_update_bits(component, reg,
  1247. WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
  1248. val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
  1249. /* Set DEM INP Select */
  1250. return snd_soc_dapm_put_enum_double(kc, ucontrol);
  1251. }
  1252. static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
  1253. SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
  1254. snd_soc_dapm_get_enum_double,
  1255. wcd9335_int_dem_inp_mux_put);
  1256. static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
  1257. SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
  1258. snd_soc_dapm_get_enum_double,
  1259. wcd9335_int_dem_inp_mux_put);
  1260. static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
  1261. SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
  1262. snd_soc_dapm_get_enum_double,
  1263. wcd9335_int_dem_inp_mux_put);
  1264. static const struct snd_kcontrol_new tx_adc_mux0 =
  1265. SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
  1266. snd_soc_dapm_get_enum_double,
  1267. wcd9335_put_dec_enum);
  1268. static const struct snd_kcontrol_new tx_adc_mux1 =
  1269. SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
  1270. snd_soc_dapm_get_enum_double,
  1271. wcd9335_put_dec_enum);
  1272. static const struct snd_kcontrol_new tx_adc_mux2 =
  1273. SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
  1274. snd_soc_dapm_get_enum_double,
  1275. wcd9335_put_dec_enum);
  1276. static const struct snd_kcontrol_new tx_adc_mux3 =
  1277. SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
  1278. snd_soc_dapm_get_enum_double,
  1279. wcd9335_put_dec_enum);
  1280. static const struct snd_kcontrol_new tx_adc_mux4 =
  1281. SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
  1282. snd_soc_dapm_get_enum_double,
  1283. wcd9335_put_dec_enum);
  1284. static const struct snd_kcontrol_new tx_adc_mux5 =
  1285. SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
  1286. snd_soc_dapm_get_enum_double,
  1287. wcd9335_put_dec_enum);
  1288. static const struct snd_kcontrol_new tx_adc_mux6 =
  1289. SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
  1290. snd_soc_dapm_get_enum_double,
  1291. wcd9335_put_dec_enum);
  1292. static const struct snd_kcontrol_new tx_adc_mux7 =
  1293. SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
  1294. snd_soc_dapm_get_enum_double,
  1295. wcd9335_put_dec_enum);
  1296. static const struct snd_kcontrol_new tx_adc_mux8 =
  1297. SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
  1298. snd_soc_dapm_get_enum_double,
  1299. wcd9335_put_dec_enum);
  1300. static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
  1301. int rate_val,
  1302. u32 rate)
  1303. {
  1304. struct snd_soc_component *component = dai->component;
  1305. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  1306. struct wcd9335_slim_ch *ch;
  1307. int val, j;
  1308. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1309. for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
  1310. val = snd_soc_component_read(component,
  1311. WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
  1312. WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1313. if (val == (ch->shift + INTn_2_INP_SEL_RX0))
  1314. snd_soc_component_update_bits(component,
  1315. WCD9335_CDC_RX_PATH_MIX_CTL(j),
  1316. WCD9335_CDC_MIX_PCM_RATE_MASK,
  1317. rate_val);
  1318. }
  1319. }
  1320. return 0;
  1321. }
  1322. static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
  1323. u8 rate_val,
  1324. u32 rate)
  1325. {
  1326. struct snd_soc_component *comp = dai->component;
  1327. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  1328. struct wcd9335_slim_ch *ch;
  1329. u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
  1330. int inp, j;
  1331. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1332. inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
  1333. /*
  1334. * Loop through all interpolator MUX inputs and find out
  1335. * to which interpolator input, the slim rx port
  1336. * is connected
  1337. */
  1338. for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
  1339. cfg0 = snd_soc_component_read(comp,
  1340. WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
  1341. cfg1 = snd_soc_component_read(comp,
  1342. WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
  1343. inp0_sel = cfg0 &
  1344. WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1345. inp1_sel = (cfg0 >> 4) &
  1346. WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1347. inp2_sel = (cfg1 >> 4) &
  1348. WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1349. if ((inp0_sel == inp) || (inp1_sel == inp) ||
  1350. (inp2_sel == inp)) {
  1351. /* rate is in Hz */
  1352. if ((j == 0) && (rate == 44100))
  1353. dev_info(wcd->dev,
  1354. "Cannot set 44.1KHz on INT0\n");
  1355. else
  1356. snd_soc_component_update_bits(comp,
  1357. WCD9335_CDC_RX_PATH_CTL(j),
  1358. WCD9335_CDC_MIX_PCM_RATE_MASK,
  1359. rate_val);
  1360. }
  1361. }
  1362. }
  1363. return 0;
  1364. }
  1365. static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
  1366. {
  1367. int i;
  1368. /* set mixing path rate */
  1369. for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
  1370. if (rate == int_mix_rate_val[i].rate) {
  1371. wcd9335_set_mix_interpolator_rate(dai,
  1372. int_mix_rate_val[i].rate_val, rate);
  1373. break;
  1374. }
  1375. }
  1376. /* set primary path sample rate */
  1377. for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
  1378. if (rate == int_prim_rate_val[i].rate) {
  1379. wcd9335_set_prim_interpolator_rate(dai,
  1380. int_prim_rate_val[i].rate_val, rate);
  1381. break;
  1382. }
  1383. }
  1384. return 0;
  1385. }
  1386. static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
  1387. struct wcd_slim_codec_dai_data *dai_data,
  1388. int direction)
  1389. {
  1390. struct list_head *slim_ch_list = &dai_data->slim_ch_list;
  1391. struct slim_stream_config *cfg = &dai_data->sconfig;
  1392. struct wcd9335_slim_ch *ch;
  1393. u16 payload = 0;
  1394. int ret, i;
  1395. cfg->ch_count = 0;
  1396. cfg->direction = direction;
  1397. cfg->port_mask = 0;
  1398. /* Configure slave interface device */
  1399. list_for_each_entry(ch, slim_ch_list, list) {
  1400. cfg->ch_count++;
  1401. payload |= 1 << ch->shift;
  1402. cfg->port_mask |= BIT(ch->port);
  1403. }
  1404. cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
  1405. if (!cfg->chs)
  1406. return -ENOMEM;
  1407. i = 0;
  1408. list_for_each_entry(ch, slim_ch_list, list) {
  1409. cfg->chs[i++] = ch->ch_num;
  1410. if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  1411. /* write to interface device */
  1412. ret = regmap_write(wcd->if_regmap,
  1413. WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
  1414. payload);
  1415. if (ret < 0)
  1416. goto err;
  1417. /* configure the slave port for water mark and enable*/
  1418. ret = regmap_write(wcd->if_regmap,
  1419. WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
  1420. WCD9335_SLIM_WATER_MARK_VAL);
  1421. if (ret < 0)
  1422. goto err;
  1423. } else {
  1424. ret = regmap_write(wcd->if_regmap,
  1425. WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
  1426. payload & 0x00FF);
  1427. if (ret < 0)
  1428. goto err;
  1429. /* ports 8,9 */
  1430. ret = regmap_write(wcd->if_regmap,
  1431. WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
  1432. (payload & 0xFF00)>>8);
  1433. if (ret < 0)
  1434. goto err;
  1435. /* configure the slave port for water mark and enable*/
  1436. ret = regmap_write(wcd->if_regmap,
  1437. WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
  1438. WCD9335_SLIM_WATER_MARK_VAL);
  1439. if (ret < 0)
  1440. goto err;
  1441. }
  1442. }
  1443. dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
  1444. return 0;
  1445. err:
  1446. dev_err(wcd->dev, "Error Setting slim hw params\n");
  1447. kfree(cfg->chs);
  1448. cfg->chs = NULL;
  1449. return ret;
  1450. }
  1451. static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
  1452. u8 rate_val, u32 rate)
  1453. {
  1454. struct snd_soc_component *comp = dai->component;
  1455. struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
  1456. u8 shift = 0, shift_val = 0, tx_mux_sel;
  1457. struct wcd9335_slim_ch *ch;
  1458. int tx_port, tx_port_reg;
  1459. int decimator = -1;
  1460. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1461. tx_port = ch->port;
  1462. if ((tx_port == 12) || (tx_port >= 14)) {
  1463. dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
  1464. tx_port, dai->id);
  1465. return -EINVAL;
  1466. }
  1467. /* Find the SB TX MUX input - which decimator is connected */
  1468. if (tx_port < 4) {
  1469. tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
  1470. shift = (tx_port << 1);
  1471. shift_val = 0x03;
  1472. } else if ((tx_port >= 4) && (tx_port < 8)) {
  1473. tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
  1474. shift = ((tx_port - 4) << 1);
  1475. shift_val = 0x03;
  1476. } else if ((tx_port >= 8) && (tx_port < 11)) {
  1477. tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
  1478. shift = ((tx_port - 8) << 1);
  1479. shift_val = 0x03;
  1480. } else if (tx_port == 11) {
  1481. tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
  1482. shift = 0;
  1483. shift_val = 0x0F;
  1484. } else if (tx_port == 13) {
  1485. tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
  1486. shift = 4;
  1487. shift_val = 0x03;
  1488. } else {
  1489. return -EINVAL;
  1490. }
  1491. tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
  1492. (shift_val << shift);
  1493. tx_mux_sel = tx_mux_sel >> shift;
  1494. if (tx_port <= 8) {
  1495. if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
  1496. decimator = tx_port;
  1497. } else if (tx_port <= 10) {
  1498. if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
  1499. decimator = ((tx_port == 9) ? 7 : 6);
  1500. } else if (tx_port == 11) {
  1501. if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
  1502. decimator = tx_mux_sel - 1;
  1503. } else if (tx_port == 13) {
  1504. if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
  1505. decimator = 5;
  1506. }
  1507. if (decimator >= 0) {
  1508. snd_soc_component_update_bits(comp,
  1509. WCD9335_CDC_TX_PATH_CTL(decimator),
  1510. WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
  1511. rate_val);
  1512. } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
  1513. /* Check if the TX Mux input is RX MIX TXn */
  1514. dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
  1515. tx_port, tx_port);
  1516. } else {
  1517. dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
  1518. decimator);
  1519. return -EINVAL;
  1520. }
  1521. }
  1522. return 0;
  1523. }
  1524. static int wcd9335_hw_params(struct snd_pcm_substream *substream,
  1525. struct snd_pcm_hw_params *params,
  1526. struct snd_soc_dai *dai)
  1527. {
  1528. struct wcd9335_codec *wcd;
  1529. int ret, tx_fs_rate = 0;
  1530. wcd = snd_soc_component_get_drvdata(dai->component);
  1531. switch (substream->stream) {
  1532. case SNDRV_PCM_STREAM_PLAYBACK:
  1533. ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
  1534. if (ret) {
  1535. dev_err(wcd->dev, "cannot set sample rate: %u\n",
  1536. params_rate(params));
  1537. return ret;
  1538. }
  1539. switch (params_width(params)) {
  1540. case 16 ... 24:
  1541. wcd->dai[dai->id].sconfig.bps = params_width(params);
  1542. break;
  1543. default:
  1544. dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
  1545. __func__, params_width(params));
  1546. return -EINVAL;
  1547. }
  1548. break;
  1549. case SNDRV_PCM_STREAM_CAPTURE:
  1550. switch (params_rate(params)) {
  1551. case 8000:
  1552. tx_fs_rate = 0;
  1553. break;
  1554. case 16000:
  1555. tx_fs_rate = 1;
  1556. break;
  1557. case 32000:
  1558. tx_fs_rate = 3;
  1559. break;
  1560. case 48000:
  1561. tx_fs_rate = 4;
  1562. break;
  1563. case 96000:
  1564. tx_fs_rate = 5;
  1565. break;
  1566. case 192000:
  1567. tx_fs_rate = 6;
  1568. break;
  1569. case 384000:
  1570. tx_fs_rate = 7;
  1571. break;
  1572. default:
  1573. dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
  1574. __func__, params_rate(params));
  1575. return -EINVAL;
  1576. }
  1577. ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
  1578. params_rate(params));
  1579. if (ret < 0) {
  1580. dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
  1581. return ret;
  1582. }
  1583. switch (params_width(params)) {
  1584. case 16 ... 32:
  1585. wcd->dai[dai->id].sconfig.bps = params_width(params);
  1586. break;
  1587. default:
  1588. dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
  1589. __func__, params_width(params));
  1590. return -EINVAL;
  1591. }
  1592. break;
  1593. default:
  1594. dev_err(wcd->dev, "Invalid stream type %d\n",
  1595. substream->stream);
  1596. return -EINVAL;
  1597. }
  1598. wcd->dai[dai->id].sconfig.rate = params_rate(params);
  1599. wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
  1600. return 0;
  1601. }
  1602. static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
  1603. struct snd_soc_dai *dai)
  1604. {
  1605. struct wcd_slim_codec_dai_data *dai_data;
  1606. struct wcd9335_codec *wcd;
  1607. struct slim_stream_config *cfg;
  1608. wcd = snd_soc_component_get_drvdata(dai->component);
  1609. dai_data = &wcd->dai[dai->id];
  1610. switch (cmd) {
  1611. case SNDRV_PCM_TRIGGER_START:
  1612. case SNDRV_PCM_TRIGGER_RESUME:
  1613. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1614. cfg = &dai_data->sconfig;
  1615. slim_stream_prepare(dai_data->sruntime, cfg);
  1616. slim_stream_enable(dai_data->sruntime);
  1617. break;
  1618. case SNDRV_PCM_TRIGGER_STOP:
  1619. case SNDRV_PCM_TRIGGER_SUSPEND:
  1620. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1621. slim_stream_unprepare(dai_data->sruntime);
  1622. slim_stream_disable(dai_data->sruntime);
  1623. break;
  1624. default:
  1625. break;
  1626. }
  1627. return 0;
  1628. }
  1629. static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
  1630. unsigned int tx_num, unsigned int *tx_slot,
  1631. unsigned int rx_num, unsigned int *rx_slot)
  1632. {
  1633. struct wcd9335_codec *wcd;
  1634. int i;
  1635. wcd = snd_soc_component_get_drvdata(dai->component);
  1636. if (!tx_slot || !rx_slot) {
  1637. dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
  1638. tx_slot, rx_slot);
  1639. return -EINVAL;
  1640. }
  1641. wcd->num_rx_port = rx_num;
  1642. for (i = 0; i < rx_num; i++) {
  1643. wcd->rx_chs[i].ch_num = rx_slot[i];
  1644. INIT_LIST_HEAD(&wcd->rx_chs[i].list);
  1645. }
  1646. wcd->num_tx_port = tx_num;
  1647. for (i = 0; i < tx_num; i++) {
  1648. wcd->tx_chs[i].ch_num = tx_slot[i];
  1649. INIT_LIST_HEAD(&wcd->tx_chs[i].list);
  1650. }
  1651. return 0;
  1652. }
  1653. static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
  1654. unsigned int *tx_num, unsigned int *tx_slot,
  1655. unsigned int *rx_num, unsigned int *rx_slot)
  1656. {
  1657. struct wcd9335_slim_ch *ch;
  1658. struct wcd9335_codec *wcd;
  1659. int i = 0;
  1660. wcd = snd_soc_component_get_drvdata(dai->component);
  1661. switch (dai->id) {
  1662. case AIF1_PB:
  1663. case AIF2_PB:
  1664. case AIF3_PB:
  1665. case AIF4_PB:
  1666. if (!rx_slot || !rx_num) {
  1667. dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
  1668. rx_slot, rx_num);
  1669. return -EINVAL;
  1670. }
  1671. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
  1672. rx_slot[i++] = ch->ch_num;
  1673. *rx_num = i;
  1674. break;
  1675. case AIF1_CAP:
  1676. case AIF2_CAP:
  1677. case AIF3_CAP:
  1678. if (!tx_slot || !tx_num) {
  1679. dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
  1680. tx_slot, tx_num);
  1681. return -EINVAL;
  1682. }
  1683. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
  1684. tx_slot[i++] = ch->ch_num;
  1685. *tx_num = i;
  1686. break;
  1687. default:
  1688. dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
  1689. break;
  1690. }
  1691. return 0;
  1692. }
  1693. static struct snd_soc_dai_ops wcd9335_dai_ops = {
  1694. .hw_params = wcd9335_hw_params,
  1695. .trigger = wcd9335_trigger,
  1696. .set_channel_map = wcd9335_set_channel_map,
  1697. .get_channel_map = wcd9335_get_channel_map,
  1698. };
  1699. static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
  1700. [0] = {
  1701. .name = "wcd9335_rx1",
  1702. .id = AIF1_PB,
  1703. .playback = {
  1704. .stream_name = "AIF1 Playback",
  1705. .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
  1706. SNDRV_PCM_RATE_384000,
  1707. .formats = WCD9335_FORMATS_S16_S24_LE,
  1708. .rate_max = 384000,
  1709. .rate_min = 8000,
  1710. .channels_min = 1,
  1711. .channels_max = 2,
  1712. },
  1713. .ops = &wcd9335_dai_ops,
  1714. },
  1715. [1] = {
  1716. .name = "wcd9335_tx1",
  1717. .id = AIF1_CAP,
  1718. .capture = {
  1719. .stream_name = "AIF1 Capture",
  1720. .rates = WCD9335_RATES_MASK,
  1721. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1722. .rate_min = 8000,
  1723. .rate_max = 192000,
  1724. .channels_min = 1,
  1725. .channels_max = 4,
  1726. },
  1727. .ops = &wcd9335_dai_ops,
  1728. },
  1729. [2] = {
  1730. .name = "wcd9335_rx2",
  1731. .id = AIF2_PB,
  1732. .playback = {
  1733. .stream_name = "AIF2 Playback",
  1734. .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
  1735. SNDRV_PCM_RATE_384000,
  1736. .formats = WCD9335_FORMATS_S16_S24_LE,
  1737. .rate_min = 8000,
  1738. .rate_max = 384000,
  1739. .channels_min = 1,
  1740. .channels_max = 2,
  1741. },
  1742. .ops = &wcd9335_dai_ops,
  1743. },
  1744. [3] = {
  1745. .name = "wcd9335_tx2",
  1746. .id = AIF2_CAP,
  1747. .capture = {
  1748. .stream_name = "AIF2 Capture",
  1749. .rates = WCD9335_RATES_MASK,
  1750. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1751. .rate_min = 8000,
  1752. .rate_max = 192000,
  1753. .channels_min = 1,
  1754. .channels_max = 4,
  1755. },
  1756. .ops = &wcd9335_dai_ops,
  1757. },
  1758. [4] = {
  1759. .name = "wcd9335_rx3",
  1760. .id = AIF3_PB,
  1761. .playback = {
  1762. .stream_name = "AIF3 Playback",
  1763. .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
  1764. SNDRV_PCM_RATE_384000,
  1765. .formats = WCD9335_FORMATS_S16_S24_LE,
  1766. .rate_min = 8000,
  1767. .rate_max = 384000,
  1768. .channels_min = 1,
  1769. .channels_max = 2,
  1770. },
  1771. .ops = &wcd9335_dai_ops,
  1772. },
  1773. [5] = {
  1774. .name = "wcd9335_tx3",
  1775. .id = AIF3_CAP,
  1776. .capture = {
  1777. .stream_name = "AIF3 Capture",
  1778. .rates = WCD9335_RATES_MASK,
  1779. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1780. .rate_min = 8000,
  1781. .rate_max = 192000,
  1782. .channels_min = 1,
  1783. .channels_max = 4,
  1784. },
  1785. .ops = &wcd9335_dai_ops,
  1786. },
  1787. [6] = {
  1788. .name = "wcd9335_rx4",
  1789. .id = AIF4_PB,
  1790. .playback = {
  1791. .stream_name = "AIF4 Playback",
  1792. .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
  1793. SNDRV_PCM_RATE_384000,
  1794. .formats = WCD9335_FORMATS_S16_S24_LE,
  1795. .rate_min = 8000,
  1796. .rate_max = 384000,
  1797. .channels_min = 1,
  1798. .channels_max = 2,
  1799. },
  1800. .ops = &wcd9335_dai_ops,
  1801. },
  1802. };
  1803. static int wcd9335_get_compander(struct snd_kcontrol *kc,
  1804. struct snd_ctl_elem_value *ucontrol)
  1805. {
  1806. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  1807. int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
  1808. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  1809. ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
  1810. return 0;
  1811. }
  1812. static int wcd9335_set_compander(struct snd_kcontrol *kc,
  1813. struct snd_ctl_elem_value *ucontrol)
  1814. {
  1815. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  1816. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  1817. int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
  1818. int value = ucontrol->value.integer.value[0];
  1819. int sel;
  1820. wcd->comp_enabled[comp] = value;
  1821. sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
  1822. WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
  1823. /* Any specific register configuration for compander */
  1824. switch (comp) {
  1825. case COMPANDER_1:
  1826. /* Set Gain Source Select based on compander enable/disable */
  1827. snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
  1828. WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
  1829. break;
  1830. case COMPANDER_2:
  1831. snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
  1832. WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
  1833. break;
  1834. case COMPANDER_5:
  1835. snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
  1836. WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
  1837. break;
  1838. case COMPANDER_6:
  1839. snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
  1840. WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
  1841. break;
  1842. default:
  1843. break;
  1844. }
  1845. return 0;
  1846. }
  1847. static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
  1848. struct snd_ctl_elem_value *ucontrol)
  1849. {
  1850. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  1851. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  1852. ucontrol->value.enumerated.item[0] = wcd->hph_mode;
  1853. return 0;
  1854. }
  1855. static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
  1856. struct snd_ctl_elem_value *ucontrol)
  1857. {
  1858. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  1859. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  1860. u32 mode_val;
  1861. mode_val = ucontrol->value.enumerated.item[0];
  1862. if (mode_val == 0) {
  1863. dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
  1864. mode_val = CLS_H_HIFI;
  1865. }
  1866. wcd->hph_mode = mode_val;
  1867. return 0;
  1868. }
  1869. static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
  1870. /* -84dB min - 40dB max */
  1871. SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
  1872. 0, -84, 40, digital_gain),
  1873. SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
  1874. 0, -84, 40, digital_gain),
  1875. SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
  1876. 0, -84, 40, digital_gain),
  1877. SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
  1878. 0, -84, 40, digital_gain),
  1879. SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
  1880. 0, -84, 40, digital_gain),
  1881. SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
  1882. 0, -84, 40, digital_gain),
  1883. SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
  1884. 0, -84, 40, digital_gain),
  1885. SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
  1886. 0, -84, 40, digital_gain),
  1887. SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
  1888. 0, -84, 40, digital_gain),
  1889. SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume",
  1890. WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
  1891. 0, -84, 40, digital_gain),
  1892. SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume",
  1893. WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
  1894. 0, -84, 40, digital_gain),
  1895. SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume",
  1896. WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
  1897. 0, -84, 40, digital_gain),
  1898. SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume",
  1899. WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
  1900. 0, -84, 40, digital_gain),
  1901. SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume",
  1902. WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
  1903. 0, -84, 40, digital_gain),
  1904. SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume",
  1905. WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
  1906. 0, -84, 40, digital_gain),
  1907. SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume",
  1908. WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
  1909. 0, -84, 40, digital_gain),
  1910. SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume",
  1911. WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
  1912. 0, -84, 40, digital_gain),
  1913. SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume",
  1914. WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
  1915. 0, -84, 40, digital_gain),
  1916. SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
  1917. SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
  1918. SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
  1919. SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
  1920. SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
  1921. SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
  1922. SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
  1923. SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
  1924. SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
  1925. SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
  1926. SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
  1927. SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
  1928. SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
  1929. SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
  1930. SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
  1931. SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
  1932. SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
  1933. SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
  1934. SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
  1935. wcd9335_get_compander, wcd9335_set_compander),
  1936. SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
  1937. wcd9335_get_compander, wcd9335_set_compander),
  1938. SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
  1939. wcd9335_get_compander, wcd9335_set_compander),
  1940. SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
  1941. wcd9335_get_compander, wcd9335_set_compander),
  1942. SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
  1943. wcd9335_get_compander, wcd9335_set_compander),
  1944. SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
  1945. wcd9335_get_compander, wcd9335_set_compander),
  1946. SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
  1947. wcd9335_get_compander, wcd9335_set_compander),
  1948. SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
  1949. wcd9335_get_compander, wcd9335_set_compander),
  1950. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1951. wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
  1952. /* Gain Controls */
  1953. SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
  1954. ear_pa_gain),
  1955. SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
  1956. line_gain),
  1957. SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
  1958. line_gain),
  1959. SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
  1960. 3, 16, 1, line_gain),
  1961. SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
  1962. 3, 16, 1, line_gain),
  1963. SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
  1964. line_gain),
  1965. SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
  1966. line_gain),
  1967. SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
  1968. analog_gain),
  1969. SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
  1970. analog_gain),
  1971. SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
  1972. analog_gain),
  1973. SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
  1974. analog_gain),
  1975. SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
  1976. analog_gain),
  1977. SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
  1978. analog_gain),
  1979. SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
  1980. SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
  1981. SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
  1982. SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
  1983. SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
  1984. SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
  1985. SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
  1986. SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
  1987. SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
  1988. };
  1989. static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
  1990. {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
  1991. {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
  1992. {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
  1993. {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
  1994. {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
  1995. {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
  1996. {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
  1997. {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
  1998. {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
  1999. {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
  2000. {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
  2001. {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
  2002. {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
  2003. {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
  2004. {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
  2005. {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
  2006. {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
  2007. {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
  2008. {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
  2009. {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
  2010. {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
  2011. {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
  2012. {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
  2013. {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
  2014. {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
  2015. {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
  2016. {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
  2017. {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
  2018. {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
  2019. {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
  2020. {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
  2021. {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
  2022. {"SLIM RX0", NULL, "SLIM RX0 MUX"},
  2023. {"SLIM RX1", NULL, "SLIM RX1 MUX"},
  2024. {"SLIM RX2", NULL, "SLIM RX2 MUX"},
  2025. {"SLIM RX3", NULL, "SLIM RX3 MUX"},
  2026. {"SLIM RX4", NULL, "SLIM RX4 MUX"},
  2027. {"SLIM RX5", NULL, "SLIM RX5 MUX"},
  2028. {"SLIM RX6", NULL, "SLIM RX6 MUX"},
  2029. {"SLIM RX7", NULL, "SLIM RX7 MUX"},
  2030. WCD9335_INTERPOLATOR_PATH(0),
  2031. WCD9335_INTERPOLATOR_PATH(1),
  2032. WCD9335_INTERPOLATOR_PATH(2),
  2033. WCD9335_INTERPOLATOR_PATH(3),
  2034. WCD9335_INTERPOLATOR_PATH(4),
  2035. WCD9335_INTERPOLATOR_PATH(5),
  2036. WCD9335_INTERPOLATOR_PATH(6),
  2037. WCD9335_INTERPOLATOR_PATH(7),
  2038. WCD9335_INTERPOLATOR_PATH(8),
  2039. /* EAR PA */
  2040. {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
  2041. {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
  2042. {"RX INT0 DAC", NULL, "RX_BIAS"},
  2043. {"EAR PA", NULL, "RX INT0 DAC"},
  2044. {"EAR", NULL, "EAR PA"},
  2045. /* HPHL */
  2046. {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
  2047. {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
  2048. {"RX INT1 DAC", NULL, "RX_BIAS"},
  2049. {"HPHL PA", NULL, "RX INT1 DAC"},
  2050. {"HPHL", NULL, "HPHL PA"},
  2051. /* HPHR */
  2052. {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
  2053. {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
  2054. {"RX INT2 DAC", NULL, "RX_BIAS"},
  2055. {"HPHR PA", NULL, "RX INT2 DAC"},
  2056. {"HPHR", NULL, "HPHR PA"},
  2057. /* LINEOUT1 */
  2058. {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
  2059. {"RX INT3 DAC", NULL, "RX_BIAS"},
  2060. {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
  2061. {"LINEOUT1", NULL, "LINEOUT1 PA"},
  2062. /* LINEOUT2 */
  2063. {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
  2064. {"RX INT4 DAC", NULL, "RX_BIAS"},
  2065. {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
  2066. {"LINEOUT2", NULL, "LINEOUT2 PA"},
  2067. /* LINEOUT3 */
  2068. {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
  2069. {"RX INT5 DAC", NULL, "RX_BIAS"},
  2070. {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
  2071. {"LINEOUT3", NULL, "LINEOUT3 PA"},
  2072. /* LINEOUT4 */
  2073. {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
  2074. {"RX INT6 DAC", NULL, "RX_BIAS"},
  2075. {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
  2076. {"LINEOUT4", NULL, "LINEOUT4 PA"},
  2077. /* SLIMBUS Connections */
  2078. {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
  2079. {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
  2080. {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
  2081. /* ADC Mux */
  2082. WCD9335_ADC_MUX_PATH(0),
  2083. WCD9335_ADC_MUX_PATH(1),
  2084. WCD9335_ADC_MUX_PATH(2),
  2085. WCD9335_ADC_MUX_PATH(3),
  2086. WCD9335_ADC_MUX_PATH(4),
  2087. WCD9335_ADC_MUX_PATH(5),
  2088. WCD9335_ADC_MUX_PATH(6),
  2089. WCD9335_ADC_MUX_PATH(7),
  2090. WCD9335_ADC_MUX_PATH(8),
  2091. /* ADC Connections */
  2092. {"ADC1", NULL, "AMIC1"},
  2093. {"ADC2", NULL, "AMIC2"},
  2094. {"ADC3", NULL, "AMIC3"},
  2095. {"ADC4", NULL, "AMIC4"},
  2096. {"ADC5", NULL, "AMIC5"},
  2097. {"ADC6", NULL, "AMIC6"},
  2098. };
  2099. static int wcd9335_micbias_control(struct snd_soc_component *component,
  2100. int micb_num, int req, bool is_dapm)
  2101. {
  2102. struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
  2103. int micb_index = micb_num - 1;
  2104. u16 micb_reg;
  2105. if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
  2106. dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
  2107. micb_index);
  2108. return -EINVAL;
  2109. }
  2110. switch (micb_num) {
  2111. case MIC_BIAS_1:
  2112. micb_reg = WCD9335_ANA_MICB1;
  2113. break;
  2114. case MIC_BIAS_2:
  2115. micb_reg = WCD9335_ANA_MICB2;
  2116. break;
  2117. case MIC_BIAS_3:
  2118. micb_reg = WCD9335_ANA_MICB3;
  2119. break;
  2120. case MIC_BIAS_4:
  2121. micb_reg = WCD9335_ANA_MICB4;
  2122. break;
  2123. default:
  2124. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  2125. __func__, micb_num);
  2126. return -EINVAL;
  2127. }
  2128. switch (req) {
  2129. case MICB_PULLUP_ENABLE:
  2130. wcd->pullup_ref[micb_index]++;
  2131. if ((wcd->pullup_ref[micb_index] == 1) &&
  2132. (wcd->micb_ref[micb_index] == 0))
  2133. snd_soc_component_update_bits(component, micb_reg,
  2134. 0xC0, 0x80);
  2135. break;
  2136. case MICB_PULLUP_DISABLE:
  2137. wcd->pullup_ref[micb_index]--;
  2138. if ((wcd->pullup_ref[micb_index] == 0) &&
  2139. (wcd->micb_ref[micb_index] == 0))
  2140. snd_soc_component_update_bits(component, micb_reg,
  2141. 0xC0, 0x00);
  2142. break;
  2143. case MICB_ENABLE:
  2144. wcd->micb_ref[micb_index]++;
  2145. if (wcd->micb_ref[micb_index] == 1)
  2146. snd_soc_component_update_bits(component, micb_reg,
  2147. 0xC0, 0x40);
  2148. break;
  2149. case MICB_DISABLE:
  2150. wcd->micb_ref[micb_index]--;
  2151. if ((wcd->micb_ref[micb_index] == 0) &&
  2152. (wcd->pullup_ref[micb_index] > 0))
  2153. snd_soc_component_update_bits(component, micb_reg,
  2154. 0xC0, 0x80);
  2155. else if ((wcd->micb_ref[micb_index] == 0) &&
  2156. (wcd->pullup_ref[micb_index] == 0)) {
  2157. snd_soc_component_update_bits(component, micb_reg,
  2158. 0xC0, 0x00);
  2159. }
  2160. break;
  2161. }
  2162. return 0;
  2163. }
  2164. static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2165. int event)
  2166. {
  2167. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2168. int micb_num;
  2169. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2170. micb_num = MIC_BIAS_1;
  2171. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2172. micb_num = MIC_BIAS_2;
  2173. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2174. micb_num = MIC_BIAS_3;
  2175. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2176. micb_num = MIC_BIAS_4;
  2177. else
  2178. return -EINVAL;
  2179. switch (event) {
  2180. case SND_SOC_DAPM_PRE_PMU:
  2181. /*
  2182. * MIC BIAS can also be requested by MBHC,
  2183. * so use ref count to handle micbias pullup
  2184. * and enable requests
  2185. */
  2186. wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
  2187. break;
  2188. case SND_SOC_DAPM_POST_PMU:
  2189. /* wait for cnp time */
  2190. usleep_range(1000, 1100);
  2191. break;
  2192. case SND_SOC_DAPM_POST_PMD:
  2193. wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
  2194. break;
  2195. }
  2196. return 0;
  2197. }
  2198. static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2199. struct snd_kcontrol *kc, int event)
  2200. {
  2201. return __wcd9335_codec_enable_micbias(w, event);
  2202. }
  2203. static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
  2204. u16 amic_reg, bool set)
  2205. {
  2206. u8 mask = 0x20;
  2207. u8 val;
  2208. if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
  2209. amic_reg == WCD9335_ANA_AMIC5)
  2210. mask = 0x40;
  2211. val = set ? mask : 0x00;
  2212. switch (amic_reg) {
  2213. case WCD9335_ANA_AMIC1:
  2214. case WCD9335_ANA_AMIC2:
  2215. snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
  2216. val);
  2217. break;
  2218. case WCD9335_ANA_AMIC3:
  2219. case WCD9335_ANA_AMIC4:
  2220. snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
  2221. val);
  2222. break;
  2223. case WCD9335_ANA_AMIC5:
  2224. case WCD9335_ANA_AMIC6:
  2225. snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
  2226. val);
  2227. break;
  2228. default:
  2229. dev_err(comp->dev, "%s: invalid amic: %d\n",
  2230. __func__, amic_reg);
  2231. break;
  2232. }
  2233. }
  2234. static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
  2235. struct snd_kcontrol *kc, int event)
  2236. {
  2237. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2238. switch (event) {
  2239. case SND_SOC_DAPM_PRE_PMU:
  2240. wcd9335_codec_set_tx_hold(comp, w->reg, true);
  2241. break;
  2242. default:
  2243. break;
  2244. }
  2245. return 0;
  2246. }
  2247. static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
  2248. int adc_mux_n)
  2249. {
  2250. int mux_sel, reg, mreg;
  2251. if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
  2252. adc_mux_n == WCD9335_INVALID_ADC_MUX)
  2253. return 0;
  2254. /* Check whether adc mux input is AMIC or DMIC */
  2255. if (adc_mux_n < 4) {
  2256. reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
  2257. mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
  2258. mux_sel = snd_soc_component_read(comp, reg) & 0x3;
  2259. } else {
  2260. reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
  2261. mreg = reg;
  2262. mux_sel = snd_soc_component_read(comp, reg) >> 6;
  2263. }
  2264. if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
  2265. return 0;
  2266. return snd_soc_component_read(comp, mreg) & 0x07;
  2267. }
  2268. static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
  2269. int amic)
  2270. {
  2271. u16 pwr_level_reg = 0;
  2272. switch (amic) {
  2273. case 1:
  2274. case 2:
  2275. pwr_level_reg = WCD9335_ANA_AMIC1;
  2276. break;
  2277. case 3:
  2278. case 4:
  2279. pwr_level_reg = WCD9335_ANA_AMIC3;
  2280. break;
  2281. case 5:
  2282. case 6:
  2283. pwr_level_reg = WCD9335_ANA_AMIC5;
  2284. break;
  2285. default:
  2286. dev_err(comp->dev, "invalid amic: %d\n", amic);
  2287. break;
  2288. }
  2289. return pwr_level_reg;
  2290. }
  2291. static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
  2292. struct snd_kcontrol *kc, int event)
  2293. {
  2294. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2295. unsigned int decimator;
  2296. char *dec_adc_mux_name = NULL;
  2297. char *widget_name = NULL;
  2298. char *wname;
  2299. int ret = 0, amic_n;
  2300. u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
  2301. u16 tx_gain_ctl_reg;
  2302. char *dec;
  2303. u8 hpf_coff_freq;
  2304. widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
  2305. if (!widget_name)
  2306. return -ENOMEM;
  2307. wname = widget_name;
  2308. dec_adc_mux_name = strsep(&widget_name, " ");
  2309. if (!dec_adc_mux_name) {
  2310. dev_err(comp->dev, "%s: Invalid decimator = %s\n",
  2311. __func__, w->name);
  2312. ret = -EINVAL;
  2313. goto out;
  2314. }
  2315. dec_adc_mux_name = widget_name;
  2316. dec = strpbrk(dec_adc_mux_name, "012345678");
  2317. if (!dec) {
  2318. dev_err(comp->dev, "%s: decimator index not found\n",
  2319. __func__);
  2320. ret = -EINVAL;
  2321. goto out;
  2322. }
  2323. ret = kstrtouint(dec, 10, &decimator);
  2324. if (ret < 0) {
  2325. dev_err(comp->dev, "%s: Invalid decimator = %s\n",
  2326. __func__, wname);
  2327. ret = -EINVAL;
  2328. goto out;
  2329. }
  2330. tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
  2331. hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
  2332. dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
  2333. tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
  2334. switch (event) {
  2335. case SND_SOC_DAPM_PRE_PMU:
  2336. amic_n = wcd9335_codec_find_amic_input(comp, decimator);
  2337. if (amic_n)
  2338. pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
  2339. amic_n);
  2340. if (pwr_level_reg) {
  2341. switch ((snd_soc_component_read(comp, pwr_level_reg) &
  2342. WCD9335_AMIC_PWR_LVL_MASK) >>
  2343. WCD9335_AMIC_PWR_LVL_SHIFT) {
  2344. case WCD9335_AMIC_PWR_LEVEL_LP:
  2345. snd_soc_component_update_bits(comp, dec_cfg_reg,
  2346. WCD9335_DEC_PWR_LVL_MASK,
  2347. WCD9335_DEC_PWR_LVL_LP);
  2348. break;
  2349. case WCD9335_AMIC_PWR_LEVEL_HP:
  2350. snd_soc_component_update_bits(comp, dec_cfg_reg,
  2351. WCD9335_DEC_PWR_LVL_MASK,
  2352. WCD9335_DEC_PWR_LVL_HP);
  2353. break;
  2354. case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
  2355. default:
  2356. snd_soc_component_update_bits(comp, dec_cfg_reg,
  2357. WCD9335_DEC_PWR_LVL_MASK,
  2358. WCD9335_DEC_PWR_LVL_DF);
  2359. break;
  2360. }
  2361. }
  2362. hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
  2363. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  2364. if (hpf_coff_freq != CF_MIN_3DB_150HZ)
  2365. snd_soc_component_update_bits(comp, dec_cfg_reg,
  2366. TX_HPF_CUT_OFF_FREQ_MASK,
  2367. CF_MIN_3DB_150HZ << 5);
  2368. /* Enable TX PGA Mute */
  2369. snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
  2370. 0x10, 0x10);
  2371. /* Enable APC */
  2372. snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
  2373. break;
  2374. case SND_SOC_DAPM_POST_PMU:
  2375. snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
  2376. if (decimator == 0) {
  2377. snd_soc_component_write(comp,
  2378. WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
  2379. snd_soc_component_write(comp,
  2380. WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
  2381. snd_soc_component_write(comp,
  2382. WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
  2383. snd_soc_component_write(comp,
  2384. WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
  2385. }
  2386. snd_soc_component_update_bits(comp, hpf_gate_reg,
  2387. 0x01, 0x01);
  2388. snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
  2389. 0x10, 0x00);
  2390. snd_soc_component_write(comp, tx_gain_ctl_reg,
  2391. snd_soc_component_read(comp, tx_gain_ctl_reg));
  2392. break;
  2393. case SND_SOC_DAPM_PRE_PMD:
  2394. hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
  2395. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  2396. snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
  2397. snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
  2398. if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
  2399. snd_soc_component_update_bits(comp, dec_cfg_reg,
  2400. TX_HPF_CUT_OFF_FREQ_MASK,
  2401. hpf_coff_freq << 5);
  2402. }
  2403. break;
  2404. case SND_SOC_DAPM_POST_PMD:
  2405. snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
  2406. break;
  2407. }
  2408. out:
  2409. kfree(wname);
  2410. return ret;
  2411. }
  2412. static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
  2413. u32 mclk_rate, u32 dmic_clk_rate)
  2414. {
  2415. u32 div_factor;
  2416. u8 dmic_ctl_val;
  2417. dev_err(component->dev,
  2418. "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
  2419. __func__, mclk_rate, dmic_clk_rate);
  2420. /* Default value to return in case of error */
  2421. if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
  2422. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
  2423. else
  2424. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
  2425. if (dmic_clk_rate == 0) {
  2426. dev_err(component->dev,
  2427. "%s: dmic_sample_rate cannot be 0\n",
  2428. __func__);
  2429. goto done;
  2430. }
  2431. div_factor = mclk_rate / dmic_clk_rate;
  2432. switch (div_factor) {
  2433. case 2:
  2434. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
  2435. break;
  2436. case 3:
  2437. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
  2438. break;
  2439. case 4:
  2440. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
  2441. break;
  2442. case 6:
  2443. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
  2444. break;
  2445. case 8:
  2446. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
  2447. break;
  2448. case 16:
  2449. dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
  2450. break;
  2451. default:
  2452. dev_err(component->dev,
  2453. "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
  2454. __func__, div_factor, mclk_rate, dmic_clk_rate);
  2455. break;
  2456. }
  2457. done:
  2458. return dmic_ctl_val;
  2459. }
  2460. static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  2461. struct snd_kcontrol *kc, int event)
  2462. {
  2463. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2464. struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
  2465. u8 dmic_clk_en = 0x01;
  2466. u16 dmic_clk_reg;
  2467. s32 *dmic_clk_cnt;
  2468. u8 dmic_rate_val, dmic_rate_shift = 1;
  2469. unsigned int dmic;
  2470. int ret;
  2471. char *wname;
  2472. wname = strpbrk(w->name, "012345");
  2473. if (!wname) {
  2474. dev_err(comp->dev, "%s: widget not found\n", __func__);
  2475. return -EINVAL;
  2476. }
  2477. ret = kstrtouint(wname, 10, &dmic);
  2478. if (ret < 0) {
  2479. dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
  2480. __func__);
  2481. return -EINVAL;
  2482. }
  2483. switch (dmic) {
  2484. case 0:
  2485. case 1:
  2486. dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
  2487. dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
  2488. break;
  2489. case 2:
  2490. case 3:
  2491. dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
  2492. dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
  2493. break;
  2494. case 4:
  2495. case 5:
  2496. dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
  2497. dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
  2498. break;
  2499. default:
  2500. dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
  2501. __func__);
  2502. return -EINVAL;
  2503. }
  2504. switch (event) {
  2505. case SND_SOC_DAPM_PRE_PMU:
  2506. dmic_rate_val =
  2507. wcd9335_get_dmic_clk_val(comp,
  2508. wcd->mclk_rate,
  2509. wcd->dmic_sample_rate);
  2510. (*dmic_clk_cnt)++;
  2511. if (*dmic_clk_cnt == 1) {
  2512. snd_soc_component_update_bits(comp, dmic_clk_reg,
  2513. 0x07 << dmic_rate_shift,
  2514. dmic_rate_val << dmic_rate_shift);
  2515. snd_soc_component_update_bits(comp, dmic_clk_reg,
  2516. dmic_clk_en, dmic_clk_en);
  2517. }
  2518. break;
  2519. case SND_SOC_DAPM_POST_PMD:
  2520. dmic_rate_val =
  2521. wcd9335_get_dmic_clk_val(comp,
  2522. wcd->mclk_rate,
  2523. wcd->mad_dmic_sample_rate);
  2524. (*dmic_clk_cnt)--;
  2525. if (*dmic_clk_cnt == 0) {
  2526. snd_soc_component_update_bits(comp, dmic_clk_reg,
  2527. dmic_clk_en, 0);
  2528. snd_soc_component_update_bits(comp, dmic_clk_reg,
  2529. 0x07 << dmic_rate_shift,
  2530. dmic_rate_val << dmic_rate_shift);
  2531. }
  2532. break;
  2533. }
  2534. return 0;
  2535. }
  2536. static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
  2537. struct snd_soc_component *component)
  2538. {
  2539. int port_num = 0;
  2540. unsigned short reg = 0;
  2541. unsigned int val = 0;
  2542. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  2543. struct wcd9335_slim_ch *ch;
  2544. list_for_each_entry(ch, &dai->slim_ch_list, list) {
  2545. if (ch->port >= WCD9335_RX_START) {
  2546. port_num = ch->port - WCD9335_RX_START;
  2547. reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
  2548. } else {
  2549. port_num = ch->port;
  2550. reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
  2551. }
  2552. regmap_read(wcd->if_regmap, reg, &val);
  2553. if (!(val & BIT(port_num % 8)))
  2554. regmap_write(wcd->if_regmap, reg,
  2555. val | BIT(port_num % 8));
  2556. }
  2557. }
  2558. static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
  2559. struct snd_kcontrol *kc,
  2560. int event)
  2561. {
  2562. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2563. struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
  2564. struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
  2565. switch (event) {
  2566. case SND_SOC_DAPM_POST_PMU:
  2567. wcd9335_codec_enable_int_port(dai, comp);
  2568. break;
  2569. case SND_SOC_DAPM_POST_PMD:
  2570. kfree(dai->sconfig.chs);
  2571. break;
  2572. }
  2573. return 0;
  2574. }
  2575. static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
  2576. struct snd_kcontrol *kc, int event)
  2577. {
  2578. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2579. u16 gain_reg;
  2580. int offset_val = 0;
  2581. int val = 0;
  2582. switch (w->reg) {
  2583. case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
  2584. gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
  2585. break;
  2586. case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
  2587. gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
  2588. break;
  2589. case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
  2590. gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
  2591. break;
  2592. case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
  2593. gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
  2594. break;
  2595. case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
  2596. gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
  2597. break;
  2598. case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
  2599. gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
  2600. break;
  2601. case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
  2602. gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
  2603. break;
  2604. case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
  2605. gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
  2606. break;
  2607. case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
  2608. gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
  2609. break;
  2610. default:
  2611. dev_err(comp->dev, "%s: No gain register avail for %s\n",
  2612. __func__, w->name);
  2613. return 0;
  2614. }
  2615. switch (event) {
  2616. case SND_SOC_DAPM_POST_PMU:
  2617. val = snd_soc_component_read(comp, gain_reg);
  2618. val += offset_val;
  2619. snd_soc_component_write(comp, gain_reg, val);
  2620. break;
  2621. case SND_SOC_DAPM_POST_PMD:
  2622. break;
  2623. }
  2624. return 0;
  2625. }
  2626. static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
  2627. {
  2628. u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
  2629. switch (reg) {
  2630. case WCD9335_CDC_RX0_RX_PATH_CTL:
  2631. case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
  2632. prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
  2633. *ind = 0;
  2634. break;
  2635. case WCD9335_CDC_RX1_RX_PATH_CTL:
  2636. case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
  2637. prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
  2638. *ind = 1;
  2639. break;
  2640. case WCD9335_CDC_RX2_RX_PATH_CTL:
  2641. case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
  2642. prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
  2643. *ind = 2;
  2644. break;
  2645. case WCD9335_CDC_RX3_RX_PATH_CTL:
  2646. case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
  2647. prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
  2648. *ind = 3;
  2649. break;
  2650. case WCD9335_CDC_RX4_RX_PATH_CTL:
  2651. case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
  2652. prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
  2653. *ind = 4;
  2654. break;
  2655. case WCD9335_CDC_RX5_RX_PATH_CTL:
  2656. case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
  2657. prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
  2658. *ind = 5;
  2659. break;
  2660. case WCD9335_CDC_RX6_RX_PATH_CTL:
  2661. case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
  2662. prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
  2663. *ind = 6;
  2664. break;
  2665. case WCD9335_CDC_RX7_RX_PATH_CTL:
  2666. case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
  2667. prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
  2668. *ind = 7;
  2669. break;
  2670. case WCD9335_CDC_RX8_RX_PATH_CTL:
  2671. case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
  2672. prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
  2673. *ind = 8;
  2674. break;
  2675. }
  2676. return prim_int_reg;
  2677. }
  2678. static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
  2679. u16 prim_int_reg, int event)
  2680. {
  2681. u16 hd2_scale_reg;
  2682. u16 hd2_enable_reg = 0;
  2683. if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
  2684. hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
  2685. hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
  2686. }
  2687. if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
  2688. hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
  2689. hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
  2690. }
  2691. if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
  2692. snd_soc_component_update_bits(component, hd2_scale_reg,
  2693. WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
  2694. WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
  2695. snd_soc_component_update_bits(component, hd2_scale_reg,
  2696. WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
  2697. WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
  2698. snd_soc_component_update_bits(component, hd2_enable_reg,
  2699. WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
  2700. WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
  2701. }
  2702. if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
  2703. snd_soc_component_update_bits(component, hd2_enable_reg,
  2704. WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
  2705. WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
  2706. snd_soc_component_update_bits(component, hd2_scale_reg,
  2707. WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
  2708. WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
  2709. snd_soc_component_update_bits(component, hd2_scale_reg,
  2710. WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
  2711. WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
  2712. }
  2713. }
  2714. static int wcd9335_codec_enable_prim_interpolator(
  2715. struct snd_soc_component *comp,
  2716. u16 reg, int event)
  2717. {
  2718. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  2719. u16 ind = 0;
  2720. int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
  2721. switch (event) {
  2722. case SND_SOC_DAPM_PRE_PMU:
  2723. wcd->prim_int_users[ind]++;
  2724. if (wcd->prim_int_users[ind] == 1) {
  2725. snd_soc_component_update_bits(comp, prim_int_reg,
  2726. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  2727. WCD9335_CDC_RX_PGA_MUTE_ENABLE);
  2728. wcd9335_codec_hd2_control(comp, prim_int_reg, event);
  2729. snd_soc_component_update_bits(comp, prim_int_reg,
  2730. WCD9335_CDC_RX_CLK_EN_MASK,
  2731. WCD9335_CDC_RX_CLK_ENABLE);
  2732. }
  2733. if ((reg != prim_int_reg) &&
  2734. ((snd_soc_component_read(comp, prim_int_reg)) &
  2735. WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
  2736. snd_soc_component_update_bits(comp, reg,
  2737. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  2738. WCD9335_CDC_RX_PGA_MUTE_ENABLE);
  2739. break;
  2740. case SND_SOC_DAPM_POST_PMD:
  2741. wcd->prim_int_users[ind]--;
  2742. if (wcd->prim_int_users[ind] == 0) {
  2743. snd_soc_component_update_bits(comp, prim_int_reg,
  2744. WCD9335_CDC_RX_CLK_EN_MASK,
  2745. WCD9335_CDC_RX_CLK_DISABLE);
  2746. snd_soc_component_update_bits(comp, prim_int_reg,
  2747. WCD9335_CDC_RX_RESET_MASK,
  2748. WCD9335_CDC_RX_RESET_ENABLE);
  2749. snd_soc_component_update_bits(comp, prim_int_reg,
  2750. WCD9335_CDC_RX_RESET_MASK,
  2751. WCD9335_CDC_RX_RESET_DISABLE);
  2752. wcd9335_codec_hd2_control(comp, prim_int_reg, event);
  2753. }
  2754. break;
  2755. }
  2756. return 0;
  2757. }
  2758. static int wcd9335_config_compander(struct snd_soc_component *component,
  2759. int interp_n, int event)
  2760. {
  2761. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  2762. int comp;
  2763. u16 comp_ctl0_reg, rx_path_cfg0_reg;
  2764. /* EAR does not have compander */
  2765. if (!interp_n)
  2766. return 0;
  2767. comp = interp_n - 1;
  2768. if (!wcd->comp_enabled[comp])
  2769. return 0;
  2770. comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
  2771. rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
  2772. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2773. /* Enable Compander Clock */
  2774. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2775. WCD9335_CDC_COMPANDER_CLK_EN_MASK,
  2776. WCD9335_CDC_COMPANDER_CLK_ENABLE);
  2777. /* Reset comander */
  2778. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2779. WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
  2780. WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
  2781. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2782. WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
  2783. WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
  2784. /* Enables DRE in this path */
  2785. snd_soc_component_update_bits(component, rx_path_cfg0_reg,
  2786. WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
  2787. WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
  2788. }
  2789. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  2790. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2791. WCD9335_CDC_COMPANDER_HALT_MASK,
  2792. WCD9335_CDC_COMPANDER_HALT);
  2793. snd_soc_component_update_bits(component, rx_path_cfg0_reg,
  2794. WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
  2795. WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
  2796. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2797. WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
  2798. WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
  2799. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2800. WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
  2801. WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
  2802. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2803. WCD9335_CDC_COMPANDER_CLK_EN_MASK,
  2804. WCD9335_CDC_COMPANDER_CLK_DISABLE);
  2805. snd_soc_component_update_bits(component, comp_ctl0_reg,
  2806. WCD9335_CDC_COMPANDER_HALT_MASK,
  2807. WCD9335_CDC_COMPANDER_NOHALT);
  2808. }
  2809. return 0;
  2810. }
  2811. static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
  2812. struct snd_kcontrol *kc, int event)
  2813. {
  2814. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2815. u16 gain_reg;
  2816. u16 reg;
  2817. int val;
  2818. int offset_val = 0;
  2819. if (!(strcmp(w->name, "RX INT0 INTERP"))) {
  2820. reg = WCD9335_CDC_RX0_RX_PATH_CTL;
  2821. gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
  2822. } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
  2823. reg = WCD9335_CDC_RX1_RX_PATH_CTL;
  2824. gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
  2825. } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
  2826. reg = WCD9335_CDC_RX2_RX_PATH_CTL;
  2827. gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
  2828. } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
  2829. reg = WCD9335_CDC_RX3_RX_PATH_CTL;
  2830. gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
  2831. } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
  2832. reg = WCD9335_CDC_RX4_RX_PATH_CTL;
  2833. gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
  2834. } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
  2835. reg = WCD9335_CDC_RX5_RX_PATH_CTL;
  2836. gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
  2837. } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
  2838. reg = WCD9335_CDC_RX6_RX_PATH_CTL;
  2839. gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
  2840. } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
  2841. reg = WCD9335_CDC_RX7_RX_PATH_CTL;
  2842. gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
  2843. } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
  2844. reg = WCD9335_CDC_RX8_RX_PATH_CTL;
  2845. gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
  2846. } else {
  2847. dev_err(comp->dev, "%s: Interpolator reg not found\n",
  2848. __func__);
  2849. return -EINVAL;
  2850. }
  2851. switch (event) {
  2852. case SND_SOC_DAPM_PRE_PMU:
  2853. /* Reset if needed */
  2854. wcd9335_codec_enable_prim_interpolator(comp, reg, event);
  2855. break;
  2856. case SND_SOC_DAPM_POST_PMU:
  2857. wcd9335_config_compander(comp, w->shift, event);
  2858. val = snd_soc_component_read(comp, gain_reg);
  2859. val += offset_val;
  2860. snd_soc_component_write(comp, gain_reg, val);
  2861. break;
  2862. case SND_SOC_DAPM_POST_PMD:
  2863. wcd9335_config_compander(comp, w->shift, event);
  2864. wcd9335_codec_enable_prim_interpolator(comp, reg, event);
  2865. break;
  2866. }
  2867. return 0;
  2868. }
  2869. static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
  2870. u8 gain)
  2871. {
  2872. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  2873. u8 hph_l_en, hph_r_en;
  2874. u8 l_val, r_val;
  2875. u8 hph_pa_status;
  2876. bool is_hphl_pa, is_hphr_pa;
  2877. hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
  2878. is_hphl_pa = hph_pa_status >> 7;
  2879. is_hphr_pa = (hph_pa_status & 0x40) >> 6;
  2880. hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
  2881. hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
  2882. l_val = (hph_l_en & 0xC0) | 0x20 | gain;
  2883. r_val = (hph_r_en & 0xC0) | 0x20 | gain;
  2884. /*
  2885. * Set HPH_L & HPH_R gain source selection to REGISTER
  2886. * for better click and pop only if corresponding PAs are
  2887. * not enabled. Also cache the values of the HPHL/R
  2888. * PA gains to be applied after PAs are enabled
  2889. */
  2890. if ((l_val != hph_l_en) && !is_hphl_pa) {
  2891. snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
  2892. wcd->hph_l_gain = hph_l_en & 0x1F;
  2893. }
  2894. if ((r_val != hph_r_en) && !is_hphr_pa) {
  2895. snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
  2896. wcd->hph_r_gain = hph_r_en & 0x1F;
  2897. }
  2898. }
  2899. static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
  2900. int event)
  2901. {
  2902. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2903. snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
  2904. WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
  2905. 0x06);
  2906. snd_soc_component_update_bits(comp,
  2907. WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
  2908. 0xF0, 0x40);
  2909. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  2910. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  2911. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
  2912. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2913. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  2914. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
  2915. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
  2916. WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
  2917. 0x0C);
  2918. wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
  2919. }
  2920. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  2921. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2922. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  2923. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
  2924. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  2925. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  2926. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
  2927. snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
  2928. 0x8A);
  2929. snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
  2930. WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
  2931. 0x0A);
  2932. }
  2933. }
  2934. static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
  2935. int event)
  2936. {
  2937. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2938. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
  2939. WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
  2940. 0x0C);
  2941. wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
  2942. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  2943. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  2944. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
  2945. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2946. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  2947. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
  2948. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2949. WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
  2950. WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
  2951. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2952. WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
  2953. WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
  2954. snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
  2955. WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
  2956. WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
  2957. snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
  2958. WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
  2959. WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
  2960. snd_soc_component_update_bits(comp,
  2961. WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
  2962. snd_soc_component_update_bits(comp,
  2963. WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
  2964. }
  2965. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  2966. snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
  2967. 0x88);
  2968. snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
  2969. 0x33);
  2970. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2971. WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
  2972. WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
  2973. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2974. WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
  2975. WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
  2976. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2977. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  2978. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
  2979. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  2980. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  2981. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
  2982. snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
  2983. WCD9335_HPH_CONST_SEL_L_MASK,
  2984. WCD9335_HPH_CONST_SEL_L_HQ_PATH);
  2985. snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
  2986. WCD9335_HPH_CONST_SEL_L_MASK,
  2987. WCD9335_HPH_CONST_SEL_L_HQ_PATH);
  2988. }
  2989. }
  2990. static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
  2991. int event)
  2992. {
  2993. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2994. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  2995. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  2996. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
  2997. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  2998. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  2999. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
  3000. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
  3001. WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
  3002. 0x0C);
  3003. wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
  3004. }
  3005. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  3006. snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
  3007. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
  3008. WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
  3009. snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
  3010. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
  3011. WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
  3012. }
  3013. }
  3014. static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
  3015. int event, int mode)
  3016. {
  3017. switch (mode) {
  3018. case CLS_H_LP:
  3019. wcd9335_codec_hph_lp_config(component, event);
  3020. break;
  3021. case CLS_H_LOHIFI:
  3022. wcd9335_codec_hph_lohifi_config(component, event);
  3023. break;
  3024. case CLS_H_HIFI:
  3025. wcd9335_codec_hph_hifi_config(component, event);
  3026. break;
  3027. }
  3028. }
  3029. static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  3030. struct snd_kcontrol *kc,
  3031. int event)
  3032. {
  3033. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3034. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3035. int hph_mode = wcd->hph_mode;
  3036. u8 dem_inp;
  3037. switch (event) {
  3038. case SND_SOC_DAPM_PRE_PMU:
  3039. /* Read DEM INP Select */
  3040. dem_inp = snd_soc_component_read(comp,
  3041. WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
  3042. if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
  3043. (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
  3044. dev_err(comp->dev, "Incorrect DEM Input\n");
  3045. return -EINVAL;
  3046. }
  3047. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3048. WCD_CLSH_STATE_HPHL,
  3049. ((hph_mode == CLS_H_LOHIFI) ?
  3050. CLS_H_HIFI : hph_mode));
  3051. wcd9335_codec_hph_mode_config(comp, event, hph_mode);
  3052. break;
  3053. case SND_SOC_DAPM_POST_PMU:
  3054. usleep_range(1000, 1100);
  3055. break;
  3056. case SND_SOC_DAPM_PRE_PMD:
  3057. break;
  3058. case SND_SOC_DAPM_POST_PMD:
  3059. /* 1000us required as per HW requirement */
  3060. usleep_range(1000, 1100);
  3061. if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
  3062. WCD_CLSH_STATE_HPHR))
  3063. wcd9335_codec_hph_mode_config(comp, event, hph_mode);
  3064. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3065. WCD_CLSH_STATE_HPHL,
  3066. ((hph_mode == CLS_H_LOHIFI) ?
  3067. CLS_H_HIFI : hph_mode));
  3068. break;
  3069. }
  3070. return 0;
  3071. }
  3072. static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
  3073. struct snd_kcontrol *kc, int event)
  3074. {
  3075. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3076. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3077. switch (event) {
  3078. case SND_SOC_DAPM_PRE_PMU:
  3079. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3080. WCD_CLSH_STATE_LO, CLS_AB);
  3081. break;
  3082. case SND_SOC_DAPM_POST_PMD:
  3083. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3084. WCD_CLSH_STATE_LO, CLS_AB);
  3085. break;
  3086. }
  3087. return 0;
  3088. }
  3089. static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  3090. struct snd_kcontrol *kc, int event)
  3091. {
  3092. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3093. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3094. switch (event) {
  3095. case SND_SOC_DAPM_PRE_PMU:
  3096. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3097. WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
  3098. break;
  3099. case SND_SOC_DAPM_POST_PMD:
  3100. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3101. WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
  3102. break;
  3103. }
  3104. return 0;
  3105. }
  3106. static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
  3107. int mode, int event)
  3108. {
  3109. u8 scale_val = 0;
  3110. switch (event) {
  3111. case SND_SOC_DAPM_POST_PMU:
  3112. switch (mode) {
  3113. case CLS_H_HIFI:
  3114. scale_val = 0x3;
  3115. break;
  3116. case CLS_H_LOHIFI:
  3117. scale_val = 0x1;
  3118. break;
  3119. }
  3120. break;
  3121. case SND_SOC_DAPM_PRE_PMD:
  3122. scale_val = 0x6;
  3123. break;
  3124. }
  3125. if (scale_val)
  3126. snd_soc_component_update_bits(wcd->component,
  3127. WCD9335_HPH_PA_CTL1,
  3128. WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
  3129. scale_val << 1);
  3130. if (SND_SOC_DAPM_EVENT_ON(event)) {
  3131. if (wcd->comp_enabled[COMPANDER_1] ||
  3132. wcd->comp_enabled[COMPANDER_2]) {
  3133. /* GAIN Source Selection */
  3134. snd_soc_component_update_bits(wcd->component,
  3135. WCD9335_HPH_L_EN,
  3136. WCD9335_HPH_GAIN_SRC_SEL_MASK,
  3137. WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
  3138. snd_soc_component_update_bits(wcd->component,
  3139. WCD9335_HPH_R_EN,
  3140. WCD9335_HPH_GAIN_SRC_SEL_MASK,
  3141. WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
  3142. snd_soc_component_update_bits(wcd->component,
  3143. WCD9335_HPH_AUTO_CHOP,
  3144. WCD9335_HPH_AUTO_CHOP_MASK,
  3145. WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
  3146. }
  3147. snd_soc_component_update_bits(wcd->component,
  3148. WCD9335_HPH_L_EN,
  3149. WCD9335_HPH_PA_GAIN_MASK,
  3150. wcd->hph_l_gain);
  3151. snd_soc_component_update_bits(wcd->component,
  3152. WCD9335_HPH_R_EN,
  3153. WCD9335_HPH_PA_GAIN_MASK,
  3154. wcd->hph_r_gain);
  3155. }
  3156. if (SND_SOC_DAPM_EVENT_OFF(event))
  3157. snd_soc_component_update_bits(wcd->component,
  3158. WCD9335_HPH_AUTO_CHOP,
  3159. WCD9335_HPH_AUTO_CHOP_MASK,
  3160. WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
  3161. }
  3162. static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  3163. struct snd_kcontrol *kc,
  3164. int event)
  3165. {
  3166. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3167. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3168. int hph_mode = wcd->hph_mode;
  3169. u8 dem_inp;
  3170. switch (event) {
  3171. case SND_SOC_DAPM_PRE_PMU:
  3172. /* Read DEM INP Select */
  3173. dem_inp = snd_soc_component_read(comp,
  3174. WCD9335_CDC_RX2_RX_PATH_SEC0) &
  3175. WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
  3176. if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
  3177. (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
  3178. dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
  3179. hph_mode);
  3180. return -EINVAL;
  3181. }
  3182. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
  3183. WCD_CLSH_EVENT_PRE_DAC,
  3184. WCD_CLSH_STATE_HPHR,
  3185. ((hph_mode == CLS_H_LOHIFI) ?
  3186. CLS_H_HIFI : hph_mode));
  3187. wcd9335_codec_hph_mode_config(comp, event, hph_mode);
  3188. break;
  3189. case SND_SOC_DAPM_POST_PMD:
  3190. /* 1000us required as per HW requirement */
  3191. usleep_range(1000, 1100);
  3192. if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
  3193. WCD_CLSH_STATE_HPHL))
  3194. wcd9335_codec_hph_mode_config(comp, event, hph_mode);
  3195. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3196. WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
  3197. CLS_H_HIFI : hph_mode));
  3198. break;
  3199. }
  3200. return 0;
  3201. }
  3202. static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  3203. struct snd_kcontrol *kc,
  3204. int event)
  3205. {
  3206. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3207. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3208. int hph_mode = wcd->hph_mode;
  3209. switch (event) {
  3210. case SND_SOC_DAPM_PRE_PMU:
  3211. break;
  3212. case SND_SOC_DAPM_POST_PMU:
  3213. /*
  3214. * 7ms sleep is required after PA is enabled as per
  3215. * HW requirement
  3216. */
  3217. usleep_range(7000, 7100);
  3218. wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
  3219. snd_soc_component_update_bits(comp,
  3220. WCD9335_CDC_RX1_RX_PATH_CTL,
  3221. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3222. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3223. /* Remove mix path mute if it is enabled */
  3224. if ((snd_soc_component_read(comp,
  3225. WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
  3226. WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
  3227. snd_soc_component_update_bits(comp,
  3228. WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
  3229. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3230. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3231. break;
  3232. case SND_SOC_DAPM_PRE_PMD:
  3233. wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
  3234. break;
  3235. case SND_SOC_DAPM_POST_PMD:
  3236. /* 5ms sleep is required after PA is disabled as per
  3237. * HW requirement
  3238. */
  3239. usleep_range(5000, 5500);
  3240. break;
  3241. }
  3242. return 0;
  3243. }
  3244. static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
  3245. struct snd_kcontrol *kc,
  3246. int event)
  3247. {
  3248. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3249. int vol_reg = 0, mix_vol_reg = 0;
  3250. if (w->reg == WCD9335_ANA_LO_1_2) {
  3251. if (w->shift == 7) {
  3252. vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
  3253. mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
  3254. } else if (w->shift == 6) {
  3255. vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
  3256. mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
  3257. }
  3258. } else if (w->reg == WCD9335_ANA_LO_3_4) {
  3259. if (w->shift == 7) {
  3260. vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
  3261. mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
  3262. } else if (w->shift == 6) {
  3263. vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
  3264. mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
  3265. }
  3266. } else {
  3267. dev_err(comp->dev, "Error enabling lineout PA\n");
  3268. return -EINVAL;
  3269. }
  3270. switch (event) {
  3271. case SND_SOC_DAPM_POST_PMU:
  3272. /* 5ms sleep is required after PA is enabled as per
  3273. * HW requirement
  3274. */
  3275. usleep_range(5000, 5500);
  3276. snd_soc_component_update_bits(comp, vol_reg,
  3277. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3278. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3279. /* Remove mix path mute if it is enabled */
  3280. if ((snd_soc_component_read(comp, mix_vol_reg)) &
  3281. WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
  3282. snd_soc_component_update_bits(comp, mix_vol_reg,
  3283. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3284. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3285. break;
  3286. case SND_SOC_DAPM_POST_PMD:
  3287. /* 5ms sleep is required after PA is disabled as per
  3288. * HW requirement
  3289. */
  3290. usleep_range(5000, 5500);
  3291. break;
  3292. }
  3293. return 0;
  3294. }
  3295. static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
  3296. {
  3297. snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
  3298. WCD9335_HPH_CONST_SEL_L_MASK,
  3299. WCD9335_HPH_CONST_SEL_L_BYPASS);
  3300. snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
  3301. WCD9335_HPH_CONST_SEL_L_MASK,
  3302. WCD9335_HPH_CONST_SEL_L_BYPASS);
  3303. snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
  3304. WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
  3305. WCD9335_RX_BIAS_FLYB_I_0P0_UA);
  3306. snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
  3307. WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
  3308. WCD9335_RX_BIAS_FLYB_I_0P0_UA);
  3309. }
  3310. static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
  3311. struct snd_kcontrol *kc, int event)
  3312. {
  3313. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3314. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3315. switch (event) {
  3316. case SND_SOC_DAPM_PRE_PMU:
  3317. wcd->rx_bias_count++;
  3318. if (wcd->rx_bias_count == 1) {
  3319. wcd9335_codec_init_flyback(comp);
  3320. snd_soc_component_update_bits(comp,
  3321. WCD9335_ANA_RX_SUPPLIES,
  3322. WCD9335_ANA_RX_BIAS_ENABLE_MASK,
  3323. WCD9335_ANA_RX_BIAS_ENABLE);
  3324. }
  3325. break;
  3326. case SND_SOC_DAPM_POST_PMD:
  3327. wcd->rx_bias_count--;
  3328. if (!wcd->rx_bias_count)
  3329. snd_soc_component_update_bits(comp,
  3330. WCD9335_ANA_RX_SUPPLIES,
  3331. WCD9335_ANA_RX_BIAS_ENABLE_MASK,
  3332. WCD9335_ANA_RX_BIAS_DISABLE);
  3333. break;
  3334. }
  3335. return 0;
  3336. }
  3337. static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  3338. struct snd_kcontrol *kc, int event)
  3339. {
  3340. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3341. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  3342. int hph_mode = wcd->hph_mode;
  3343. switch (event) {
  3344. case SND_SOC_DAPM_PRE_PMU:
  3345. break;
  3346. case SND_SOC_DAPM_POST_PMU:
  3347. /*
  3348. * 7ms sleep is required after PA is enabled as per
  3349. * HW requirement
  3350. */
  3351. usleep_range(7000, 7100);
  3352. wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
  3353. snd_soc_component_update_bits(comp,
  3354. WCD9335_CDC_RX2_RX_PATH_CTL,
  3355. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3356. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3357. /* Remove mix path mute if it is enabled */
  3358. if ((snd_soc_component_read(comp,
  3359. WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
  3360. WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
  3361. snd_soc_component_update_bits(comp,
  3362. WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
  3363. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3364. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3365. break;
  3366. case SND_SOC_DAPM_PRE_PMD:
  3367. wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
  3368. break;
  3369. case SND_SOC_DAPM_POST_PMD:
  3370. /* 5ms sleep is required after PA is disabled as per
  3371. * HW requirement
  3372. */
  3373. usleep_range(5000, 5500);
  3374. break;
  3375. }
  3376. return 0;
  3377. }
  3378. static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  3379. struct snd_kcontrol *kc, int event)
  3380. {
  3381. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3382. switch (event) {
  3383. case SND_SOC_DAPM_POST_PMU:
  3384. /* 5ms sleep is required after PA is enabled as per
  3385. * HW requirement
  3386. */
  3387. usleep_range(5000, 5500);
  3388. snd_soc_component_update_bits(comp,
  3389. WCD9335_CDC_RX0_RX_PATH_CTL,
  3390. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3391. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3392. /* Remove mix path mute if it is enabled */
  3393. if ((snd_soc_component_read(comp,
  3394. WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
  3395. WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
  3396. snd_soc_component_update_bits(comp,
  3397. WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
  3398. WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
  3399. WCD9335_CDC_RX_PGA_MUTE_DISABLE);
  3400. break;
  3401. case SND_SOC_DAPM_POST_PMD:
  3402. /* 5ms sleep is required after PA is disabled as per
  3403. * HW requirement
  3404. */
  3405. usleep_range(5000, 5500);
  3406. break;
  3407. }
  3408. return 0;
  3409. }
  3410. static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
  3411. {
  3412. struct wcd9335_codec *wcd = data;
  3413. unsigned long status = 0;
  3414. int i, j, port_id;
  3415. unsigned int val, int_val = 0;
  3416. irqreturn_t ret = IRQ_NONE;
  3417. bool tx;
  3418. unsigned short reg = 0;
  3419. for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
  3420. i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
  3421. regmap_read(wcd->if_regmap, i, &val);
  3422. status |= ((u32)val << (8 * j));
  3423. }
  3424. for_each_set_bit(j, &status, 32) {
  3425. tx = (j >= 16 ? true : false);
  3426. port_id = (tx ? j - 16 : j);
  3427. regmap_read(wcd->if_regmap,
  3428. WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
  3429. if (val) {
  3430. if (!tx)
  3431. reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
  3432. (port_id / 8);
  3433. else
  3434. reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
  3435. (port_id / 8);
  3436. regmap_read(
  3437. wcd->if_regmap, reg, &int_val);
  3438. /*
  3439. * Ignore interrupts for ports for which the
  3440. * interrupts are not specifically enabled.
  3441. */
  3442. if (!(int_val & (1 << (port_id % 8))))
  3443. continue;
  3444. }
  3445. if (val & WCD9335_SLIM_IRQ_OVERFLOW)
  3446. dev_err_ratelimited(wcd->dev,
  3447. "%s: overflow error on %s port %d, value %x\n",
  3448. __func__, (tx ? "TX" : "RX"), port_id, val);
  3449. if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
  3450. dev_err_ratelimited(wcd->dev,
  3451. "%s: underflow error on %s port %d, value %x\n",
  3452. __func__, (tx ? "TX" : "RX"), port_id, val);
  3453. if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
  3454. (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
  3455. if (!tx)
  3456. reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
  3457. (port_id / 8);
  3458. else
  3459. reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
  3460. (port_id / 8);
  3461. regmap_read(
  3462. wcd->if_regmap, reg, &int_val);
  3463. if (int_val & (1 << (port_id % 8))) {
  3464. int_val = int_val ^ (1 << (port_id % 8));
  3465. regmap_write(wcd->if_regmap,
  3466. reg, int_val);
  3467. }
  3468. }
  3469. regmap_write(wcd->if_regmap,
  3470. WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
  3471. BIT(j % 8));
  3472. ret = IRQ_HANDLED;
  3473. }
  3474. return ret;
  3475. }
  3476. static struct wcd9335_irq wcd9335_irqs[] = {
  3477. {
  3478. .irq = WCD9335_IRQ_SLIMBUS,
  3479. .handler = wcd9335_slimbus_irq,
  3480. .name = "SLIM Slave",
  3481. },
  3482. };
  3483. static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
  3484. {
  3485. int irq, ret, i;
  3486. for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
  3487. irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
  3488. if (irq < 0) {
  3489. dev_err(wcd->dev, "Failed to get %s\n",
  3490. wcd9335_irqs[i].name);
  3491. return irq;
  3492. }
  3493. ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
  3494. wcd9335_irqs[i].handler,
  3495. IRQF_TRIGGER_RISING |
  3496. IRQF_ONESHOT,
  3497. wcd9335_irqs[i].name, wcd);
  3498. if (ret) {
  3499. dev_err(wcd->dev, "Failed to request %s\n",
  3500. wcd9335_irqs[i].name);
  3501. return ret;
  3502. }
  3503. }
  3504. /* enable interrupts on all slave ports */
  3505. for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
  3506. regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
  3507. 0xFF);
  3508. return ret;
  3509. }
  3510. static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
  3511. {
  3512. int i;
  3513. /* disable interrupts on all slave ports */
  3514. for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
  3515. regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
  3516. 0x00);
  3517. }
  3518. static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
  3519. bool ccl_flag)
  3520. {
  3521. struct snd_soc_component *comp = wcd->component;
  3522. if (ccl_flag) {
  3523. if (++wcd->sido_ccl_cnt == 1)
  3524. snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
  3525. WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
  3526. } else {
  3527. if (wcd->sido_ccl_cnt == 0) {
  3528. dev_err(wcd->dev, "sido_ccl already disabled\n");
  3529. return;
  3530. }
  3531. if (--wcd->sido_ccl_cnt == 0)
  3532. snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
  3533. WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
  3534. }
  3535. }
  3536. static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
  3537. {
  3538. wcd->master_bias_users++;
  3539. if (wcd->master_bias_users == 1) {
  3540. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3541. WCD9335_ANA_BIAS_EN_MASK,
  3542. WCD9335_ANA_BIAS_ENABLE);
  3543. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3544. WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
  3545. WCD9335_ANA_BIAS_PRECHRG_ENABLE);
  3546. /*
  3547. * 1ms delay is required after pre-charge is enabled
  3548. * as per HW requirement
  3549. */
  3550. usleep_range(1000, 1100);
  3551. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3552. WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
  3553. WCD9335_ANA_BIAS_PRECHRG_DISABLE);
  3554. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3555. WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
  3556. WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
  3557. }
  3558. return 0;
  3559. }
  3560. static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
  3561. {
  3562. /* Enable mclk requires master bias to be enabled first */
  3563. if (wcd->master_bias_users <= 0)
  3564. return -EINVAL;
  3565. if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
  3566. ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
  3567. dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
  3568. wcd->clk_type);
  3569. return -EINVAL;
  3570. }
  3571. if (++wcd->clk_mclk_users == 1) {
  3572. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3573. WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
  3574. WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
  3575. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3576. WCD9335_ANA_CLK_MCLK_SRC_MASK,
  3577. WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
  3578. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3579. WCD9335_ANA_CLK_MCLK_EN_MASK,
  3580. WCD9335_ANA_CLK_MCLK_ENABLE);
  3581. regmap_update_bits(wcd->regmap,
  3582. WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
  3583. WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
  3584. WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
  3585. regmap_update_bits(wcd->regmap,
  3586. WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
  3587. WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
  3588. WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
  3589. /*
  3590. * 10us sleep is required after clock is enabled
  3591. * as per HW requirement
  3592. */
  3593. usleep_range(10, 15);
  3594. }
  3595. wcd->clk_type = WCD_CLK_MCLK;
  3596. return 0;
  3597. }
  3598. static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
  3599. {
  3600. if (wcd->clk_mclk_users <= 0)
  3601. return -EINVAL;
  3602. if (--wcd->clk_mclk_users == 0) {
  3603. if (wcd->clk_rco_users > 0) {
  3604. /* MCLK to RCO switch */
  3605. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3606. WCD9335_ANA_CLK_MCLK_SRC_MASK,
  3607. WCD9335_ANA_CLK_MCLK_SRC_RCO);
  3608. wcd->clk_type = WCD_CLK_RCO;
  3609. } else {
  3610. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3611. WCD9335_ANA_CLK_MCLK_EN_MASK,
  3612. WCD9335_ANA_CLK_MCLK_DISABLE);
  3613. wcd->clk_type = WCD_CLK_OFF;
  3614. }
  3615. regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
  3616. WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
  3617. WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
  3618. }
  3619. return 0;
  3620. }
  3621. static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
  3622. {
  3623. if (wcd->master_bias_users <= 0)
  3624. return -EINVAL;
  3625. wcd->master_bias_users--;
  3626. if (wcd->master_bias_users == 0) {
  3627. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3628. WCD9335_ANA_BIAS_EN_MASK,
  3629. WCD9335_ANA_BIAS_DISABLE);
  3630. regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
  3631. WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
  3632. WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
  3633. }
  3634. return 0;
  3635. }
  3636. static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
  3637. bool enable)
  3638. {
  3639. int ret = 0;
  3640. if (enable) {
  3641. wcd9335_cdc_sido_ccl_enable(wcd, true);
  3642. ret = clk_prepare_enable(wcd->mclk);
  3643. if (ret) {
  3644. dev_err(wcd->dev, "%s: ext clk enable failed\n",
  3645. __func__);
  3646. goto err;
  3647. }
  3648. /* get BG */
  3649. wcd9335_enable_master_bias(wcd);
  3650. /* get MCLK */
  3651. wcd9335_enable_mclk(wcd);
  3652. } else {
  3653. /* put MCLK */
  3654. wcd9335_disable_mclk(wcd);
  3655. /* put BG */
  3656. wcd9335_disable_master_bias(wcd);
  3657. clk_disable_unprepare(wcd->mclk);
  3658. wcd9335_cdc_sido_ccl_enable(wcd, false);
  3659. }
  3660. err:
  3661. return ret;
  3662. }
  3663. static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
  3664. enum wcd9335_sido_voltage req_mv)
  3665. {
  3666. struct snd_soc_component *comp = wcd->component;
  3667. int vout_d_val;
  3668. if (req_mv == wcd->sido_voltage)
  3669. return;
  3670. /* compute the vout_d step value */
  3671. vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
  3672. WCD9335_ANA_BUCK_VOUT_MASK;
  3673. snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
  3674. snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
  3675. WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
  3676. WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
  3677. /* 1 msec sleep required after SIDO Vout_D voltage change */
  3678. usleep_range(1000, 1100);
  3679. wcd->sido_voltage = req_mv;
  3680. snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
  3681. WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
  3682. WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
  3683. }
  3684. static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
  3685. enum wcd9335_sido_voltage req_mv)
  3686. {
  3687. int ret = 0;
  3688. /* enable mclk before setting SIDO voltage */
  3689. ret = wcd9335_cdc_req_mclk_enable(wcd, true);
  3690. if (ret) {
  3691. dev_err(wcd->dev, "Ext clk enable failed\n");
  3692. goto err;
  3693. }
  3694. wcd9335_codec_apply_sido_voltage(wcd, req_mv);
  3695. wcd9335_cdc_req_mclk_enable(wcd, false);
  3696. err:
  3697. return ret;
  3698. }
  3699. static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
  3700. int enable)
  3701. {
  3702. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  3703. int ret;
  3704. if (enable) {
  3705. ret = wcd9335_cdc_req_mclk_enable(wcd, true);
  3706. if (ret)
  3707. return ret;
  3708. wcd9335_codec_apply_sido_voltage(wcd,
  3709. SIDO_VOLTAGE_NOMINAL_MV);
  3710. } else {
  3711. wcd9335_codec_update_sido_voltage(wcd,
  3712. wcd->sido_voltage);
  3713. wcd9335_cdc_req_mclk_enable(wcd, false);
  3714. }
  3715. return 0;
  3716. }
  3717. static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
  3718. struct snd_kcontrol *kc, int event)
  3719. {
  3720. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3721. switch (event) {
  3722. case SND_SOC_DAPM_PRE_PMU:
  3723. return _wcd9335_codec_enable_mclk(comp, true);
  3724. case SND_SOC_DAPM_POST_PMD:
  3725. return _wcd9335_codec_enable_mclk(comp, false);
  3726. }
  3727. return 0;
  3728. }
  3729. static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
  3730. /* TODO SPK1 & SPK2 OUT*/
  3731. SND_SOC_DAPM_OUTPUT("EAR"),
  3732. SND_SOC_DAPM_OUTPUT("HPHL"),
  3733. SND_SOC_DAPM_OUTPUT("HPHR"),
  3734. SND_SOC_DAPM_OUTPUT("LINEOUT1"),
  3735. SND_SOC_DAPM_OUTPUT("LINEOUT2"),
  3736. SND_SOC_DAPM_OUTPUT("LINEOUT3"),
  3737. SND_SOC_DAPM_OUTPUT("LINEOUT4"),
  3738. SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
  3739. AIF1_PB, 0, wcd9335_codec_enable_slim,
  3740. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3741. SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
  3742. AIF2_PB, 0, wcd9335_codec_enable_slim,
  3743. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3744. SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
  3745. AIF3_PB, 0, wcd9335_codec_enable_slim,
  3746. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3747. SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
  3748. AIF4_PB, 0, wcd9335_codec_enable_slim,
  3749. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3750. SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
  3751. &slim_rx_mux[WCD9335_RX0]),
  3752. SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
  3753. &slim_rx_mux[WCD9335_RX1]),
  3754. SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
  3755. &slim_rx_mux[WCD9335_RX2]),
  3756. SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
  3757. &slim_rx_mux[WCD9335_RX3]),
  3758. SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
  3759. &slim_rx_mux[WCD9335_RX4]),
  3760. SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
  3761. &slim_rx_mux[WCD9335_RX5]),
  3762. SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
  3763. &slim_rx_mux[WCD9335_RX6]),
  3764. SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
  3765. &slim_rx_mux[WCD9335_RX7]),
  3766. SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
  3767. SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3768. SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3769. SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3770. SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
  3771. SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
  3772. SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
  3773. SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
  3774. SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
  3775. 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
  3776. SND_SOC_DAPM_POST_PMU),
  3777. SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
  3778. 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
  3779. SND_SOC_DAPM_POST_PMU),
  3780. SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
  3781. 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
  3782. SND_SOC_DAPM_POST_PMU),
  3783. SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
  3784. 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
  3785. SND_SOC_DAPM_POST_PMU),
  3786. SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
  3787. 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
  3788. SND_SOC_DAPM_POST_PMU),
  3789. SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
  3790. 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
  3791. SND_SOC_DAPM_POST_PMU),
  3792. SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
  3793. 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
  3794. SND_SOC_DAPM_POST_PMU),
  3795. SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
  3796. 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
  3797. SND_SOC_DAPM_POST_PMU),
  3798. SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
  3799. 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
  3800. SND_SOC_DAPM_POST_PMU),
  3801. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3802. &rx_int0_1_mix_inp0_mux),
  3803. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3804. &rx_int0_1_mix_inp1_mux),
  3805. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3806. &rx_int0_1_mix_inp2_mux),
  3807. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3808. &rx_int1_1_mix_inp0_mux),
  3809. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3810. &rx_int1_1_mix_inp1_mux),
  3811. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3812. &rx_int1_1_mix_inp2_mux),
  3813. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3814. &rx_int2_1_mix_inp0_mux),
  3815. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3816. &rx_int2_1_mix_inp1_mux),
  3817. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3818. &rx_int2_1_mix_inp2_mux),
  3819. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3820. &rx_int3_1_mix_inp0_mux),
  3821. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3822. &rx_int3_1_mix_inp1_mux),
  3823. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3824. &rx_int3_1_mix_inp2_mux),
  3825. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3826. &rx_int4_1_mix_inp0_mux),
  3827. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3828. &rx_int4_1_mix_inp1_mux),
  3829. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3830. &rx_int4_1_mix_inp2_mux),
  3831. SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3832. &rx_int5_1_mix_inp0_mux),
  3833. SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3834. &rx_int5_1_mix_inp1_mux),
  3835. SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3836. &rx_int5_1_mix_inp2_mux),
  3837. SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3838. &rx_int6_1_mix_inp0_mux),
  3839. SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3840. &rx_int6_1_mix_inp1_mux),
  3841. SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3842. &rx_int6_1_mix_inp2_mux),
  3843. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3844. &rx_int7_1_mix_inp0_mux),
  3845. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3846. &rx_int7_1_mix_inp1_mux),
  3847. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3848. &rx_int7_1_mix_inp2_mux),
  3849. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3850. &rx_int8_1_mix_inp0_mux),
  3851. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3852. &rx_int8_1_mix_inp1_mux),
  3853. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3854. &rx_int8_1_mix_inp2_mux),
  3855. SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3856. SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3857. SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3858. SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3859. SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3860. SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3861. SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3862. SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3863. SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3864. SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3865. SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3866. SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3867. SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3868. SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3869. SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3870. SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3871. SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3872. SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3873. SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3874. SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3875. SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3876. SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3877. SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3878. SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3879. SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3880. SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3881. SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3882. SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
  3883. &rx_int0_dem_inp_mux),
  3884. SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
  3885. &rx_int1_dem_inp_mux),
  3886. SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
  3887. &rx_int2_dem_inp_mux),
  3888. SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
  3889. INTERP_EAR, 0, &rx_int0_interp_mux,
  3890. wcd9335_codec_enable_interpolator,
  3891. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3892. SND_SOC_DAPM_POST_PMD),
  3893. SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
  3894. INTERP_HPHL, 0, &rx_int1_interp_mux,
  3895. wcd9335_codec_enable_interpolator,
  3896. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3897. SND_SOC_DAPM_POST_PMD),
  3898. SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
  3899. INTERP_HPHR, 0, &rx_int2_interp_mux,
  3900. wcd9335_codec_enable_interpolator,
  3901. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3902. SND_SOC_DAPM_POST_PMD),
  3903. SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
  3904. INTERP_LO1, 0, &rx_int3_interp_mux,
  3905. wcd9335_codec_enable_interpolator,
  3906. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3907. SND_SOC_DAPM_POST_PMD),
  3908. SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
  3909. INTERP_LO2, 0, &rx_int4_interp_mux,
  3910. wcd9335_codec_enable_interpolator,
  3911. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3912. SND_SOC_DAPM_POST_PMD),
  3913. SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
  3914. INTERP_LO3, 0, &rx_int5_interp_mux,
  3915. wcd9335_codec_enable_interpolator,
  3916. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3917. SND_SOC_DAPM_POST_PMD),
  3918. SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
  3919. INTERP_LO4, 0, &rx_int6_interp_mux,
  3920. wcd9335_codec_enable_interpolator,
  3921. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3922. SND_SOC_DAPM_POST_PMD),
  3923. SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
  3924. INTERP_SPKR1, 0, &rx_int7_interp_mux,
  3925. wcd9335_codec_enable_interpolator,
  3926. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3927. SND_SOC_DAPM_POST_PMD),
  3928. SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
  3929. INTERP_SPKR2, 0, &rx_int8_interp_mux,
  3930. wcd9335_codec_enable_interpolator,
  3931. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3932. SND_SOC_DAPM_POST_PMD),
  3933. SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
  3934. 0, 0, wcd9335_codec_ear_dac_event,
  3935. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3936. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3937. SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
  3938. 5, 0, wcd9335_codec_hphl_dac_event,
  3939. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3940. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3941. SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
  3942. 4, 0, wcd9335_codec_hphr_dac_event,
  3943. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3944. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3945. SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
  3946. 0, 0, wcd9335_codec_lineout_dac_event,
  3947. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3948. SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
  3949. 0, 0, wcd9335_codec_lineout_dac_event,
  3950. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3951. SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
  3952. 0, 0, wcd9335_codec_lineout_dac_event,
  3953. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3954. SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
  3955. 0, 0, wcd9335_codec_lineout_dac_event,
  3956. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3957. SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
  3958. wcd9335_codec_enable_hphl_pa,
  3959. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3960. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3961. SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
  3962. wcd9335_codec_enable_hphr_pa,
  3963. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3964. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3965. SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
  3966. wcd9335_codec_enable_ear_pa,
  3967. SND_SOC_DAPM_POST_PMU |
  3968. SND_SOC_DAPM_POST_PMD),
  3969. SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
  3970. wcd9335_codec_enable_lineout_pa,
  3971. SND_SOC_DAPM_POST_PMU |
  3972. SND_SOC_DAPM_POST_PMD),
  3973. SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
  3974. wcd9335_codec_enable_lineout_pa,
  3975. SND_SOC_DAPM_POST_PMU |
  3976. SND_SOC_DAPM_POST_PMD),
  3977. SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
  3978. wcd9335_codec_enable_lineout_pa,
  3979. SND_SOC_DAPM_POST_PMU |
  3980. SND_SOC_DAPM_POST_PMD),
  3981. SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
  3982. wcd9335_codec_enable_lineout_pa,
  3983. SND_SOC_DAPM_POST_PMU |
  3984. SND_SOC_DAPM_POST_PMD),
  3985. SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
  3986. wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
  3987. SND_SOC_DAPM_POST_PMD),
  3988. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3989. wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
  3990. SND_SOC_DAPM_POST_PMD),
  3991. /* TX */
  3992. SND_SOC_DAPM_INPUT("AMIC1"),
  3993. SND_SOC_DAPM_INPUT("AMIC2"),
  3994. SND_SOC_DAPM_INPUT("AMIC3"),
  3995. SND_SOC_DAPM_INPUT("AMIC4"),
  3996. SND_SOC_DAPM_INPUT("AMIC5"),
  3997. SND_SOC_DAPM_INPUT("AMIC6"),
  3998. SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
  3999. AIF1_CAP, 0, wcd9335_codec_enable_slim,
  4000. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4001. SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
  4002. AIF2_CAP, 0, wcd9335_codec_enable_slim,
  4003. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4004. SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
  4005. AIF3_CAP, 0, wcd9335_codec_enable_slim,
  4006. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4007. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  4008. wcd9335_codec_enable_micbias,
  4009. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4010. SND_SOC_DAPM_POST_PMD),
  4011. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  4012. wcd9335_codec_enable_micbias,
  4013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4014. SND_SOC_DAPM_POST_PMD),
  4015. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  4016. wcd9335_codec_enable_micbias,
  4017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4018. SND_SOC_DAPM_POST_PMD),
  4019. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  4020. wcd9335_codec_enable_micbias,
  4021. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4022. SND_SOC_DAPM_POST_PMD),
  4023. SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
  4024. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4025. SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
  4026. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4027. SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
  4028. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4029. SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
  4030. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4031. SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
  4032. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4033. SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
  4034. wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4035. /* Digital Mic Inputs */
  4036. SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
  4037. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4038. SND_SOC_DAPM_POST_PMD),
  4039. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  4040. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4041. SND_SOC_DAPM_POST_PMD),
  4042. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
  4043. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4044. SND_SOC_DAPM_POST_PMD),
  4045. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
  4046. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4047. SND_SOC_DAPM_POST_PMD),
  4048. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
  4049. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4050. SND_SOC_DAPM_POST_PMD),
  4051. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
  4052. wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  4053. SND_SOC_DAPM_POST_PMD),
  4054. SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
  4055. &tx_dmic_mux0),
  4056. SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
  4057. &tx_dmic_mux1),
  4058. SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
  4059. &tx_dmic_mux2),
  4060. SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
  4061. &tx_dmic_mux3),
  4062. SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
  4063. &tx_dmic_mux4),
  4064. SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
  4065. &tx_dmic_mux5),
  4066. SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
  4067. &tx_dmic_mux6),
  4068. SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
  4069. &tx_dmic_mux7),
  4070. SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
  4071. &tx_dmic_mux8),
  4072. SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
  4073. &tx_amic_mux0),
  4074. SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
  4075. &tx_amic_mux1),
  4076. SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
  4077. &tx_amic_mux2),
  4078. SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
  4079. &tx_amic_mux3),
  4080. SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
  4081. &tx_amic_mux4),
  4082. SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
  4083. &tx_amic_mux5),
  4084. SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
  4085. &tx_amic_mux6),
  4086. SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
  4087. &tx_amic_mux7),
  4088. SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
  4089. &tx_amic_mux8),
  4090. SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
  4091. aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
  4092. SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
  4093. aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
  4094. SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
  4095. aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
  4096. SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
  4097. &sb_tx0_mux),
  4098. SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
  4099. &sb_tx1_mux),
  4100. SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
  4101. &sb_tx2_mux),
  4102. SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
  4103. &sb_tx3_mux),
  4104. SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
  4105. &sb_tx4_mux),
  4106. SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
  4107. &sb_tx5_mux),
  4108. SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
  4109. &sb_tx6_mux),
  4110. SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
  4111. &sb_tx7_mux),
  4112. SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
  4113. &sb_tx8_mux),
  4114. SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
  4115. &tx_adc_mux0, wcd9335_codec_enable_dec,
  4116. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4117. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4118. SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
  4119. &tx_adc_mux1, wcd9335_codec_enable_dec,
  4120. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4121. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4122. SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
  4123. &tx_adc_mux2, wcd9335_codec_enable_dec,
  4124. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4125. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4126. SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
  4127. &tx_adc_mux3, wcd9335_codec_enable_dec,
  4128. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4129. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4130. SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
  4131. &tx_adc_mux4, wcd9335_codec_enable_dec,
  4132. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4133. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4134. SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
  4135. &tx_adc_mux5, wcd9335_codec_enable_dec,
  4136. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4137. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4138. SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
  4139. &tx_adc_mux6, wcd9335_codec_enable_dec,
  4140. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4141. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4142. SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
  4143. &tx_adc_mux7, wcd9335_codec_enable_dec,
  4144. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4145. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4146. SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
  4147. &tx_adc_mux8, wcd9335_codec_enable_dec,
  4148. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4149. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4150. };
  4151. static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
  4152. {
  4153. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  4154. snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
  4155. WCD9335_ANA_RCO_BG_EN_MASK,
  4156. WCD9335_ANA_RCO_BG_ENABLE);
  4157. snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
  4158. WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
  4159. WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
  4160. /* 100us sleep needed after IREF settings */
  4161. usleep_range(100, 110);
  4162. snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
  4163. WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
  4164. WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
  4165. /* 100us sleep needed after VREF settings */
  4166. usleep_range(100, 110);
  4167. wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
  4168. }
  4169. static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
  4170. {
  4171. _wcd9335_codec_enable_mclk(comp, true);
  4172. snd_soc_component_update_bits(comp,
  4173. WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
  4174. WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
  4175. WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
  4176. /*
  4177. * 5ms sleep required after enabling efuse control
  4178. * before checking the status.
  4179. */
  4180. usleep_range(5000, 5500);
  4181. if (!(snd_soc_component_read(comp,
  4182. WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
  4183. WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
  4184. WARN(1, "%s: Efuse sense is not complete\n", __func__);
  4185. wcd9335_enable_sido_buck(comp);
  4186. _wcd9335_codec_enable_mclk(comp, false);
  4187. return 0;
  4188. }
  4189. static void wcd9335_codec_init(struct snd_soc_component *component)
  4190. {
  4191. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  4192. int i;
  4193. /* ungate MCLK and set clk rate */
  4194. regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
  4195. WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
  4196. regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
  4197. WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
  4198. WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
  4199. for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
  4200. snd_soc_component_update_bits(component,
  4201. wcd9335_codec_reg_init[i].reg,
  4202. wcd9335_codec_reg_init[i].mask,
  4203. wcd9335_codec_reg_init[i].val);
  4204. wcd9335_enable_efuse_sensing(component);
  4205. }
  4206. static int wcd9335_codec_probe(struct snd_soc_component *component)
  4207. {
  4208. struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
  4209. int ret;
  4210. int i;
  4211. snd_soc_component_init_regmap(component, wcd->regmap);
  4212. /* Class-H Init*/
  4213. wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
  4214. if (IS_ERR(wcd->clsh_ctrl))
  4215. return PTR_ERR(wcd->clsh_ctrl);
  4216. /* Default HPH Mode to Class-H HiFi */
  4217. wcd->hph_mode = CLS_H_HIFI;
  4218. wcd->component = component;
  4219. wcd9335_codec_init(component);
  4220. for (i = 0; i < NUM_CODEC_DAIS; i++)
  4221. INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
  4222. ret = wcd9335_setup_irqs(wcd);
  4223. if (ret)
  4224. goto free_clsh_ctrl;
  4225. return 0;
  4226. free_clsh_ctrl:
  4227. wcd_clsh_ctrl_free(wcd->clsh_ctrl);
  4228. return ret;
  4229. }
  4230. static void wcd9335_codec_remove(struct snd_soc_component *comp)
  4231. {
  4232. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  4233. wcd_clsh_ctrl_free(wcd->clsh_ctrl);
  4234. wcd9335_teardown_irqs(wcd);
  4235. }
  4236. static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
  4237. int clk_id, int source,
  4238. unsigned int freq, int dir)
  4239. {
  4240. struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
  4241. wcd->mclk_rate = freq;
  4242. if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
  4243. snd_soc_component_update_bits(comp,
  4244. WCD9335_CODEC_RPM_CLK_MCLK_CFG,
  4245. WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
  4246. WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
  4247. else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
  4248. snd_soc_component_update_bits(comp,
  4249. WCD9335_CODEC_RPM_CLK_MCLK_CFG,
  4250. WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
  4251. WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
  4252. return clk_set_rate(wcd->mclk, freq);
  4253. }
  4254. static const struct snd_soc_component_driver wcd9335_component_drv = {
  4255. .probe = wcd9335_codec_probe,
  4256. .remove = wcd9335_codec_remove,
  4257. .set_sysclk = wcd9335_codec_set_sysclk,
  4258. .controls = wcd9335_snd_controls,
  4259. .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
  4260. .dapm_widgets = wcd9335_dapm_widgets,
  4261. .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
  4262. .dapm_routes = wcd9335_audio_map,
  4263. .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
  4264. };
  4265. static int wcd9335_probe(struct wcd9335_codec *wcd)
  4266. {
  4267. struct device *dev = wcd->dev;
  4268. memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
  4269. memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
  4270. wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
  4271. wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
  4272. return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
  4273. wcd9335_slim_dais,
  4274. ARRAY_SIZE(wcd9335_slim_dais));
  4275. }
  4276. static const struct regmap_range_cfg wcd9335_ranges[] = {
  4277. {
  4278. .name = "WCD9335",
  4279. .range_min = 0x0,
  4280. .range_max = WCD9335_MAX_REGISTER,
  4281. .selector_reg = WCD9335_SEL_REGISTER,
  4282. .selector_mask = 0xff,
  4283. .selector_shift = 0,
  4284. .window_start = 0x800,
  4285. .window_len = 0x100,
  4286. },
  4287. };
  4288. static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
  4289. {
  4290. switch (reg) {
  4291. case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
  4292. case WCD9335_ANA_MBHC_RESULT_3:
  4293. case WCD9335_ANA_MBHC_RESULT_2:
  4294. case WCD9335_ANA_MBHC_RESULT_1:
  4295. case WCD9335_ANA_MBHC_MECH:
  4296. case WCD9335_ANA_MBHC_ELECT:
  4297. case WCD9335_ANA_MBHC_ZDET:
  4298. case WCD9335_ANA_MICB2:
  4299. case WCD9335_ANA_RCO:
  4300. case WCD9335_ANA_BIAS:
  4301. return true;
  4302. default:
  4303. return false;
  4304. }
  4305. }
  4306. static struct regmap_config wcd9335_regmap_config = {
  4307. .reg_bits = 16,
  4308. .val_bits = 8,
  4309. .cache_type = REGCACHE_RBTREE,
  4310. .max_register = WCD9335_MAX_REGISTER,
  4311. .can_multi_write = true,
  4312. .ranges = wcd9335_ranges,
  4313. .num_ranges = ARRAY_SIZE(wcd9335_ranges),
  4314. .volatile_reg = wcd9335_is_volatile_register,
  4315. };
  4316. static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
  4317. {
  4318. .name = "WCD9335-IFC-DEV",
  4319. .range_min = 0x0,
  4320. .range_max = WCD9335_MAX_REGISTER,
  4321. .selector_reg = WCD9335_SEL_REGISTER,
  4322. .selector_mask = 0xfff,
  4323. .selector_shift = 0,
  4324. .window_start = 0x800,
  4325. .window_len = 0x400,
  4326. },
  4327. };
  4328. static struct regmap_config wcd9335_ifc_regmap_config = {
  4329. .reg_bits = 16,
  4330. .val_bits = 8,
  4331. .can_multi_write = true,
  4332. .max_register = WCD9335_MAX_REGISTER,
  4333. .ranges = wcd9335_ifc_ranges,
  4334. .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
  4335. };
  4336. static const struct regmap_irq wcd9335_codec_irqs[] = {
  4337. /* INTR_REG 0 */
  4338. [WCD9335_IRQ_SLIMBUS] = {
  4339. .reg_offset = 0,
  4340. .mask = BIT(0),
  4341. .type = {
  4342. .type_reg_offset = 0,
  4343. .types_supported = IRQ_TYPE_EDGE_BOTH,
  4344. .type_reg_mask = BIT(0),
  4345. },
  4346. },
  4347. };
  4348. static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
  4349. .name = "wcd9335_pin1_irq",
  4350. .status_base = WCD9335_INTR_PIN1_STATUS0,
  4351. .mask_base = WCD9335_INTR_PIN1_MASK0,
  4352. .ack_base = WCD9335_INTR_PIN1_CLEAR0,
  4353. .type_base = WCD9335_INTR_LEVEL0,
  4354. .num_type_reg = 4,
  4355. .num_regs = 4,
  4356. .irqs = wcd9335_codec_irqs,
  4357. .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
  4358. };
  4359. static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
  4360. {
  4361. struct device *dev = wcd->dev;
  4362. struct device_node *np = dev->of_node;
  4363. int ret;
  4364. wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
  4365. if (wcd->reset_gpio < 0) {
  4366. dev_err(dev, "Reset GPIO missing from DT\n");
  4367. return wcd->reset_gpio;
  4368. }
  4369. wcd->mclk = devm_clk_get(dev, "mclk");
  4370. if (IS_ERR(wcd->mclk)) {
  4371. dev_err(dev, "mclk not found\n");
  4372. return PTR_ERR(wcd->mclk);
  4373. }
  4374. wcd->native_clk = devm_clk_get(dev, "slimbus");
  4375. if (IS_ERR(wcd->native_clk)) {
  4376. dev_err(dev, "slimbus clock not found\n");
  4377. return PTR_ERR(wcd->native_clk);
  4378. }
  4379. wcd->supplies[0].supply = "vdd-buck";
  4380. wcd->supplies[1].supply = "vdd-buck-sido";
  4381. wcd->supplies[2].supply = "vdd-tx";
  4382. wcd->supplies[3].supply = "vdd-rx";
  4383. wcd->supplies[4].supply = "vdd-io";
  4384. ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
  4385. if (ret) {
  4386. dev_err(dev, "Failed to get supplies: err = %d\n", ret);
  4387. return ret;
  4388. }
  4389. return 0;
  4390. }
  4391. static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
  4392. {
  4393. struct device *dev = wcd->dev;
  4394. int ret;
  4395. ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
  4396. if (ret) {
  4397. dev_err(dev, "Failed to get supplies: err = %d\n", ret);
  4398. return ret;
  4399. }
  4400. /*
  4401. * For WCD9335, it takes about 600us for the Vout_A and
  4402. * Vout_D to be ready after BUCK_SIDO is powered up.
  4403. * SYS_RST_N shouldn't be pulled high during this time
  4404. * Toggle the reset line to make sure the reset pulse is
  4405. * correctly applied
  4406. */
  4407. usleep_range(600, 650);
  4408. gpio_direction_output(wcd->reset_gpio, 0);
  4409. msleep(20);
  4410. gpio_set_value(wcd->reset_gpio, 1);
  4411. msleep(20);
  4412. return 0;
  4413. }
  4414. static int wcd9335_bring_up(struct wcd9335_codec *wcd)
  4415. {
  4416. struct regmap *rm = wcd->regmap;
  4417. int val, byte0;
  4418. regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
  4419. regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
  4420. if ((val < 0) || (byte0 < 0)) {
  4421. dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
  4422. return -EINVAL;
  4423. }
  4424. if (byte0 == 0x1) {
  4425. dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
  4426. wcd->version = WCD9335_VERSION_2_0;
  4427. regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
  4428. regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
  4429. regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
  4430. regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
  4431. regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
  4432. regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
  4433. regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
  4434. regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
  4435. } else {
  4436. dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
  4437. return -EINVAL;
  4438. }
  4439. return 0;
  4440. }
  4441. static int wcd9335_irq_init(struct wcd9335_codec *wcd)
  4442. {
  4443. int ret;
  4444. /*
  4445. * INTR1 consists of all possible interrupt sources Ear OCP,
  4446. * HPH OCP, MBHC, MAD, VBAT, and SVA
  4447. * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
  4448. */
  4449. wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
  4450. if (wcd->intr1 < 0) {
  4451. if (wcd->intr1 != -EPROBE_DEFER)
  4452. dev_err(wcd->dev, "Unable to configure IRQ\n");
  4453. return wcd->intr1;
  4454. }
  4455. ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
  4456. IRQF_TRIGGER_HIGH, 0,
  4457. &wcd9335_regmap_irq1_chip, &wcd->irq_data);
  4458. if (ret)
  4459. dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret);
  4460. return ret;
  4461. }
  4462. static int wcd9335_slim_probe(struct slim_device *slim)
  4463. {
  4464. struct device *dev = &slim->dev;
  4465. struct wcd9335_codec *wcd;
  4466. int ret;
  4467. wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
  4468. if (!wcd)
  4469. return -ENOMEM;
  4470. wcd->dev = dev;
  4471. ret = wcd9335_parse_dt(wcd);
  4472. if (ret) {
  4473. dev_err(dev, "Error parsing DT: %d\n", ret);
  4474. return ret;
  4475. }
  4476. ret = wcd9335_power_on_reset(wcd);
  4477. if (ret)
  4478. return ret;
  4479. dev_set_drvdata(dev, wcd);
  4480. return 0;
  4481. }
  4482. static int wcd9335_slim_status(struct slim_device *sdev,
  4483. enum slim_device_status status)
  4484. {
  4485. struct device *dev = &sdev->dev;
  4486. struct device_node *ifc_dev_np;
  4487. struct wcd9335_codec *wcd;
  4488. int ret;
  4489. wcd = dev_get_drvdata(dev);
  4490. ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
  4491. if (!ifc_dev_np) {
  4492. dev_err(dev, "No Interface device found\n");
  4493. return -EINVAL;
  4494. }
  4495. wcd->slim = sdev;
  4496. wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
  4497. of_node_put(ifc_dev_np);
  4498. if (!wcd->slim_ifc_dev) {
  4499. dev_err(dev, "Unable to get SLIM Interface device\n");
  4500. return -EINVAL;
  4501. }
  4502. slim_get_logical_addr(wcd->slim_ifc_dev);
  4503. wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
  4504. if (IS_ERR(wcd->regmap)) {
  4505. dev_err(dev, "Failed to allocate slim register map\n");
  4506. return PTR_ERR(wcd->regmap);
  4507. }
  4508. wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
  4509. &wcd9335_ifc_regmap_config);
  4510. if (IS_ERR(wcd->if_regmap)) {
  4511. dev_err(dev, "Failed to allocate ifc register map\n");
  4512. return PTR_ERR(wcd->if_regmap);
  4513. }
  4514. ret = wcd9335_bring_up(wcd);
  4515. if (ret) {
  4516. dev_err(dev, "Failed to bringup WCD9335\n");
  4517. return ret;
  4518. }
  4519. ret = wcd9335_irq_init(wcd);
  4520. if (ret)
  4521. return ret;
  4522. wcd9335_probe(wcd);
  4523. return ret;
  4524. }
  4525. static const struct slim_device_id wcd9335_slim_id[] = {
  4526. {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
  4527. {}
  4528. };
  4529. MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
  4530. static struct slim_driver wcd9335_slim_driver = {
  4531. .driver = {
  4532. .name = "wcd9335-slim",
  4533. },
  4534. .probe = wcd9335_slim_probe,
  4535. .device_status = wcd9335_slim_status,
  4536. .id_table = wcd9335_slim_id,
  4537. };
  4538. module_slim_driver(wcd9335_slim_driver);
  4539. MODULE_DESCRIPTION("WCD9335 slim driver");
  4540. MODULE_LICENSE("GPL v2");
  4541. MODULE_ALIAS("slim:217:1a0:*");