tscs454.c 107 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // tscs454.c -- TSCS454 ALSA SoC Audio driver
  3. // Copyright 2018 Tempo Semiconductor, Inc.
  4. // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
  5. #include <linux/kernel.h>
  6. #include <linux/clk.h>
  7. #include <linux/device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/i2c.h>
  10. #include <linux/err.h>
  11. #include <linux/string.h>
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/mutex.h>
  15. #include <sound/tlv.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/pcm.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include "tscs454.h"
  21. static const unsigned int PLL_44_1K_RATE = (44100 * 256);
  22. #define COEFF_SIZE 3
  23. #define BIQUAD_COEFF_COUNT 5
  24. #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
  25. #define COEFF_RAM_MAX_ADDR 0xcd
  26. #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
  27. #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
  28. enum {
  29. TSCS454_DAI1_ID,
  30. TSCS454_DAI2_ID,
  31. TSCS454_DAI3_ID,
  32. TSCS454_DAI_COUNT,
  33. };
  34. struct pll {
  35. int id;
  36. unsigned int users;
  37. struct mutex lock;
  38. };
  39. static inline void pll_init(struct pll *pll, int id)
  40. {
  41. pll->id = id;
  42. mutex_init(&pll->lock);
  43. }
  44. struct internal_rate {
  45. struct pll *pll;
  46. };
  47. struct aif {
  48. unsigned int id;
  49. bool master;
  50. struct pll *pll;
  51. };
  52. static inline void aif_init(struct aif *aif, unsigned int id)
  53. {
  54. aif->id = id;
  55. }
  56. struct coeff_ram {
  57. u8 cache[COEFF_RAM_SIZE];
  58. bool synced;
  59. struct mutex lock;
  60. };
  61. static inline void init_coeff_ram_cache(u8 *cache)
  62. {
  63. static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
  64. 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
  65. 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
  66. 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
  67. 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
  68. int i;
  69. for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
  70. cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
  71. }
  72. static inline void coeff_ram_init(struct coeff_ram *ram)
  73. {
  74. init_coeff_ram_cache(ram->cache);
  75. mutex_init(&ram->lock);
  76. }
  77. struct aifs_status {
  78. u8 streams;
  79. };
  80. static inline void set_aif_status_active(struct aifs_status *status,
  81. int aif_id, bool playback)
  82. {
  83. u8 mask = 0x01 << (aif_id * 2 + !playback);
  84. status->streams |= mask;
  85. }
  86. static inline void set_aif_status_inactive(struct aifs_status *status,
  87. int aif_id, bool playback)
  88. {
  89. u8 mask = ~(0x01 << (aif_id * 2 + !playback));
  90. status->streams &= mask;
  91. }
  92. static bool aifs_active(struct aifs_status *status)
  93. {
  94. return status->streams;
  95. }
  96. static bool aif_active(struct aifs_status *status, int aif_id)
  97. {
  98. return (0x03 << aif_id * 2) & status->streams;
  99. }
  100. struct tscs454 {
  101. struct regmap *regmap;
  102. struct aif aifs[TSCS454_DAI_COUNT];
  103. struct aifs_status aifs_status;
  104. struct mutex aifs_status_lock;
  105. struct pll pll1;
  106. struct pll pll2;
  107. struct internal_rate internal_rate;
  108. struct coeff_ram dac_ram;
  109. struct coeff_ram spk_ram;
  110. struct coeff_ram sub_ram;
  111. struct clk *sysclk;
  112. int sysclk_src_id;
  113. unsigned int bclk_freq;
  114. };
  115. struct coeff_ram_ctl {
  116. unsigned int addr;
  117. struct soc_bytes_ext bytes_ext;
  118. };
  119. static const struct reg_sequence tscs454_patch[] = {
  120. /* Assign ASRC out of the box so DAI 1 just works */
  121. { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
  122. { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
  123. { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
  124. { R_TDMCTL0, FV_TDMMD_256 },
  125. { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
  126. };
  127. static bool tscs454_volatile(struct device *dev, unsigned int reg)
  128. {
  129. switch (reg) {
  130. case R_PLLSTAT:
  131. case R_SPKCRRDL:
  132. case R_SPKCRRDM:
  133. case R_SPKCRRDH:
  134. case R_SPKCRS:
  135. case R_DACCRRDL:
  136. case R_DACCRRDM:
  137. case R_DACCRRDH:
  138. case R_DACCRS:
  139. case R_SUBCRRDL:
  140. case R_SUBCRRDM:
  141. case R_SUBCRRDH:
  142. case R_SUBCRS:
  143. return true;
  144. default:
  145. return false;
  146. };
  147. }
  148. static bool tscs454_writable(struct device *dev, unsigned int reg)
  149. {
  150. switch (reg) {
  151. case R_SPKCRRDL:
  152. case R_SPKCRRDM:
  153. case R_SPKCRRDH:
  154. case R_DACCRRDL:
  155. case R_DACCRRDM:
  156. case R_DACCRRDH:
  157. case R_SUBCRRDL:
  158. case R_SUBCRRDM:
  159. case R_SUBCRRDH:
  160. return false;
  161. default:
  162. return true;
  163. };
  164. }
  165. static bool tscs454_readable(struct device *dev, unsigned int reg)
  166. {
  167. switch (reg) {
  168. case R_SPKCRWDL:
  169. case R_SPKCRWDM:
  170. case R_SPKCRWDH:
  171. case R_DACCRWDL:
  172. case R_DACCRWDM:
  173. case R_DACCRWDH:
  174. case R_SUBCRWDL:
  175. case R_SUBCRWDM:
  176. case R_SUBCRWDH:
  177. return false;
  178. default:
  179. return true;
  180. };
  181. }
  182. static bool tscs454_precious(struct device *dev, unsigned int reg)
  183. {
  184. switch (reg) {
  185. case R_SPKCRWDL:
  186. case R_SPKCRWDM:
  187. case R_SPKCRWDH:
  188. case R_SPKCRRDL:
  189. case R_SPKCRRDM:
  190. case R_SPKCRRDH:
  191. case R_DACCRWDL:
  192. case R_DACCRWDM:
  193. case R_DACCRWDH:
  194. case R_DACCRRDL:
  195. case R_DACCRRDM:
  196. case R_DACCRRDH:
  197. case R_SUBCRWDL:
  198. case R_SUBCRWDM:
  199. case R_SUBCRWDH:
  200. case R_SUBCRRDL:
  201. case R_SUBCRRDM:
  202. case R_SUBCRRDH:
  203. return true;
  204. default:
  205. return false;
  206. };
  207. }
  208. static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
  209. .name = "Pages",
  210. .range_min = VIRT_BASE,
  211. .range_max = VIRT_ADDR(0xFE, 0x02),
  212. .selector_reg = R_PAGESEL,
  213. .selector_mask = 0xff,
  214. .selector_shift = 0,
  215. .window_start = 0,
  216. .window_len = 0x100,
  217. };
  218. static struct regmap_config const tscs454_regmap_cfg = {
  219. .reg_bits = 8,
  220. .val_bits = 8,
  221. .writeable_reg = tscs454_writable,
  222. .readable_reg = tscs454_readable,
  223. .volatile_reg = tscs454_volatile,
  224. .precious_reg = tscs454_precious,
  225. .ranges = &tscs454_regmap_range_cfg,
  226. .num_ranges = 1,
  227. .max_register = VIRT_ADDR(0xFE, 0x02),
  228. .cache_type = REGCACHE_RBTREE,
  229. };
  230. static inline int tscs454_data_init(struct tscs454 *tscs454,
  231. struct i2c_client *i2c)
  232. {
  233. int i;
  234. int ret;
  235. tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
  236. if (IS_ERR(tscs454->regmap)) {
  237. ret = PTR_ERR(tscs454->regmap);
  238. return ret;
  239. }
  240. for (i = 0; i < TSCS454_DAI_COUNT; i++)
  241. aif_init(&tscs454->aifs[i], i);
  242. mutex_init(&tscs454->aifs_status_lock);
  243. pll_init(&tscs454->pll1, 1);
  244. pll_init(&tscs454->pll2, 2);
  245. coeff_ram_init(&tscs454->dac_ram);
  246. coeff_ram_init(&tscs454->spk_ram);
  247. coeff_ram_init(&tscs454->sub_ram);
  248. return 0;
  249. }
  250. struct reg_setting {
  251. unsigned int addr;
  252. unsigned int val;
  253. };
  254. static int coeff_ram_get(struct snd_kcontrol *kcontrol,
  255. struct snd_ctl_elem_value *ucontrol)
  256. {
  257. struct snd_soc_component *component =
  258. snd_soc_kcontrol_component(kcontrol);
  259. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  260. struct coeff_ram_ctl *ctl =
  261. (struct coeff_ram_ctl *)kcontrol->private_value;
  262. struct soc_bytes_ext *params = &ctl->bytes_ext;
  263. u8 *coeff_ram;
  264. struct mutex *coeff_ram_lock;
  265. if (strstr(kcontrol->id.name, "DAC")) {
  266. coeff_ram = tscs454->dac_ram.cache;
  267. coeff_ram_lock = &tscs454->dac_ram.lock;
  268. } else if (strstr(kcontrol->id.name, "Speaker")) {
  269. coeff_ram = tscs454->spk_ram.cache;
  270. coeff_ram_lock = &tscs454->spk_ram.lock;
  271. } else if (strstr(kcontrol->id.name, "Sub")) {
  272. coeff_ram = tscs454->sub_ram.cache;
  273. coeff_ram_lock = &tscs454->sub_ram.lock;
  274. } else {
  275. return -EINVAL;
  276. }
  277. mutex_lock(coeff_ram_lock);
  278. memcpy(ucontrol->value.bytes.data,
  279. &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
  280. mutex_unlock(coeff_ram_lock);
  281. return 0;
  282. }
  283. #define DACCRSTAT_MAX_TRYS 10
  284. static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
  285. unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
  286. unsigned int coeff_addr, unsigned int coeff_cnt)
  287. {
  288. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  289. unsigned int val;
  290. int cnt;
  291. int trys;
  292. int ret;
  293. for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
  294. for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
  295. val = snd_soc_component_read(component, r_stat);
  296. if (!val)
  297. break;
  298. }
  299. if (trys == DACCRSTAT_MAX_TRYS) {
  300. ret = -EIO;
  301. dev_err(component->dev,
  302. "Coefficient write error (%d)\n", ret);
  303. return ret;
  304. }
  305. ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
  306. if (ret < 0) {
  307. dev_err(component->dev,
  308. "Failed to write dac ram address (%d)\n", ret);
  309. return ret;
  310. }
  311. ret = regmap_bulk_write(tscs454->regmap, r_wr,
  312. &coeff_ram[coeff_addr * COEFF_SIZE],
  313. COEFF_SIZE);
  314. if (ret < 0) {
  315. dev_err(component->dev,
  316. "Failed to write dac ram (%d)\n", ret);
  317. return ret;
  318. }
  319. }
  320. return 0;
  321. }
  322. static int coeff_ram_put(struct snd_kcontrol *kcontrol,
  323. struct snd_ctl_elem_value *ucontrol)
  324. {
  325. struct snd_soc_component *component =
  326. snd_soc_kcontrol_component(kcontrol);
  327. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  328. struct coeff_ram_ctl *ctl =
  329. (struct coeff_ram_ctl *)kcontrol->private_value;
  330. struct soc_bytes_ext *params = &ctl->bytes_ext;
  331. unsigned int coeff_cnt = params->max / COEFF_SIZE;
  332. u8 *coeff_ram;
  333. struct mutex *coeff_ram_lock;
  334. bool *coeff_ram_synced;
  335. unsigned int r_stat;
  336. unsigned int r_addr;
  337. unsigned int r_wr;
  338. unsigned int val;
  339. int ret;
  340. if (strstr(kcontrol->id.name, "DAC")) {
  341. coeff_ram = tscs454->dac_ram.cache;
  342. coeff_ram_lock = &tscs454->dac_ram.lock;
  343. coeff_ram_synced = &tscs454->dac_ram.synced;
  344. r_stat = R_DACCRS;
  345. r_addr = R_DACCRADD;
  346. r_wr = R_DACCRWDL;
  347. } else if (strstr(kcontrol->id.name, "Speaker")) {
  348. coeff_ram = tscs454->spk_ram.cache;
  349. coeff_ram_lock = &tscs454->spk_ram.lock;
  350. coeff_ram_synced = &tscs454->spk_ram.synced;
  351. r_stat = R_SPKCRS;
  352. r_addr = R_SPKCRADD;
  353. r_wr = R_SPKCRWDL;
  354. } else if (strstr(kcontrol->id.name, "Sub")) {
  355. coeff_ram = tscs454->sub_ram.cache;
  356. coeff_ram_lock = &tscs454->sub_ram.lock;
  357. coeff_ram_synced = &tscs454->sub_ram.synced;
  358. r_stat = R_SUBCRS;
  359. r_addr = R_SUBCRADD;
  360. r_wr = R_SUBCRWDL;
  361. } else {
  362. return -EINVAL;
  363. }
  364. mutex_lock(coeff_ram_lock);
  365. *coeff_ram_synced = false;
  366. memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
  367. ucontrol->value.bytes.data, params->max);
  368. mutex_lock(&tscs454->pll1.lock);
  369. mutex_lock(&tscs454->pll2.lock);
  370. val = snd_soc_component_read(component, R_PLLSTAT);
  371. if (val) { /* PLLs locked */
  372. ret = write_coeff_ram(component, coeff_ram,
  373. r_stat, r_addr, r_wr,
  374. ctl->addr, coeff_cnt);
  375. if (ret < 0) {
  376. dev_err(component->dev,
  377. "Failed to flush coeff ram cache (%d)\n", ret);
  378. goto exit;
  379. }
  380. *coeff_ram_synced = true;
  381. }
  382. ret = 0;
  383. exit:
  384. mutex_unlock(&tscs454->pll2.lock);
  385. mutex_unlock(&tscs454->pll1.lock);
  386. mutex_unlock(coeff_ram_lock);
  387. return ret;
  388. }
  389. static inline int coeff_ram_sync(struct snd_soc_component *component,
  390. struct tscs454 *tscs454)
  391. {
  392. int ret;
  393. mutex_lock(&tscs454->dac_ram.lock);
  394. if (!tscs454->dac_ram.synced) {
  395. ret = write_coeff_ram(component, tscs454->dac_ram.cache,
  396. R_DACCRS, R_DACCRADD, R_DACCRWDL,
  397. 0x00, COEFF_RAM_COEFF_COUNT);
  398. if (ret < 0) {
  399. mutex_unlock(&tscs454->dac_ram.lock);
  400. return ret;
  401. }
  402. }
  403. mutex_unlock(&tscs454->dac_ram.lock);
  404. mutex_lock(&tscs454->spk_ram.lock);
  405. if (!tscs454->spk_ram.synced) {
  406. ret = write_coeff_ram(component, tscs454->spk_ram.cache,
  407. R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
  408. 0x00, COEFF_RAM_COEFF_COUNT);
  409. if (ret < 0) {
  410. mutex_unlock(&tscs454->spk_ram.lock);
  411. return ret;
  412. }
  413. }
  414. mutex_unlock(&tscs454->spk_ram.lock);
  415. mutex_lock(&tscs454->sub_ram.lock);
  416. if (!tscs454->sub_ram.synced) {
  417. ret = write_coeff_ram(component, tscs454->sub_ram.cache,
  418. R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
  419. 0x00, COEFF_RAM_COEFF_COUNT);
  420. if (ret < 0) {
  421. mutex_unlock(&tscs454->sub_ram.lock);
  422. return ret;
  423. }
  424. }
  425. mutex_unlock(&tscs454->sub_ram.lock);
  426. return 0;
  427. }
  428. #define PLL_REG_SETTINGS_COUNT 11
  429. struct pll_ctl {
  430. int freq_in;
  431. struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
  432. };
  433. #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
  434. { \
  435. .freq_in = f, \
  436. .settings = { \
  437. {R_PLL1CTL, c1}, \
  438. {R_PLL1RDIV, r1}, \
  439. {R_PLL1ODIV, o1}, \
  440. {R_PLL1FDIVL, f1l}, \
  441. {R_PLL1FDIVH, f1h}, \
  442. {R_PLL2CTL, c2}, \
  443. {R_PLL2RDIV, r2}, \
  444. {R_PLL2ODIV, o2}, \
  445. {R_PLL2FDIVL, f2l}, \
  446. {R_PLL2FDIVH, f2h}, \
  447. {R_TIMEBASE, t}, \
  448. }, \
  449. }
  450. static const struct pll_ctl pll_ctls[] = {
  451. PLL_CTL(1411200, 0x05,
  452. 0xB9, 0x07, 0x02, 0xC3, 0x04,
  453. 0x5A, 0x02, 0x03, 0xE0, 0x01),
  454. PLL_CTL(1536000, 0x05,
  455. 0x5A, 0x02, 0x03, 0xE0, 0x01,
  456. 0x5A, 0x02, 0x03, 0xB9, 0x01),
  457. PLL_CTL(2822400, 0x0A,
  458. 0x63, 0x07, 0x04, 0xC3, 0x04,
  459. 0x62, 0x07, 0x03, 0x48, 0x03),
  460. PLL_CTL(3072000, 0x0B,
  461. 0x62, 0x07, 0x03, 0x48, 0x03,
  462. 0x5A, 0x04, 0x03, 0xB9, 0x01),
  463. PLL_CTL(5644800, 0x15,
  464. 0x63, 0x0E, 0x04, 0xC3, 0x04,
  465. 0x5A, 0x08, 0x03, 0xE0, 0x01),
  466. PLL_CTL(6144000, 0x17,
  467. 0x5A, 0x08, 0x03, 0xE0, 0x01,
  468. 0x5A, 0x08, 0x03, 0xB9, 0x01),
  469. PLL_CTL(12000000, 0x2E,
  470. 0x5B, 0x19, 0x03, 0x00, 0x03,
  471. 0x6A, 0x19, 0x05, 0x98, 0x04),
  472. PLL_CTL(19200000, 0x4A,
  473. 0x53, 0x14, 0x03, 0x80, 0x01,
  474. 0x5A, 0x19, 0x03, 0xB9, 0x01),
  475. PLL_CTL(22000000, 0x55,
  476. 0x6A, 0x37, 0x05, 0x00, 0x06,
  477. 0x62, 0x26, 0x03, 0x49, 0x02),
  478. PLL_CTL(22579200, 0x57,
  479. 0x62, 0x31, 0x03, 0x20, 0x03,
  480. 0x53, 0x1D, 0x03, 0xB3, 0x01),
  481. PLL_CTL(24000000, 0x5D,
  482. 0x53, 0x19, 0x03, 0x80, 0x01,
  483. 0x5B, 0x19, 0x05, 0x4C, 0x02),
  484. PLL_CTL(24576000, 0x5F,
  485. 0x53, 0x1D, 0x03, 0xB3, 0x01,
  486. 0x62, 0x40, 0x03, 0x72, 0x03),
  487. PLL_CTL(27000000, 0x68,
  488. 0x62, 0x4B, 0x03, 0x00, 0x04,
  489. 0x6A, 0x7D, 0x03, 0x20, 0x06),
  490. PLL_CTL(36000000, 0x8C,
  491. 0x5B, 0x4B, 0x03, 0x00, 0x03,
  492. 0x6A, 0x7D, 0x03, 0x98, 0x04),
  493. PLL_CTL(11289600, 0x2B,
  494. 0x6A, 0x31, 0x03, 0x40, 0x06,
  495. 0x5A, 0x12, 0x03, 0x1C, 0x02),
  496. PLL_CTL(26000000, 0x65,
  497. 0x63, 0x41, 0x05, 0x00, 0x06,
  498. 0x5A, 0x26, 0x03, 0xEF, 0x01),
  499. PLL_CTL(12288000, 0x2F,
  500. 0x5A, 0x12, 0x03, 0x1C, 0x02,
  501. 0x62, 0x20, 0x03, 0x72, 0x03),
  502. PLL_CTL(40000000, 0x9B,
  503. 0xA2, 0x7D, 0x03, 0x80, 0x04,
  504. 0x63, 0x7D, 0x05, 0xE4, 0x06),
  505. PLL_CTL(512000, 0x01,
  506. 0x62, 0x01, 0x03, 0xD0, 0x02,
  507. 0x5B, 0x01, 0x04, 0x72, 0x03),
  508. PLL_CTL(705600, 0x02,
  509. 0x62, 0x02, 0x03, 0x15, 0x04,
  510. 0x62, 0x01, 0x04, 0x80, 0x02),
  511. PLL_CTL(1024000, 0x03,
  512. 0x62, 0x02, 0x03, 0xD0, 0x02,
  513. 0x5B, 0x02, 0x04, 0x72, 0x03),
  514. PLL_CTL(2048000, 0x07,
  515. 0x62, 0x04, 0x03, 0xD0, 0x02,
  516. 0x5B, 0x04, 0x04, 0x72, 0x03),
  517. PLL_CTL(2400000, 0x08,
  518. 0x62, 0x05, 0x03, 0x00, 0x03,
  519. 0x63, 0x05, 0x05, 0x98, 0x04),
  520. };
  521. static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
  522. {
  523. int i;
  524. struct pll_ctl const *pll_ctl = NULL;
  525. for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
  526. if (pll_ctls[i].freq_in == freq_in) {
  527. pll_ctl = &pll_ctls[i];
  528. break;
  529. }
  530. return pll_ctl;
  531. }
  532. enum {
  533. PLL_INPUT_XTAL = 0,
  534. PLL_INPUT_MCLK1,
  535. PLL_INPUT_MCLK2,
  536. PLL_INPUT_BCLK,
  537. };
  538. static int set_sysclk(struct snd_soc_component *component)
  539. {
  540. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  541. struct pll_ctl const *pll_ctl;
  542. unsigned long freq;
  543. int i;
  544. int ret;
  545. if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
  546. freq = clk_get_rate(tscs454->sysclk);
  547. else
  548. freq = tscs454->bclk_freq;
  549. pll_ctl = get_pll_ctl(freq);
  550. if (!pll_ctl) {
  551. ret = -EINVAL;
  552. dev_err(component->dev,
  553. "Invalid PLL input %lu (%d)\n", freq, ret);
  554. return ret;
  555. }
  556. for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
  557. ret = snd_soc_component_write(component,
  558. pll_ctl->settings[i].addr,
  559. pll_ctl->settings[i].val);
  560. if (ret < 0) {
  561. dev_err(component->dev,
  562. "Failed to set pll setting (%d)\n",
  563. ret);
  564. return ret;
  565. }
  566. }
  567. return 0;
  568. }
  569. static inline void reserve_pll(struct pll *pll)
  570. {
  571. mutex_lock(&pll->lock);
  572. pll->users++;
  573. mutex_unlock(&pll->lock);
  574. }
  575. static inline void free_pll(struct pll *pll)
  576. {
  577. mutex_lock(&pll->lock);
  578. pll->users--;
  579. mutex_unlock(&pll->lock);
  580. }
  581. static int pll_connected(struct snd_soc_dapm_widget *source,
  582. struct snd_soc_dapm_widget *sink)
  583. {
  584. struct snd_soc_component *component =
  585. snd_soc_dapm_to_component(source->dapm);
  586. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  587. int users;
  588. if (strstr(source->name, "PLL 1")) {
  589. mutex_lock(&tscs454->pll1.lock);
  590. users = tscs454->pll1.users;
  591. mutex_unlock(&tscs454->pll1.lock);
  592. dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
  593. users);
  594. } else {
  595. mutex_lock(&tscs454->pll2.lock);
  596. users = tscs454->pll2.users;
  597. mutex_unlock(&tscs454->pll2.lock);
  598. dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
  599. users);
  600. }
  601. return users;
  602. }
  603. /*
  604. * PLL must be enabled after power up and must be disabled before power down
  605. * for proper clock switching.
  606. */
  607. static int pll_power_event(struct snd_soc_dapm_widget *w,
  608. struct snd_kcontrol *kcontrol, int event)
  609. {
  610. struct snd_soc_component *component =
  611. snd_soc_dapm_to_component(w->dapm);
  612. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  613. bool enable;
  614. bool pll1;
  615. unsigned int msk;
  616. unsigned int val;
  617. int ret;
  618. if (strstr(w->name, "PLL 1"))
  619. pll1 = true;
  620. else
  621. pll1 = false;
  622. msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
  623. if (event == SND_SOC_DAPM_POST_PMU)
  624. enable = true;
  625. else
  626. enable = false;
  627. if (enable)
  628. val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
  629. else
  630. val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE;
  631. ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
  632. if (ret < 0) {
  633. dev_err(component->dev, "Failed to %s PLL %d (%d)\n",
  634. enable ? "enable" : "disable",
  635. pll1 ? 1 : 2,
  636. ret);
  637. return ret;
  638. }
  639. if (enable) {
  640. msleep(20); // Wait for lock
  641. ret = coeff_ram_sync(component, tscs454);
  642. if (ret < 0) {
  643. dev_err(component->dev,
  644. "Failed to sync coeff ram (%d)\n", ret);
  645. return ret;
  646. }
  647. }
  648. return 0;
  649. }
  650. static inline int aif_set_master(struct snd_soc_component *component,
  651. unsigned int aif_id, bool master)
  652. {
  653. unsigned int reg;
  654. unsigned int mask;
  655. unsigned int val;
  656. int ret;
  657. switch (aif_id) {
  658. case TSCS454_DAI1_ID:
  659. reg = R_I2SP1CTL;
  660. break;
  661. case TSCS454_DAI2_ID:
  662. reg = R_I2SP2CTL;
  663. break;
  664. case TSCS454_DAI3_ID:
  665. reg = R_I2SP3CTL;
  666. break;
  667. default:
  668. ret = -ENODEV;
  669. dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
  670. return ret;
  671. }
  672. mask = FM_I2SPCTL_PORTMS;
  673. val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
  674. ret = snd_soc_component_update_bits(component, reg, mask, val);
  675. if (ret < 0) {
  676. dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
  677. aif_id, master ? "master" : "slave", ret);
  678. return ret;
  679. }
  680. return 0;
  681. }
  682. static inline
  683. int aif_prepare(struct snd_soc_component *component, struct aif *aif)
  684. {
  685. int ret;
  686. ret = aif_set_master(component, aif->id, aif->master);
  687. if (ret < 0)
  688. return ret;
  689. return 0;
  690. }
  691. static inline int aif_free(struct snd_soc_component *component,
  692. struct aif *aif, bool playback)
  693. {
  694. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  695. mutex_lock(&tscs454->aifs_status_lock);
  696. dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
  697. set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
  698. dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
  699. aif->id, tscs454->aifs_status.streams);
  700. if (!aif_active(&tscs454->aifs_status, aif->id)) {
  701. /* Do config in slave mode */
  702. aif_set_master(component, aif->id, false);
  703. dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
  704. aif->pll->id, aif->id);
  705. free_pll(aif->pll);
  706. }
  707. if (!aifs_active(&tscs454->aifs_status)) {
  708. dev_dbg(component->dev, "Freeing pll %d from ir\n",
  709. tscs454->internal_rate.pll->id);
  710. free_pll(tscs454->internal_rate.pll);
  711. }
  712. mutex_unlock(&tscs454->aifs_status_lock);
  713. return 0;
  714. }
  715. /* R_PLLCTL PG 0 ADDR 0x15 */
  716. static char const * const bclk_sel_txt[] = {
  717. "BCLK 1", "BCLK 2", "BCLK 3"};
  718. static struct soc_enum const bclk_sel_enum =
  719. SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
  720. ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
  721. /* R_ISRC PG 0 ADDR 0x16 */
  722. static char const * const isrc_br_txt[] = {
  723. "44.1kHz", "48kHz"};
  724. static struct soc_enum const isrc_br_enum =
  725. SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
  726. ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
  727. static char const * const isrc_bm_txt[] = {
  728. "0.25x", "0.5x", "1.0x", "2.0x"};
  729. static struct soc_enum const isrc_bm_enum =
  730. SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
  731. ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
  732. /* R_SCLKCTL PG 0 ADDR 0x18 */
  733. static char const * const modular_rate_txt[] = {
  734. "Reserved", "Half", "Full", "Auto",};
  735. static struct soc_enum const adc_modular_rate_enum =
  736. SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
  737. ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
  738. static struct soc_enum const dac_modular_rate_enum =
  739. SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
  740. ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
  741. /* R_I2SIDCTL PG 0 ADDR 0x38 */
  742. static char const * const data_ctrl_txt[] = {
  743. "L/R", "L/L", "R/R", "R/L"};
  744. static struct soc_enum const data_in_ctrl_enums[] = {
  745. SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
  746. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  747. SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
  748. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  749. SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
  750. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  751. };
  752. /* R_I2SODCTL PG 0 ADDR 0x39 */
  753. static struct soc_enum const data_out_ctrl_enums[] = {
  754. SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
  755. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  756. SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
  757. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  758. SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
  759. ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
  760. };
  761. /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
  762. static char const * const asrc_mux_txt[] = {
  763. "None", "DAI 1", "DAI 2", "DAI 3"};
  764. static struct soc_enum const asrc_in_mux_enum =
  765. SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
  766. ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
  767. static char const * const dai_mux_txt[] = {
  768. "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
  769. "DMic 2", "ClassD", "DAC", "Sub"};
  770. static struct soc_enum const dai2_mux_enum =
  771. SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
  772. ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
  773. static struct snd_kcontrol_new const dai2_mux_dapm_enum =
  774. SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum);
  775. static struct soc_enum const dai1_mux_enum =
  776. SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
  777. ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
  778. static struct snd_kcontrol_new const dai1_mux_dapm_enum =
  779. SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
  780. /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
  781. static struct soc_enum const asrc_out_mux_enum =
  782. SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
  783. ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
  784. static struct soc_enum const dac_mux_enum =
  785. SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
  786. ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
  787. static struct snd_kcontrol_new const dac_mux_dapm_enum =
  788. SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
  789. static struct soc_enum const dai3_mux_enum =
  790. SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
  791. ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
  792. static struct snd_kcontrol_new const dai3_mux_dapm_enum =
  793. SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
  794. /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
  795. static char const * const sub_mux_txt[] = {
  796. "CH 0", "CH 1", "CH 0 + 1",
  797. "CH 2", "CH 3", "CH 2 + 3",
  798. "CH 4", "CH 5", "CH 4 + 5",
  799. "ADC/DMic 1 Left", "ADC/DMic 1 Right",
  800. "ADC/DMic 1 Left Plus Right",
  801. "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
  802. "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
  803. static struct soc_enum const sub_mux_enum =
  804. SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
  805. ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
  806. static struct snd_kcontrol_new const sub_mux_dapm_enum =
  807. SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
  808. static struct soc_enum const classd_mux_enum =
  809. SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
  810. ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
  811. static struct snd_kcontrol_new const classd_mux_dapm_enum =
  812. SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
  813. /* R_HSDCTL1 PG 1 ADDR 0x01 */
  814. static char const * const jack_type_txt[] = {
  815. "3 Terminal", "4 Terminal"};
  816. static struct soc_enum const hp_jack_type_enum =
  817. SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
  818. ARRAY_SIZE(jack_type_txt), jack_type_txt);
  819. static char const * const hs_det_pol_txt[] = {
  820. "Rising", "Falling"};
  821. static struct soc_enum const hs_det_pol_enum =
  822. SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
  823. ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
  824. /* R_HSDCTL1 PG 1 ADDR 0x02 */
  825. static char const * const hs_mic_bias_force_txt[] = {
  826. "Off", "Ring", "Sleeve"};
  827. static struct soc_enum const hs_mic_bias_force_enum =
  828. SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
  829. ARRAY_SIZE(hs_mic_bias_force_txt),
  830. hs_mic_bias_force_txt);
  831. static char const * const plug_type_txt[] = {
  832. "OMTP", "CTIA", "Reserved", "Headphone"};
  833. static struct soc_enum const plug_type_force_enum =
  834. SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
  835. ARRAY_SIZE(plug_type_txt), plug_type_txt);
  836. /* R_CH0AIC PG 1 ADDR 0x06 */
  837. static char const * const in_bst_mux_txt[] = {
  838. "Input 1", "Input 2", "Input 3", "D2S"};
  839. static struct soc_enum const in_bst_mux_ch0_enum =
  840. SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
  841. ARRAY_SIZE(in_bst_mux_txt),
  842. in_bst_mux_txt);
  843. static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
  844. SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
  845. in_bst_mux_ch0_enum);
  846. static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
  847. static char const * const adc_mux_txt[] = {
  848. "Input 1 Boost Bypass", "Input 2 Boost Bypass",
  849. "Input 3 Boost Bypass", "Input Boost"};
  850. static struct soc_enum const adc_mux_ch0_enum =
  851. SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
  852. ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
  853. static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
  854. SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
  855. static char const * const in_proc_mux_txt[] = {
  856. "ADC", "DMic"};
  857. static struct soc_enum const in_proc_ch0_enum =
  858. SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
  859. ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
  860. static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
  861. SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
  862. in_proc_ch0_enum);
  863. /* R_CH1AIC PG 1 ADDR 0x07 */
  864. static struct soc_enum const in_bst_mux_ch1_enum =
  865. SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
  866. ARRAY_SIZE(in_bst_mux_txt),
  867. in_bst_mux_txt);
  868. static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
  869. SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
  870. in_bst_mux_ch1_enum);
  871. static struct soc_enum const adc_mux_ch1_enum =
  872. SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
  873. ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
  874. static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
  875. SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
  876. static struct soc_enum const in_proc_ch1_enum =
  877. SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
  878. ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
  879. static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
  880. SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
  881. in_proc_ch1_enum);
  882. /* R_ICTL0 PG 1 ADDR 0x0A */
  883. static char const * const pol_txt[] = {
  884. "Normal", "Invert"};
  885. static struct soc_enum const in_pol_ch1_enum =
  886. SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
  887. ARRAY_SIZE(pol_txt), pol_txt);
  888. static struct soc_enum const in_pol_ch0_enum =
  889. SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
  890. ARRAY_SIZE(pol_txt), pol_txt);
  891. static char const * const in_proc_ch_sel_txt[] = {
  892. "Normal", "Mono Mix to Channel 0",
  893. "Mono Mix to Channel 1", "Add"};
  894. static struct soc_enum const in_proc_ch01_sel_enum =
  895. SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
  896. ARRAY_SIZE(in_proc_ch_sel_txt),
  897. in_proc_ch_sel_txt);
  898. /* R_ICTL1 PG 1 ADDR 0x0B */
  899. static struct soc_enum const in_pol_ch3_enum =
  900. SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
  901. ARRAY_SIZE(pol_txt), pol_txt);
  902. static struct soc_enum const in_pol_ch2_enum =
  903. SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
  904. ARRAY_SIZE(pol_txt), pol_txt);
  905. static struct soc_enum const in_proc_ch23_sel_enum =
  906. SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
  907. ARRAY_SIZE(in_proc_ch_sel_txt),
  908. in_proc_ch_sel_txt);
  909. /* R_MICBIAS PG 1 ADDR 0x0C */
  910. static char const * const mic_bias_txt[] = {
  911. "2.5V", "2.1V", "1.8V", "Vdd"};
  912. static struct soc_enum const mic_bias_2_enum =
  913. SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
  914. ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
  915. static struct soc_enum const mic_bias_1_enum =
  916. SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
  917. ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
  918. /* R_PGACTL0 PG 1 ADDR 0x0D */
  919. /* R_PGACTL1 PG 1 ADDR 0x0E */
  920. /* R_PGACTL2 PG 1 ADDR 0x0F */
  921. /* R_PGACTL3 PG 1 ADDR 0x10 */
  922. static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
  923. /* R_ICH0VOL PG1 ADDR 0x12 */
  924. /* R_ICH1VOL PG1 ADDR 0x13 */
  925. /* R_ICH2VOL PG1 ADDR 0x14 */
  926. /* R_ICH3VOL PG1 ADDR 0x15 */
  927. static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
  928. /* R_ASRCILVOL PG1 ADDR 0x16 */
  929. /* R_ASRCIRVOL PG1 ADDR 0x17 */
  930. /* R_ASRCOLVOL PG1 ADDR 0x18 */
  931. /* R_ASRCORVOL PG1 ADDR 0x19 */
  932. static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
  933. /* R_ALCCTL0 PG1 ADDR 0x1D */
  934. static char const * const alc_mode_txt[] = {
  935. "ALC", "Limiter"};
  936. static struct soc_enum const alc_mode_enum =
  937. SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
  938. ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
  939. static char const * const alc_ref_text[] = {
  940. "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
  941. static struct soc_enum const alc_ref_enum =
  942. SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
  943. ARRAY_SIZE(alc_ref_text), alc_ref_text);
  944. /* R_ALCCTL1 PG 1 ADDR 0x1E */
  945. static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
  946. static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
  947. /* R_ALCCTL2 PG 1 ADDR 0x1F */
  948. static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
  949. /* R_NGATE PG 1 ADDR 0x21 */
  950. static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
  951. static char const * const ngate_type_txt[] = {
  952. "PGA Constant", "ADC Mute"};
  953. static struct soc_enum const ngate_type_enum =
  954. SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
  955. ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
  956. /* R_DMICCTL PG 1 ADDR 0x22 */
  957. static char const * const dmic_mono_sel_txt[] = {
  958. "Stereo", "Mono"};
  959. static struct soc_enum const dmic_mono_sel_enum =
  960. SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
  961. ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
  962. /* R_DACCTL PG 2 ADDR 0x01 */
  963. static struct soc_enum const dac_pol_r_enum =
  964. SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
  965. ARRAY_SIZE(pol_txt), pol_txt);
  966. static struct soc_enum const dac_pol_l_enum =
  967. SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
  968. ARRAY_SIZE(pol_txt), pol_txt);
  969. static char const * const dac_dith_txt[] = {
  970. "Half", "Full", "Disabled", "Static"};
  971. static struct soc_enum const dac_dith_enum =
  972. SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
  973. ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
  974. /* R_SPKCTL PG 2 ADDR 0x02 */
  975. static struct soc_enum const spk_pol_r_enum =
  976. SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
  977. ARRAY_SIZE(pol_txt), pol_txt);
  978. static struct soc_enum const spk_pol_l_enum =
  979. SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
  980. ARRAY_SIZE(pol_txt), pol_txt);
  981. /* R_SUBCTL PG 2 ADDR 0x03 */
  982. static struct soc_enum const sub_pol_enum =
  983. SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
  984. ARRAY_SIZE(pol_txt), pol_txt);
  985. /* R_MVOLL PG 2 ADDR 0x08 */
  986. /* R_MVOLR PG 2 ADDR 0x09 */
  987. static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
  988. /* R_HPVOLL PG 2 ADDR 0x0A */
  989. /* R_HPVOLR PG 2 ADDR 0x0B */
  990. static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
  991. /* R_SPKVOLL PG 2 ADDR 0x0C */
  992. /* R_SPKVOLR PG 2 ADDR 0x0D */
  993. static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
  994. /* R_SPKEQFILT PG 3 ADDR 0x01 */
  995. static char const * const eq_txt[] = {
  996. "Pre Scale",
  997. "Pre Scale + EQ Band 0",
  998. "Pre Scale + EQ Band 0 - 1",
  999. "Pre Scale + EQ Band 0 - 2",
  1000. "Pre Scale + EQ Band 0 - 3",
  1001. "Pre Scale + EQ Band 0 - 4",
  1002. "Pre Scale + EQ Band 0 - 5",
  1003. };
  1004. static struct soc_enum const spk_eq_enums[] = {
  1005. SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
  1006. ARRAY_SIZE(eq_txt), eq_txt),
  1007. SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
  1008. ARRAY_SIZE(eq_txt), eq_txt),
  1009. };
  1010. /* R_SPKMBCCTL PG 3 ADDR 0x0B */
  1011. static char const * const lvl_mode_txt[] = {
  1012. "Average", "Peak"};
  1013. static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
  1014. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
  1015. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1016. static char const * const win_sel_txt[] = {
  1017. "512", "64"};
  1018. static struct soc_enum const spk_mbc3_win_sel_enum =
  1019. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
  1020. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1021. static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
  1022. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
  1023. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1024. static struct soc_enum const spk_mbc2_win_sel_enum =
  1025. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
  1026. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1027. static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
  1028. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
  1029. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1030. static struct soc_enum const spk_mbc1_win_sel_enum =
  1031. SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
  1032. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1033. /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
  1034. static struct soc_enum const spk_mbc1_phase_pol_enum =
  1035. SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
  1036. ARRAY_SIZE(pol_txt), pol_txt);
  1037. static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
  1038. /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
  1039. static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
  1040. /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
  1041. static char const * const comp_rat_txt[] = {
  1042. "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
  1043. "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
  1044. "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
  1045. static struct soc_enum const spk_mbc1_comp_rat_enum =
  1046. SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
  1047. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1048. /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
  1049. static struct soc_enum const spk_mbc2_phase_pol_enum =
  1050. SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
  1051. ARRAY_SIZE(pol_txt), pol_txt);
  1052. /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
  1053. static struct soc_enum const spk_mbc2_comp_rat_enum =
  1054. SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
  1055. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1056. /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
  1057. static struct soc_enum const spk_mbc3_phase_pol_enum =
  1058. SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
  1059. ARRAY_SIZE(pol_txt), pol_txt);
  1060. /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
  1061. static struct soc_enum const spk_mbc3_comp_rat_enum =
  1062. SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
  1063. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1064. /* R_SPKCLECTL PG 3 ADDR 0x21 */
  1065. static struct soc_enum const spk_cle_lvl_mode_enum =
  1066. SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
  1067. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1068. static struct soc_enum const spk_cle_win_sel_enum =
  1069. SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
  1070. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1071. /* R_SPKCLEMUG PG 3 ADDR 0x22 */
  1072. static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
  1073. /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
  1074. static struct soc_enum const spk_comp_rat_enum =
  1075. SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
  1076. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1077. /* R_SPKEXPTHR PG 3 ADDR 0x2F */
  1078. static char const * const exp_rat_txt[] = {
  1079. "Reserved", "Reserved", "1:2", "1:3",
  1080. "1:4", "1:5", "1:6", "1:7"};
  1081. static struct soc_enum const spk_exp_rat_enum =
  1082. SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
  1083. ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
  1084. /* R_DACEQFILT PG 4 ADDR 0x01 */
  1085. static struct soc_enum const dac_eq_enums[] = {
  1086. SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
  1087. ARRAY_SIZE(eq_txt), eq_txt),
  1088. SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
  1089. ARRAY_SIZE(eq_txt), eq_txt),
  1090. };
  1091. /* R_DACMBCCTL PG 4 ADDR 0x0B */
  1092. static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
  1093. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
  1094. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1095. static struct soc_enum const dac_mbc3_win_sel_enum =
  1096. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
  1097. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1098. static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
  1099. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
  1100. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1101. static struct soc_enum const dac_mbc2_win_sel_enum =
  1102. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
  1103. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1104. static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
  1105. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
  1106. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1107. static struct soc_enum const dac_mbc1_win_sel_enum =
  1108. SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
  1109. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1110. /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
  1111. static struct soc_enum const dac_mbc1_phase_pol_enum =
  1112. SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
  1113. ARRAY_SIZE(pol_txt), pol_txt);
  1114. /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
  1115. static struct soc_enum const dac_mbc1_comp_rat_enum =
  1116. SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
  1117. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1118. /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
  1119. static struct soc_enum const dac_mbc2_phase_pol_enum =
  1120. SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
  1121. ARRAY_SIZE(pol_txt), pol_txt);
  1122. /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
  1123. static struct soc_enum const dac_mbc2_comp_rat_enum =
  1124. SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
  1125. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1126. /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
  1127. static struct soc_enum const dac_mbc3_phase_pol_enum =
  1128. SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
  1129. ARRAY_SIZE(pol_txt), pol_txt);
  1130. /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
  1131. static struct soc_enum const dac_mbc3_comp_rat_enum =
  1132. SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
  1133. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1134. /* R_DACCLECTL PG 4 ADDR 0x21 */
  1135. static struct soc_enum const dac_cle_lvl_mode_enum =
  1136. SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
  1137. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1138. static struct soc_enum const dac_cle_win_sel_enum =
  1139. SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
  1140. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1141. /* R_DACCOMPRAT PG 4 ADDR 0x24 */
  1142. static struct soc_enum const dac_comp_rat_enum =
  1143. SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
  1144. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1145. /* R_DACEXPRAT PG 4 ADDR 0x30 */
  1146. static struct soc_enum const dac_exp_rat_enum =
  1147. SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
  1148. ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
  1149. /* R_SUBEQFILT PG 5 ADDR 0x01 */
  1150. static struct soc_enum const sub_eq_enums[] = {
  1151. SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
  1152. ARRAY_SIZE(eq_txt), eq_txt),
  1153. SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
  1154. ARRAY_SIZE(eq_txt), eq_txt),
  1155. };
  1156. /* R_SUBMBCCTL PG 5 ADDR 0x0B */
  1157. static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
  1158. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
  1159. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1160. static struct soc_enum const sub_mbc3_win_sel_enum =
  1161. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
  1162. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1163. static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
  1164. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
  1165. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1166. static struct soc_enum const sub_mbc2_win_sel_enum =
  1167. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
  1168. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1169. static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
  1170. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
  1171. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1172. static struct soc_enum const sub_mbc1_win_sel_enum =
  1173. SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
  1174. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1175. /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
  1176. static struct soc_enum const sub_mbc1_phase_pol_enum =
  1177. SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
  1178. ARRAY_SIZE(pol_txt), pol_txt);
  1179. /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
  1180. static struct soc_enum const sub_mbc1_comp_rat_enum =
  1181. SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
  1182. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1183. /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
  1184. static struct soc_enum const sub_mbc2_phase_pol_enum =
  1185. SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
  1186. ARRAY_SIZE(pol_txt), pol_txt);
  1187. /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
  1188. static struct soc_enum const sub_mbc2_comp_rat_enum =
  1189. SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
  1190. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1191. /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
  1192. static struct soc_enum const sub_mbc3_phase_pol_enum =
  1193. SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
  1194. ARRAY_SIZE(pol_txt), pol_txt);
  1195. /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
  1196. static struct soc_enum const sub_mbc3_comp_rat_enum =
  1197. SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
  1198. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1199. /* R_SUBCLECTL PG 5 ADDR 0x21 */
  1200. static struct soc_enum const sub_cle_lvl_mode_enum =
  1201. SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
  1202. ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
  1203. static struct soc_enum const sub_cle_win_sel_enum =
  1204. SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
  1205. ARRAY_SIZE(win_sel_txt), win_sel_txt);
  1206. /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
  1207. static struct soc_enum const sub_comp_rat_enum =
  1208. SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
  1209. ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
  1210. /* R_SUBEXPRAT PG 5 ADDR 0x30 */
  1211. static struct soc_enum const sub_exp_rat_enum =
  1212. SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
  1213. ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
  1214. static int bytes_info_ext(struct snd_kcontrol *kcontrol,
  1215. struct snd_ctl_elem_info *ucontrol)
  1216. {
  1217. struct coeff_ram_ctl *ctl =
  1218. (struct coeff_ram_ctl *)kcontrol->private_value;
  1219. struct soc_bytes_ext *params = &ctl->bytes_ext;
  1220. ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1221. ucontrol->count = params->max;
  1222. return 0;
  1223. }
  1224. /* CH 0_1 Input Mux */
  1225. static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
  1226. static struct soc_enum const ch_0_1_mux_enum =
  1227. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1228. ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
  1229. static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
  1230. SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
  1231. /* CH 2_3 Input Mux */
  1232. static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
  1233. static struct soc_enum const ch_2_3_mux_enum =
  1234. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1235. ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
  1236. static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
  1237. SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
  1238. /* CH 4_5 Input Mux */
  1239. static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
  1240. static struct soc_enum const ch_4_5_mux_enum =
  1241. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
  1242. ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
  1243. static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
  1244. SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
  1245. #define COEFF_RAM_CTL(xname, xcount, xaddr) \
  1246. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1247. .info = bytes_info_ext, \
  1248. .get = coeff_ram_get, .put = coeff_ram_put, \
  1249. .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
  1250. .addr = xaddr, \
  1251. .bytes_ext = {.max = xcount, }, \
  1252. } \
  1253. }
  1254. static struct snd_kcontrol_new const tscs454_snd_controls[] = {
  1255. /* R_PLLCTL PG 0 ADDR 0x15 */
  1256. SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
  1257. /* R_ISRC PG 0 ADDR 0x16 */
  1258. SOC_ENUM("Internal Rate", isrc_br_enum),
  1259. SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
  1260. /* R_SCLKCTL PG 0 ADDR 0x18 */
  1261. SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
  1262. SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
  1263. /* R_ASRC PG 0 ADDR 0x28 */
  1264. SOC_SINGLE("ASRC Out High Bandwidth Switch",
  1265. R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
  1266. SOC_SINGLE("ASRC In High Bandwidth Switch",
  1267. R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
  1268. /* R_I2SIDCTL PG 0 ADDR 0x38 */
  1269. SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
  1270. SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
  1271. SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
  1272. /* R_I2SODCTL PG 0 ADDR 0x39 */
  1273. SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
  1274. SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
  1275. SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
  1276. /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
  1277. SOC_ENUM("ASRC In", asrc_in_mux_enum),
  1278. /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
  1279. SOC_ENUM("ASRC Out", asrc_out_mux_enum),
  1280. /* R_HSDCTL1 PG 1 ADDR 0x01 */
  1281. SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
  1282. SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
  1283. SOC_SINGLE("Headphone Detection Switch",
  1284. R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
  1285. SOC_SINGLE("Headset OMTP/CTIA Switch",
  1286. R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
  1287. /* R_HSDCTL1 PG 1 ADDR 0x02 */
  1288. SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
  1289. SOC_SINGLE("Manual Mic Bias Switch",
  1290. R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
  1291. SOC_SINGLE("Ring/Sleeve Auto Switch",
  1292. R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
  1293. SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
  1294. /* R_CH0AIC PG 1 ADDR 0x06 */
  1295. SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
  1296. FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
  1297. /* R_CH1AIC PG 1 ADDR 0x07 */
  1298. SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
  1299. FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
  1300. /* R_CH2AIC PG 1 ADDR 0x08 */
  1301. SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
  1302. FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
  1303. /* R_CH3AIC PG 1 ADDR 0x09 */
  1304. SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
  1305. FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
  1306. /* R_ICTL0 PG 1 ADDR 0x0A */
  1307. SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
  1308. SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
  1309. SOC_ENUM("Input Processor Channel 0/1 Operation",
  1310. in_proc_ch01_sel_enum),
  1311. SOC_SINGLE("Input Channel 1 Mute Switch",
  1312. R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
  1313. SOC_SINGLE("Input Channel 0 Mute Switch",
  1314. R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
  1315. SOC_SINGLE("Input Channel 1 HPF Disable Switch",
  1316. R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
  1317. SOC_SINGLE("Input Channel 0 HPF Disable Switch",
  1318. R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
  1319. /* R_ICTL1 PG 1 ADDR 0x0B */
  1320. SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
  1321. SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
  1322. SOC_ENUM("Input Processor Channel 2/3 Operation",
  1323. in_proc_ch23_sel_enum),
  1324. SOC_SINGLE("Input Channel 3 Mute Switch",
  1325. R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
  1326. SOC_SINGLE("Input Channel 2 Mute Switch",
  1327. R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
  1328. SOC_SINGLE("Input Channel 3 HPF Disable Switch",
  1329. R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
  1330. SOC_SINGLE("Input Channel 2 HPF Disable Switch",
  1331. R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
  1332. /* R_MICBIAS PG 1 ADDR 0x0C */
  1333. SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
  1334. SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
  1335. /* R_PGACTL0 PG 1 ADDR 0x0D */
  1336. SOC_SINGLE("Input Channel 0 PGA Mute Switch",
  1337. R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
  1338. SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
  1339. FB_PGACTL_PGAVOL,
  1340. FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
  1341. /* R_PGACTL1 PG 1 ADDR 0x0E */
  1342. SOC_SINGLE("Input Channel 1 PGA Mute Switch",
  1343. R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
  1344. SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
  1345. FB_PGACTL_PGAVOL,
  1346. FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
  1347. /* R_PGACTL2 PG 1 ADDR 0x0F */
  1348. SOC_SINGLE("Input Channel 2 PGA Mute Switch",
  1349. R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
  1350. SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
  1351. FB_PGACTL_PGAVOL,
  1352. FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
  1353. /* R_PGACTL3 PG 1 ADDR 0x10 */
  1354. SOC_SINGLE("Input Channel 3 PGA Mute Switch",
  1355. R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
  1356. SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
  1357. FB_PGACTL_PGAVOL,
  1358. FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
  1359. /* R_ICH0VOL PG 1 ADDR 0x12 */
  1360. SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
  1361. FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
  1362. /* R_ICH1VOL PG 1 ADDR 0x13 */
  1363. SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
  1364. FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
  1365. /* R_ICH2VOL PG 1 ADDR 0x14 */
  1366. SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
  1367. FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
  1368. /* R_ICH3VOL PG 1 ADDR 0x15 */
  1369. SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
  1370. FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
  1371. /* R_ASRCILVOL PG 1 ADDR 0x16 */
  1372. SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
  1373. FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
  1374. 0, asrc_vol_tlv_arr),
  1375. /* R_ASRCIRVOL PG 1 ADDR 0x17 */
  1376. SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
  1377. FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
  1378. 0, asrc_vol_tlv_arr),
  1379. /* R_ASRCOLVOL PG 1 ADDR 0x18 */
  1380. SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
  1381. FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
  1382. 0, asrc_vol_tlv_arr),
  1383. /* R_ASRCORVOL PG 1 ADDR 0x19 */
  1384. SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
  1385. FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
  1386. 0, asrc_vol_tlv_arr),
  1387. /* R_IVOLCTLU PG 1 ADDR 0x1C */
  1388. /* R_ALCCTL0 PG 1 ADDR 0x1D */
  1389. SOC_ENUM("ALC Mode", alc_mode_enum),
  1390. SOC_ENUM("ALC Reference", alc_ref_enum),
  1391. SOC_SINGLE("Input Channel 3 ALC Switch",
  1392. R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
  1393. SOC_SINGLE("Input Channel 2 ALC Switch",
  1394. R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
  1395. SOC_SINGLE("Input Channel 1 ALC Switch",
  1396. R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
  1397. SOC_SINGLE("Input Channel 0 ALC Switch",
  1398. R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
  1399. /* R_ALCCTL1 PG 1 ADDR 0x1E */
  1400. SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
  1401. FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
  1402. 0, alc_max_gain_tlv_arr),
  1403. SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
  1404. FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
  1405. 0, alc_target_tlv_arr),
  1406. /* R_ALCCTL2 PG 1 ADDR 0x1F */
  1407. SOC_SINGLE("ALC Zero Cross Switch",
  1408. R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
  1409. SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
  1410. FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
  1411. 0, alc_min_gain_tlv_arr),
  1412. SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
  1413. FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
  1414. /* R_ALCCTL3 PG 1 ADDR 0x20 */
  1415. SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
  1416. FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
  1417. SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
  1418. FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
  1419. /* R_NGATE PG 1 ADDR 0x21 */
  1420. SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
  1421. FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
  1422. SOC_ENUM("Noise Gate Type", ngate_type_enum),
  1423. SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
  1424. /* R_DMICCTL PG 1 ADDR 0x22 */
  1425. SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
  1426. SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
  1427. SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
  1428. /* R_DACCTL PG 2 ADDR 0x01 */
  1429. SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
  1430. SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
  1431. SOC_ENUM("DAC Dither", dac_dith_enum),
  1432. SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
  1433. SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
  1434. /* R_SPKCTL PG 2 ADDR 0x02 */
  1435. SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
  1436. SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
  1437. SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
  1438. SOC_SINGLE("Speaker De-Emphasis Switch",
  1439. R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
  1440. /* R_SUBCTL PG 2 ADDR 0x03 */
  1441. SOC_ENUM("Sub Polarity", sub_pol_enum),
  1442. SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
  1443. SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
  1444. /* R_DCCTL PG 2 ADDR 0x04 */
  1445. SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
  1446. SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
  1447. SOC_SINGLE("Speaker DC Removal Switch",
  1448. R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
  1449. SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
  1450. FM_DCCTL_DCCOEFSEL, 0),
  1451. /* R_OVOLCTLU PG 2 ADDR 0x06 */
  1452. SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
  1453. /* R_MVOLL PG 2 ADDR 0x08 */
  1454. /* R_MVOLR PG 2 ADDR 0x09 */
  1455. SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
  1456. FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
  1457. /* R_HPVOLL PG 2 ADDR 0x0A */
  1458. /* R_HPVOLR PG 2 ADDR 0x0B */
  1459. SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
  1460. FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
  1461. hp_vol_tlv_arr),
  1462. /* R_SPKVOLL PG 2 ADDR 0x0C */
  1463. /* R_SPKVOLR PG 2 ADDR 0x0D */
  1464. SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
  1465. FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
  1466. spk_vol_tlv_arr),
  1467. /* R_SUBVOL PG 2 ADDR 0x10 */
  1468. SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
  1469. FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
  1470. /* R_SPKEQFILT PG 3 ADDR 0x01 */
  1471. SOC_SINGLE("Speaker EQ 2 Switch",
  1472. R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
  1473. SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
  1474. SOC_SINGLE("Speaker EQ 1 Switch",
  1475. R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
  1476. SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
  1477. /* R_SPKMBCEN PG 3 ADDR 0x0A */
  1478. SOC_SINGLE("Speaker MBC 3 Switch",
  1479. R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
  1480. SOC_SINGLE("Speaker MBC 2 Switch",
  1481. R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
  1482. SOC_SINGLE("Speaker MBC 1 Switch",
  1483. R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
  1484. /* R_SPKMBCCTL PG 3 ADDR 0x0B */
  1485. SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
  1486. SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
  1487. SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
  1488. SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
  1489. SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
  1490. SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
  1491. /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
  1492. SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
  1493. SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
  1494. FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
  1495. 0, mbc_mug_tlv_arr),
  1496. /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
  1497. SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
  1498. R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
  1499. 0, thr_tlv_arr),
  1500. /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
  1501. SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
  1502. /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
  1503. /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
  1504. SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
  1505. /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
  1506. /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
  1507. SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
  1508. /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
  1509. SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
  1510. SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
  1511. FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
  1512. 0, mbc_mug_tlv_arr),
  1513. /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
  1514. SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
  1515. R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
  1516. 0, thr_tlv_arr),
  1517. /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
  1518. SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
  1519. /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
  1520. /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
  1521. SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
  1522. /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
  1523. /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
  1524. SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
  1525. /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
  1526. SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
  1527. SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
  1528. FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
  1529. 0, mbc_mug_tlv_arr),
  1530. /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
  1531. SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
  1532. FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
  1533. 0, thr_tlv_arr),
  1534. /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
  1535. SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
  1536. /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
  1537. /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
  1538. SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
  1539. /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
  1540. /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
  1541. SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
  1542. /* R_SPKCLECTL PG 3 ADDR 0x21 */
  1543. SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
  1544. SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
  1545. SOC_SINGLE("Speaker CLE Expander Switch",
  1546. R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
  1547. SOC_SINGLE("Speaker CLE Limiter Switch",
  1548. R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
  1549. SOC_SINGLE("Speaker CLE Compressor Switch",
  1550. R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
  1551. /* R_SPKCLEMUG PG 3 ADDR 0x22 */
  1552. SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
  1553. FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
  1554. 0, cle_mug_tlv_arr),
  1555. /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
  1556. SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
  1557. FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
  1558. 0, thr_tlv_arr),
  1559. /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
  1560. SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
  1561. /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
  1562. /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
  1563. SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
  1564. /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
  1565. /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
  1566. SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
  1567. /* R_SPKLIMTHR PG 3 ADDR 0x29 */
  1568. SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
  1569. FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
  1570. 0, thr_tlv_arr),
  1571. /* R_SPKLIMTGT PG 3 ADDR 0x2A */
  1572. SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
  1573. FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
  1574. 0, thr_tlv_arr),
  1575. /* R_SPKLIMATKL PG 3 ADDR 0x2B */
  1576. /* R_SPKLIMATKH PG 3 ADDR 0x2C */
  1577. SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
  1578. /* R_SPKLIMRELL PG 3 ADDR 0x2D */
  1579. /* R_SPKLIMRELR PG 3 ADDR 0x2E */
  1580. SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
  1581. /* R_SPKEXPTHR PG 3 ADDR 0x2F */
  1582. SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
  1583. FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
  1584. 0, thr_tlv_arr),
  1585. /* R_SPKEXPRAT PG 3 ADDR 0x30 */
  1586. SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
  1587. /* R_SPKEXPATKL PG 3 ADDR 0x31 */
  1588. /* R_SPKEXPATKR PG 3 ADDR 0x32 */
  1589. SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
  1590. /* R_SPKEXPRELL PG 3 ADDR 0x33 */
  1591. /* R_SPKEXPRELR PG 3 ADDR 0x34 */
  1592. SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
  1593. /* R_SPKFXCTL PG 3 ADDR 0x35 */
  1594. SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
  1595. SOC_SINGLE("Speaker Treble Enhancement Switch",
  1596. R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
  1597. SOC_SINGLE("Speaker Treble NLF Switch",
  1598. R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
  1599. SOC_SINGLE("Speaker Bass Enhancement Switch",
  1600. R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
  1601. SOC_SINGLE("Speaker Bass NLF Switch",
  1602. R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
  1603. /* R_DACEQFILT PG 4 ADDR 0x01 */
  1604. SOC_SINGLE("DAC EQ 2 Switch",
  1605. R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
  1606. SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
  1607. SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
  1608. SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
  1609. /* R_DACMBCEN PG 4 ADDR 0x0A */
  1610. SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
  1611. SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
  1612. SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
  1613. /* R_DACMBCCTL PG 4 ADDR 0x0B */
  1614. SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
  1615. SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
  1616. SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
  1617. SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
  1618. SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
  1619. SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
  1620. /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
  1621. SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
  1622. SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
  1623. FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
  1624. 0, mbc_mug_tlv_arr),
  1625. /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
  1626. SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
  1627. FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
  1628. 0, thr_tlv_arr),
  1629. /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
  1630. SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
  1631. /* R_DACMBCATK1L PG 4 ADDR 0x0F */
  1632. /* R_DACMBCATK1H PG 4 ADDR 0x10 */
  1633. SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
  1634. /* R_DACMBCREL1L PG 4 ADDR 0x11 */
  1635. /* R_DACMBCREL1H PG 4 ADDR 0x12 */
  1636. SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
  1637. /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
  1638. SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
  1639. SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
  1640. FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
  1641. 0, mbc_mug_tlv_arr),
  1642. /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
  1643. SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
  1644. FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
  1645. 0, thr_tlv_arr),
  1646. /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
  1647. SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
  1648. /* R_DACMBCATK2L PG 4 ADDR 0x16 */
  1649. /* R_DACMBCATK2H PG 4 ADDR 0x17 */
  1650. SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
  1651. /* R_DACMBCREL2L PG 4 ADDR 0x18 */
  1652. /* R_DACMBCREL2H PG 4 ADDR 0x19 */
  1653. SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
  1654. /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
  1655. SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
  1656. SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
  1657. FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
  1658. 0, mbc_mug_tlv_arr),
  1659. /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
  1660. SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
  1661. FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
  1662. 0, thr_tlv_arr),
  1663. /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
  1664. SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
  1665. /* R_DACMBCATK3L PG 4 ADDR 0x1D */
  1666. /* R_DACMBCATK3H PG 4 ADDR 0x1E */
  1667. SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
  1668. /* R_DACMBCREL3L PG 4 ADDR 0x1F */
  1669. /* R_DACMBCREL3H PG 4 ADDR 0x20 */
  1670. SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
  1671. /* R_DACCLECTL PG 4 ADDR 0x21 */
  1672. SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
  1673. SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
  1674. SOC_SINGLE("DAC CLE Expander Switch",
  1675. R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
  1676. SOC_SINGLE("DAC CLE Limiter Switch",
  1677. R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
  1678. SOC_SINGLE("DAC CLE Compressor Switch",
  1679. R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
  1680. /* R_DACCLEMUG PG 4 ADDR 0x22 */
  1681. SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
  1682. FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
  1683. 0, cle_mug_tlv_arr),
  1684. /* R_DACCOMPTHR PG 4 ADDR 0x23 */
  1685. SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
  1686. FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
  1687. 0, thr_tlv_arr),
  1688. /* R_DACCOMPRAT PG 4 ADDR 0x24 */
  1689. SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
  1690. /* R_DACCOMPATKL PG 4 ADDR 0x25 */
  1691. /* R_DACCOMPATKH PG 4 ADDR 0x26 */
  1692. SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
  1693. /* R_DACCOMPRELL PG 4 ADDR 0x27 */
  1694. /* R_DACCOMPRELH PG 4 ADDR 0x28 */
  1695. SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
  1696. /* R_DACLIMTHR PG 4 ADDR 0x29 */
  1697. SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
  1698. FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
  1699. 0, thr_tlv_arr),
  1700. /* R_DACLIMTGT PG 4 ADDR 0x2A */
  1701. SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
  1702. FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
  1703. 0, thr_tlv_arr),
  1704. /* R_DACLIMATKL PG 4 ADDR 0x2B */
  1705. /* R_DACLIMATKH PG 4 ADDR 0x2C */
  1706. SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
  1707. /* R_DACLIMRELL PG 4 ADDR 0x2D */
  1708. /* R_DACLIMRELR PG 4 ADDR 0x2E */
  1709. SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
  1710. /* R_DACEXPTHR PG 4 ADDR 0x2F */
  1711. SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
  1712. FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
  1713. 0, thr_tlv_arr),
  1714. /* R_DACEXPRAT PG 4 ADDR 0x30 */
  1715. SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
  1716. /* R_DACEXPATKL PG 4 ADDR 0x31 */
  1717. /* R_DACEXPATKR PG 4 ADDR 0x32 */
  1718. SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
  1719. /* R_DACEXPRELL PG 4 ADDR 0x33 */
  1720. /* R_DACEXPRELR PG 4 ADDR 0x34 */
  1721. SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
  1722. /* R_DACFXCTL PG 4 ADDR 0x35 */
  1723. SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
  1724. SOC_SINGLE("DAC Treble Enhancement Switch",
  1725. R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
  1726. SOC_SINGLE("DAC Treble NLF Switch",
  1727. R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
  1728. SOC_SINGLE("DAC Bass Enhancement Switch",
  1729. R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
  1730. SOC_SINGLE("DAC Bass NLF Switch",
  1731. R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
  1732. /* R_SUBEQFILT PG 5 ADDR 0x01 */
  1733. SOC_SINGLE("Sub EQ 2 Switch",
  1734. R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
  1735. SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
  1736. SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
  1737. SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
  1738. /* R_SUBMBCEN PG 5 ADDR 0x0A */
  1739. SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
  1740. SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
  1741. SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
  1742. /* R_SUBMBCCTL PG 5 ADDR 0x0B */
  1743. SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
  1744. SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
  1745. SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
  1746. SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
  1747. SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
  1748. SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
  1749. /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
  1750. SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
  1751. SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
  1752. FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
  1753. 0, mbc_mug_tlv_arr),
  1754. /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
  1755. SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
  1756. FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
  1757. 0, thr_tlv_arr),
  1758. /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
  1759. SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
  1760. /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
  1761. /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
  1762. SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
  1763. /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
  1764. /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
  1765. SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
  1766. /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
  1767. SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
  1768. SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
  1769. FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
  1770. 0, mbc_mug_tlv_arr),
  1771. /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
  1772. SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
  1773. FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
  1774. 0, thr_tlv_arr),
  1775. /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
  1776. SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
  1777. /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
  1778. /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
  1779. SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
  1780. /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
  1781. /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
  1782. SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
  1783. /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
  1784. SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
  1785. SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
  1786. FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
  1787. 0, mbc_mug_tlv_arr),
  1788. /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
  1789. SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
  1790. FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
  1791. 0, thr_tlv_arr),
  1792. /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
  1793. SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
  1794. /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
  1795. /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
  1796. SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
  1797. /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
  1798. /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
  1799. SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
  1800. /* R_SUBCLECTL PG 5 ADDR 0x21 */
  1801. SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
  1802. SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
  1803. SOC_SINGLE("Sub CLE Expander Switch",
  1804. R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
  1805. SOC_SINGLE("Sub CLE Limiter Switch",
  1806. R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
  1807. SOC_SINGLE("Sub CLE Compressor Switch",
  1808. R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
  1809. /* R_SUBCLEMUG PG 5 ADDR 0x22 */
  1810. SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
  1811. FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
  1812. 0, cle_mug_tlv_arr),
  1813. /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
  1814. SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
  1815. FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
  1816. 0, thr_tlv_arr),
  1817. /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
  1818. SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
  1819. /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
  1820. /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
  1821. SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
  1822. /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
  1823. /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
  1824. SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
  1825. /* R_SUBLIMTHR PG 5 ADDR 0x29 */
  1826. SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
  1827. FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
  1828. 0, thr_tlv_arr),
  1829. /* R_SUBLIMTGT PG 5 ADDR 0x2A */
  1830. SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
  1831. FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
  1832. 0, thr_tlv_arr),
  1833. /* R_SUBLIMATKL PG 5 ADDR 0x2B */
  1834. /* R_SUBLIMATKH PG 5 ADDR 0x2C */
  1835. SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
  1836. /* R_SUBLIMRELL PG 5 ADDR 0x2D */
  1837. /* R_SUBLIMRELR PG 5 ADDR 0x2E */
  1838. SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
  1839. /* R_SUBEXPTHR PG 5 ADDR 0x2F */
  1840. SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
  1841. FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
  1842. 0, thr_tlv_arr),
  1843. /* R_SUBEXPRAT PG 5 ADDR 0x30 */
  1844. SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
  1845. /* R_SUBEXPATKL PG 5 ADDR 0x31 */
  1846. /* R_SUBEXPATKR PG 5 ADDR 0x32 */
  1847. SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
  1848. /* R_SUBEXPRELL PG 5 ADDR 0x33 */
  1849. /* R_SUBEXPRELR PG 5 ADDR 0x34 */
  1850. SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
  1851. /* R_SUBFXCTL PG 5 ADDR 0x35 */
  1852. SOC_SINGLE("Sub Treble Enhancement Switch",
  1853. R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
  1854. SOC_SINGLE("Sub Treble NLF Switch",
  1855. R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
  1856. SOC_SINGLE("Sub Bass Enhancement Switch",
  1857. R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
  1858. SOC_SINGLE("Sub Bass NLF Switch",
  1859. R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
  1860. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
  1861. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
  1862. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
  1863. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
  1864. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
  1865. COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
  1866. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
  1867. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
  1868. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
  1869. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
  1870. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
  1871. COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
  1872. COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
  1873. COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
  1874. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
  1875. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
  1876. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
  1877. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
  1878. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
  1879. COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
  1880. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
  1881. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
  1882. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
  1883. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
  1884. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
  1885. COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
  1886. COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
  1887. COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
  1888. COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
  1889. COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
  1890. COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
  1891. COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
  1892. COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
  1893. COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
  1894. COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
  1895. COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
  1896. COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
  1897. COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
  1898. COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
  1899. COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
  1900. COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
  1901. COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
  1902. COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
  1903. COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
  1904. COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
  1905. COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
  1906. COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
  1907. COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
  1908. COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
  1909. COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
  1910. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
  1911. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
  1912. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
  1913. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
  1914. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
  1915. COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
  1916. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
  1917. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
  1918. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
  1919. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
  1920. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
  1921. COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
  1922. COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
  1923. COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
  1924. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
  1925. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
  1926. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
  1927. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
  1928. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
  1929. COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
  1930. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
  1931. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
  1932. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
  1933. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
  1934. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
  1935. COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
  1936. COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
  1937. COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
  1938. COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
  1939. COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
  1940. COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
  1941. COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
  1942. COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
  1943. COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
  1944. COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
  1945. COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
  1946. COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
  1947. COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
  1948. COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
  1949. COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
  1950. COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
  1951. COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
  1952. COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
  1953. COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
  1954. COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
  1955. COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
  1956. COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
  1957. COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
  1958. COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
  1959. COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
  1960. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
  1961. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
  1962. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
  1963. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
  1964. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
  1965. COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
  1966. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
  1967. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
  1968. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
  1969. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
  1970. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
  1971. COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
  1972. COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
  1973. COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
  1974. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
  1975. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
  1976. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
  1977. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
  1978. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
  1979. COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
  1980. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
  1981. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
  1982. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
  1983. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
  1984. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
  1985. COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
  1986. COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
  1987. COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
  1988. COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
  1989. COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
  1990. COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
  1991. COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
  1992. COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
  1993. COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
  1994. COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
  1995. COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
  1996. COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
  1997. COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
  1998. COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
  1999. COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
  2000. COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
  2001. COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
  2002. COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
  2003. COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
  2004. COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
  2005. COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
  2006. COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
  2007. COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
  2008. COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
  2009. COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
  2010. };
  2011. static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
  2012. /* R_PLLCTL PG 0 ADDR 0x15 */
  2013. SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
  2014. pll_power_event,
  2015. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
  2016. SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
  2017. pll_power_event,
  2018. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
  2019. /* R_I2SPINC0 PG 0 ADDR 0x22 */
  2020. SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
  2021. R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
  2022. SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
  2023. R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
  2024. SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
  2025. R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
  2026. /* R_PWRM0 PG 0 ADDR 0x33 */
  2027. SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
  2028. R_PWRM0, FB_PWRM0_INPROC3PU, 0),
  2029. SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
  2030. R_PWRM0, FB_PWRM0_INPROC2PU, 0),
  2031. SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
  2032. R_PWRM0, FB_PWRM0_INPROC1PU, 0),
  2033. SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
  2034. R_PWRM0, FB_PWRM0_INPROC0PU, 0),
  2035. SND_SOC_DAPM_SUPPLY("Mic Bias 2",
  2036. R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
  2037. SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
  2038. FB_PWRM0_MICB1PU, 0, NULL, 0),
  2039. /* R_PWRM1 PG 0 ADDR 0x34 */
  2040. SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
  2041. SND_SOC_DAPM_SUPPLY("Headphone Left Power",
  2042. R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
  2043. SND_SOC_DAPM_SUPPLY("Headphone Right Power",
  2044. R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
  2045. SND_SOC_DAPM_SUPPLY("Speaker Left Power",
  2046. R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
  2047. SND_SOC_DAPM_SUPPLY("Speaker Right Power",
  2048. R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
  2049. SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
  2050. R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
  2051. SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
  2052. R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
  2053. /* R_PWRM2 PG 0 ADDR 0x35 */
  2054. SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
  2055. R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
  2056. SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
  2057. R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
  2058. SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
  2059. R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
  2060. SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
  2061. R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
  2062. SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
  2063. R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
  2064. SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
  2065. R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
  2066. /* R_PWRM3 PG 0 ADDR 0x36 */
  2067. SND_SOC_DAPM_SUPPLY("Line Out Left Power",
  2068. R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
  2069. SND_SOC_DAPM_SUPPLY("Line Out Right Power",
  2070. R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
  2071. /* R_PWRM4 PG 0 ADDR 0x37 */
  2072. SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
  2073. SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
  2074. SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
  2075. SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
  2076. SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
  2077. /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
  2078. SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
  2079. &dai2_mux_dapm_enum),
  2080. SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
  2081. &dai1_mux_dapm_enum),
  2082. /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
  2083. SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
  2084. &dac_mux_dapm_enum),
  2085. SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
  2086. &dai3_mux_dapm_enum),
  2087. /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
  2088. SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
  2089. &sub_mux_dapm_enum),
  2090. SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
  2091. &classd_mux_dapm_enum),
  2092. /* R_HSDCTL1 PG 1 ADDR 0x01 */
  2093. SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
  2094. FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
  2095. /* R_CH0AIC PG 1 ADDR 0x06 */
  2096. SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
  2097. &in_bst_mux_ch0_dapm_enum),
  2098. SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
  2099. &adc_mux_ch0_dapm_enum),
  2100. SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
  2101. &in_proc_mux_ch0_dapm_enum),
  2102. /* R_CH1AIC PG 1 ADDR 0x07 */
  2103. SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
  2104. &in_bst_mux_ch1_dapm_enum),
  2105. SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
  2106. &adc_mux_ch1_dapm_enum),
  2107. SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
  2108. &in_proc_mux_ch1_dapm_enum),
  2109. /* Virtual */
  2110. SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
  2111. SND_SOC_NOPM, 0, 0),
  2112. SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
  2113. SND_SOC_NOPM, 0, 0),
  2114. SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
  2115. SND_SOC_NOPM, 0, 0),
  2116. SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
  2117. SND_SOC_DAPM_OUTPUT("Sub Out"),
  2118. SND_SOC_DAPM_OUTPUT("Headphone Left"),
  2119. SND_SOC_DAPM_OUTPUT("Headphone Right"),
  2120. SND_SOC_DAPM_OUTPUT("Speaker Left"),
  2121. SND_SOC_DAPM_OUTPUT("Speaker Right"),
  2122. SND_SOC_DAPM_OUTPUT("Line Out Left"),
  2123. SND_SOC_DAPM_OUTPUT("Line Out Right"),
  2124. SND_SOC_DAPM_INPUT("D2S 2"),
  2125. SND_SOC_DAPM_INPUT("D2S 1"),
  2126. SND_SOC_DAPM_INPUT("Line In 1 Left"),
  2127. SND_SOC_DAPM_INPUT("Line In 1 Right"),
  2128. SND_SOC_DAPM_INPUT("Line In 2 Left"),
  2129. SND_SOC_DAPM_INPUT("Line In 2 Right"),
  2130. SND_SOC_DAPM_INPUT("Line In 3 Left"),
  2131. SND_SOC_DAPM_INPUT("Line In 3 Right"),
  2132. SND_SOC_DAPM_INPUT("DMic 1"),
  2133. SND_SOC_DAPM_INPUT("DMic 2"),
  2134. SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
  2135. &ch_0_1_mux_dapm_enum),
  2136. SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
  2137. &ch_2_3_mux_dapm_enum),
  2138. SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
  2139. &ch_4_5_mux_dapm_enum),
  2140. };
  2141. static struct snd_soc_dapm_route const tscs454_intercon[] = {
  2142. /* PLLs */
  2143. {"PLLs", NULL, "PLL 1 Power", pll_connected},
  2144. {"PLLs", NULL, "PLL 2 Power", pll_connected},
  2145. /* Inputs */
  2146. {"DAI 3 In", NULL, "DAI 3 In Power"},
  2147. {"DAI 2 In", NULL, "DAI 2 In Power"},
  2148. {"DAI 1 In", NULL, "DAI 1 In Power"},
  2149. /* Outputs */
  2150. {"DAI 3 Out", NULL, "DAI 3 Out Power"},
  2151. {"DAI 2 Out", NULL, "DAI 2 Out Power"},
  2152. {"DAI 1 Out", NULL, "DAI 1 Out Power"},
  2153. /* Ch Muxing */
  2154. {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
  2155. {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
  2156. {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
  2157. {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
  2158. {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
  2159. {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
  2160. /* In/Out Muxing */
  2161. {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
  2162. {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
  2163. {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
  2164. {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
  2165. {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
  2166. {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
  2167. {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
  2168. {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
  2169. {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
  2170. /******************
  2171. * Playback Paths *
  2172. ******************/
  2173. /* DAC Path */
  2174. {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
  2175. {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
  2176. {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
  2177. {"DAC Left", NULL, "DAC Mux"},
  2178. {"DAC Right", NULL, "DAC Mux"},
  2179. {"DAC Left", NULL, "PLLs"},
  2180. {"DAC Right", NULL, "PLLs"},
  2181. {"Headphone Left", NULL, "Headphone Left Power"},
  2182. {"Headphone Right", NULL, "Headphone Right Power"},
  2183. {"Headphone Left", NULL, "DAC Left"},
  2184. {"Headphone Right", NULL, "DAC Right"},
  2185. /* Line Out */
  2186. {"Line Out Left", NULL, "Line Out Left Power"},
  2187. {"Line Out Right", NULL, "Line Out Right Power"},
  2188. {"Line Out Left", NULL, "DAC Left"},
  2189. {"Line Out Right", NULL, "DAC Right"},
  2190. /* ClassD Path */
  2191. {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
  2192. {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
  2193. {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
  2194. {"ClassD Left", NULL, "Speaker Mux"},
  2195. {"ClassD Right", NULL, "Speaker Mux"},
  2196. {"ClassD Left", NULL, "PLLs"},
  2197. {"ClassD Right", NULL, "PLLs"},
  2198. {"Speaker Left", NULL, "Speaker Left Power"},
  2199. {"Speaker Right", NULL, "Speaker Right Power"},
  2200. {"Speaker Left", NULL, "ClassD Left"},
  2201. {"Speaker Right", NULL, "ClassD Right"},
  2202. /* Sub Path */
  2203. {"Sub Mux", "CH 4", "CH 4_5 Mux"},
  2204. {"Sub Mux", "CH 5", "CH 4_5 Mux"},
  2205. {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
  2206. {"Sub Mux", "CH 2", "CH 2_3 Mux"},
  2207. {"Sub Mux", "CH 3", "CH 2_3 Mux"},
  2208. {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
  2209. {"Sub Mux", "CH 0", "CH 0_1 Mux"},
  2210. {"Sub Mux", "CH 1", "CH 0_1 Mux"},
  2211. {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
  2212. {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
  2213. {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
  2214. {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
  2215. {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
  2216. {"Sub Mux", "DMic 2 Left", "DMic 2"},
  2217. {"Sub Mux", "DMic 2 Right", "DMic 2"},
  2218. {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
  2219. {"Sub Mux", "ClassD Left", "ClassD Left"},
  2220. {"Sub Mux", "ClassD Right", "ClassD Right"},
  2221. {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
  2222. {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
  2223. {"Sub", NULL, "Sub Mux"},
  2224. {"Sub", NULL, "PLLs"},
  2225. {"Sub Out", NULL, "Sub Power"},
  2226. {"Sub Out", NULL, "Sub"},
  2227. /*****************
  2228. * Capture Paths *
  2229. *****************/
  2230. {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
  2231. {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
  2232. {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
  2233. {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
  2234. {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
  2235. {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
  2236. {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
  2237. {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
  2238. {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
  2239. {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
  2240. {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
  2241. {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
  2242. {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
  2243. {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
  2244. {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
  2245. {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
  2246. {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
  2247. {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
  2248. {"Input Processor Channel 0", NULL, "PLLs"},
  2249. {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
  2250. {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
  2251. {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
  2252. {"Input Processor Channel 1", NULL, "PLLs"},
  2253. {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
  2254. {"Input Processor Channel 2", NULL, "PLLs"},
  2255. {"Input Processor Channel 2", NULL, "DMic 2"},
  2256. {"Input Processor Channel 3", NULL, "PLLs"},
  2257. {"Input Processor Channel 3", NULL, "DMic 2"},
  2258. {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
  2259. {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
  2260. {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
  2261. {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
  2262. {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
  2263. {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
  2264. {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
  2265. {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
  2266. {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
  2267. {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
  2268. {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
  2269. {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
  2270. {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
  2271. {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
  2272. {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
  2273. };
  2274. /* This is used when BCLK is sourcing the PLLs */
  2275. static int tscs454_set_sysclk(struct snd_soc_dai *dai,
  2276. int clk_id, unsigned int freq, int dir)
  2277. {
  2278. struct snd_soc_component *component = dai->component;
  2279. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2280. unsigned int val;
  2281. int bclk_dai;
  2282. dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
  2283. val = snd_soc_component_read(component, R_PLLCTL);
  2284. bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
  2285. if (bclk_dai != dai->id)
  2286. return 0;
  2287. tscs454->bclk_freq = freq;
  2288. return set_sysclk(component);
  2289. }
  2290. static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
  2291. unsigned int ratio)
  2292. {
  2293. unsigned int mask;
  2294. int ret;
  2295. struct snd_soc_component *component = dai->component;
  2296. unsigned int val;
  2297. int shift;
  2298. dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
  2299. dai->id, ratio);
  2300. switch (dai->id) {
  2301. case TSCS454_DAI1_ID:
  2302. mask = FM_I2SCMC_BCMP1;
  2303. shift = FB_I2SCMC_BCMP1;
  2304. break;
  2305. case TSCS454_DAI2_ID:
  2306. mask = FM_I2SCMC_BCMP2;
  2307. shift = FB_I2SCMC_BCMP2;
  2308. break;
  2309. case TSCS454_DAI3_ID:
  2310. mask = FM_I2SCMC_BCMP3;
  2311. shift = FB_I2SCMC_BCMP3;
  2312. break;
  2313. default:
  2314. ret = -EINVAL;
  2315. dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
  2316. return ret;
  2317. }
  2318. switch (ratio) {
  2319. case 32:
  2320. val = I2SCMC_BCMP_32X;
  2321. break;
  2322. case 40:
  2323. val = I2SCMC_BCMP_40X;
  2324. break;
  2325. case 64:
  2326. val = I2SCMC_BCMP_64X;
  2327. break;
  2328. default:
  2329. ret = -EINVAL;
  2330. dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
  2331. return ret;
  2332. }
  2333. ret = snd_soc_component_update_bits(component,
  2334. R_I2SCMC, mask, val << shift);
  2335. if (ret < 0) {
  2336. dev_err(component->dev,
  2337. "Failed to set DAI BCLK ratio (%d)\n", ret);
  2338. return ret;
  2339. }
  2340. return 0;
  2341. }
  2342. static inline int set_aif_master_from_fmt(struct snd_soc_component *component,
  2343. struct aif *aif, unsigned int fmt)
  2344. {
  2345. int ret;
  2346. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2347. case SND_SOC_DAIFMT_CBM_CFM:
  2348. aif->master = true;
  2349. break;
  2350. case SND_SOC_DAIFMT_CBS_CFS:
  2351. aif->master = false;
  2352. break;
  2353. default:
  2354. ret = -EINVAL;
  2355. dev_err(component->dev, "Unsupported format (%d)\n", ret);
  2356. return ret;
  2357. }
  2358. return 0;
  2359. }
  2360. static inline int set_aif_tdm_delay(struct snd_soc_component *component,
  2361. unsigned int dai_id, bool delay)
  2362. {
  2363. unsigned int reg;
  2364. int ret;
  2365. switch (dai_id) {
  2366. case TSCS454_DAI1_ID:
  2367. reg = R_TDMCTL0;
  2368. break;
  2369. case TSCS454_DAI2_ID:
  2370. reg = R_PCMP2CTL0;
  2371. break;
  2372. case TSCS454_DAI3_ID:
  2373. reg = R_PCMP3CTL0;
  2374. break;
  2375. default:
  2376. ret = -EINVAL;
  2377. dev_err(component->dev,
  2378. "DAI %d unknown (%d)\n", dai_id + 1, ret);
  2379. return ret;
  2380. }
  2381. ret = snd_soc_component_update_bits(component,
  2382. reg, FM_TDMCTL0_BDELAY, delay);
  2383. if (ret < 0) {
  2384. dev_err(component->dev, "Failed to setup tdm format (%d)\n",
  2385. ret);
  2386. return ret;
  2387. }
  2388. return 0;
  2389. }
  2390. static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
  2391. unsigned int dai_id, unsigned int fmt)
  2392. {
  2393. unsigned int reg;
  2394. unsigned int val;
  2395. int ret;
  2396. switch (dai_id) {
  2397. case TSCS454_DAI1_ID:
  2398. reg = R_I2SP1CTL;
  2399. break;
  2400. case TSCS454_DAI2_ID:
  2401. reg = R_I2SP2CTL;
  2402. break;
  2403. case TSCS454_DAI3_ID:
  2404. reg = R_I2SP3CTL;
  2405. break;
  2406. default:
  2407. ret = -EINVAL;
  2408. dev_err(component->dev,
  2409. "DAI %d unknown (%d)\n", dai_id + 1, ret);
  2410. return ret;
  2411. }
  2412. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2413. case SND_SOC_DAIFMT_RIGHT_J:
  2414. val = FV_FORMAT_RIGHT;
  2415. break;
  2416. case SND_SOC_DAIFMT_LEFT_J:
  2417. val = FV_FORMAT_LEFT;
  2418. break;
  2419. case SND_SOC_DAIFMT_I2S:
  2420. val = FV_FORMAT_I2S;
  2421. break;
  2422. case SND_SOC_DAIFMT_DSP_A:
  2423. ret = set_aif_tdm_delay(component, dai_id, true);
  2424. if (ret < 0)
  2425. return ret;
  2426. val = FV_FORMAT_TDM;
  2427. break;
  2428. case SND_SOC_DAIFMT_DSP_B:
  2429. ret = set_aif_tdm_delay(component, dai_id, false);
  2430. if (ret < 0)
  2431. return ret;
  2432. val = FV_FORMAT_TDM;
  2433. break;
  2434. default:
  2435. ret = -EINVAL;
  2436. dev_err(component->dev, "Format unsupported (%d)\n", ret);
  2437. return ret;
  2438. }
  2439. ret = snd_soc_component_update_bits(component,
  2440. reg, FM_I2SPCTL_FORMAT, val);
  2441. if (ret < 0) {
  2442. dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
  2443. dai_id + 1, ret);
  2444. return ret;
  2445. }
  2446. return 0;
  2447. }
  2448. static inline int
  2449. set_aif_clock_format_from_fmt(struct snd_soc_component *component,
  2450. unsigned int dai_id, unsigned int fmt)
  2451. {
  2452. unsigned int reg;
  2453. unsigned int val;
  2454. int ret;
  2455. switch (dai_id) {
  2456. case TSCS454_DAI1_ID:
  2457. reg = R_I2SP1CTL;
  2458. break;
  2459. case TSCS454_DAI2_ID:
  2460. reg = R_I2SP2CTL;
  2461. break;
  2462. case TSCS454_DAI3_ID:
  2463. reg = R_I2SP3CTL;
  2464. break;
  2465. default:
  2466. ret = -EINVAL;
  2467. dev_err(component->dev,
  2468. "DAI %d unknown (%d)\n", dai_id + 1, ret);
  2469. return ret;
  2470. }
  2471. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2472. case SND_SOC_DAIFMT_NB_NF:
  2473. val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
  2474. break;
  2475. case SND_SOC_DAIFMT_NB_IF:
  2476. val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
  2477. break;
  2478. case SND_SOC_DAIFMT_IB_NF:
  2479. val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
  2480. break;
  2481. case SND_SOC_DAIFMT_IB_IF:
  2482. val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
  2483. break;
  2484. default:
  2485. ret = -EINVAL;
  2486. dev_err(component->dev, "Format unknown (%d)\n", ret);
  2487. return ret;
  2488. }
  2489. ret = snd_soc_component_update_bits(component, reg,
  2490. FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
  2491. if (ret < 0) {
  2492. dev_err(component->dev,
  2493. "Failed to set clock polarity for DAI%d (%d)\n",
  2494. dai_id + 1, ret);
  2495. return ret;
  2496. }
  2497. return 0;
  2498. }
  2499. static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2500. {
  2501. struct snd_soc_component *component = dai->component;
  2502. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2503. struct aif *aif = &tscs454->aifs[dai->id];
  2504. int ret;
  2505. ret = set_aif_master_from_fmt(component, aif, fmt);
  2506. if (ret < 0)
  2507. return ret;
  2508. ret = set_aif_format_from_fmt(component, dai->id, fmt);
  2509. if (ret < 0)
  2510. return ret;
  2511. ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
  2512. if (ret < 0)
  2513. return ret;
  2514. return 0;
  2515. }
  2516. static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
  2517. unsigned int tx_mask, unsigned int rx_mask, int slots,
  2518. int slot_width)
  2519. {
  2520. struct snd_soc_component *component = dai->component;
  2521. unsigned int val;
  2522. int ret;
  2523. if (!slots)
  2524. return 0;
  2525. if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
  2526. ret = -EINVAL;
  2527. dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
  2528. return ret;
  2529. }
  2530. switch (slots) {
  2531. case 2:
  2532. val = FV_TDMSO_2 | FV_TDMSI_2;
  2533. break;
  2534. case 4:
  2535. val = FV_TDMSO_4 | FV_TDMSI_4;
  2536. break;
  2537. case 6:
  2538. val = FV_TDMSO_6 | FV_TDMSI_6;
  2539. break;
  2540. default:
  2541. ret = -EINVAL;
  2542. dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
  2543. return ret;
  2544. }
  2545. switch (slot_width) {
  2546. case 16:
  2547. val = val | FV_TDMDSS_16;
  2548. break;
  2549. case 24:
  2550. val = val | FV_TDMDSS_24;
  2551. break;
  2552. case 32:
  2553. val = val | FV_TDMDSS_32;
  2554. break;
  2555. default:
  2556. ret = -EINVAL;
  2557. dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
  2558. return ret;
  2559. }
  2560. ret = snd_soc_component_write(component, R_TDMCTL1, val);
  2561. if (ret < 0) {
  2562. dev_err(component->dev, "Failed to set slots (%d)\n", ret);
  2563. return ret;
  2564. }
  2565. return 0;
  2566. }
  2567. static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
  2568. unsigned int tx_mask, unsigned int rx_mask, int slots,
  2569. int slot_width)
  2570. {
  2571. struct snd_soc_component *component = dai->component;
  2572. unsigned int reg;
  2573. unsigned int val;
  2574. int ret;
  2575. if (!slots)
  2576. return 0;
  2577. if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
  2578. ret = -EINVAL;
  2579. dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
  2580. return ret;
  2581. }
  2582. switch (dai->id) {
  2583. case TSCS454_DAI2_ID:
  2584. reg = R_PCMP2CTL1;
  2585. break;
  2586. case TSCS454_DAI3_ID:
  2587. reg = R_PCMP3CTL1;
  2588. break;
  2589. default:
  2590. ret = -EINVAL;
  2591. dev_err(component->dev, "Unrecognized interface %d (%d)\n",
  2592. dai->id, ret);
  2593. return ret;
  2594. }
  2595. switch (slots) {
  2596. case 1:
  2597. val = FV_PCMSOP_1 | FV_PCMSIP_1;
  2598. break;
  2599. case 2:
  2600. val = FV_PCMSOP_2 | FV_PCMSIP_2;
  2601. break;
  2602. default:
  2603. ret = -EINVAL;
  2604. dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
  2605. return ret;
  2606. }
  2607. switch (slot_width) {
  2608. case 16:
  2609. val = val | FV_PCMDSSP_16;
  2610. break;
  2611. case 24:
  2612. val = val | FV_PCMDSSP_24;
  2613. break;
  2614. case 32:
  2615. val = val | FV_PCMDSSP_32;
  2616. break;
  2617. default:
  2618. ret = -EINVAL;
  2619. dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
  2620. return ret;
  2621. }
  2622. ret = snd_soc_component_write(component, reg, val);
  2623. if (ret < 0) {
  2624. dev_err(component->dev, "Failed to set slots (%d)\n", ret);
  2625. return ret;
  2626. }
  2627. return 0;
  2628. }
  2629. static int set_aif_fs(struct snd_soc_component *component,
  2630. unsigned int id,
  2631. unsigned int rate)
  2632. {
  2633. unsigned int reg;
  2634. unsigned int br;
  2635. unsigned int bm;
  2636. int ret;
  2637. switch (rate) {
  2638. case 8000:
  2639. br = FV_I2SMBR_32;
  2640. bm = FV_I2SMBM_0PT25;
  2641. break;
  2642. case 16000:
  2643. br = FV_I2SMBR_32;
  2644. bm = FV_I2SMBM_0PT5;
  2645. break;
  2646. case 24000:
  2647. br = FV_I2SMBR_48;
  2648. bm = FV_I2SMBM_0PT5;
  2649. break;
  2650. case 32000:
  2651. br = FV_I2SMBR_32;
  2652. bm = FV_I2SMBM_1;
  2653. break;
  2654. case 48000:
  2655. br = FV_I2SMBR_48;
  2656. bm = FV_I2SMBM_1;
  2657. break;
  2658. case 96000:
  2659. br = FV_I2SMBR_48;
  2660. bm = FV_I2SMBM_2;
  2661. break;
  2662. case 11025:
  2663. br = FV_I2SMBR_44PT1;
  2664. bm = FV_I2SMBM_0PT25;
  2665. break;
  2666. case 22050:
  2667. br = FV_I2SMBR_44PT1;
  2668. bm = FV_I2SMBM_0PT5;
  2669. break;
  2670. case 44100:
  2671. br = FV_I2SMBR_44PT1;
  2672. bm = FV_I2SMBM_1;
  2673. break;
  2674. case 88200:
  2675. br = FV_I2SMBR_44PT1;
  2676. bm = FV_I2SMBM_2;
  2677. break;
  2678. default:
  2679. ret = -EINVAL;
  2680. dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
  2681. return ret;
  2682. }
  2683. switch (id) {
  2684. case TSCS454_DAI1_ID:
  2685. reg = R_I2S1MRATE;
  2686. break;
  2687. case TSCS454_DAI2_ID:
  2688. reg = R_I2S2MRATE;
  2689. break;
  2690. case TSCS454_DAI3_ID:
  2691. reg = R_I2S3MRATE;
  2692. break;
  2693. default:
  2694. ret = -EINVAL;
  2695. dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
  2696. return ret;
  2697. }
  2698. ret = snd_soc_component_update_bits(component, reg,
  2699. FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
  2700. if (ret < 0) {
  2701. dev_err(component->dev,
  2702. "Failed to update register (%d)\n", ret);
  2703. return ret;
  2704. }
  2705. return 0;
  2706. }
  2707. static int set_aif_sample_format(struct snd_soc_component *component,
  2708. snd_pcm_format_t format,
  2709. int aif_id)
  2710. {
  2711. unsigned int reg;
  2712. unsigned int width;
  2713. int ret;
  2714. switch (format) {
  2715. case SNDRV_PCM_FORMAT_S16_LE:
  2716. width = FV_WL_16;
  2717. break;
  2718. case SNDRV_PCM_FORMAT_S20_3LE:
  2719. width = FV_WL_20;
  2720. break;
  2721. case SNDRV_PCM_FORMAT_S24_3LE:
  2722. width = FV_WL_24;
  2723. break;
  2724. case SNDRV_PCM_FORMAT_S24_LE:
  2725. case SNDRV_PCM_FORMAT_S32_LE:
  2726. width = FV_WL_32;
  2727. break;
  2728. default:
  2729. ret = -EINVAL;
  2730. dev_err(component->dev, "Unsupported format width (%d)\n", ret);
  2731. return ret;
  2732. }
  2733. switch (aif_id) {
  2734. case TSCS454_DAI1_ID:
  2735. reg = R_I2SP1CTL;
  2736. break;
  2737. case TSCS454_DAI2_ID:
  2738. reg = R_I2SP2CTL;
  2739. break;
  2740. case TSCS454_DAI3_ID:
  2741. reg = R_I2SP3CTL;
  2742. break;
  2743. default:
  2744. ret = -EINVAL;
  2745. dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
  2746. return ret;
  2747. }
  2748. ret = snd_soc_component_update_bits(component,
  2749. reg, FM_I2SPCTL_WL, width);
  2750. if (ret < 0) {
  2751. dev_err(component->dev,
  2752. "Failed to set sample width (%d)\n", ret);
  2753. return ret;
  2754. }
  2755. return 0;
  2756. }
  2757. static int tscs454_hw_params(struct snd_pcm_substream *substream,
  2758. struct snd_pcm_hw_params *params,
  2759. struct snd_soc_dai *dai)
  2760. {
  2761. struct snd_soc_component *component = dai->component;
  2762. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2763. unsigned int fs = params_rate(params);
  2764. struct aif *aif = &tscs454->aifs[dai->id];
  2765. unsigned int val;
  2766. int ret;
  2767. mutex_lock(&tscs454->aifs_status_lock);
  2768. dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
  2769. aif->id, fs);
  2770. if (!aif_active(&tscs454->aifs_status, aif->id)) {
  2771. if (PLL_44_1K_RATE % fs)
  2772. aif->pll = &tscs454->pll1;
  2773. else
  2774. aif->pll = &tscs454->pll2;
  2775. dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
  2776. aif->pll->id, aif->id);
  2777. reserve_pll(aif->pll);
  2778. }
  2779. if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
  2780. val = snd_soc_component_read(component, R_ISRC);
  2781. if ((val & FM_ISRC_IBR) == FV_IBR_48)
  2782. tscs454->internal_rate.pll = &tscs454->pll1;
  2783. else
  2784. tscs454->internal_rate.pll = &tscs454->pll2;
  2785. dev_dbg(component->dev, "Reserving pll %d for ir\n",
  2786. tscs454->internal_rate.pll->id);
  2787. reserve_pll(tscs454->internal_rate.pll);
  2788. }
  2789. ret = set_aif_fs(component, aif->id, fs);
  2790. if (ret < 0) {
  2791. dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
  2792. goto exit;
  2793. }
  2794. ret = set_aif_sample_format(component, params_format(params), aif->id);
  2795. if (ret < 0) {
  2796. dev_err(component->dev,
  2797. "Failed to set aif sample format (%d)\n", ret);
  2798. goto exit;
  2799. }
  2800. set_aif_status_active(&tscs454->aifs_status, aif->id,
  2801. substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  2802. dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
  2803. aif->id, tscs454->aifs_status.streams);
  2804. ret = 0;
  2805. exit:
  2806. mutex_unlock(&tscs454->aifs_status_lock);
  2807. return ret;
  2808. }
  2809. static int tscs454_hw_free(struct snd_pcm_substream *substream,
  2810. struct snd_soc_dai *dai)
  2811. {
  2812. struct snd_soc_component *component = dai->component;
  2813. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2814. struct aif *aif = &tscs454->aifs[dai->id];
  2815. return aif_free(component, aif,
  2816. substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  2817. }
  2818. static int tscs454_prepare(struct snd_pcm_substream *substream,
  2819. struct snd_soc_dai *dai)
  2820. {
  2821. int ret;
  2822. struct snd_soc_component *component = dai->component;
  2823. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2824. struct aif *aif = &tscs454->aifs[dai->id];
  2825. ret = aif_prepare(component, aif);
  2826. if (ret < 0)
  2827. return ret;
  2828. return 0;
  2829. }
  2830. static struct snd_soc_dai_ops const tscs454_dai1_ops = {
  2831. .set_sysclk = tscs454_set_sysclk,
  2832. .set_bclk_ratio = tscs454_set_bclk_ratio,
  2833. .set_fmt = tscs454_set_dai_fmt,
  2834. .set_tdm_slot = tscs454_dai1_set_tdm_slot,
  2835. .hw_params = tscs454_hw_params,
  2836. .hw_free = tscs454_hw_free,
  2837. .prepare = tscs454_prepare,
  2838. };
  2839. static struct snd_soc_dai_ops const tscs454_dai23_ops = {
  2840. .set_sysclk = tscs454_set_sysclk,
  2841. .set_bclk_ratio = tscs454_set_bclk_ratio,
  2842. .set_fmt = tscs454_set_dai_fmt,
  2843. .set_tdm_slot = tscs454_dai23_set_tdm_slot,
  2844. .hw_params = tscs454_hw_params,
  2845. .hw_free = tscs454_hw_free,
  2846. .prepare = tscs454_prepare,
  2847. };
  2848. static int tscs454_probe(struct snd_soc_component *component)
  2849. {
  2850. struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
  2851. unsigned int val;
  2852. int ret = 0;
  2853. switch (tscs454->sysclk_src_id) {
  2854. case PLL_INPUT_XTAL:
  2855. val = FV_PLLISEL_XTAL;
  2856. break;
  2857. case PLL_INPUT_MCLK1:
  2858. val = FV_PLLISEL_MCLK1;
  2859. break;
  2860. case PLL_INPUT_MCLK2:
  2861. val = FV_PLLISEL_MCLK2;
  2862. break;
  2863. case PLL_INPUT_BCLK:
  2864. val = FV_PLLISEL_BCLK;
  2865. break;
  2866. default:
  2867. ret = -EINVAL;
  2868. dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
  2869. return ret;
  2870. }
  2871. ret = snd_soc_component_update_bits(component, R_PLLCTL,
  2872. FM_PLLCTL_PLLISEL, val);
  2873. if (ret < 0) {
  2874. dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
  2875. return ret;
  2876. }
  2877. if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
  2878. ret = set_sysclk(component);
  2879. return ret;
  2880. }
  2881. static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
  2882. .probe = tscs454_probe,
  2883. .dapm_widgets = tscs454_dapm_widgets,
  2884. .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
  2885. .dapm_routes = tscs454_intercon,
  2886. .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
  2887. .controls = tscs454_snd_controls,
  2888. .num_controls = ARRAY_SIZE(tscs454_snd_controls),
  2889. };
  2890. #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
  2891. #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
  2892. | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
  2893. | SNDRV_PCM_FMTBIT_S32_LE)
  2894. static struct snd_soc_dai_driver tscs454_dais[] = {
  2895. {
  2896. .name = "tscs454-dai1",
  2897. .id = TSCS454_DAI1_ID,
  2898. .playback = {
  2899. .stream_name = "DAI 1 Playback",
  2900. .channels_min = 1,
  2901. .channels_max = 6,
  2902. .rates = TSCS454_RATES,
  2903. .formats = TSCS454_FORMATS,},
  2904. .capture = {
  2905. .stream_name = "DAI 1 Capture",
  2906. .channels_min = 1,
  2907. .channels_max = 6,
  2908. .rates = TSCS454_RATES,
  2909. .formats = TSCS454_FORMATS,},
  2910. .ops = &tscs454_dai1_ops,
  2911. .symmetric_rates = 1,
  2912. .symmetric_channels = 1,
  2913. .symmetric_samplebits = 1,
  2914. },
  2915. {
  2916. .name = "tscs454-dai2",
  2917. .id = TSCS454_DAI2_ID,
  2918. .playback = {
  2919. .stream_name = "DAI 2 Playback",
  2920. .channels_min = 1,
  2921. .channels_max = 2,
  2922. .rates = TSCS454_RATES,
  2923. .formats = TSCS454_FORMATS,},
  2924. .capture = {
  2925. .stream_name = "DAI 2 Capture",
  2926. .channels_min = 1,
  2927. .channels_max = 2,
  2928. .rates = TSCS454_RATES,
  2929. .formats = TSCS454_FORMATS,},
  2930. .ops = &tscs454_dai23_ops,
  2931. .symmetric_rates = 1,
  2932. .symmetric_channels = 1,
  2933. .symmetric_samplebits = 1,
  2934. },
  2935. {
  2936. .name = "tscs454-dai3",
  2937. .id = TSCS454_DAI3_ID,
  2938. .playback = {
  2939. .stream_name = "DAI 3 Playback",
  2940. .channels_min = 1,
  2941. .channels_max = 2,
  2942. .rates = TSCS454_RATES,
  2943. .formats = TSCS454_FORMATS,},
  2944. .capture = {
  2945. .stream_name = "DAI 3 Capture",
  2946. .channels_min = 1,
  2947. .channels_max = 2,
  2948. .rates = TSCS454_RATES,
  2949. .formats = TSCS454_FORMATS,},
  2950. .ops = &tscs454_dai23_ops,
  2951. .symmetric_rates = 1,
  2952. .symmetric_channels = 1,
  2953. .symmetric_samplebits = 1,
  2954. },
  2955. };
  2956. static char const * const src_names[] = {
  2957. "xtal", "mclk1", "mclk2", "bclk"};
  2958. static int tscs454_i2c_probe(struct i2c_client *i2c,
  2959. const struct i2c_device_id *id)
  2960. {
  2961. struct tscs454 *tscs454;
  2962. int src;
  2963. int ret;
  2964. tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
  2965. if (!tscs454)
  2966. return -ENOMEM;
  2967. ret = tscs454_data_init(tscs454, i2c);
  2968. if (ret < 0)
  2969. return ret;
  2970. i2c_set_clientdata(i2c, tscs454);
  2971. for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
  2972. tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
  2973. if (!IS_ERR(tscs454->sysclk)) {
  2974. break;
  2975. } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
  2976. ret = PTR_ERR(tscs454->sysclk);
  2977. dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
  2978. return ret;
  2979. }
  2980. }
  2981. dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
  2982. tscs454->sysclk_src_id = src;
  2983. ret = regmap_write(tscs454->regmap,
  2984. R_RESET, FV_RESET_PWR_ON_DEFAULTS);
  2985. if (ret < 0) {
  2986. dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
  2987. return ret;
  2988. }
  2989. regcache_mark_dirty(tscs454->regmap);
  2990. ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
  2991. ARRAY_SIZE(tscs454_patch));
  2992. if (ret < 0) {
  2993. dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
  2994. return ret;
  2995. }
  2996. /* Sync pg sel reg with cache */
  2997. regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
  2998. ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
  2999. tscs454_dais, ARRAY_SIZE(tscs454_dais));
  3000. if (ret) {
  3001. dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
  3002. return ret;
  3003. }
  3004. return 0;
  3005. }
  3006. static const struct i2c_device_id tscs454_i2c_id[] = {
  3007. { "tscs454", 0 },
  3008. { }
  3009. };
  3010. MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
  3011. static const struct of_device_id tscs454_of_match[] = {
  3012. { .compatible = "tempo,tscs454", },
  3013. { }
  3014. };
  3015. MODULE_DEVICE_TABLE(of, tscs454_of_match);
  3016. static struct i2c_driver tscs454_i2c_driver = {
  3017. .driver = {
  3018. .name = "tscs454",
  3019. .of_match_table = tscs454_of_match,
  3020. },
  3021. .probe = tscs454_i2c_probe,
  3022. .id_table = tscs454_i2c_id,
  3023. };
  3024. module_i2c_driver(tscs454_i2c_driver);
  3025. MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
  3026. MODULE_DESCRIPTION("ASoC TSCS454 driver");
  3027. MODULE_LICENSE("GPL v2");