tscs42xx.h 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // tscs42xx.h -- TSCS42xx ALSA SoC Audio driver
  3. // Copyright 2017 Tempo Semiconductor, Inc.
  4. // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
  5. #ifndef __WOOKIE_H__
  6. #define __WOOKIE_H__
  7. enum {
  8. TSCS42XX_PLL_SRC_XTAL,
  9. TSCS42XX_PLL_SRC_MCLK1,
  10. TSCS42XX_PLL_SRC_MCLK2,
  11. TSCS42XX_PLL_SRC_CNT,
  12. };
  13. #define R_HPVOLL 0x0
  14. #define R_HPVOLR 0x1
  15. #define R_SPKVOLL 0x2
  16. #define R_SPKVOLR 0x3
  17. #define R_DACVOLL 0x4
  18. #define R_DACVOLR 0x5
  19. #define R_ADCVOLL 0x6
  20. #define R_ADCVOLR 0x7
  21. #define R_INVOLL 0x8
  22. #define R_INVOLR 0x9
  23. #define R_INMODE 0x0B
  24. #define R_INSELL 0x0C
  25. #define R_INSELR 0x0D
  26. #define R_AIC1 0x13
  27. #define R_AIC2 0x14
  28. #define R_CNVRTR0 0x16
  29. #define R_ADCSR 0x17
  30. #define R_CNVRTR1 0x18
  31. #define R_DACSR 0x19
  32. #define R_PWRM1 0x1A
  33. #define R_PWRM2 0x1B
  34. #define R_CTL 0x1C
  35. #define R_CONFIG0 0x1F
  36. #define R_CONFIG1 0x20
  37. #define R_DMICCTL 0x24
  38. #define R_CLECTL 0x25
  39. #define R_MUGAIN 0x26
  40. #define R_COMPTH 0x27
  41. #define R_CMPRAT 0x28
  42. #define R_CATKTCL 0x29
  43. #define R_CATKTCH 0x2A
  44. #define R_CRELTCL 0x2B
  45. #define R_CRELTCH 0x2C
  46. #define R_LIMTH 0x2D
  47. #define R_LIMTGT 0x2E
  48. #define R_LATKTCL 0x2F
  49. #define R_LATKTCH 0x30
  50. #define R_LRELTCL 0x31
  51. #define R_LRELTCH 0x32
  52. #define R_EXPTH 0x33
  53. #define R_EXPRAT 0x34
  54. #define R_XATKTCL 0x35
  55. #define R_XATKTCH 0x36
  56. #define R_XRELTCL 0x37
  57. #define R_XRELTCH 0x38
  58. #define R_FXCTL 0x39
  59. #define R_DACCRWRL 0x3A
  60. #define R_DACCRWRM 0x3B
  61. #define R_DACCRWRH 0x3C
  62. #define R_DACCRRDL 0x3D
  63. #define R_DACCRRDM 0x3E
  64. #define R_DACCRRDH 0x3F
  65. #define R_DACCRADDR 0x40
  66. #define R_DCOFSEL 0x41
  67. #define R_PLLCTL9 0x4E
  68. #define R_PLLCTLA 0x4F
  69. #define R_PLLCTLB 0x50
  70. #define R_PLLCTLC 0x51
  71. #define R_PLLCTLD 0x52
  72. #define R_PLLCTLE 0x53
  73. #define R_PLLCTLF 0x54
  74. #define R_PLLCTL10 0x55
  75. #define R_PLLCTL11 0x56
  76. #define R_PLLCTL12 0x57
  77. #define R_PLLCTL1B 0x60
  78. #define R_PLLCTL1C 0x61
  79. #define R_TIMEBASE 0x77
  80. #define R_DEVIDL 0x7D
  81. #define R_DEVIDH 0x7E
  82. #define R_RESET 0x80
  83. #define R_DACCRSTAT 0x8A
  84. #define R_PLLCTL0 0x8E
  85. #define R_PLLREFSEL 0x8F
  86. #define R_DACMBCEN 0xC7
  87. #define R_DACMBCCTL 0xC8
  88. #define R_DACMBCMUG1 0xC9
  89. #define R_DACMBCTHR1 0xCA
  90. #define R_DACMBCRAT1 0xCB
  91. #define R_DACMBCATK1L 0xCC
  92. #define R_DACMBCATK1H 0xCD
  93. #define R_DACMBCREL1L 0xCE
  94. #define R_DACMBCREL1H 0xCF
  95. #define R_DACMBCMUG2 0xD0
  96. #define R_DACMBCTHR2 0xD1
  97. #define R_DACMBCRAT2 0xD2
  98. #define R_DACMBCATK2L 0xD3
  99. #define R_DACMBCATK2H 0xD4
  100. #define R_DACMBCREL2L 0xD5
  101. #define R_DACMBCREL2H 0xD6
  102. #define R_DACMBCMUG3 0xD7
  103. #define R_DACMBCTHR3 0xD8
  104. #define R_DACMBCRAT3 0xD9
  105. #define R_DACMBCATK3L 0xDA
  106. #define R_DACMBCATK3H 0xDB
  107. #define R_DACMBCREL3L 0xDC
  108. #define R_DACMBCREL3H 0xDD
  109. /* Helpers */
  110. #define RM(m, b) ((m)<<(b))
  111. #define RV(v, b) ((v)<<(b))
  112. /****************************
  113. * R_HPVOLL (0x0) *
  114. ****************************/
  115. /* Field Offsets */
  116. #define FB_HPVOLL 0
  117. /* Field Masks */
  118. #define FM_HPVOLL 0X7F
  119. /* Field Values */
  120. #define FV_HPVOLL_P6DB 0x7F
  121. #define FV_HPVOLL_N88PT5DB 0x1
  122. #define FV_HPVOLL_MUTE 0x0
  123. /* Register Masks */
  124. #define RM_HPVOLL RM(FM_HPVOLL, FB_HPVOLL)
  125. /* Register Values */
  126. #define RV_HPVOLL_P6DB RV(FV_HPVOLL_P6DB, FB_HPVOLL)
  127. #define RV_HPVOLL_N88PT5DB RV(FV_HPVOLL_N88PT5DB, FB_HPVOLL)
  128. #define RV_HPVOLL_MUTE RV(FV_HPVOLL_MUTE, FB_HPVOLL)
  129. /****************************
  130. * R_HPVOLR (0x1) *
  131. ****************************/
  132. /* Field Offsets */
  133. #define FB_HPVOLR 0
  134. /* Field Masks */
  135. #define FM_HPVOLR 0X7F
  136. /* Field Values */
  137. #define FV_HPVOLR_P6DB 0x7F
  138. #define FV_HPVOLR_N88PT5DB 0x1
  139. #define FV_HPVOLR_MUTE 0x0
  140. /* Register Masks */
  141. #define RM_HPVOLR RM(FM_HPVOLR, FB_HPVOLR)
  142. /* Register Values */
  143. #define RV_HPVOLR_P6DB RV(FV_HPVOLR_P6DB, FB_HPVOLR)
  144. #define RV_HPVOLR_N88PT5DB RV(FV_HPVOLR_N88PT5DB, FB_HPVOLR)
  145. #define RV_HPVOLR_MUTE RV(FV_HPVOLR_MUTE, FB_HPVOLR)
  146. /*****************************
  147. * R_SPKVOLL (0x2) *
  148. *****************************/
  149. /* Field Offsets */
  150. #define FB_SPKVOLL 0
  151. /* Field Masks */
  152. #define FM_SPKVOLL 0X7F
  153. /* Field Values */
  154. #define FV_SPKVOLL_P12DB 0x7F
  155. #define FV_SPKVOLL_N77PT25DB 0x8
  156. #define FV_SPKVOLL_MUTE 0x0
  157. /* Register Masks */
  158. #define RM_SPKVOLL RM(FM_SPKVOLL, FB_SPKVOLL)
  159. /* Register Values */
  160. #define RV_SPKVOLL_P12DB RV(FV_SPKVOLL_P12DB, FB_SPKVOLL)
  161. #define RV_SPKVOLL_N77PT25DB \
  162. RV(FV_SPKVOLL_N77PT25DB, FB_SPKVOLL)
  163. #define RV_SPKVOLL_MUTE RV(FV_SPKVOLL_MUTE, FB_SPKVOLL)
  164. /*****************************
  165. * R_SPKVOLR (0x3) *
  166. *****************************/
  167. /* Field Offsets */
  168. #define FB_SPKVOLR 0
  169. /* Field Masks */
  170. #define FM_SPKVOLR 0X7F
  171. /* Field Values */
  172. #define FV_SPKVOLR_P12DB 0x7F
  173. #define FV_SPKVOLR_N77PT25DB 0x8
  174. #define FV_SPKVOLR_MUTE 0x0
  175. /* Register Masks */
  176. #define RM_SPKVOLR RM(FM_SPKVOLR, FB_SPKVOLR)
  177. /* Register Values */
  178. #define RV_SPKVOLR_P12DB RV(FV_SPKVOLR_P12DB, FB_SPKVOLR)
  179. #define RV_SPKVOLR_N77PT25DB \
  180. RV(FV_SPKVOLR_N77PT25DB, FB_SPKVOLR)
  181. #define RV_SPKVOLR_MUTE RV(FV_SPKVOLR_MUTE, FB_SPKVOLR)
  182. /*****************************
  183. * R_DACVOLL (0x4) *
  184. *****************************/
  185. /* Field Offsets */
  186. #define FB_DACVOLL 0
  187. /* Field Masks */
  188. #define FM_DACVOLL 0XFF
  189. /* Field Values */
  190. #define FV_DACVOLL_0DB 0xFF
  191. #define FV_DACVOLL_N95PT625DB 0x1
  192. #define FV_DACVOLL_MUTE 0x0
  193. /* Register Masks */
  194. #define RM_DACVOLL RM(FM_DACVOLL, FB_DACVOLL)
  195. /* Register Values */
  196. #define RV_DACVOLL_0DB RV(FV_DACVOLL_0DB, FB_DACVOLL)
  197. #define RV_DACVOLL_N95PT625DB \
  198. RV(FV_DACVOLL_N95PT625DB, FB_DACVOLL)
  199. #define RV_DACVOLL_MUTE RV(FV_DACVOLL_MUTE, FB_DACVOLL)
  200. /*****************************
  201. * R_DACVOLR (0x5) *
  202. *****************************/
  203. /* Field Offsets */
  204. #define FB_DACVOLR 0
  205. /* Field Masks */
  206. #define FM_DACVOLR 0XFF
  207. /* Field Values */
  208. #define FV_DACVOLR_0DB 0xFF
  209. #define FV_DACVOLR_N95PT625DB 0x1
  210. #define FV_DACVOLR_MUTE 0x0
  211. /* Register Masks */
  212. #define RM_DACVOLR RM(FM_DACVOLR, FB_DACVOLR)
  213. /* Register Values */
  214. #define RV_DACVOLR_0DB RV(FV_DACVOLR_0DB, FB_DACVOLR)
  215. #define RV_DACVOLR_N95PT625DB \
  216. RV(FV_DACVOLR_N95PT625DB, FB_DACVOLR)
  217. #define RV_DACVOLR_MUTE RV(FV_DACVOLR_MUTE, FB_DACVOLR)
  218. /*****************************
  219. * R_ADCVOLL (0x6) *
  220. *****************************/
  221. /* Field Offsets */
  222. #define FB_ADCVOLL 0
  223. /* Field Masks */
  224. #define FM_ADCVOLL 0XFF
  225. /* Field Values */
  226. #define FV_ADCVOLL_P24DB 0xFF
  227. #define FV_ADCVOLL_N71PT25DB 0x1
  228. #define FV_ADCVOLL_MUTE 0x0
  229. /* Register Masks */
  230. #define RM_ADCVOLL RM(FM_ADCVOLL, FB_ADCVOLL)
  231. /* Register Values */
  232. #define RV_ADCVOLL_P24DB RV(FV_ADCVOLL_P24DB, FB_ADCVOLL)
  233. #define RV_ADCVOLL_N71PT25DB \
  234. RV(FV_ADCVOLL_N71PT25DB, FB_ADCVOLL)
  235. #define RV_ADCVOLL_MUTE RV(FV_ADCVOLL_MUTE, FB_ADCVOLL)
  236. /*****************************
  237. * R_ADCVOLR (0x7) *
  238. *****************************/
  239. /* Field Offsets */
  240. #define FB_ADCVOLR 0
  241. /* Field Masks */
  242. #define FM_ADCVOLR 0XFF
  243. /* Field Values */
  244. #define FV_ADCVOLR_P24DB 0xFF
  245. #define FV_ADCVOLR_N71PT25DB 0x1
  246. #define FV_ADCVOLR_MUTE 0x0
  247. /* Register Masks */
  248. #define RM_ADCVOLR RM(FM_ADCVOLR, FB_ADCVOLR)
  249. /* Register Values */
  250. #define RV_ADCVOLR_P24DB RV(FV_ADCVOLR_P24DB, FB_ADCVOLR)
  251. #define RV_ADCVOLR_N71PT25DB \
  252. RV(FV_ADCVOLR_N71PT25DB, FB_ADCVOLR)
  253. #define RV_ADCVOLR_MUTE RV(FV_ADCVOLR_MUTE, FB_ADCVOLR)
  254. /****************************
  255. * R_INVOLL (0x8) *
  256. ****************************/
  257. /* Field Offsets */
  258. #define FB_INVOLL_INMUTEL 7
  259. #define FB_INVOLL_IZCL 6
  260. #define FB_INVOLL 0
  261. /* Field Masks */
  262. #define FM_INVOLL_INMUTEL 0X1
  263. #define FM_INVOLL_IZCL 0X1
  264. #define FM_INVOLL 0X3F
  265. /* Field Values */
  266. #define FV_INVOLL_INMUTEL_ENABLE 0x1
  267. #define FV_INVOLL_INMUTEL_DISABLE 0x0
  268. #define FV_INVOLL_IZCL_ENABLE 0x1
  269. #define FV_INVOLL_IZCL_DISABLE 0x0
  270. #define FV_INVOLL_P30DB 0x3F
  271. #define FV_INVOLL_N17PT25DB 0x0
  272. /* Register Masks */
  273. #define RM_INVOLL_INMUTEL \
  274. RM(FM_INVOLL_INMUTEL, FB_INVOLL_INMUTEL)
  275. #define RM_INVOLL_IZCL RM(FM_INVOLL_IZCL, FB_INVOLL_IZCL)
  276. #define RM_INVOLL RM(FM_INVOLL, FB_INVOLL)
  277. /* Register Values */
  278. #define RV_INVOLL_INMUTEL_ENABLE \
  279. RV(FV_INVOLL_INMUTEL_ENABLE, FB_INVOLL_INMUTEL)
  280. #define RV_INVOLL_INMUTEL_DISABLE \
  281. RV(FV_INVOLL_INMUTEL_DISABLE, FB_INVOLL_INMUTEL)
  282. #define RV_INVOLL_IZCL_ENABLE \
  283. RV(FV_INVOLL_IZCL_ENABLE, FB_INVOLL_IZCL)
  284. #define RV_INVOLL_IZCL_DISABLE \
  285. RV(FV_INVOLL_IZCL_DISABLE, FB_INVOLL_IZCL)
  286. #define RV_INVOLL_P30DB RV(FV_INVOLL_P30DB, FB_INVOLL)
  287. #define RV_INVOLL_N17PT25DB RV(FV_INVOLL_N17PT25DB, FB_INVOLL)
  288. /****************************
  289. * R_INVOLR (0x9) *
  290. ****************************/
  291. /* Field Offsets */
  292. #define FB_INVOLR_INMUTER 7
  293. #define FB_INVOLR_IZCR 6
  294. #define FB_INVOLR 0
  295. /* Field Masks */
  296. #define FM_INVOLR_INMUTER 0X1
  297. #define FM_INVOLR_IZCR 0X1
  298. #define FM_INVOLR 0X3F
  299. /* Field Values */
  300. #define FV_INVOLR_INMUTER_ENABLE 0x1
  301. #define FV_INVOLR_INMUTER_DISABLE 0x0
  302. #define FV_INVOLR_IZCR_ENABLE 0x1
  303. #define FV_INVOLR_IZCR_DISABLE 0x0
  304. #define FV_INVOLR_P30DB 0x3F
  305. #define FV_INVOLR_N17PT25DB 0x0
  306. /* Register Masks */
  307. #define RM_INVOLR_INMUTER \
  308. RM(FM_INVOLR_INMUTER, FB_INVOLR_INMUTER)
  309. #define RM_INVOLR_IZCR RM(FM_INVOLR_IZCR, FB_INVOLR_IZCR)
  310. #define RM_INVOLR RM(FM_INVOLR, FB_INVOLR)
  311. /* Register Values */
  312. #define RV_INVOLR_INMUTER_ENABLE \
  313. RV(FV_INVOLR_INMUTER_ENABLE, FB_INVOLR_INMUTER)
  314. #define RV_INVOLR_INMUTER_DISABLE \
  315. RV(FV_INVOLR_INMUTER_DISABLE, FB_INVOLR_INMUTER)
  316. #define RV_INVOLR_IZCR_ENABLE \
  317. RV(FV_INVOLR_IZCR_ENABLE, FB_INVOLR_IZCR)
  318. #define RV_INVOLR_IZCR_DISABLE \
  319. RV(FV_INVOLR_IZCR_DISABLE, FB_INVOLR_IZCR)
  320. #define RV_INVOLR_P30DB RV(FV_INVOLR_P30DB, FB_INVOLR)
  321. #define RV_INVOLR_N17PT25DB RV(FV_INVOLR_N17PT25DB, FB_INVOLR)
  322. /*****************************
  323. * R_INMODE (0x0B) *
  324. *****************************/
  325. /* Field Offsets */
  326. #define FB_INMODE_DS 0
  327. /* Field Masks */
  328. #define FM_INMODE_DS 0X1
  329. /* Field Values */
  330. #define FV_INMODE_DS_LRIN1 0x0
  331. #define FV_INMODE_DS_LRIN2 0x1
  332. /* Register Masks */
  333. #define RM_INMODE_DS RM(FM_INMODE_DS, FB_INMODE_DS)
  334. /* Register Values */
  335. #define RV_INMODE_DS_LRIN1 \
  336. RV(FV_INMODE_DS_LRIN1, FB_INMODE_DS)
  337. #define RV_INMODE_DS_LRIN2 \
  338. RV(FV_INMODE_DS_LRIN2, FB_INMODE_DS)
  339. /*****************************
  340. * R_INSELL (0x0C) *
  341. *****************************/
  342. /* Field Offsets */
  343. #define FB_INSELL 6
  344. #define FB_INSELL_MICBSTL 4
  345. /* Field Masks */
  346. #define FM_INSELL 0X3
  347. #define FM_INSELL_MICBSTL 0X3
  348. /* Field Values */
  349. #define FV_INSELL_IN1 0x0
  350. #define FV_INSELL_IN2 0x1
  351. #define FV_INSELL_IN3 0x2
  352. #define FV_INSELL_D2S 0x3
  353. #define FV_INSELL_MICBSTL_OFF 0x0
  354. #define FV_INSELL_MICBSTL_10DB 0x1
  355. #define FV_INSELL_MICBSTL_20DB 0x2
  356. #define FV_INSELL_MICBSTL_30DB 0x3
  357. /* Register Masks */
  358. #define RM_INSELL RM(FM_INSELL, FB_INSELL)
  359. #define RM_INSELL_MICBSTL \
  360. RM(FM_INSELL_MICBSTL, FB_INSELL_MICBSTL)
  361. /* Register Values */
  362. #define RV_INSELL_IN1 RV(FV_INSELL_IN1, FB_INSELL)
  363. #define RV_INSELL_IN2 RV(FV_INSELL_IN2, FB_INSELL)
  364. #define RV_INSELL_IN3 RV(FV_INSELL_IN3, FB_INSELL)
  365. #define RV_INSELL_D2S RV(FV_INSELL_D2S, FB_INSELL)
  366. #define RV_INSELL_MICBSTL_OFF \
  367. RV(FV_INSELL_MICBSTL_OFF, FB_INSELL_MICBSTL)
  368. #define RV_INSELL_MICBSTL_10DB \
  369. RV(FV_INSELL_MICBSTL_10DB, FB_INSELL_MICBSTL)
  370. #define RV_INSELL_MICBSTL_20DB \
  371. RV(FV_INSELL_MICBSTL_20DB, FB_INSELL_MICBSTL)
  372. #define RV_INSELL_MICBSTL_30DB \
  373. RV(FV_INSELL_MICBSTL_30DB, FB_INSELL_MICBSTL)
  374. /*****************************
  375. * R_INSELR (0x0D) *
  376. *****************************/
  377. /* Field Offsets */
  378. #define FB_INSELR 6
  379. #define FB_INSELR_MICBSTR 4
  380. /* Field Masks */
  381. #define FM_INSELR 0X3
  382. #define FM_INSELR_MICBSTR 0X3
  383. /* Field Values */
  384. #define FV_INSELR_IN1 0x0
  385. #define FV_INSELR_IN2 0x1
  386. #define FV_INSELR_IN3 0x2
  387. #define FV_INSELR_D2S 0x3
  388. #define FV_INSELR_MICBSTR_OFF 0x0
  389. #define FV_INSELR_MICBSTR_10DB 0x1
  390. #define FV_INSELR_MICBSTR_20DB 0x2
  391. #define FV_INSELR_MICBSTR_30DB 0x3
  392. /* Register Masks */
  393. #define RM_INSELR RM(FM_INSELR, FB_INSELR)
  394. #define RM_INSELR_MICBSTR \
  395. RM(FM_INSELR_MICBSTR, FB_INSELR_MICBSTR)
  396. /* Register Values */
  397. #define RV_INSELR_IN1 RV(FV_INSELR_IN1, FB_INSELR)
  398. #define RV_INSELR_IN2 RV(FV_INSELR_IN2, FB_INSELR)
  399. #define RV_INSELR_IN3 RV(FV_INSELR_IN3, FB_INSELR)
  400. #define RV_INSELR_D2S RV(FV_INSELR_D2S, FB_INSELR)
  401. #define RV_INSELR_MICBSTR_OFF \
  402. RV(FV_INSELR_MICBSTR_OFF, FB_INSELR_MICBSTR)
  403. #define RV_INSELR_MICBSTR_10DB \
  404. RV(FV_INSELR_MICBSTR_10DB, FB_INSELR_MICBSTR)
  405. #define RV_INSELR_MICBSTR_20DB \
  406. RV(FV_INSELR_MICBSTR_20DB, FB_INSELR_MICBSTR)
  407. #define RV_INSELR_MICBSTR_30DB \
  408. RV(FV_INSELR_MICBSTR_30DB, FB_INSELR_MICBSTR)
  409. /***************************
  410. * R_AIC1 (0x13) *
  411. ***************************/
  412. /* Field Offsets */
  413. #define FB_AIC1_BCLKINV 6
  414. #define FB_AIC1_MS 5
  415. #define FB_AIC1_LRP 4
  416. #define FB_AIC1_WL 2
  417. #define FB_AIC1_FORMAT 0
  418. /* Field Masks */
  419. #define FM_AIC1_BCLKINV 0X1
  420. #define FM_AIC1_MS 0X1
  421. #define FM_AIC1_LRP 0X1
  422. #define FM_AIC1_WL 0X3
  423. #define FM_AIC1_FORMAT 0X3
  424. /* Field Values */
  425. #define FV_AIC1_BCLKINV_ENABLE 0x1
  426. #define FV_AIC1_BCLKINV_DISABLE 0x0
  427. #define FV_AIC1_MS_MASTER 0x1
  428. #define FV_AIC1_MS_SLAVE 0x0
  429. #define FV_AIC1_LRP_INVERT 0x1
  430. #define FV_AIC1_LRP_NORMAL 0x0
  431. #define FV_AIC1_WL_16 0x0
  432. #define FV_AIC1_WL_20 0x1
  433. #define FV_AIC1_WL_24 0x2
  434. #define FV_AIC1_WL_32 0x3
  435. #define FV_AIC1_FORMAT_RIGHT 0x0
  436. #define FV_AIC1_FORMAT_LEFT 0x1
  437. #define FV_AIC1_FORMAT_I2S 0x2
  438. /* Register Masks */
  439. #define RM_AIC1_BCLKINV \
  440. RM(FM_AIC1_BCLKINV, FB_AIC1_BCLKINV)
  441. #define RM_AIC1_MS RM(FM_AIC1_MS, FB_AIC1_MS)
  442. #define RM_AIC1_LRP RM(FM_AIC1_LRP, FB_AIC1_LRP)
  443. #define RM_AIC1_WL RM(FM_AIC1_WL, FB_AIC1_WL)
  444. #define RM_AIC1_FORMAT RM(FM_AIC1_FORMAT, FB_AIC1_FORMAT)
  445. /* Register Values */
  446. #define RV_AIC1_BCLKINV_ENABLE \
  447. RV(FV_AIC1_BCLKINV_ENABLE, FB_AIC1_BCLKINV)
  448. #define RV_AIC1_BCLKINV_DISABLE \
  449. RV(FV_AIC1_BCLKINV_DISABLE, FB_AIC1_BCLKINV)
  450. #define RV_AIC1_MS_MASTER RV(FV_AIC1_MS_MASTER, FB_AIC1_MS)
  451. #define RV_AIC1_MS_SLAVE RV(FV_AIC1_MS_SLAVE, FB_AIC1_MS)
  452. #define RV_AIC1_LRP_INVERT \
  453. RV(FV_AIC1_LRP_INVERT, FB_AIC1_LRP)
  454. #define RV_AIC1_LRP_NORMAL \
  455. RV(FV_AIC1_LRP_NORMAL, FB_AIC1_LRP)
  456. #define RV_AIC1_WL_16 RV(FV_AIC1_WL_16, FB_AIC1_WL)
  457. #define RV_AIC1_WL_20 RV(FV_AIC1_WL_20, FB_AIC1_WL)
  458. #define RV_AIC1_WL_24 RV(FV_AIC1_WL_24, FB_AIC1_WL)
  459. #define RV_AIC1_WL_32 RV(FV_AIC1_WL_32, FB_AIC1_WL)
  460. #define RV_AIC1_FORMAT_RIGHT \
  461. RV(FV_AIC1_FORMAT_RIGHT, FB_AIC1_FORMAT)
  462. #define RV_AIC1_FORMAT_LEFT \
  463. RV(FV_AIC1_FORMAT_LEFT, FB_AIC1_FORMAT)
  464. #define RV_AIC1_FORMAT_I2S \
  465. RV(FV_AIC1_FORMAT_I2S, FB_AIC1_FORMAT)
  466. /***************************
  467. * R_AIC2 (0x14) *
  468. ***************************/
  469. /* Field Offsets */
  470. #define FB_AIC2_DACDSEL 6
  471. #define FB_AIC2_ADCDSEL 4
  472. #define FB_AIC2_TRI 3
  473. #define FB_AIC2_BLRCM 0
  474. /* Field Masks */
  475. #define FM_AIC2_DACDSEL 0X3
  476. #define FM_AIC2_ADCDSEL 0X3
  477. #define FM_AIC2_TRI 0X1
  478. #define FM_AIC2_BLRCM 0X7
  479. /* Field Values */
  480. #define FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED 0x3
  481. /* Register Masks */
  482. #define RM_AIC2_DACDSEL \
  483. RM(FM_AIC2_DACDSEL, FB_AIC2_DACDSEL)
  484. #define RM_AIC2_ADCDSEL \
  485. RM(FM_AIC2_ADCDSEL, FB_AIC2_ADCDSEL)
  486. #define RM_AIC2_TRI RM(FM_AIC2_TRI, FB_AIC2_TRI)
  487. #define RM_AIC2_BLRCM RM(FM_AIC2_BLRCM, FB_AIC2_BLRCM)
  488. /* Register Values */
  489. #define RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED \
  490. RV(FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED, FB_AIC2_BLRCM)
  491. /******************************
  492. * R_CNVRTR0 (0x16) *
  493. ******************************/
  494. /* Field Offsets */
  495. #define FB_CNVRTR0_ADCPOLR 7
  496. #define FB_CNVRTR0_ADCPOLL 6
  497. #define FB_CNVRTR0_AMONOMIX 4
  498. #define FB_CNVRTR0_ADCMU 3
  499. #define FB_CNVRTR0_HPOR 2
  500. #define FB_CNVRTR0_ADCHPDR 1
  501. #define FB_CNVRTR0_ADCHPDL 0
  502. /* Field Masks */
  503. #define FM_CNVRTR0_ADCPOLR 0X1
  504. #define FM_CNVRTR0_ADCPOLL 0X1
  505. #define FM_CNVRTR0_AMONOMIX 0X3
  506. #define FM_CNVRTR0_ADCMU 0X1
  507. #define FM_CNVRTR0_HPOR 0X1
  508. #define FM_CNVRTR0_ADCHPDR 0X1
  509. #define FM_CNVRTR0_ADCHPDL 0X1
  510. /* Field Values */
  511. #define FV_CNVRTR0_ADCPOLR_INVERT 0x1
  512. #define FV_CNVRTR0_ADCPOLR_NORMAL 0x0
  513. #define FV_CNVRTR0_ADCPOLL_INVERT 0x1
  514. #define FV_CNVRTR0_ADCPOLL_NORMAL 0x0
  515. #define FV_CNVRTR0_ADCMU_ENABLE 0x1
  516. #define FV_CNVRTR0_ADCMU_DISABLE 0x0
  517. #define FV_CNVRTR0_ADCHPDR_ENABLE 0x1
  518. #define FV_CNVRTR0_ADCHPDR_DISABLE 0x0
  519. #define FV_CNVRTR0_ADCHPDL_ENABLE 0x1
  520. #define FV_CNVRTR0_ADCHPDL_DISABLE 0x0
  521. /* Register Masks */
  522. #define RM_CNVRTR0_ADCPOLR \
  523. RM(FM_CNVRTR0_ADCPOLR, FB_CNVRTR0_ADCPOLR)
  524. #define RM_CNVRTR0_ADCPOLL \
  525. RM(FM_CNVRTR0_ADCPOLL, FB_CNVRTR0_ADCPOLL)
  526. #define RM_CNVRTR0_AMONOMIX \
  527. RM(FM_CNVRTR0_AMONOMIX, FB_CNVRTR0_AMONOMIX)
  528. #define RM_CNVRTR0_ADCMU \
  529. RM(FM_CNVRTR0_ADCMU, FB_CNVRTR0_ADCMU)
  530. #define RM_CNVRTR0_HPOR \
  531. RM(FM_CNVRTR0_HPOR, FB_CNVRTR0_HPOR)
  532. #define RM_CNVRTR0_ADCHPDR \
  533. RM(FM_CNVRTR0_ADCHPDR, FB_CNVRTR0_ADCHPDR)
  534. #define RM_CNVRTR0_ADCHPDL \
  535. RM(FM_CNVRTR0_ADCHPDL, FB_CNVRTR0_ADCHPDL)
  536. /* Register Values */
  537. #define RV_CNVRTR0_ADCPOLR_INVERT \
  538. RV(FV_CNVRTR0_ADCPOLR_INVERT, FB_CNVRTR0_ADCPOLR)
  539. #define RV_CNVRTR0_ADCPOLR_NORMAL \
  540. RV(FV_CNVRTR0_ADCPOLR_NORMAL, FB_CNVRTR0_ADCPOLR)
  541. #define RV_CNVRTR0_ADCPOLL_INVERT \
  542. RV(FV_CNVRTR0_ADCPOLL_INVERT, FB_CNVRTR0_ADCPOLL)
  543. #define RV_CNVRTR0_ADCPOLL_NORMAL \
  544. RV(FV_CNVRTR0_ADCPOLL_NORMAL, FB_CNVRTR0_ADCPOLL)
  545. #define RV_CNVRTR0_ADCMU_ENABLE \
  546. RV(FV_CNVRTR0_ADCMU_ENABLE, FB_CNVRTR0_ADCMU)
  547. #define RV_CNVRTR0_ADCMU_DISABLE \
  548. RV(FV_CNVRTR0_ADCMU_DISABLE, FB_CNVRTR0_ADCMU)
  549. #define RV_CNVRTR0_ADCHPDR_ENABLE \
  550. RV(FV_CNVRTR0_ADCHPDR_ENABLE, FB_CNVRTR0_ADCHPDR)
  551. #define RV_CNVRTR0_ADCHPDR_DISABLE \
  552. RV(FV_CNVRTR0_ADCHPDR_DISABLE, FB_CNVRTR0_ADCHPDR)
  553. #define RV_CNVRTR0_ADCHPDL_ENABLE \
  554. RV(FV_CNVRTR0_ADCHPDL_ENABLE, FB_CNVRTR0_ADCHPDL)
  555. #define RV_CNVRTR0_ADCHPDL_DISABLE \
  556. RV(FV_CNVRTR0_ADCHPDL_DISABLE, FB_CNVRTR0_ADCHPDL)
  557. /****************************
  558. * R_ADCSR (0x17) *
  559. ****************************/
  560. /* Field Offsets */
  561. #define FB_ADCSR_ABCM 6
  562. #define FB_ADCSR_ABR 3
  563. #define FB_ADCSR_ABM 0
  564. /* Field Masks */
  565. #define FM_ADCSR_ABCM 0X3
  566. #define FM_ADCSR_ABR 0X3
  567. #define FM_ADCSR_ABM 0X7
  568. /* Field Values */
  569. #define FV_ADCSR_ABCM_AUTO 0x0
  570. #define FV_ADCSR_ABCM_32 0x1
  571. #define FV_ADCSR_ABCM_40 0x2
  572. #define FV_ADCSR_ABCM_64 0x3
  573. #define FV_ADCSR_ABR_32 0x0
  574. #define FV_ADCSR_ABR_44_1 0x1
  575. #define FV_ADCSR_ABR_48 0x2
  576. #define FV_ADCSR_ABM_PT25 0x0
  577. #define FV_ADCSR_ABM_PT5 0x1
  578. #define FV_ADCSR_ABM_1 0x2
  579. #define FV_ADCSR_ABM_2 0x3
  580. /* Register Masks */
  581. #define RM_ADCSR_ABCM RM(FM_ADCSR_ABCM, FB_ADCSR_ABCM)
  582. #define RM_ADCSR_ABR RM(FM_ADCSR_ABR, FB_ADCSR_ABR)
  583. #define RM_ADCSR_ABM RM(FM_ADCSR_ABM, FB_ADCSR_ABM)
  584. /* Register Values */
  585. #define RV_ADCSR_ABCM_AUTO \
  586. RV(FV_ADCSR_ABCM_AUTO, FB_ADCSR_ABCM)
  587. #define RV_ADCSR_ABCM_32 \
  588. RV(FV_ADCSR_ABCM_32, FB_ADCSR_ABCM)
  589. #define RV_ADCSR_ABCM_40 \
  590. RV(FV_ADCSR_ABCM_40, FB_ADCSR_ABCM)
  591. #define RV_ADCSR_ABCM_64 \
  592. RV(FV_ADCSR_ABCM_64, FB_ADCSR_ABCM)
  593. #define RV_ADCSR_ABR_32 RV(FV_ADCSR_ABR_32, FB_ADCSR_ABR)
  594. #define RV_ADCSR_ABR_44_1 \
  595. RV(FV_ADCSR_ABR_44_1, FB_ADCSR_ABR)
  596. #define RV_ADCSR_ABR_48 RV(FV_ADCSR_ABR_48, FB_ADCSR_ABR)
  597. #define RV_ADCSR_ABR_ RV(FV_ADCSR_ABR_, FB_ADCSR_ABR)
  598. #define RV_ADCSR_ABM_PT25 \
  599. RV(FV_ADCSR_ABM_PT25, FB_ADCSR_ABM)
  600. #define RV_ADCSR_ABM_PT5 RV(FV_ADCSR_ABM_PT5, FB_ADCSR_ABM)
  601. #define RV_ADCSR_ABM_1 RV(FV_ADCSR_ABM_1, FB_ADCSR_ABM)
  602. #define RV_ADCSR_ABM_2 RV(FV_ADCSR_ABM_2, FB_ADCSR_ABM)
  603. /******************************
  604. * R_CNVRTR1 (0x18) *
  605. ******************************/
  606. /* Field Offsets */
  607. #define FB_CNVRTR1_DACPOLR 7
  608. #define FB_CNVRTR1_DACPOLL 6
  609. #define FB_CNVRTR1_DMONOMIX 4
  610. #define FB_CNVRTR1_DACMU 3
  611. #define FB_CNVRTR1_DEEMPH 2
  612. #define FB_CNVRTR1_DACDITH 0
  613. /* Field Masks */
  614. #define FM_CNVRTR1_DACPOLR 0X1
  615. #define FM_CNVRTR1_DACPOLL 0X1
  616. #define FM_CNVRTR1_DMONOMIX 0X3
  617. #define FM_CNVRTR1_DACMU 0X1
  618. #define FM_CNVRTR1_DEEMPH 0X1
  619. #define FM_CNVRTR1_DACDITH 0X3
  620. /* Field Values */
  621. #define FV_CNVRTR1_DACPOLR_INVERT 0x1
  622. #define FV_CNVRTR1_DACPOLR_NORMAL 0x0
  623. #define FV_CNVRTR1_DACPOLL_INVERT 0x1
  624. #define FV_CNVRTR1_DACPOLL_NORMAL 0x0
  625. #define FV_CNVRTR1_DMONOMIX_ENABLE 0x1
  626. #define FV_CNVRTR1_DMONOMIX_DISABLE 0x0
  627. #define FV_CNVRTR1_DACMU_ENABLE 0x1
  628. #define FV_CNVRTR1_DACMU_DISABLE 0x0
  629. /* Register Masks */
  630. #define RM_CNVRTR1_DACPOLR \
  631. RM(FM_CNVRTR1_DACPOLR, FB_CNVRTR1_DACPOLR)
  632. #define RM_CNVRTR1_DACPOLL \
  633. RM(FM_CNVRTR1_DACPOLL, FB_CNVRTR1_DACPOLL)
  634. #define RM_CNVRTR1_DMONOMIX \
  635. RM(FM_CNVRTR1_DMONOMIX, FB_CNVRTR1_DMONOMIX)
  636. #define RM_CNVRTR1_DACMU \
  637. RM(FM_CNVRTR1_DACMU, FB_CNVRTR1_DACMU)
  638. #define RM_CNVRTR1_DEEMPH \
  639. RM(FM_CNVRTR1_DEEMPH, FB_CNVRTR1_DEEMPH)
  640. #define RM_CNVRTR1_DACDITH \
  641. RM(FM_CNVRTR1_DACDITH, FB_CNVRTR1_DACDITH)
  642. /* Register Values */
  643. #define RV_CNVRTR1_DACPOLR_INVERT \
  644. RV(FV_CNVRTR1_DACPOLR_INVERT, FB_CNVRTR1_DACPOLR)
  645. #define RV_CNVRTR1_DACPOLR_NORMAL \
  646. RV(FV_CNVRTR1_DACPOLR_NORMAL, FB_CNVRTR1_DACPOLR)
  647. #define RV_CNVRTR1_DACPOLL_INVERT \
  648. RV(FV_CNVRTR1_DACPOLL_INVERT, FB_CNVRTR1_DACPOLL)
  649. #define RV_CNVRTR1_DACPOLL_NORMAL \
  650. RV(FV_CNVRTR1_DACPOLL_NORMAL, FB_CNVRTR1_DACPOLL)
  651. #define RV_CNVRTR1_DMONOMIX_ENABLE \
  652. RV(FV_CNVRTR1_DMONOMIX_ENABLE, FB_CNVRTR1_DMONOMIX)
  653. #define RV_CNVRTR1_DMONOMIX_DISABLE \
  654. RV(FV_CNVRTR1_DMONOMIX_DISABLE, FB_CNVRTR1_DMONOMIX)
  655. #define RV_CNVRTR1_DACMU_ENABLE \
  656. RV(FV_CNVRTR1_DACMU_ENABLE, FB_CNVRTR1_DACMU)
  657. #define RV_CNVRTR1_DACMU_DISABLE \
  658. RV(FV_CNVRTR1_DACMU_DISABLE, FB_CNVRTR1_DACMU)
  659. /****************************
  660. * R_DACSR (0x19) *
  661. ****************************/
  662. /* Field Offsets */
  663. #define FB_DACSR_DBCM 6
  664. #define FB_DACSR_DBR 3
  665. #define FB_DACSR_DBM 0
  666. /* Field Masks */
  667. #define FM_DACSR_DBCM 0X3
  668. #define FM_DACSR_DBR 0X3
  669. #define FM_DACSR_DBM 0X7
  670. /* Field Values */
  671. #define FV_DACSR_DBCM_AUTO 0x0
  672. #define FV_DACSR_DBCM_32 0x1
  673. #define FV_DACSR_DBCM_40 0x2
  674. #define FV_DACSR_DBCM_64 0x3
  675. #define FV_DACSR_DBR_32 0x0
  676. #define FV_DACSR_DBR_44_1 0x1
  677. #define FV_DACSR_DBR_48 0x2
  678. #define FV_DACSR_DBM_PT25 0x0
  679. #define FV_DACSR_DBM_PT5 0x1
  680. #define FV_DACSR_DBM_1 0x2
  681. #define FV_DACSR_DBM_2 0x3
  682. /* Register Masks */
  683. #define RM_DACSR_DBCM RM(FM_DACSR_DBCM, FB_DACSR_DBCM)
  684. #define RM_DACSR_DBR RM(FM_DACSR_DBR, FB_DACSR_DBR)
  685. #define RM_DACSR_DBM RM(FM_DACSR_DBM, FB_DACSR_DBM)
  686. /* Register Values */
  687. #define RV_DACSR_DBCM_AUTO \
  688. RV(FV_DACSR_DBCM_AUTO, FB_DACSR_DBCM)
  689. #define RV_DACSR_DBCM_32 \
  690. RV(FV_DACSR_DBCM_32, FB_DACSR_DBCM)
  691. #define RV_DACSR_DBCM_40 \
  692. RV(FV_DACSR_DBCM_40, FB_DACSR_DBCM)
  693. #define RV_DACSR_DBCM_64 \
  694. RV(FV_DACSR_DBCM_64, FB_DACSR_DBCM)
  695. #define RV_DACSR_DBR_32 RV(FV_DACSR_DBR_32, FB_DACSR_DBR)
  696. #define RV_DACSR_DBR_44_1 \
  697. RV(FV_DACSR_DBR_44_1, FB_DACSR_DBR)
  698. #define RV_DACSR_DBR_48 RV(FV_DACSR_DBR_48, FB_DACSR_DBR)
  699. #define RV_DACSR_DBM_PT25 \
  700. RV(FV_DACSR_DBM_PT25, FB_DACSR_DBM)
  701. #define RV_DACSR_DBM_PT5 RV(FV_DACSR_DBM_PT5, FB_DACSR_DBM)
  702. #define RV_DACSR_DBM_1 RV(FV_DACSR_DBM_1, FB_DACSR_DBM)
  703. #define RV_DACSR_DBM_2 RV(FV_DACSR_DBM_2, FB_DACSR_DBM)
  704. /****************************
  705. * R_PWRM1 (0x1A) *
  706. ****************************/
  707. /* Field Offsets */
  708. #define FB_PWRM1_BSTL 7
  709. #define FB_PWRM1_BSTR 6
  710. #define FB_PWRM1_PGAL 5
  711. #define FB_PWRM1_PGAR 4
  712. #define FB_PWRM1_ADCL 3
  713. #define FB_PWRM1_ADCR 2
  714. #define FB_PWRM1_MICB 1
  715. #define FB_PWRM1_DIGENB 0
  716. /* Field Masks */
  717. #define FM_PWRM1_BSTL 0X1
  718. #define FM_PWRM1_BSTR 0X1
  719. #define FM_PWRM1_PGAL 0X1
  720. #define FM_PWRM1_PGAR 0X1
  721. #define FM_PWRM1_ADCL 0X1
  722. #define FM_PWRM1_ADCR 0X1
  723. #define FM_PWRM1_MICB 0X1
  724. #define FM_PWRM1_DIGENB 0X1
  725. /* Field Values */
  726. #define FV_PWRM1_BSTL_ENABLE 0x1
  727. #define FV_PWRM1_BSTL_DISABLE 0x0
  728. #define FV_PWRM1_BSTR_ENABLE 0x1
  729. #define FV_PWRM1_BSTR_DISABLE 0x0
  730. #define FV_PWRM1_PGAL_ENABLE 0x1
  731. #define FV_PWRM1_PGAL_DISABLE 0x0
  732. #define FV_PWRM1_PGAR_ENABLE 0x1
  733. #define FV_PWRM1_PGAR_DISABLE 0x0
  734. #define FV_PWRM1_ADCL_ENABLE 0x1
  735. #define FV_PWRM1_ADCL_DISABLE 0x0
  736. #define FV_PWRM1_ADCR_ENABLE 0x1
  737. #define FV_PWRM1_ADCR_DISABLE 0x0
  738. #define FV_PWRM1_MICB_ENABLE 0x1
  739. #define FV_PWRM1_MICB_DISABLE 0x0
  740. #define FV_PWRM1_DIGENB_DISABLE 0x1
  741. #define FV_PWRM1_DIGENB_ENABLE 0x0
  742. /* Register Masks */
  743. #define RM_PWRM1_BSTL RM(FM_PWRM1_BSTL, FB_PWRM1_BSTL)
  744. #define RM_PWRM1_BSTR RM(FM_PWRM1_BSTR, FB_PWRM1_BSTR)
  745. #define RM_PWRM1_PGAL RM(FM_PWRM1_PGAL, FB_PWRM1_PGAL)
  746. #define RM_PWRM1_PGAR RM(FM_PWRM1_PGAR, FB_PWRM1_PGAR)
  747. #define RM_PWRM1_ADCL RM(FM_PWRM1_ADCL, FB_PWRM1_ADCL)
  748. #define RM_PWRM1_ADCR RM(FM_PWRM1_ADCR, FB_PWRM1_ADCR)
  749. #define RM_PWRM1_MICB RM(FM_PWRM1_MICB, FB_PWRM1_MICB)
  750. #define RM_PWRM1_DIGENB \
  751. RM(FM_PWRM1_DIGENB, FB_PWRM1_DIGENB)
  752. /* Register Values */
  753. #define RV_PWRM1_BSTL_ENABLE \
  754. RV(FV_PWRM1_BSTL_ENABLE, FB_PWRM1_BSTL)
  755. #define RV_PWRM1_BSTL_DISABLE \
  756. RV(FV_PWRM1_BSTL_DISABLE, FB_PWRM1_BSTL)
  757. #define RV_PWRM1_BSTR_ENABLE \
  758. RV(FV_PWRM1_BSTR_ENABLE, FB_PWRM1_BSTR)
  759. #define RV_PWRM1_BSTR_DISABLE \
  760. RV(FV_PWRM1_BSTR_DISABLE, FB_PWRM1_BSTR)
  761. #define RV_PWRM1_PGAL_ENABLE \
  762. RV(FV_PWRM1_PGAL_ENABLE, FB_PWRM1_PGAL)
  763. #define RV_PWRM1_PGAL_DISABLE \
  764. RV(FV_PWRM1_PGAL_DISABLE, FB_PWRM1_PGAL)
  765. #define RV_PWRM1_PGAR_ENABLE \
  766. RV(FV_PWRM1_PGAR_ENABLE, FB_PWRM1_PGAR)
  767. #define RV_PWRM1_PGAR_DISABLE \
  768. RV(FV_PWRM1_PGAR_DISABLE, FB_PWRM1_PGAR)
  769. #define RV_PWRM1_ADCL_ENABLE \
  770. RV(FV_PWRM1_ADCL_ENABLE, FB_PWRM1_ADCL)
  771. #define RV_PWRM1_ADCL_DISABLE \
  772. RV(FV_PWRM1_ADCL_DISABLE, FB_PWRM1_ADCL)
  773. #define RV_PWRM1_ADCR_ENABLE \
  774. RV(FV_PWRM1_ADCR_ENABLE, FB_PWRM1_ADCR)
  775. #define RV_PWRM1_ADCR_DISABLE \
  776. RV(FV_PWRM1_ADCR_DISABLE, FB_PWRM1_ADCR)
  777. #define RV_PWRM1_MICB_ENABLE \
  778. RV(FV_PWRM1_MICB_ENABLE, FB_PWRM1_MICB)
  779. #define RV_PWRM1_MICB_DISABLE \
  780. RV(FV_PWRM1_MICB_DISABLE, FB_PWRM1_MICB)
  781. #define RV_PWRM1_DIGENB_DISABLE \
  782. RV(FV_PWRM1_DIGENB_DISABLE, FB_PWRM1_DIGENB)
  783. #define RV_PWRM1_DIGENB_ENABLE \
  784. RV(FV_PWRM1_DIGENB_ENABLE, FB_PWRM1_DIGENB)
  785. /****************************
  786. * R_PWRM2 (0x1B) *
  787. ****************************/
  788. /* Field Offsets */
  789. #define FB_PWRM2_D2S 7
  790. #define FB_PWRM2_HPL 6
  791. #define FB_PWRM2_HPR 5
  792. #define FB_PWRM2_SPKL 4
  793. #define FB_PWRM2_SPKR 3
  794. #define FB_PWRM2_INSELL 2
  795. #define FB_PWRM2_INSELR 1
  796. #define FB_PWRM2_VREF 0
  797. /* Field Masks */
  798. #define FM_PWRM2_D2S 0X1
  799. #define FM_PWRM2_HPL 0X1
  800. #define FM_PWRM2_HPR 0X1
  801. #define FM_PWRM2_SPKL 0X1
  802. #define FM_PWRM2_SPKR 0X1
  803. #define FM_PWRM2_INSELL 0X1
  804. #define FM_PWRM2_INSELR 0X1
  805. #define FM_PWRM2_VREF 0X1
  806. /* Field Values */
  807. #define FV_PWRM2_D2S_ENABLE 0x1
  808. #define FV_PWRM2_D2S_DISABLE 0x0
  809. #define FV_PWRM2_HPL_ENABLE 0x1
  810. #define FV_PWRM2_HPL_DISABLE 0x0
  811. #define FV_PWRM2_HPR_ENABLE 0x1
  812. #define FV_PWRM2_HPR_DISABLE 0x0
  813. #define FV_PWRM2_SPKL_ENABLE 0x1
  814. #define FV_PWRM2_SPKL_DISABLE 0x0
  815. #define FV_PWRM2_SPKR_ENABLE 0x1
  816. #define FV_PWRM2_SPKR_DISABLE 0x0
  817. #define FV_PWRM2_INSELL_ENABLE 0x1
  818. #define FV_PWRM2_INSELL_DISABLE 0x0
  819. #define FV_PWRM2_INSELR_ENABLE 0x1
  820. #define FV_PWRM2_INSELR_DISABLE 0x0
  821. #define FV_PWRM2_VREF_ENABLE 0x1
  822. #define FV_PWRM2_VREF_DISABLE 0x0
  823. /* Register Masks */
  824. #define RM_PWRM2_D2S RM(FM_PWRM2_D2S, FB_PWRM2_D2S)
  825. #define RM_PWRM2_HPL RM(FM_PWRM2_HPL, FB_PWRM2_HPL)
  826. #define RM_PWRM2_HPR RM(FM_PWRM2_HPR, FB_PWRM2_HPR)
  827. #define RM_PWRM2_SPKL RM(FM_PWRM2_SPKL, FB_PWRM2_SPKL)
  828. #define RM_PWRM2_SPKR RM(FM_PWRM2_SPKR, FB_PWRM2_SPKR)
  829. #define RM_PWRM2_INSELL \
  830. RM(FM_PWRM2_INSELL, FB_PWRM2_INSELL)
  831. #define RM_PWRM2_INSELR \
  832. RM(FM_PWRM2_INSELR, FB_PWRM2_INSELR)
  833. #define RM_PWRM2_VREF RM(FM_PWRM2_VREF, FB_PWRM2_VREF)
  834. /* Register Values */
  835. #define RV_PWRM2_D2S_ENABLE \
  836. RV(FV_PWRM2_D2S_ENABLE, FB_PWRM2_D2S)
  837. #define RV_PWRM2_D2S_DISABLE \
  838. RV(FV_PWRM2_D2S_DISABLE, FB_PWRM2_D2S)
  839. #define RV_PWRM2_HPL_ENABLE \
  840. RV(FV_PWRM2_HPL_ENABLE, FB_PWRM2_HPL)
  841. #define RV_PWRM2_HPL_DISABLE \
  842. RV(FV_PWRM2_HPL_DISABLE, FB_PWRM2_HPL)
  843. #define RV_PWRM2_HPR_ENABLE \
  844. RV(FV_PWRM2_HPR_ENABLE, FB_PWRM2_HPR)
  845. #define RV_PWRM2_HPR_DISABLE \
  846. RV(FV_PWRM2_HPR_DISABLE, FB_PWRM2_HPR)
  847. #define RV_PWRM2_SPKL_ENABLE \
  848. RV(FV_PWRM2_SPKL_ENABLE, FB_PWRM2_SPKL)
  849. #define RV_PWRM2_SPKL_DISABLE \
  850. RV(FV_PWRM2_SPKL_DISABLE, FB_PWRM2_SPKL)
  851. #define RV_PWRM2_SPKR_ENABLE \
  852. RV(FV_PWRM2_SPKR_ENABLE, FB_PWRM2_SPKR)
  853. #define RV_PWRM2_SPKR_DISABLE \
  854. RV(FV_PWRM2_SPKR_DISABLE, FB_PWRM2_SPKR)
  855. #define RV_PWRM2_INSELL_ENABLE \
  856. RV(FV_PWRM2_INSELL_ENABLE, FB_PWRM2_INSELL)
  857. #define RV_PWRM2_INSELL_DISABLE \
  858. RV(FV_PWRM2_INSELL_DISABLE, FB_PWRM2_INSELL)
  859. #define RV_PWRM2_INSELR_ENABLE \
  860. RV(FV_PWRM2_INSELR_ENABLE, FB_PWRM2_INSELR)
  861. #define RV_PWRM2_INSELR_DISABLE \
  862. RV(FV_PWRM2_INSELR_DISABLE, FB_PWRM2_INSELR)
  863. #define RV_PWRM2_VREF_ENABLE \
  864. RV(FV_PWRM2_VREF_ENABLE, FB_PWRM2_VREF)
  865. #define RV_PWRM2_VREF_DISABLE \
  866. RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
  867. /******************************
  868. * R_CTL (0x1C) *
  869. ******************************/
  870. /* Fiel Offsets */
  871. #define FB_CTL_HPSWEN 7
  872. #define FB_CTL_HPSWPOL 6
  873. /******************************
  874. * R_CONFIG0 (0x1F) *
  875. ******************************/
  876. /* Field Offsets */
  877. #define FB_CONFIG0_ASDM 6
  878. #define FB_CONFIG0_DSDM 4
  879. #define FB_CONFIG0_DC_BYPASS 1
  880. #define FB_CONFIG0_SD_FORCE_ON 0
  881. /* Field Masks */
  882. #define FM_CONFIG0_ASDM 0X3
  883. #define FM_CONFIG0_DSDM 0X3
  884. #define FM_CONFIG0_DC_BYPASS 0X1
  885. #define FM_CONFIG0_SD_FORCE_ON 0X1
  886. /* Field Values */
  887. #define FV_CONFIG0_ASDM_HALF 0x1
  888. #define FV_CONFIG0_ASDM_FULL 0x2
  889. #define FV_CONFIG0_ASDM_AUTO 0x3
  890. #define FV_CONFIG0_DSDM_HALF 0x1
  891. #define FV_CONFIG0_DSDM_FULL 0x2
  892. #define FV_CONFIG0_DSDM_AUTO 0x3
  893. #define FV_CONFIG0_DC_BYPASS_ENABLE 0x1
  894. #define FV_CONFIG0_DC_BYPASS_DISABLE 0x0
  895. #define FV_CONFIG0_SD_FORCE_ON_ENABLE 0x1
  896. #define FV_CONFIG0_SD_FORCE_ON_DISABLE 0x0
  897. /* Register Masks */
  898. #define RM_CONFIG0_ASDM \
  899. RM(FM_CONFIG0_ASDM, FB_CONFIG0_ASDM)
  900. #define RM_CONFIG0_DSDM \
  901. RM(FM_CONFIG0_DSDM, FB_CONFIG0_DSDM)
  902. #define RM_CONFIG0_DC_BYPASS \
  903. RM(FM_CONFIG0_DC_BYPASS, FB_CONFIG0_DC_BYPASS)
  904. #define RM_CONFIG0_SD_FORCE_ON \
  905. RM(FM_CONFIG0_SD_FORCE_ON, FB_CONFIG0_SD_FORCE_ON)
  906. /* Register Values */
  907. #define RV_CONFIG0_ASDM_HALF \
  908. RV(FV_CONFIG0_ASDM_HALF, FB_CONFIG0_ASDM)
  909. #define RV_CONFIG0_ASDM_FULL \
  910. RV(FV_CONFIG0_ASDM_FULL, FB_CONFIG0_ASDM)
  911. #define RV_CONFIG0_ASDM_AUTO \
  912. RV(FV_CONFIG0_ASDM_AUTO, FB_CONFIG0_ASDM)
  913. #define RV_CONFIG0_DSDM_HALF \
  914. RV(FV_CONFIG0_DSDM_HALF, FB_CONFIG0_DSDM)
  915. #define RV_CONFIG0_DSDM_FULL \
  916. RV(FV_CONFIG0_DSDM_FULL, FB_CONFIG0_DSDM)
  917. #define RV_CONFIG0_DSDM_AUTO \
  918. RV(FV_CONFIG0_DSDM_AUTO, FB_CONFIG0_DSDM)
  919. #define RV_CONFIG0_DC_BYPASS_ENABLE \
  920. RV(FV_CONFIG0_DC_BYPASS_ENABLE, FB_CONFIG0_DC_BYPASS)
  921. #define RV_CONFIG0_DC_BYPASS_DISABLE \
  922. RV(FV_CONFIG0_DC_BYPASS_DISABLE, FB_CONFIG0_DC_BYPASS)
  923. #define RV_CONFIG0_SD_FORCE_ON_ENABLE \
  924. RV(FV_CONFIG0_SD_FORCE_ON_ENABLE, FB_CONFIG0_SD_FORCE_ON)
  925. #define RV_CONFIG0_SD_FORCE_ON_DISABLE \
  926. RV(FV_CONFIG0_SD_FORCE_ON_DISABLE, FB_CONFIG0_SD_FORCE_ON)
  927. /******************************
  928. * R_CONFIG1 (0x20) *
  929. ******************************/
  930. /* Field Offsets */
  931. #define FB_CONFIG1_EQ2_EN 7
  932. #define FB_CONFIG1_EQ2_BE 4
  933. #define FB_CONFIG1_EQ1_EN 3
  934. #define FB_CONFIG1_EQ1_BE 0
  935. /* Field Masks */
  936. #define FM_CONFIG1_EQ2_EN 0X1
  937. #define FM_CONFIG1_EQ2_BE 0X7
  938. #define FM_CONFIG1_EQ1_EN 0X1
  939. #define FM_CONFIG1_EQ1_BE 0X7
  940. /* Field Values */
  941. #define FV_CONFIG1_EQ2_EN_ENABLE 0x1
  942. #define FV_CONFIG1_EQ2_EN_DISABLE 0x0
  943. #define FV_CONFIG1_EQ2_BE_PRE 0x0
  944. #define FV_CONFIG1_EQ2_BE_PRE_EQ_0 0x1
  945. #define FV_CONFIG1_EQ2_BE_PRE_EQ0_1 0x2
  946. #define FV_CONFIG1_EQ2_BE_PRE_EQ0_2 0x3
  947. #define FV_CONFIG1_EQ2_BE_PRE_EQ0_3 0x4
  948. #define FV_CONFIG1_EQ2_BE_PRE_EQ0_4 0x5
  949. #define FV_CONFIG1_EQ2_BE_PRE_EQ0_5 0x6
  950. #define FV_CONFIG1_EQ1_EN_ENABLE 0x1
  951. #define FV_CONFIG1_EQ1_EN_DISABLE 0x0
  952. #define FV_CONFIG1_EQ1_BE_PRE 0x0
  953. #define FV_CONFIG1_EQ1_BE_PRE_EQ_0 0x1
  954. #define FV_CONFIG1_EQ1_BE_PRE_EQ0_1 0x2
  955. #define FV_CONFIG1_EQ1_BE_PRE_EQ0_2 0x3
  956. #define FV_CONFIG1_EQ1_BE_PRE_EQ0_3 0x4
  957. #define FV_CONFIG1_EQ1_BE_PRE_EQ0_4 0x5
  958. #define FV_CONFIG1_EQ1_BE_PRE_EQ0_5 0x6
  959. /* Register Masks */
  960. #define RM_CONFIG1_EQ2_EN \
  961. RM(FM_CONFIG1_EQ2_EN, FB_CONFIG1_EQ2_EN)
  962. #define RM_CONFIG1_EQ2_BE \
  963. RM(FM_CONFIG1_EQ2_BE, FB_CONFIG1_EQ2_BE)
  964. #define RM_CONFIG1_EQ1_EN \
  965. RM(FM_CONFIG1_EQ1_EN, FB_CONFIG1_EQ1_EN)
  966. #define RM_CONFIG1_EQ1_BE \
  967. RM(FM_CONFIG1_EQ1_BE, FB_CONFIG1_EQ1_BE)
  968. /* Register Values */
  969. #define RV_CONFIG1_EQ2_EN_ENABLE \
  970. RV(FV_CONFIG1_EQ2_EN_ENABLE, FB_CONFIG1_EQ2_EN)
  971. #define RV_CONFIG1_EQ2_EN_DISABLE \
  972. RV(FV_CONFIG1_EQ2_EN_DISABLE, FB_CONFIG1_EQ2_EN)
  973. #define RV_CONFIG1_EQ2_BE_PRE \
  974. RV(FV_CONFIG1_EQ2_BE_PRE, FB_CONFIG1_EQ2_BE)
  975. #define RV_CONFIG1_EQ2_BE_PRE_EQ_0 \
  976. RV(FV_CONFIG1_EQ2_BE_PRE_EQ_0, FB_CONFIG1_EQ2_BE)
  977. #define RV_CONFIG1_EQ2_BE_PRE_EQ0_1 \
  978. RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_1, FB_CONFIG1_EQ2_BE)
  979. #define RV_CONFIG1_EQ2_BE_PRE_EQ0_2 \
  980. RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_2, FB_CONFIG1_EQ2_BE)
  981. #define RV_CONFIG1_EQ2_BE_PRE_EQ0_3 \
  982. RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_3, FB_CONFIG1_EQ2_BE)
  983. #define RV_CONFIG1_EQ2_BE_PRE_EQ0_4 \
  984. RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_4, FB_CONFIG1_EQ2_BE)
  985. #define RV_CONFIG1_EQ2_BE_PRE_EQ0_5 \
  986. RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_5, FB_CONFIG1_EQ2_BE)
  987. #define RV_CONFIG1_EQ1_EN_ENABLE \
  988. RV(FV_CONFIG1_EQ1_EN_ENABLE, FB_CONFIG1_EQ1_EN)
  989. #define RV_CONFIG1_EQ1_EN_DISABLE \
  990. RV(FV_CONFIG1_EQ1_EN_DISABLE, FB_CONFIG1_EQ1_EN)
  991. #define RV_CONFIG1_EQ1_BE_PRE \
  992. RV(FV_CONFIG1_EQ1_BE_PRE, FB_CONFIG1_EQ1_BE)
  993. #define RV_CONFIG1_EQ1_BE_PRE_EQ_0 \
  994. RV(FV_CONFIG1_EQ1_BE_PRE_EQ_0, FB_CONFIG1_EQ1_BE)
  995. #define RV_CONFIG1_EQ1_BE_PRE_EQ0_1 \
  996. RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_1, FB_CONFIG1_EQ1_BE)
  997. #define RV_CONFIG1_EQ1_BE_PRE_EQ0_2 \
  998. RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_2, FB_CONFIG1_EQ1_BE)
  999. #define RV_CONFIG1_EQ1_BE_PRE_EQ0_3 \
  1000. RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_3, FB_CONFIG1_EQ1_BE)
  1001. #define RV_CONFIG1_EQ1_BE_PRE_EQ0_4 \
  1002. RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_4, FB_CONFIG1_EQ1_BE)
  1003. #define RV_CONFIG1_EQ1_BE_PRE_EQ0_5 \
  1004. RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_5, FB_CONFIG1_EQ1_BE)
  1005. /******************************
  1006. * R_DMICCTL (0x24) *
  1007. ******************************/
  1008. /* Field Offsets */
  1009. #define FB_DMICCTL_DMICEN 7
  1010. #define FB_DMICCTL_DMONO 4
  1011. #define FB_DMICCTL_DMPHADJ 2
  1012. #define FB_DMICCTL_DMRATE 0
  1013. /* Field Masks */
  1014. #define FM_DMICCTL_DMICEN 0X1
  1015. #define FM_DMICCTL_DMONO 0X1
  1016. #define FM_DMICCTL_DMPHADJ 0X3
  1017. #define FM_DMICCTL_DMRATE 0X3
  1018. /* Field Values */
  1019. #define FV_DMICCTL_DMICEN_ENABLE 0x1
  1020. #define FV_DMICCTL_DMICEN_DISABLE 0x0
  1021. #define FV_DMICCTL_DMONO_STEREO 0x0
  1022. #define FV_DMICCTL_DMONO_MONO 0x1
  1023. /* Register Masks */
  1024. #define RM_DMICCTL_DMICEN \
  1025. RM(FM_DMICCTL_DMICEN, FB_DMICCTL_DMICEN)
  1026. #define RM_DMICCTL_DMONO \
  1027. RM(FM_DMICCTL_DMONO, FB_DMICCTL_DMONO)
  1028. #define RM_DMICCTL_DMPHADJ \
  1029. RM(FM_DMICCTL_DMPHADJ, FB_DMICCTL_DMPHADJ)
  1030. #define RM_DMICCTL_DMRATE \
  1031. RM(FM_DMICCTL_DMRATE, FB_DMICCTL_DMRATE)
  1032. /* Register Values */
  1033. #define RV_DMICCTL_DMICEN_ENABLE \
  1034. RV(FV_DMICCTL_DMICEN_ENABLE, FB_DMICCTL_DMICEN)
  1035. #define RV_DMICCTL_DMICEN_DISABLE \
  1036. RV(FV_DMICCTL_DMICEN_DISABLE, FB_DMICCTL_DMICEN)
  1037. #define RV_DMICCTL_DMONO_STEREO \
  1038. RV(FV_DMICCTL_DMONO_STEREO, FB_DMICCTL_DMONO)
  1039. #define RV_DMICCTL_DMONO_MONO \
  1040. RV(FV_DMICCTL_DMONO_MONO, FB_DMICCTL_DMONO)
  1041. /*****************************
  1042. * R_CLECTL (0x25) *
  1043. *****************************/
  1044. /* Field Offsets */
  1045. #define FB_CLECTL_LVL_MODE 4
  1046. #define FB_CLECTL_WINDOWSEL 3
  1047. #define FB_CLECTL_EXP_EN 2
  1048. #define FB_CLECTL_LIMIT_EN 1
  1049. #define FB_CLECTL_COMP_EN 0
  1050. /* Field Masks */
  1051. #define FM_CLECTL_LVL_MODE 0X1
  1052. #define FM_CLECTL_WINDOWSEL 0X1
  1053. #define FM_CLECTL_EXP_EN 0X1
  1054. #define FM_CLECTL_LIMIT_EN 0X1
  1055. #define FM_CLECTL_COMP_EN 0X1
  1056. /* Field Values */
  1057. #define FV_CLECTL_LVL_MODE_AVG 0x0
  1058. #define FV_CLECTL_LVL_MODE_PEAK 0x1
  1059. #define FV_CLECTL_WINDOWSEL_512 0x0
  1060. #define FV_CLECTL_WINDOWSEL_64 0x1
  1061. #define FV_CLECTL_EXP_EN_ENABLE 0x1
  1062. #define FV_CLECTL_EXP_EN_DISABLE 0x0
  1063. #define FV_CLECTL_LIMIT_EN_ENABLE 0x1
  1064. #define FV_CLECTL_LIMIT_EN_DISABLE 0x0
  1065. #define FV_CLECTL_COMP_EN_ENABLE 0x1
  1066. #define FV_CLECTL_COMP_EN_DISABLE 0x0
  1067. /* Register Masks */
  1068. #define RM_CLECTL_LVL_MODE \
  1069. RM(FM_CLECTL_LVL_MODE, FB_CLECTL_LVL_MODE)
  1070. #define RM_CLECTL_WINDOWSEL \
  1071. RM(FM_CLECTL_WINDOWSEL, FB_CLECTL_WINDOWSEL)
  1072. #define RM_CLECTL_EXP_EN \
  1073. RM(FM_CLECTL_EXP_EN, FB_CLECTL_EXP_EN)
  1074. #define RM_CLECTL_LIMIT_EN \
  1075. RM(FM_CLECTL_LIMIT_EN, FB_CLECTL_LIMIT_EN)
  1076. #define RM_CLECTL_COMP_EN \
  1077. RM(FM_CLECTL_COMP_EN, FB_CLECTL_COMP_EN)
  1078. /* Register Values */
  1079. #define RV_CLECTL_LVL_MODE_AVG \
  1080. RV(FV_CLECTL_LVL_MODE_AVG, FB_CLECTL_LVL_MODE)
  1081. #define RV_CLECTL_LVL_MODE_PEAK \
  1082. RV(FV_CLECTL_LVL_MODE_PEAK, FB_CLECTL_LVL_MODE)
  1083. #define RV_CLECTL_WINDOWSEL_512 \
  1084. RV(FV_CLECTL_WINDOWSEL_512, FB_CLECTL_WINDOWSEL)
  1085. #define RV_CLECTL_WINDOWSEL_64 \
  1086. RV(FV_CLECTL_WINDOWSEL_64, FB_CLECTL_WINDOWSEL)
  1087. #define RV_CLECTL_EXP_EN_ENABLE \
  1088. RV(FV_CLECTL_EXP_EN_ENABLE, FB_CLECTL_EXP_EN)
  1089. #define RV_CLECTL_EXP_EN_DISABLE \
  1090. RV(FV_CLECTL_EXP_EN_DISABLE, FB_CLECTL_EXP_EN)
  1091. #define RV_CLECTL_LIMIT_EN_ENABLE \
  1092. RV(FV_CLECTL_LIMIT_EN_ENABLE, FB_CLECTL_LIMIT_EN)
  1093. #define RV_CLECTL_LIMIT_EN_DISABLE \
  1094. RV(FV_CLECTL_LIMIT_EN_DISABLE, FB_CLECTL_LIMIT_EN)
  1095. #define RV_CLECTL_COMP_EN_ENABLE \
  1096. RV(FV_CLECTL_COMP_EN_ENABLE, FB_CLECTL_COMP_EN)
  1097. #define RV_CLECTL_COMP_EN_DISABLE \
  1098. RV(FV_CLECTL_COMP_EN_DISABLE, FB_CLECTL_COMP_EN)
  1099. /*****************************
  1100. * R_MUGAIN (0x26) *
  1101. *****************************/
  1102. /* Field Offsets */
  1103. #define FB_MUGAIN_CLEMUG 0
  1104. /* Field Masks */
  1105. #define FM_MUGAIN_CLEMUG 0X1F
  1106. /* Field Values */
  1107. #define FV_MUGAIN_CLEMUG_46PT5DB 0x1F
  1108. #define FV_MUGAIN_CLEMUG_0DB 0x0
  1109. /* Register Masks */
  1110. #define RM_MUGAIN_CLEMUG \
  1111. RM(FM_MUGAIN_CLEMUG, FB_MUGAIN_CLEMUG)
  1112. /* Register Values */
  1113. #define RV_MUGAIN_CLEMUG_46PT5DB \
  1114. RV(FV_MUGAIN_CLEMUG_46PT5DB, FB_MUGAIN_CLEMUG)
  1115. #define RV_MUGAIN_CLEMUG_0DB \
  1116. RV(FV_MUGAIN_CLEMUG_0DB, FB_MUGAIN_CLEMUG)
  1117. /*****************************
  1118. * R_COMPTH (0x27) *
  1119. *****************************/
  1120. /* Field Offsets */
  1121. #define FB_COMPTH 0
  1122. /* Field Masks */
  1123. #define FM_COMPTH 0XFF
  1124. /* Field Values */
  1125. #define FV_COMPTH_0DB 0xFF
  1126. #define FV_COMPTH_N95PT625DB 0x0
  1127. /* Register Masks */
  1128. #define RM_COMPTH RM(FM_COMPTH, FB_COMPTH)
  1129. /* Register Values */
  1130. #define RV_COMPTH_0DB RV(FV_COMPTH_0DB, FB_COMPTH)
  1131. #define RV_COMPTH_N95PT625DB \
  1132. RV(FV_COMPTH_N95PT625DB, FB_COMPTH)
  1133. /*****************************
  1134. * R_CMPRAT (0x28) *
  1135. *****************************/
  1136. /* Field Offsets */
  1137. #define FB_CMPRAT 0
  1138. /* Field Masks */
  1139. #define FM_CMPRAT 0X1F
  1140. /* Register Masks */
  1141. #define RM_CMPRAT RM(FM_CMPRAT, FB_CMPRAT)
  1142. /******************************
  1143. * R_CATKTCL (0x29) *
  1144. ******************************/
  1145. /* Field Offsets */
  1146. #define FB_CATKTCL 0
  1147. /* Field Masks */
  1148. #define FM_CATKTCL 0XFF
  1149. /* Register Masks */
  1150. #define RM_CATKTCL RM(FM_CATKTCL, FB_CATKTCL)
  1151. /******************************
  1152. * R_CATKTCH (0x2A) *
  1153. ******************************/
  1154. /* Field Offsets */
  1155. #define FB_CATKTCH 0
  1156. /* Field Masks */
  1157. #define FM_CATKTCH 0XFF
  1158. /* Register Masks */
  1159. #define RM_CATKTCH RM(FM_CATKTCH, FB_CATKTCH)
  1160. /******************************
  1161. * R_CRELTCL (0x2B) *
  1162. ******************************/
  1163. /* Field Offsets */
  1164. #define FB_CRELTCL 0
  1165. /* Field Masks */
  1166. #define FM_CRELTCL 0XFF
  1167. /* Register Masks */
  1168. #define RM_CRELTCL RM(FM_CRELTCL, FB_CRELTCL)
  1169. /******************************
  1170. * R_CRELTCH (0x2C) *
  1171. ******************************/
  1172. /* Field Offsets */
  1173. #define FB_CRELTCH 0
  1174. /* Field Masks */
  1175. #define FM_CRELTCH 0XFF
  1176. /* Register Masks */
  1177. #define RM_CRELTCH RM(FM_CRELTCH, FB_CRELTCH)
  1178. /****************************
  1179. * R_LIMTH (0x2D) *
  1180. ****************************/
  1181. /* Field Offsets */
  1182. #define FB_LIMTH 0
  1183. /* Field Masks */
  1184. #define FM_LIMTH 0XFF
  1185. /* Field Values */
  1186. #define FV_LIMTH_0DB 0xFF
  1187. #define FV_LIMTH_N95PT625DB 0x0
  1188. /* Register Masks */
  1189. #define RM_LIMTH RM(FM_LIMTH, FB_LIMTH)
  1190. /* Register Values */
  1191. #define RV_LIMTH_0DB RV(FV_LIMTH_0DB, FB_LIMTH)
  1192. #define RV_LIMTH_N95PT625DB RV(FV_LIMTH_N95PT625DB, FB_LIMTH)
  1193. /*****************************
  1194. * R_LIMTGT (0x2E) *
  1195. *****************************/
  1196. /* Field Offsets */
  1197. #define FB_LIMTGT 0
  1198. /* Field Masks */
  1199. #define FM_LIMTGT 0XFF
  1200. /* Field Values */
  1201. #define FV_LIMTGT_0DB 0xFF
  1202. #define FV_LIMTGT_N95PT625DB 0x0
  1203. /* Register Masks */
  1204. #define RM_LIMTGT RM(FM_LIMTGT, FB_LIMTGT)
  1205. /* Register Values */
  1206. #define RV_LIMTGT_0DB RV(FV_LIMTGT_0DB, FB_LIMTGT)
  1207. #define RV_LIMTGT_N95PT625DB \
  1208. RV(FV_LIMTGT_N95PT625DB, FB_LIMTGT)
  1209. /******************************
  1210. * R_LATKTCL (0x2F) *
  1211. ******************************/
  1212. /* Field Offsets */
  1213. #define FB_LATKTCL 0
  1214. /* Field Masks */
  1215. #define FM_LATKTCL 0XFF
  1216. /* Register Masks */
  1217. #define RM_LATKTCL RM(FM_LATKTCL, FB_LATKTCL)
  1218. /******************************
  1219. * R_LATKTCH (0x30) *
  1220. ******************************/
  1221. /* Field Offsets */
  1222. #define FB_LATKTCH 0
  1223. /* Field Masks */
  1224. #define FM_LATKTCH 0XFF
  1225. /* Register Masks */
  1226. #define RM_LATKTCH RM(FM_LATKTCH, FB_LATKTCH)
  1227. /******************************
  1228. * R_LRELTCL (0x31) *
  1229. ******************************/
  1230. /* Field Offsets */
  1231. #define FB_LRELTCL 0
  1232. /* Field Masks */
  1233. #define FM_LRELTCL 0XFF
  1234. /* Register Masks */
  1235. #define RM_LRELTCL RM(FM_LRELTCL, FB_LRELTCL)
  1236. /******************************
  1237. * R_LRELTCH (0x32) *
  1238. ******************************/
  1239. /* Field Offsets */
  1240. #define FB_LRELTCH 0
  1241. /* Field Masks */
  1242. #define FM_LRELTCH 0XFF
  1243. /* Register Masks */
  1244. #define RM_LRELTCH RM(FM_LRELTCH, FB_LRELTCH)
  1245. /****************************
  1246. * R_EXPTH (0x33) *
  1247. ****************************/
  1248. /* Field Offsets */
  1249. #define FB_EXPTH 0
  1250. /* Field Masks */
  1251. #define FM_EXPTH 0XFF
  1252. /* Field Values */
  1253. #define FV_EXPTH_0DB 0xFF
  1254. #define FV_EXPTH_N95PT625DB 0x0
  1255. /* Register Masks */
  1256. #define RM_EXPTH RM(FM_EXPTH, FB_EXPTH)
  1257. /* Register Values */
  1258. #define RV_EXPTH_0DB RV(FV_EXPTH_0DB, FB_EXPTH)
  1259. #define RV_EXPTH_N95PT625DB RV(FV_EXPTH_N95PT625DB, FB_EXPTH)
  1260. /*****************************
  1261. * R_EXPRAT (0x34) *
  1262. *****************************/
  1263. /* Field Offsets */
  1264. #define FB_EXPRAT 0
  1265. /* Field Masks */
  1266. #define FM_EXPRAT 0X7
  1267. /* Register Masks */
  1268. #define RM_EXPRAT RM(FM_EXPRAT, FB_EXPRAT)
  1269. /******************************
  1270. * R_XATKTCL (0x35) *
  1271. ******************************/
  1272. /* Field Offsets */
  1273. #define FB_XATKTCL 0
  1274. /* Field Masks */
  1275. #define FM_XATKTCL 0XFF
  1276. /* Register Masks */
  1277. #define RM_XATKTCL RM(FM_XATKTCL, FB_XATKTCL)
  1278. /******************************
  1279. * R_XATKTCH (0x36) *
  1280. ******************************/
  1281. /* Field Offsets */
  1282. #define FB_XATKTCH 0
  1283. /* Field Masks */
  1284. #define FM_XATKTCH 0XFF
  1285. /* Register Masks */
  1286. #define RM_XATKTCH RM(FM_XATKTCH, FB_XATKTCH)
  1287. /******************************
  1288. * R_XRELTCL (0x37) *
  1289. ******************************/
  1290. /* Field Offsets */
  1291. #define FB_XRELTCL 0
  1292. /* Field Masks */
  1293. #define FM_XRELTCL 0XFF
  1294. /* Register Masks */
  1295. #define RM_XRELTCL RM(FM_XRELTCL, FB_XRELTCL)
  1296. /******************************
  1297. * R_XRELTCH (0x38) *
  1298. ******************************/
  1299. /* Field Offsets */
  1300. #define FB_XRELTCH 0
  1301. /* Field Masks */
  1302. #define FM_XRELTCH 0XFF
  1303. /* Register Masks */
  1304. #define RM_XRELTCH RM(FM_XRELTCH, FB_XRELTCH)
  1305. /****************************
  1306. * R_FXCTL (0x39) *
  1307. ****************************/
  1308. /* Field Offsets */
  1309. #define FB_FXCTL_3DEN 4
  1310. #define FB_FXCTL_TEEN 3
  1311. #define FB_FXCTL_TNLFBYPASS 2
  1312. #define FB_FXCTL_BEEN 1
  1313. #define FB_FXCTL_BNLFBYPASS 0
  1314. /* Field Masks */
  1315. #define FM_FXCTL_3DEN 0X1
  1316. #define FM_FXCTL_TEEN 0X1
  1317. #define FM_FXCTL_TNLFBYPASS 0X1
  1318. #define FM_FXCTL_BEEN 0X1
  1319. #define FM_FXCTL_BNLFBYPASS 0X1
  1320. /* Field Values */
  1321. #define FV_FXCTL_3DEN_ENABLE 0x1
  1322. #define FV_FXCTL_3DEN_DISABLE 0x0
  1323. #define FV_FXCTL_TEEN_ENABLE 0x1
  1324. #define FV_FXCTL_TEEN_DISABLE 0x0
  1325. #define FV_FXCTL_TNLFBYPASS_ENABLE 0x1
  1326. #define FV_FXCTL_TNLFBYPASS_DISABLE 0x0
  1327. #define FV_FXCTL_BEEN_ENABLE 0x1
  1328. #define FV_FXCTL_BEEN_DISABLE 0x0
  1329. #define FV_FXCTL_BNLFBYPASS_ENABLE 0x1
  1330. #define FV_FXCTL_BNLFBYPASS_DISABLE 0x0
  1331. /* Register Masks */
  1332. #define RM_FXCTL_3DEN RM(FM_FXCTL_3DEN, FB_FXCTL_3DEN)
  1333. #define RM_FXCTL_TEEN RM(FM_FXCTL_TEEN, FB_FXCTL_TEEN)
  1334. #define RM_FXCTL_TNLFBYPASS \
  1335. RM(FM_FXCTL_TNLFBYPASS, FB_FXCTL_TNLFBYPASS)
  1336. #define RM_FXCTL_BEEN RM(FM_FXCTL_BEEN, FB_FXCTL_BEEN)
  1337. #define RM_FXCTL_BNLFBYPASS \
  1338. RM(FM_FXCTL_BNLFBYPASS, FB_FXCTL_BNLFBYPASS)
  1339. /* Register Values */
  1340. #define RV_FXCTL_3DEN_ENABLE \
  1341. RV(FV_FXCTL_3DEN_ENABLE, FB_FXCTL_3DEN)
  1342. #define RV_FXCTL_3DEN_DISABLE \
  1343. RV(FV_FXCTL_3DEN_DISABLE, FB_FXCTL_3DEN)
  1344. #define RV_FXCTL_TEEN_ENABLE \
  1345. RV(FV_FXCTL_TEEN_ENABLE, FB_FXCTL_TEEN)
  1346. #define RV_FXCTL_TEEN_DISABLE \
  1347. RV(FV_FXCTL_TEEN_DISABLE, FB_FXCTL_TEEN)
  1348. #define RV_FXCTL_TNLFBYPASS_ENABLE \
  1349. RV(FV_FXCTL_TNLFBYPASS_ENABLE, FB_FXCTL_TNLFBYPASS)
  1350. #define RV_FXCTL_TNLFBYPASS_DISABLE \
  1351. RV(FV_FXCTL_TNLFBYPASS_DISABLE, FB_FXCTL_TNLFBYPASS)
  1352. #define RV_FXCTL_BEEN_ENABLE \
  1353. RV(FV_FXCTL_BEEN_ENABLE, FB_FXCTL_BEEN)
  1354. #define RV_FXCTL_BEEN_DISABLE \
  1355. RV(FV_FXCTL_BEEN_DISABLE, FB_FXCTL_BEEN)
  1356. #define RV_FXCTL_BNLFBYPASS_ENABLE \
  1357. RV(FV_FXCTL_BNLFBYPASS_ENABLE, FB_FXCTL_BNLFBYPASS)
  1358. #define RV_FXCTL_BNLFBYPASS_DISABLE \
  1359. RV(FV_FXCTL_BNLFBYPASS_DISABLE, FB_FXCTL_BNLFBYPASS)
  1360. /*******************************
  1361. * R_DACCRWRL (0x3A) *
  1362. *******************************/
  1363. /* Field Offsets */
  1364. #define FB_DACCRWRL_DACCRWDL 0
  1365. /* Field Masks */
  1366. #define FM_DACCRWRL_DACCRWDL 0XFF
  1367. /* Register Masks */
  1368. #define RM_DACCRWRL_DACCRWDL \
  1369. RM(FM_DACCRWRL_DACCRWDL, FB_DACCRWRL_DACCRWDL)
  1370. /*******************************
  1371. * R_DACCRWRM (0x3B) *
  1372. *******************************/
  1373. /* Field Offsets */
  1374. #define FB_DACCRWRM_DACCRWDM 0
  1375. /* Field Masks */
  1376. #define FM_DACCRWRM_DACCRWDM 0XFF
  1377. /* Register Masks */
  1378. #define RM_DACCRWRM_DACCRWDM \
  1379. RM(FM_DACCRWRM_DACCRWDM, FB_DACCRWRM_DACCRWDM)
  1380. /*******************************
  1381. * R_DACCRWRH (0x3C) *
  1382. *******************************/
  1383. /* Field Offsets */
  1384. #define FB_DACCRWRH_DACCRWDH 0
  1385. /* Field Masks */
  1386. #define FM_DACCRWRH_DACCRWDH 0XFF
  1387. /* Register Masks */
  1388. #define RM_DACCRWRH_DACCRWDH \
  1389. RM(FM_DACCRWRH_DACCRWDH, FB_DACCRWRH_DACCRWDH)
  1390. /*******************************
  1391. * R_DACCRRDL (0x3D) *
  1392. *******************************/
  1393. /* Field Offsets */
  1394. #define FB_DACCRRDL 0
  1395. /* Field Masks */
  1396. #define FM_DACCRRDL 0XFF
  1397. /* Register Masks */
  1398. #define RM_DACCRRDL RM(FM_DACCRRDL, FB_DACCRRDL)
  1399. /*******************************
  1400. * R_DACCRRDM (0x3E) *
  1401. *******************************/
  1402. /* Field Offsets */
  1403. #define FB_DACCRRDM 0
  1404. /* Field Masks */
  1405. #define FM_DACCRRDM 0XFF
  1406. /* Register Masks */
  1407. #define RM_DACCRRDM RM(FM_DACCRRDM, FB_DACCRRDM)
  1408. /*******************************
  1409. * R_DACCRRDH (0x3F) *
  1410. *******************************/
  1411. /* Field Offsets */
  1412. #define FB_DACCRRDH 0
  1413. /* Field Masks */
  1414. #define FM_DACCRRDH 0XFF
  1415. /* Register Masks */
  1416. #define RM_DACCRRDH RM(FM_DACCRRDH, FB_DACCRRDH)
  1417. /********************************
  1418. * R_DACCRADDR (0x40) *
  1419. ********************************/
  1420. /* Field Offsets */
  1421. #define FB_DACCRADDR_DACCRADD 0
  1422. /* Field Masks */
  1423. #define FM_DACCRADDR_DACCRADD 0XFF
  1424. /* Register Masks */
  1425. #define RM_DACCRADDR_DACCRADD \
  1426. RM(FM_DACCRADDR_DACCRADD, FB_DACCRADDR_DACCRADD)
  1427. /******************************
  1428. * R_DCOFSEL (0x41) *
  1429. ******************************/
  1430. /* Field Offsets */
  1431. #define FB_DCOFSEL_DC_COEF_SEL 0
  1432. /* Field Masks */
  1433. #define FM_DCOFSEL_DC_COEF_SEL 0X7
  1434. /* Field Values */
  1435. #define FV_DCOFSEL_DC_COEF_SEL_2_N8 0x0
  1436. #define FV_DCOFSEL_DC_COEF_SEL_2_N9 0x1
  1437. #define FV_DCOFSEL_DC_COEF_SEL_2_N10 0x2
  1438. #define FV_DCOFSEL_DC_COEF_SEL_2_N11 0x3
  1439. #define FV_DCOFSEL_DC_COEF_SEL_2_N12 0x4
  1440. #define FV_DCOFSEL_DC_COEF_SEL_2_N13 0x5
  1441. #define FV_DCOFSEL_DC_COEF_SEL_2_N14 0x6
  1442. #define FV_DCOFSEL_DC_COEF_SEL_2_N15 0x7
  1443. /* Register Masks */
  1444. #define RM_DCOFSEL_DC_COEF_SEL \
  1445. RM(FM_DCOFSEL_DC_COEF_SEL, FB_DCOFSEL_DC_COEF_SEL)
  1446. /* Register Values */
  1447. #define RV_DCOFSEL_DC_COEF_SEL_2_N8 \
  1448. RV(FV_DCOFSEL_DC_COEF_SEL_2_N8, FB_DCOFSEL_DC_COEF_SEL)
  1449. #define RV_DCOFSEL_DC_COEF_SEL_2_N9 \
  1450. RV(FV_DCOFSEL_DC_COEF_SEL_2_N9, FB_DCOFSEL_DC_COEF_SEL)
  1451. #define RV_DCOFSEL_DC_COEF_SEL_2_N10 \
  1452. RV(FV_DCOFSEL_DC_COEF_SEL_2_N10, FB_DCOFSEL_DC_COEF_SEL)
  1453. #define RV_DCOFSEL_DC_COEF_SEL_2_N11 \
  1454. RV(FV_DCOFSEL_DC_COEF_SEL_2_N11, FB_DCOFSEL_DC_COEF_SEL)
  1455. #define RV_DCOFSEL_DC_COEF_SEL_2_N12 \
  1456. RV(FV_DCOFSEL_DC_COEF_SEL_2_N12, FB_DCOFSEL_DC_COEF_SEL)
  1457. #define RV_DCOFSEL_DC_COEF_SEL_2_N13 \
  1458. RV(FV_DCOFSEL_DC_COEF_SEL_2_N13, FB_DCOFSEL_DC_COEF_SEL)
  1459. #define RV_DCOFSEL_DC_COEF_SEL_2_N14 \
  1460. RV(FV_DCOFSEL_DC_COEF_SEL_2_N14, FB_DCOFSEL_DC_COEF_SEL)
  1461. #define RV_DCOFSEL_DC_COEF_SEL_2_N15 \
  1462. RV(FV_DCOFSEL_DC_COEF_SEL_2_N15, FB_DCOFSEL_DC_COEF_SEL)
  1463. /******************************
  1464. * R_PLLCTL9 (0x4E) *
  1465. ******************************/
  1466. /* Field Offsets */
  1467. #define FB_PLLCTL9_REFDIV_PLL1 0
  1468. /* Field Masks */
  1469. #define FM_PLLCTL9_REFDIV_PLL1 0XFF
  1470. /* Register Masks */
  1471. #define RM_PLLCTL9_REFDIV_PLL1 \
  1472. RM(FM_PLLCTL9_REFDIV_PLL1, FB_PLLCTL9_REFDIV_PLL1)
  1473. /******************************
  1474. * R_PLLCTLA (0x4F) *
  1475. ******************************/
  1476. /* Field Offsets */
  1477. #define FB_PLLCTLA_OUTDIV_PLL1 0
  1478. /* Field Masks */
  1479. #define FM_PLLCTLA_OUTDIV_PLL1 0XFF
  1480. /* Register Masks */
  1481. #define RM_PLLCTLA_OUTDIV_PLL1 \
  1482. RM(FM_PLLCTLA_OUTDIV_PLL1, FB_PLLCTLA_OUTDIV_PLL1)
  1483. /******************************
  1484. * R_PLLCTLB (0x50) *
  1485. ******************************/
  1486. /* Field Offsets */
  1487. #define FB_PLLCTLB_FBDIV_PLL1L 0
  1488. /* Field Masks */
  1489. #define FM_PLLCTLB_FBDIV_PLL1L 0XFF
  1490. /* Register Masks */
  1491. #define RM_PLLCTLB_FBDIV_PLL1L \
  1492. RM(FM_PLLCTLB_FBDIV_PLL1L, FB_PLLCTLB_FBDIV_PLL1L)
  1493. /******************************
  1494. * R_PLLCTLC (0x51) *
  1495. ******************************/
  1496. /* Field Offsets */
  1497. #define FB_PLLCTLC_FBDIV_PLL1H 0
  1498. /* Field Masks */
  1499. #define FM_PLLCTLC_FBDIV_PLL1H 0X7
  1500. /* Register Masks */
  1501. #define RM_PLLCTLC_FBDIV_PLL1H \
  1502. RM(FM_PLLCTLC_FBDIV_PLL1H, FB_PLLCTLC_FBDIV_PLL1H)
  1503. /******************************
  1504. * R_PLLCTLD (0x52) *
  1505. ******************************/
  1506. /* Field Offsets */
  1507. #define FB_PLLCTLD_RZ_PLL1 3
  1508. #define FB_PLLCTLD_CP_PLL1 0
  1509. /* Field Masks */
  1510. #define FM_PLLCTLD_RZ_PLL1 0X7
  1511. #define FM_PLLCTLD_CP_PLL1 0X7
  1512. /* Register Masks */
  1513. #define RM_PLLCTLD_RZ_PLL1 \
  1514. RM(FM_PLLCTLD_RZ_PLL1, FB_PLLCTLD_RZ_PLL1)
  1515. #define RM_PLLCTLD_CP_PLL1 \
  1516. RM(FM_PLLCTLD_CP_PLL1, FB_PLLCTLD_CP_PLL1)
  1517. /******************************
  1518. * R_PLLCTLE (0x53) *
  1519. ******************************/
  1520. /* Field Offsets */
  1521. #define FB_PLLCTLE_REFDIV_PLL2 0
  1522. /* Field Masks */
  1523. #define FM_PLLCTLE_REFDIV_PLL2 0XFF
  1524. /* Register Masks */
  1525. #define RM_PLLCTLE_REFDIV_PLL2 \
  1526. RM(FM_PLLCTLE_REFDIV_PLL2, FB_PLLCTLE_REFDIV_PLL2)
  1527. /******************************
  1528. * R_PLLCTLF (0x54) *
  1529. ******************************/
  1530. /* Field Offsets */
  1531. #define FB_PLLCTLF_OUTDIV_PLL2 0
  1532. /* Field Masks */
  1533. #define FM_PLLCTLF_OUTDIV_PLL2 0XFF
  1534. /* Register Masks */
  1535. #define RM_PLLCTLF_OUTDIV_PLL2 \
  1536. RM(FM_PLLCTLF_OUTDIV_PLL2, FB_PLLCTLF_OUTDIV_PLL2)
  1537. /*******************************
  1538. * R_PLLCTL10 (0x55) *
  1539. *******************************/
  1540. /* Field Offsets */
  1541. #define FB_PLLCTL10_FBDIV_PLL2L 0
  1542. /* Field Masks */
  1543. #define FM_PLLCTL10_FBDIV_PLL2L 0XFF
  1544. /* Register Masks */
  1545. #define RM_PLLCTL10_FBDIV_PLL2L \
  1546. RM(FM_PLLCTL10_FBDIV_PLL2L, FB_PLLCTL10_FBDIV_PLL2L)
  1547. /*******************************
  1548. * R_PLLCTL11 (0x56) *
  1549. *******************************/
  1550. /* Field Offsets */
  1551. #define FB_PLLCTL11_FBDIV_PLL2H 0
  1552. /* Field Masks */
  1553. #define FM_PLLCTL11_FBDIV_PLL2H 0X7
  1554. /* Register Masks */
  1555. #define RM_PLLCTL11_FBDIV_PLL2H \
  1556. RM(FM_PLLCTL11_FBDIV_PLL2H, FB_PLLCTL11_FBDIV_PLL2H)
  1557. /*******************************
  1558. * R_PLLCTL12 (0x57) *
  1559. *******************************/
  1560. /* Field Offsets */
  1561. #define FB_PLLCTL12_RZ_PLL2 3
  1562. #define FB_PLLCTL12_CP_PLL2 0
  1563. /* Field Masks */
  1564. #define FM_PLLCTL12_RZ_PLL2 0X7
  1565. #define FM_PLLCTL12_CP_PLL2 0X7
  1566. /* Register Masks */
  1567. #define RM_PLLCTL12_RZ_PLL2 \
  1568. RM(FM_PLLCTL12_RZ_PLL2, FB_PLLCTL12_RZ_PLL2)
  1569. #define RM_PLLCTL12_CP_PLL2 \
  1570. RM(FM_PLLCTL12_CP_PLL2, FB_PLLCTL12_CP_PLL2)
  1571. /*******************************
  1572. * R_PLLCTL1B (0x60) *
  1573. *******************************/
  1574. /* Field Offsets */
  1575. #define FB_PLLCTL1B_VCOI_PLL2 4
  1576. #define FB_PLLCTL1B_VCOI_PLL1 2
  1577. /* Field Masks */
  1578. #define FM_PLLCTL1B_VCOI_PLL2 0X3
  1579. #define FM_PLLCTL1B_VCOI_PLL1 0X3
  1580. /* Register Masks */
  1581. #define RM_PLLCTL1B_VCOI_PLL2 \
  1582. RM(FM_PLLCTL1B_VCOI_PLL2, FB_PLLCTL1B_VCOI_PLL2)
  1583. #define RM_PLLCTL1B_VCOI_PLL1 \
  1584. RM(FM_PLLCTL1B_VCOI_PLL1, FB_PLLCTL1B_VCOI_PLL1)
  1585. /*******************************
  1586. * R_PLLCTL1C (0x61) *
  1587. *******************************/
  1588. /* Field Offsets */
  1589. #define FB_PLLCTL1C_PDB_PLL2 2
  1590. #define FB_PLLCTL1C_PDB_PLL1 1
  1591. /* Field Masks */
  1592. #define FM_PLLCTL1C_PDB_PLL2 0X1
  1593. #define FM_PLLCTL1C_PDB_PLL1 0X1
  1594. /* Field Values */
  1595. #define FV_PLLCTL1C_PDB_PLL2_ENABLE 0x1
  1596. #define FV_PLLCTL1C_PDB_PLL2_DISABLE 0x0
  1597. #define FV_PLLCTL1C_PDB_PLL1_ENABLE 0x1
  1598. #define FV_PLLCTL1C_PDB_PLL1_DISABLE 0x0
  1599. /* Register Masks */
  1600. #define RM_PLLCTL1C_PDB_PLL2 \
  1601. RM(FM_PLLCTL1C_PDB_PLL2, FB_PLLCTL1C_PDB_PLL2)
  1602. #define RM_PLLCTL1C_PDB_PLL1 \
  1603. RM(FM_PLLCTL1C_PDB_PLL1, FB_PLLCTL1C_PDB_PLL1)
  1604. /* Register Values */
  1605. #define RV_PLLCTL1C_PDB_PLL2_ENABLE \
  1606. RV(FV_PLLCTL1C_PDB_PLL2_ENABLE, FB_PLLCTL1C_PDB_PLL2)
  1607. #define RV_PLLCTL1C_PDB_PLL2_DISABLE \
  1608. RV(FV_PLLCTL1C_PDB_PLL2_DISABLE, FB_PLLCTL1C_PDB_PLL2)
  1609. #define RV_PLLCTL1C_PDB_PLL1_ENABLE \
  1610. RV(FV_PLLCTL1C_PDB_PLL1_ENABLE, FB_PLLCTL1C_PDB_PLL1)
  1611. #define RV_PLLCTL1C_PDB_PLL1_DISABLE \
  1612. RV(FV_PLLCTL1C_PDB_PLL1_DISABLE, FB_PLLCTL1C_PDB_PLL1)
  1613. /*******************************
  1614. * R_TIMEBASE (0x77) *
  1615. *******************************/
  1616. /* Field Offsets */
  1617. #define FB_TIMEBASE_DIVIDER 0
  1618. /* Field Masks */
  1619. #define FM_TIMEBASE_DIVIDER 0XFF
  1620. /* Register Masks */
  1621. #define RM_TIMEBASE_DIVIDER \
  1622. RM(FM_TIMEBASE_DIVIDER, FB_TIMEBASE_DIVIDER)
  1623. /*****************************
  1624. * R_DEVIDL (0x7D) *
  1625. *****************************/
  1626. /* Field Offsets */
  1627. #define FB_DEVIDL_DIDL 0
  1628. /* Field Masks */
  1629. #define FM_DEVIDL_DIDL 0XFF
  1630. /* Register Masks */
  1631. #define RM_DEVIDL_DIDL RM(FM_DEVIDL_DIDL, FB_DEVIDL_DIDL)
  1632. /*****************************
  1633. * R_DEVIDH (0x7E) *
  1634. *****************************/
  1635. /* Field Offsets */
  1636. #define FB_DEVIDH_DIDH 0
  1637. /* Field Masks */
  1638. #define FM_DEVIDH_DIDH 0XFF
  1639. /* Register Masks */
  1640. #define RM_DEVIDH_DIDH RM(FM_DEVIDH_DIDH, FB_DEVIDH_DIDH)
  1641. /****************************
  1642. * R_RESET (0x80) *
  1643. ****************************/
  1644. /* Field Offsets */
  1645. #define FB_RESET 0
  1646. /* Field Masks */
  1647. #define FM_RESET 0XFF
  1648. /* Field Values */
  1649. #define FV_RESET_ENABLE 0x85
  1650. /* Register Masks */
  1651. #define RM_RESET RM(FM_RESET, FB_RESET)
  1652. /* Register Values */
  1653. #define RV_RESET_ENABLE RV(FV_RESET_ENABLE, FB_RESET)
  1654. /********************************
  1655. * R_DACCRSTAT (0x8A) *
  1656. ********************************/
  1657. /* Field Offsets */
  1658. #define FB_DACCRSTAT_DACCR_BUSY 7
  1659. /* Field Masks */
  1660. #define FM_DACCRSTAT_DACCR_BUSY 0X1
  1661. /* Register Masks */
  1662. #define RM_DACCRSTAT_DACCR_BUSY \
  1663. RM(FM_DACCRSTAT_DACCR_BUSY, FB_DACCRSTAT_DACCR_BUSY)
  1664. /******************************
  1665. * R_PLLCTL0 (0x8E) *
  1666. ******************************/
  1667. /* Field Offsets */
  1668. #define FB_PLLCTL0_PLL2_LOCK 1
  1669. #define FB_PLLCTL0_PLL1_LOCK 0
  1670. /* Field Masks */
  1671. #define FM_PLLCTL0_PLL2_LOCK 0X1
  1672. #define FM_PLLCTL0_PLL1_LOCK 0X1
  1673. /* Register Masks */
  1674. #define RM_PLLCTL0_PLL2_LOCK \
  1675. RM(FM_PLLCTL0_PLL2_LOCK, FB_PLLCTL0_PLL2_LOCK)
  1676. #define RM_PLLCTL0_PLL1_LOCK \
  1677. RM(FM_PLLCTL0_PLL1_LOCK, FB_PLLCTL0_PLL1_LOCK)
  1678. /********************************
  1679. * R_PLLREFSEL (0x8F) *
  1680. ********************************/
  1681. /* Field Offsets */
  1682. #define FB_PLLREFSEL_PLL2_REF_SEL 4
  1683. #define FB_PLLREFSEL_PLL1_REF_SEL 0
  1684. /* Field Masks */
  1685. #define FM_PLLREFSEL_PLL2_REF_SEL 0X7
  1686. #define FM_PLLREFSEL_PLL1_REF_SEL 0X7
  1687. /* Field Values */
  1688. #define FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 0x0
  1689. #define FV_PLLREFSEL_PLL2_REF_SEL_MCLK2 0x1
  1690. #define FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 0x0
  1691. #define FV_PLLREFSEL_PLL1_REF_SEL_MCLK2 0x1
  1692. /* Register Masks */
  1693. #define RM_PLLREFSEL_PLL2_REF_SEL \
  1694. RM(FM_PLLREFSEL_PLL2_REF_SEL, FB_PLLREFSEL_PLL2_REF_SEL)
  1695. #define RM_PLLREFSEL_PLL1_REF_SEL \
  1696. RM(FM_PLLREFSEL_PLL1_REF_SEL, FB_PLLREFSEL_PLL1_REF_SEL)
  1697. /* Register Values */
  1698. #define RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1 \
  1699. RV(FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL2_REF_SEL)
  1700. #define RV_PLLREFSEL_PLL2_REF_SEL_MCLK2 \
  1701. RV(FV_PLLREFSEL_PLL2_REF_SEL_MCLK2, FB_PLLREFSEL_PLL2_REF_SEL)
  1702. #define RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 \
  1703. RV(FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL1_REF_SEL)
  1704. #define RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 \
  1705. RV(FV_PLLREFSEL_PLL1_REF_SEL_MCLK2, FB_PLLREFSEL_PLL1_REF_SEL)
  1706. /*******************************
  1707. * R_DACMBCEN (0xC7) *
  1708. *******************************/
  1709. /* Field Offsets */
  1710. #define FB_DACMBCEN_MBCEN3 2
  1711. #define FB_DACMBCEN_MBCEN2 1
  1712. #define FB_DACMBCEN_MBCEN1 0
  1713. /* Field Masks */
  1714. #define FM_DACMBCEN_MBCEN3 0X1
  1715. #define FM_DACMBCEN_MBCEN2 0X1
  1716. #define FM_DACMBCEN_MBCEN1 0X1
  1717. /* Register Masks */
  1718. #define RM_DACMBCEN_MBCEN3 \
  1719. RM(FM_DACMBCEN_MBCEN3, FB_DACMBCEN_MBCEN3)
  1720. #define RM_DACMBCEN_MBCEN2 \
  1721. RM(FM_DACMBCEN_MBCEN2, FB_DACMBCEN_MBCEN2)
  1722. #define RM_DACMBCEN_MBCEN1 \
  1723. RM(FM_DACMBCEN_MBCEN1, FB_DACMBCEN_MBCEN1)
  1724. /********************************
  1725. * R_DACMBCCTL (0xC8) *
  1726. ********************************/
  1727. /* Field Offsets */
  1728. #define FB_DACMBCCTL_LVLMODE3 5
  1729. #define FB_DACMBCCTL_WINSEL3 4
  1730. #define FB_DACMBCCTL_LVLMODE2 3
  1731. #define FB_DACMBCCTL_WINSEL2 2
  1732. #define FB_DACMBCCTL_LVLMODE1 1
  1733. #define FB_DACMBCCTL_WINSEL1 0
  1734. /* Field Masks */
  1735. #define FM_DACMBCCTL_LVLMODE3 0X1
  1736. #define FM_DACMBCCTL_WINSEL3 0X1
  1737. #define FM_DACMBCCTL_LVLMODE2 0X1
  1738. #define FM_DACMBCCTL_WINSEL2 0X1
  1739. #define FM_DACMBCCTL_LVLMODE1 0X1
  1740. #define FM_DACMBCCTL_WINSEL1 0X1
  1741. /* Register Masks */
  1742. #define RM_DACMBCCTL_LVLMODE3 \
  1743. RM(FM_DACMBCCTL_LVLMODE3, FB_DACMBCCTL_LVLMODE3)
  1744. #define RM_DACMBCCTL_WINSEL3 \
  1745. RM(FM_DACMBCCTL_WINSEL3, FB_DACMBCCTL_WINSEL3)
  1746. #define RM_DACMBCCTL_LVLMODE2 \
  1747. RM(FM_DACMBCCTL_LVLMODE2, FB_DACMBCCTL_LVLMODE2)
  1748. #define RM_DACMBCCTL_WINSEL2 \
  1749. RM(FM_DACMBCCTL_WINSEL2, FB_DACMBCCTL_WINSEL2)
  1750. #define RM_DACMBCCTL_LVLMODE1 \
  1751. RM(FM_DACMBCCTL_LVLMODE1, FB_DACMBCCTL_LVLMODE1)
  1752. #define RM_DACMBCCTL_WINSEL1 \
  1753. RM(FM_DACMBCCTL_WINSEL1, FB_DACMBCCTL_WINSEL1)
  1754. /*********************************
  1755. * R_DACMBCMUG1 (0xC9) *
  1756. *********************************/
  1757. /* Field Offsets */
  1758. #define FB_DACMBCMUG1_PHASE 5
  1759. #define FB_DACMBCMUG1_MUGAIN 0
  1760. /* Field Masks */
  1761. #define FM_DACMBCMUG1_PHASE 0X1
  1762. #define FM_DACMBCMUG1_MUGAIN 0X1F
  1763. /* Register Masks */
  1764. #define RM_DACMBCMUG1_PHASE \
  1765. RM(FM_DACMBCMUG1_PHASE, FB_DACMBCMUG1_PHASE)
  1766. #define RM_DACMBCMUG1_MUGAIN \
  1767. RM(FM_DACMBCMUG1_MUGAIN, FB_DACMBCMUG1_MUGAIN)
  1768. /*********************************
  1769. * R_DACMBCTHR1 (0xCA) *
  1770. *********************************/
  1771. /* Field Offsets */
  1772. #define FB_DACMBCTHR1_THRESH 0
  1773. /* Field Masks */
  1774. #define FM_DACMBCTHR1_THRESH 0XFF
  1775. /* Register Masks */
  1776. #define RM_DACMBCTHR1_THRESH \
  1777. RM(FM_DACMBCTHR1_THRESH, FB_DACMBCTHR1_THRESH)
  1778. /*********************************
  1779. * R_DACMBCRAT1 (0xCB) *
  1780. *********************************/
  1781. /* Field Offsets */
  1782. #define FB_DACMBCRAT1_RATIO 0
  1783. /* Field Masks */
  1784. #define FM_DACMBCRAT1_RATIO 0X1F
  1785. /* Register Masks */
  1786. #define RM_DACMBCRAT1_RATIO \
  1787. RM(FM_DACMBCRAT1_RATIO, FB_DACMBCRAT1_RATIO)
  1788. /**********************************
  1789. * R_DACMBCATK1L (0xCC) *
  1790. **********************************/
  1791. /* Field Offsets */
  1792. #define FB_DACMBCATK1L_TCATKL 0
  1793. /* Field Masks */
  1794. #define FM_DACMBCATK1L_TCATKL 0XFF
  1795. /* Register Masks */
  1796. #define RM_DACMBCATK1L_TCATKL \
  1797. RM(FM_DACMBCATK1L_TCATKL, FB_DACMBCATK1L_TCATKL)
  1798. /**********************************
  1799. * R_DACMBCATK1H (0xCD) *
  1800. **********************************/
  1801. /* Field Offsets */
  1802. #define FB_DACMBCATK1H_TCATKH 0
  1803. /* Field Masks */
  1804. #define FM_DACMBCATK1H_TCATKH 0XFF
  1805. /* Register Masks */
  1806. #define RM_DACMBCATK1H_TCATKH \
  1807. RM(FM_DACMBCATK1H_TCATKH, FB_DACMBCATK1H_TCATKH)
  1808. /**********************************
  1809. * R_DACMBCREL1L (0xCE) *
  1810. **********************************/
  1811. /* Field Offsets */
  1812. #define FB_DACMBCREL1L_TCRELL 0
  1813. /* Field Masks */
  1814. #define FM_DACMBCREL1L_TCRELL 0XFF
  1815. /* Register Masks */
  1816. #define RM_DACMBCREL1L_TCRELL \
  1817. RM(FM_DACMBCREL1L_TCRELL, FB_DACMBCREL1L_TCRELL)
  1818. /**********************************
  1819. * R_DACMBCREL1H (0xCF) *
  1820. **********************************/
  1821. /* Field Offsets */
  1822. #define FB_DACMBCREL1H_TCRELH 0
  1823. /* Field Masks */
  1824. #define FM_DACMBCREL1H_TCRELH 0XFF
  1825. /* Register Masks */
  1826. #define RM_DACMBCREL1H_TCRELH \
  1827. RM(FM_DACMBCREL1H_TCRELH, FB_DACMBCREL1H_TCRELH)
  1828. /*********************************
  1829. * R_DACMBCMUG2 (0xD0) *
  1830. *********************************/
  1831. /* Field Offsets */
  1832. #define FB_DACMBCMUG2_PHASE 5
  1833. #define FB_DACMBCMUG2_MUGAIN 0
  1834. /* Field Masks */
  1835. #define FM_DACMBCMUG2_PHASE 0X1
  1836. #define FM_DACMBCMUG2_MUGAIN 0X1F
  1837. /* Register Masks */
  1838. #define RM_DACMBCMUG2_PHASE \
  1839. RM(FM_DACMBCMUG2_PHASE, FB_DACMBCMUG2_PHASE)
  1840. #define RM_DACMBCMUG2_MUGAIN \
  1841. RM(FM_DACMBCMUG2_MUGAIN, FB_DACMBCMUG2_MUGAIN)
  1842. /*********************************
  1843. * R_DACMBCTHR2 (0xD1) *
  1844. *********************************/
  1845. /* Field Offsets */
  1846. #define FB_DACMBCTHR2_THRESH 0
  1847. /* Field Masks */
  1848. #define FM_DACMBCTHR2_THRESH 0XFF
  1849. /* Register Masks */
  1850. #define RM_DACMBCTHR2_THRESH \
  1851. RM(FM_DACMBCTHR2_THRESH, FB_DACMBCTHR2_THRESH)
  1852. /*********************************
  1853. * R_DACMBCRAT2 (0xD2) *
  1854. *********************************/
  1855. /* Field Offsets */
  1856. #define FB_DACMBCRAT2_RATIO 0
  1857. /* Field Masks */
  1858. #define FM_DACMBCRAT2_RATIO 0X1F
  1859. /* Register Masks */
  1860. #define RM_DACMBCRAT2_RATIO \
  1861. RM(FM_DACMBCRAT2_RATIO, FB_DACMBCRAT2_RATIO)
  1862. /**********************************
  1863. * R_DACMBCATK2L (0xD3) *
  1864. **********************************/
  1865. /* Field Offsets */
  1866. #define FB_DACMBCATK2L_TCATKL 0
  1867. /* Field Masks */
  1868. #define FM_DACMBCATK2L_TCATKL 0XFF
  1869. /* Register Masks */
  1870. #define RM_DACMBCATK2L_TCATKL \
  1871. RM(FM_DACMBCATK2L_TCATKL, FB_DACMBCATK2L_TCATKL)
  1872. /**********************************
  1873. * R_DACMBCATK2H (0xD4) *
  1874. **********************************/
  1875. /* Field Offsets */
  1876. #define FB_DACMBCATK2H_TCATKH 0
  1877. /* Field Masks */
  1878. #define FM_DACMBCATK2H_TCATKH 0XFF
  1879. /* Register Masks */
  1880. #define RM_DACMBCATK2H_TCATKH \
  1881. RM(FM_DACMBCATK2H_TCATKH, FB_DACMBCATK2H_TCATKH)
  1882. /**********************************
  1883. * R_DACMBCREL2L (0xD5) *
  1884. **********************************/
  1885. /* Field Offsets */
  1886. #define FB_DACMBCREL2L_TCRELL 0
  1887. /* Field Masks */
  1888. #define FM_DACMBCREL2L_TCRELL 0XFF
  1889. /* Register Masks */
  1890. #define RM_DACMBCREL2L_TCRELL \
  1891. RM(FM_DACMBCREL2L_TCRELL, FB_DACMBCREL2L_TCRELL)
  1892. /**********************************
  1893. * R_DACMBCREL2H (0xD6) *
  1894. **********************************/
  1895. /* Field Offsets */
  1896. #define FB_DACMBCREL2H_TCRELH 0
  1897. /* Field Masks */
  1898. #define FM_DACMBCREL2H_TCRELH 0XFF
  1899. /* Register Masks */
  1900. #define RM_DACMBCREL2H_TCRELH \
  1901. RM(FM_DACMBCREL2H_TCRELH, FB_DACMBCREL2H_TCRELH)
  1902. /*********************************
  1903. * R_DACMBCMUG3 (0xD7) *
  1904. *********************************/
  1905. /* Field Offsets */
  1906. #define FB_DACMBCMUG3_PHASE 5
  1907. #define FB_DACMBCMUG3_MUGAIN 0
  1908. /* Field Masks */
  1909. #define FM_DACMBCMUG3_PHASE 0X1
  1910. #define FM_DACMBCMUG3_MUGAIN 0X1F
  1911. /* Register Masks */
  1912. #define RM_DACMBCMUG3_PHASE \
  1913. RM(FM_DACMBCMUG3_PHASE, FB_DACMBCMUG3_PHASE)
  1914. #define RM_DACMBCMUG3_MUGAIN \
  1915. RM(FM_DACMBCMUG3_MUGAIN, FB_DACMBCMUG3_MUGAIN)
  1916. /*********************************
  1917. * R_DACMBCTHR3 (0xD8) *
  1918. *********************************/
  1919. /* Field Offsets */
  1920. #define FB_DACMBCTHR3_THRESH 0
  1921. /* Field Masks */
  1922. #define FM_DACMBCTHR3_THRESH 0XFF
  1923. /* Register Masks */
  1924. #define RM_DACMBCTHR3_THRESH \
  1925. RM(FM_DACMBCTHR3_THRESH, FB_DACMBCTHR3_THRESH)
  1926. /*********************************
  1927. * R_DACMBCRAT3 (0xD9) *
  1928. *********************************/
  1929. /* Field Offsets */
  1930. #define FB_DACMBCRAT3_RATIO 0
  1931. /* Field Masks */
  1932. #define FM_DACMBCRAT3_RATIO 0X1F
  1933. /* Register Masks */
  1934. #define RM_DACMBCRAT3_RATIO \
  1935. RM(FM_DACMBCRAT3_RATIO, FB_DACMBCRAT3_RATIO)
  1936. /**********************************
  1937. * R_DACMBCATK3L (0xDA) *
  1938. **********************************/
  1939. /* Field Offsets */
  1940. #define FB_DACMBCATK3L_TCATKL 0
  1941. /* Field Masks */
  1942. #define FM_DACMBCATK3L_TCATKL 0XFF
  1943. /* Register Masks */
  1944. #define RM_DACMBCATK3L_TCATKL \
  1945. RM(FM_DACMBCATK3L_TCATKL, FB_DACMBCATK3L_TCATKL)
  1946. /**********************************
  1947. * R_DACMBCATK3H (0xDB) *
  1948. **********************************/
  1949. /* Field Offsets */
  1950. #define FB_DACMBCATK3H_TCATKH 0
  1951. /* Field Masks */
  1952. #define FM_DACMBCATK3H_TCATKH 0XFF
  1953. /* Register Masks */
  1954. #define RM_DACMBCATK3H_TCATKH \
  1955. RM(FM_DACMBCATK3H_TCATKH, FB_DACMBCATK3H_TCATKH)
  1956. /**********************************
  1957. * R_DACMBCREL3L (0xDC) *
  1958. **********************************/
  1959. /* Field Offsets */
  1960. #define FB_DACMBCREL3L_TCRELL 0
  1961. /* Field Masks */
  1962. #define FM_DACMBCREL3L_TCRELL 0XFF
  1963. /* Register Masks */
  1964. #define RM_DACMBCREL3L_TCRELL \
  1965. RM(FM_DACMBCREL3L_TCRELL, FB_DACMBCREL3L_TCRELL)
  1966. /**********************************
  1967. * R_DACMBCREL3H (0xDD) *
  1968. **********************************/
  1969. /* Field Offsets */
  1970. #define FB_DACMBCREL3H_TCRELH 0
  1971. /* Field Masks */
  1972. #define FM_DACMBCREL3H_TCRELH 0XFF
  1973. /* Register Masks */
  1974. #define RM_DACMBCREL3H_TCRELH \
  1975. RM(FM_DACMBCREL3H_TCRELH, FB_DACMBCREL3H_TCRELH)
  1976. #endif /* __WOOKIE_H__ */