tlv320dac33.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ALSA SoC Texas Instruments TLV320DAC33 codec driver
  4. *
  5. * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  6. *
  7. * Copyright: (C) 2009 Nokia Corporation
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/gpio.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/slab.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <sound/tlv320dac33-plat.h>
  26. #include "tlv320dac33.h"
  27. /*
  28. * The internal FIFO is 24576 bytes long
  29. * It can be configured to hold 16bit or 24bit samples
  30. * In 16bit configuration the FIFO can hold 6144 stereo samples
  31. * In 24bit configuration the FIFO can hold 4096 stereo samples
  32. */
  33. #define DAC33_FIFO_SIZE_16BIT 6144
  34. #define DAC33_FIFO_SIZE_24BIT 4096
  35. #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
  36. #define BURST_BASEFREQ_HZ 49152000
  37. #define SAMPLES_TO_US(rate, samples) \
  38. (1000000000 / (((rate) * 1000) / (samples)))
  39. #define US_TO_SAMPLES(rate, us) \
  40. ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
  41. #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  42. (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
  43. static void dac33_calculate_times(struct snd_pcm_substream *substream,
  44. struct snd_soc_component *component);
  45. static int dac33_prepare_chip(struct snd_pcm_substream *substream,
  46. struct snd_soc_component *component);
  47. enum dac33_state {
  48. DAC33_IDLE = 0,
  49. DAC33_PREFILL,
  50. DAC33_PLAYBACK,
  51. DAC33_FLUSH,
  52. };
  53. enum dac33_fifo_modes {
  54. DAC33_FIFO_BYPASS = 0,
  55. DAC33_FIFO_MODE1,
  56. DAC33_FIFO_MODE7,
  57. DAC33_FIFO_LAST_MODE,
  58. };
  59. #define DAC33_NUM_SUPPLIES 3
  60. static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  61. "AVDD",
  62. "DVDD",
  63. "IOVDD",
  64. };
  65. struct tlv320dac33_priv {
  66. struct mutex mutex;
  67. struct work_struct work;
  68. struct snd_soc_component *component;
  69. struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  70. struct snd_pcm_substream *substream;
  71. int power_gpio;
  72. int chip_power;
  73. int irq;
  74. unsigned int refclk;
  75. unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
  76. enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
  77. unsigned int fifo_size; /* Size of the FIFO in samples */
  78. unsigned int nsample; /* burst read amount from host */
  79. int mode1_latency; /* latency caused by the i2c writes in
  80. * us */
  81. u8 burst_bclkdiv; /* BCLK divider value in burst mode */
  82. u8 *reg_cache;
  83. unsigned int burst_rate; /* Interface speed in Burst modes */
  84. int keep_bclk; /* Keep the BCLK continuously running
  85. * in FIFO modes */
  86. spinlock_t lock;
  87. unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
  88. unsigned long long t_stamp2; /* calculate the FIFO caused delay */
  89. unsigned int mode1_us_burst; /* Time to burst read n number of
  90. * samples */
  91. unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
  92. unsigned int uthr;
  93. enum dac33_state state;
  94. struct i2c_client *i2c;
  95. };
  96. static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
  97. 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
  98. 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
  99. 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
  100. 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
  101. 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
  102. 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
  103. 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
  104. 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
  105. 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
  106. 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
  107. 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
  108. 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
  109. 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
  110. 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
  111. 0x00, 0x00, /* 0x38 - 0x39 */
  112. /* Registers 0x3a - 0x3f are reserved */
  113. 0x00, 0x00, /* 0x3a - 0x3b */
  114. 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
  115. 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
  116. 0x00, 0x80, /* 0x44 - 0x45 */
  117. /* Registers 0x46 - 0x47 are reserved */
  118. 0x80, 0x80, /* 0x46 - 0x47 */
  119. 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
  120. /* Registers 0x4b - 0x7c are reserved */
  121. 0x00, /* 0x4b */
  122. 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
  123. 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
  124. 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
  125. 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
  126. 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
  127. 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
  128. 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
  129. 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
  130. 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
  131. 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
  132. 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
  133. 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
  134. 0x00, /* 0x7c */
  135. 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
  136. };
  137. /* Register read and write */
  138. static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component,
  139. unsigned reg)
  140. {
  141. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  142. u8 *cache = dac33->reg_cache;
  143. if (reg >= DAC33_CACHEREGNUM)
  144. return 0;
  145. return cache[reg];
  146. }
  147. static inline void dac33_write_reg_cache(struct snd_soc_component *component,
  148. u8 reg, u8 value)
  149. {
  150. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  151. u8 *cache = dac33->reg_cache;
  152. if (reg >= DAC33_CACHEREGNUM)
  153. return;
  154. cache[reg] = value;
  155. }
  156. static int dac33_read(struct snd_soc_component *component, unsigned int reg,
  157. u8 *value)
  158. {
  159. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  160. int val, ret = 0;
  161. *value = reg & 0xff;
  162. /* If powered off, return the cached value */
  163. if (dac33->chip_power) {
  164. val = i2c_smbus_read_byte_data(dac33->i2c, value[0]);
  165. if (val < 0) {
  166. dev_err(component->dev, "Read failed (%d)\n", val);
  167. value[0] = dac33_read_reg_cache(component, reg);
  168. ret = val;
  169. } else {
  170. value[0] = val;
  171. dac33_write_reg_cache(component, reg, val);
  172. }
  173. } else {
  174. value[0] = dac33_read_reg_cache(component, reg);
  175. }
  176. return ret;
  177. }
  178. static int dac33_write(struct snd_soc_component *component, unsigned int reg,
  179. unsigned int value)
  180. {
  181. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  182. u8 data[2];
  183. int ret = 0;
  184. /*
  185. * data is
  186. * D15..D8 dac33 register offset
  187. * D7...D0 register data
  188. */
  189. data[0] = reg & 0xff;
  190. data[1] = value & 0xff;
  191. dac33_write_reg_cache(component, data[0], data[1]);
  192. if (dac33->chip_power) {
  193. ret = i2c_master_send(dac33->i2c, data, 2);
  194. if (ret != 2)
  195. dev_err(component->dev, "Write failed (%d)\n", ret);
  196. else
  197. ret = 0;
  198. }
  199. return ret;
  200. }
  201. static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg,
  202. unsigned int value)
  203. {
  204. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  205. int ret;
  206. mutex_lock(&dac33->mutex);
  207. ret = dac33_write(component, reg, value);
  208. mutex_unlock(&dac33->mutex);
  209. return ret;
  210. }
  211. #define DAC33_I2C_ADDR_AUTOINC 0x80
  212. static int dac33_write16(struct snd_soc_component *component, unsigned int reg,
  213. unsigned int value)
  214. {
  215. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  216. u8 data[3];
  217. int ret = 0;
  218. /*
  219. * data is
  220. * D23..D16 dac33 register offset
  221. * D15..D8 register data MSB
  222. * D7...D0 register data LSB
  223. */
  224. data[0] = reg & 0xff;
  225. data[1] = (value >> 8) & 0xff;
  226. data[2] = value & 0xff;
  227. dac33_write_reg_cache(component, data[0], data[1]);
  228. dac33_write_reg_cache(component, data[0] + 1, data[2]);
  229. if (dac33->chip_power) {
  230. /* We need to set autoincrement mode for 16 bit writes */
  231. data[0] |= DAC33_I2C_ADDR_AUTOINC;
  232. ret = i2c_master_send(dac33->i2c, data, 3);
  233. if (ret != 3)
  234. dev_err(component->dev, "Write failed (%d)\n", ret);
  235. else
  236. ret = 0;
  237. }
  238. return ret;
  239. }
  240. static void dac33_init_chip(struct snd_soc_component *component)
  241. {
  242. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  243. if (unlikely(!dac33->chip_power))
  244. return;
  245. /* A : DAC sample rate Fsref/1.5 */
  246. dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
  247. /* B : DAC src=normal, not muted */
  248. dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
  249. DAC33_DACSRCL_LEFT);
  250. /* C : (defaults) */
  251. dac33_write(component, DAC33_DAC_CTRL_C, 0x00);
  252. /* 73 : volume soft stepping control,
  253. clock source = internal osc (?) */
  254. dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
  255. /* Restore only selected registers (gains mostly) */
  256. dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL,
  257. dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL));
  258. dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL,
  259. dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL));
  260. dac33_write(component, DAC33_LINEL_TO_LLO_VOL,
  261. dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL));
  262. dac33_write(component, DAC33_LINER_TO_RLO_VOL,
  263. dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL));
  264. dac33_write(component, DAC33_OUT_AMP_CTRL,
  265. dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL));
  266. dac33_write(component, DAC33_LDAC_PWR_CTRL,
  267. dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL));
  268. dac33_write(component, DAC33_RDAC_PWR_CTRL,
  269. dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL));
  270. }
  271. static inline int dac33_read_id(struct snd_soc_component *component)
  272. {
  273. int i, ret = 0;
  274. u8 reg;
  275. for (i = 0; i < 3; i++) {
  276. ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, &reg);
  277. if (ret < 0)
  278. break;
  279. }
  280. return ret;
  281. }
  282. static inline void dac33_soft_power(struct snd_soc_component *component, int power)
  283. {
  284. u8 reg;
  285. reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
  286. if (power)
  287. reg |= DAC33_PDNALLB;
  288. else
  289. reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
  290. DAC33_DACRPDNB | DAC33_DACLPDNB);
  291. dac33_write(component, DAC33_PWR_CTRL, reg);
  292. }
  293. static inline void dac33_disable_digital(struct snd_soc_component *component)
  294. {
  295. u8 reg;
  296. /* Stop the DAI clock */
  297. reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
  298. reg &= ~DAC33_BCLKON;
  299. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg);
  300. /* Power down the Oscillator, and DACs */
  301. reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
  302. reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
  303. dac33_write(component, DAC33_PWR_CTRL, reg);
  304. }
  305. static int dac33_hard_power(struct snd_soc_component *component, int power)
  306. {
  307. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  308. int ret = 0;
  309. mutex_lock(&dac33->mutex);
  310. /* Safety check */
  311. if (unlikely(power == dac33->chip_power)) {
  312. dev_dbg(component->dev, "Trying to set the same power state: %s\n",
  313. power ? "ON" : "OFF");
  314. goto exit;
  315. }
  316. if (power) {
  317. ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
  318. dac33->supplies);
  319. if (ret != 0) {
  320. dev_err(component->dev,
  321. "Failed to enable supplies: %d\n", ret);
  322. goto exit;
  323. }
  324. if (dac33->power_gpio >= 0)
  325. gpio_set_value(dac33->power_gpio, 1);
  326. dac33->chip_power = 1;
  327. } else {
  328. dac33_soft_power(component, 0);
  329. if (dac33->power_gpio >= 0)
  330. gpio_set_value(dac33->power_gpio, 0);
  331. ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
  332. dac33->supplies);
  333. if (ret != 0) {
  334. dev_err(component->dev,
  335. "Failed to disable supplies: %d\n", ret);
  336. goto exit;
  337. }
  338. dac33->chip_power = 0;
  339. }
  340. exit:
  341. mutex_unlock(&dac33->mutex);
  342. return ret;
  343. }
  344. static int dac33_playback_event(struct snd_soc_dapm_widget *w,
  345. struct snd_kcontrol *kcontrol, int event)
  346. {
  347. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  348. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  349. switch (event) {
  350. case SND_SOC_DAPM_PRE_PMU:
  351. if (likely(dac33->substream)) {
  352. dac33_calculate_times(dac33->substream, component);
  353. dac33_prepare_chip(dac33->substream, component);
  354. }
  355. break;
  356. case SND_SOC_DAPM_POST_PMD:
  357. dac33_disable_digital(component);
  358. break;
  359. }
  360. return 0;
  361. }
  362. static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
  363. struct snd_ctl_elem_value *ucontrol)
  364. {
  365. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  366. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  367. ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
  368. return 0;
  369. }
  370. static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
  371. struct snd_ctl_elem_value *ucontrol)
  372. {
  373. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  374. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  375. int ret = 0;
  376. if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
  377. return 0;
  378. /* Do not allow changes while stream is running*/
  379. if (snd_soc_component_active(component))
  380. return -EPERM;
  381. if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE)
  382. ret = -EINVAL;
  383. else
  384. dac33->fifo_mode = ucontrol->value.enumerated.item[0];
  385. return ret;
  386. }
  387. /* Codec operation modes */
  388. static const char *dac33_fifo_mode_texts[] = {
  389. "Bypass", "Mode 1", "Mode 7"
  390. };
  391. static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
  392. /* L/R Line Output Gain */
  393. static const char *lr_lineout_gain_texts[] = {
  394. "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
  395. "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
  396. };
  397. static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
  398. DAC33_LDAC_PWR_CTRL, 0,
  399. lr_lineout_gain_texts);
  400. static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
  401. DAC33_RDAC_PWR_CTRL, 0,
  402. lr_lineout_gain_texts);
  403. /*
  404. * DACL/R digital volume control:
  405. * from 0 dB to -63.5 in 0.5 dB steps
  406. * Need to be inverted later on:
  407. * 0x00 == 0 dB
  408. * 0x7f == -63.5 dB
  409. */
  410. static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
  411. static const struct snd_kcontrol_new dac33_snd_controls[] = {
  412. SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
  413. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
  414. 0, 0x7f, 1, dac_digivol_tlv),
  415. SOC_DOUBLE_R("DAC Digital Playback Switch",
  416. DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
  417. SOC_DOUBLE_R("Line to Line Out Volume",
  418. DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
  419. SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
  420. SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
  421. };
  422. static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
  423. SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
  424. dac33_get_fifo_mode, dac33_set_fifo_mode),
  425. };
  426. /* Analog bypass */
  427. static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
  428. SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
  429. static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
  430. SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
  431. /* LOP L/R invert selection */
  432. static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
  433. static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
  434. DAC33_OUT_AMP_CTRL, 3,
  435. dac33_lr_lom_texts);
  436. static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
  437. SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
  438. static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
  439. DAC33_OUT_AMP_CTRL, 2,
  440. dac33_lr_lom_texts);
  441. static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
  442. SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
  443. static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
  444. SND_SOC_DAPM_OUTPUT("LEFT_LO"),
  445. SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
  446. SND_SOC_DAPM_INPUT("LINEL"),
  447. SND_SOC_DAPM_INPUT("LINER"),
  448. SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
  449. SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
  450. /* Analog bypass */
  451. SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
  452. &dac33_dapm_abypassl_control),
  453. SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
  454. &dac33_dapm_abypassr_control),
  455. SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
  456. &dac33_dapm_left_lom_control),
  457. SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
  458. &dac33_dapm_right_lom_control),
  459. /*
  460. * For DAPM path, when only the anlog bypass path is enabled, and the
  461. * LOP inverted from the corresponding DAC side.
  462. * This is needed, so we can attach the DAC power supply in this case.
  463. */
  464. SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  465. SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  466. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
  467. DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
  468. SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
  469. DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
  470. SND_SOC_DAPM_SUPPLY("Left DAC Power",
  471. DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
  472. SND_SOC_DAPM_SUPPLY("Right DAC Power",
  473. DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
  474. SND_SOC_DAPM_SUPPLY("Codec Power",
  475. DAC33_PWR_CTRL, 4, 0, NULL, 0),
  476. SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
  477. SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
  478. };
  479. static const struct snd_soc_dapm_route audio_map[] = {
  480. /* Analog bypass */
  481. {"Analog Left Bypass", "Switch", "LINEL"},
  482. {"Analog Right Bypass", "Switch", "LINER"},
  483. {"Output Left Amplifier", NULL, "DACL"},
  484. {"Output Right Amplifier", NULL, "DACR"},
  485. {"Left Bypass PGA", NULL, "Analog Left Bypass"},
  486. {"Right Bypass PGA", NULL, "Analog Right Bypass"},
  487. {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
  488. {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
  489. {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
  490. {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
  491. {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
  492. {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
  493. {"DACL", NULL, "Left DAC Power"},
  494. {"DACR", NULL, "Right DAC Power"},
  495. {"Left Bypass PGA", NULL, "Left DAC Power"},
  496. {"Right Bypass PGA", NULL, "Right DAC Power"},
  497. /* output */
  498. {"LEFT_LO", NULL, "Output Left Amplifier"},
  499. {"RIGHT_LO", NULL, "Output Right Amplifier"},
  500. {"LEFT_LO", NULL, "Codec Power"},
  501. {"RIGHT_LO", NULL, "Codec Power"},
  502. };
  503. static int dac33_set_bias_level(struct snd_soc_component *component,
  504. enum snd_soc_bias_level level)
  505. {
  506. int ret;
  507. switch (level) {
  508. case SND_SOC_BIAS_ON:
  509. break;
  510. case SND_SOC_BIAS_PREPARE:
  511. break;
  512. case SND_SOC_BIAS_STANDBY:
  513. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  514. /* Coming from OFF, switch on the component */
  515. ret = dac33_hard_power(component, 1);
  516. if (ret != 0)
  517. return ret;
  518. dac33_init_chip(component);
  519. }
  520. break;
  521. case SND_SOC_BIAS_OFF:
  522. /* Do not power off, when the component is already off */
  523. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  524. return 0;
  525. ret = dac33_hard_power(component, 0);
  526. if (ret != 0)
  527. return ret;
  528. break;
  529. }
  530. return 0;
  531. }
  532. static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
  533. {
  534. struct snd_soc_component *component = dac33->component;
  535. unsigned int delay;
  536. unsigned long flags;
  537. switch (dac33->fifo_mode) {
  538. case DAC33_FIFO_MODE1:
  539. dac33_write16(component, DAC33_NSAMPLE_MSB,
  540. DAC33_THRREG(dac33->nsample));
  541. /* Take the timestamps */
  542. spin_lock_irqsave(&dac33->lock, flags);
  543. dac33->t_stamp2 = ktime_to_us(ktime_get());
  544. dac33->t_stamp1 = dac33->t_stamp2;
  545. spin_unlock_irqrestore(&dac33->lock, flags);
  546. dac33_write16(component, DAC33_PREFILL_MSB,
  547. DAC33_THRREG(dac33->alarm_threshold));
  548. /* Enable Alarm Threshold IRQ with a delay */
  549. delay = SAMPLES_TO_US(dac33->burst_rate,
  550. dac33->alarm_threshold) + 1000;
  551. usleep_range(delay, delay + 500);
  552. dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
  553. break;
  554. case DAC33_FIFO_MODE7:
  555. /* Take the timestamp */
  556. spin_lock_irqsave(&dac33->lock, flags);
  557. dac33->t_stamp1 = ktime_to_us(ktime_get());
  558. /* Move back the timestamp with drain time */
  559. dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
  560. spin_unlock_irqrestore(&dac33->lock, flags);
  561. dac33_write16(component, DAC33_PREFILL_MSB,
  562. DAC33_THRREG(DAC33_MODE7_MARGIN));
  563. /* Enable Upper Threshold IRQ */
  564. dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
  565. break;
  566. default:
  567. dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
  568. dac33->fifo_mode);
  569. break;
  570. }
  571. }
  572. static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
  573. {
  574. struct snd_soc_component *component = dac33->component;
  575. unsigned long flags;
  576. switch (dac33->fifo_mode) {
  577. case DAC33_FIFO_MODE1:
  578. /* Take the timestamp */
  579. spin_lock_irqsave(&dac33->lock, flags);
  580. dac33->t_stamp2 = ktime_to_us(ktime_get());
  581. spin_unlock_irqrestore(&dac33->lock, flags);
  582. dac33_write16(component, DAC33_NSAMPLE_MSB,
  583. DAC33_THRREG(dac33->nsample));
  584. break;
  585. case DAC33_FIFO_MODE7:
  586. /* At the moment we are not using interrupts in mode7 */
  587. break;
  588. default:
  589. dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
  590. dac33->fifo_mode);
  591. break;
  592. }
  593. }
  594. static void dac33_work(struct work_struct *work)
  595. {
  596. struct snd_soc_component *component;
  597. struct tlv320dac33_priv *dac33;
  598. u8 reg;
  599. dac33 = container_of(work, struct tlv320dac33_priv, work);
  600. component = dac33->component;
  601. mutex_lock(&dac33->mutex);
  602. switch (dac33->state) {
  603. case DAC33_PREFILL:
  604. dac33->state = DAC33_PLAYBACK;
  605. dac33_prefill_handler(dac33);
  606. break;
  607. case DAC33_PLAYBACK:
  608. dac33_playback_handler(dac33);
  609. break;
  610. case DAC33_IDLE:
  611. break;
  612. case DAC33_FLUSH:
  613. dac33->state = DAC33_IDLE;
  614. /* Mask all interrupts from dac33 */
  615. dac33_write(component, DAC33_FIFO_IRQ_MASK, 0);
  616. /* flush fifo */
  617. reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
  618. reg |= DAC33_FIFOFLUSH;
  619. dac33_write(component, DAC33_FIFO_CTRL_A, reg);
  620. break;
  621. }
  622. mutex_unlock(&dac33->mutex);
  623. }
  624. static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
  625. {
  626. struct snd_soc_component *component = dev;
  627. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  628. unsigned long flags;
  629. spin_lock_irqsave(&dac33->lock, flags);
  630. dac33->t_stamp1 = ktime_to_us(ktime_get());
  631. spin_unlock_irqrestore(&dac33->lock, flags);
  632. /* Do not schedule the workqueue in Mode7 */
  633. if (dac33->fifo_mode != DAC33_FIFO_MODE7)
  634. schedule_work(&dac33->work);
  635. return IRQ_HANDLED;
  636. }
  637. static void dac33_oscwait(struct snd_soc_component *component)
  638. {
  639. int timeout = 60;
  640. u8 reg;
  641. do {
  642. usleep_range(1000, 2000);
  643. dac33_read(component, DAC33_INT_OSC_STATUS, &reg);
  644. } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
  645. if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
  646. dev_err(component->dev,
  647. "internal oscillator calibration failed\n");
  648. }
  649. static int dac33_startup(struct snd_pcm_substream *substream,
  650. struct snd_soc_dai *dai)
  651. {
  652. struct snd_soc_component *component = dai->component;
  653. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  654. /* Stream started, save the substream pointer */
  655. dac33->substream = substream;
  656. return 0;
  657. }
  658. static void dac33_shutdown(struct snd_pcm_substream *substream,
  659. struct snd_soc_dai *dai)
  660. {
  661. struct snd_soc_component *component = dai->component;
  662. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  663. dac33->substream = NULL;
  664. }
  665. #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
  666. (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
  667. static int dac33_hw_params(struct snd_pcm_substream *substream,
  668. struct snd_pcm_hw_params *params,
  669. struct snd_soc_dai *dai)
  670. {
  671. struct snd_soc_component *component = dai->component;
  672. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  673. /* Check parameters for validity */
  674. switch (params_rate(params)) {
  675. case 44100:
  676. case 48000:
  677. break;
  678. default:
  679. dev_err(component->dev, "unsupported rate %d\n",
  680. params_rate(params));
  681. return -EINVAL;
  682. }
  683. switch (params_width(params)) {
  684. case 16:
  685. dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
  686. dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
  687. break;
  688. case 32:
  689. dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
  690. dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
  691. break;
  692. default:
  693. dev_err(component->dev, "unsupported width %d\n",
  694. params_width(params));
  695. return -EINVAL;
  696. }
  697. return 0;
  698. }
  699. #define CALC_OSCSET(rate, refclk) ( \
  700. ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
  701. #define CALC_RATIOSET(rate, refclk) ( \
  702. ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
  703. /*
  704. * tlv320dac33 is strict on the sequence of the register writes, if the register
  705. * writes happens in different order, than dac33 might end up in unknown state.
  706. * Use the known, working sequence of register writes to initialize the dac33.
  707. */
  708. static int dac33_prepare_chip(struct snd_pcm_substream *substream,
  709. struct snd_soc_component *component)
  710. {
  711. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  712. unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
  713. u8 aictrl_a, aictrl_b, fifoctrl_a;
  714. switch (substream->runtime->rate) {
  715. case 44100:
  716. case 48000:
  717. oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
  718. ratioset = CALC_RATIOSET(substream->runtime->rate,
  719. dac33->refclk);
  720. break;
  721. default:
  722. dev_err(component->dev, "unsupported rate %d\n",
  723. substream->runtime->rate);
  724. return -EINVAL;
  725. }
  726. aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
  727. aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
  728. /* Read FIFO control A, and clear FIFO flush bit */
  729. fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
  730. fifoctrl_a &= ~DAC33_FIFOFLUSH;
  731. fifoctrl_a &= ~DAC33_WIDTH;
  732. switch (substream->runtime->format) {
  733. case SNDRV_PCM_FORMAT_S16_LE:
  734. aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
  735. fifoctrl_a |= DAC33_WIDTH;
  736. break;
  737. case SNDRV_PCM_FORMAT_S32_LE:
  738. aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
  739. break;
  740. default:
  741. dev_err(component->dev, "unsupported format %d\n",
  742. substream->runtime->format);
  743. return -EINVAL;
  744. }
  745. mutex_lock(&dac33->mutex);
  746. if (!dac33->chip_power) {
  747. /*
  748. * Chip is not powered yet.
  749. * Do the init in the dac33_set_bias_level later.
  750. */
  751. mutex_unlock(&dac33->mutex);
  752. return 0;
  753. }
  754. dac33_soft_power(component, 0);
  755. dac33_soft_power(component, 1);
  756. reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
  757. dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp);
  758. /* Write registers 0x08 and 0x09 (MSB, LSB) */
  759. dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset);
  760. /* OSC calibration time */
  761. dac33_write(component, DAC33_CALIB_TIME, 96);
  762. /* adjustment treshold & step */
  763. dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
  764. DAC33_ADJSTEP(1));
  765. /* div=4 / gain=1 / div */
  766. dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
  767. pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
  768. pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
  769. dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl);
  770. dac33_oscwait(component);
  771. if (dac33->fifo_mode) {
  772. /* Generic for all FIFO modes */
  773. /* 50-51 : ASRC Control registers */
  774. dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
  775. dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */
  776. /* Write registers 0x34 and 0x35 (MSB, LSB) */
  777. dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
  778. /* Set interrupts to high active */
  779. dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
  780. } else {
  781. /* FIFO bypass mode */
  782. /* 50-51 : ASRC Control registers */
  783. dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
  784. dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */
  785. }
  786. /* Interrupt behaviour configuration */
  787. switch (dac33->fifo_mode) {
  788. case DAC33_FIFO_MODE1:
  789. dac33_write(component, DAC33_FIFO_IRQ_MODE_B,
  790. DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
  791. break;
  792. case DAC33_FIFO_MODE7:
  793. dac33_write(component, DAC33_FIFO_IRQ_MODE_A,
  794. DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
  795. break;
  796. default:
  797. /* in FIFO bypass mode, the interrupts are not used */
  798. break;
  799. }
  800. aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
  801. switch (dac33->fifo_mode) {
  802. case DAC33_FIFO_MODE1:
  803. /*
  804. * For mode1:
  805. * Disable the FIFO bypass (Enable the use of FIFO)
  806. * Select nSample mode
  807. * BCLK is only running when data is needed by DAC33
  808. */
  809. fifoctrl_a &= ~DAC33_FBYPAS;
  810. fifoctrl_a &= ~DAC33_FAUTO;
  811. if (dac33->keep_bclk)
  812. aictrl_b |= DAC33_BCLKON;
  813. else
  814. aictrl_b &= ~DAC33_BCLKON;
  815. break;
  816. case DAC33_FIFO_MODE7:
  817. /*
  818. * For mode1:
  819. * Disable the FIFO bypass (Enable the use of FIFO)
  820. * Select Threshold mode
  821. * BCLK is only running when data is needed by DAC33
  822. */
  823. fifoctrl_a &= ~DAC33_FBYPAS;
  824. fifoctrl_a |= DAC33_FAUTO;
  825. if (dac33->keep_bclk)
  826. aictrl_b |= DAC33_BCLKON;
  827. else
  828. aictrl_b &= ~DAC33_BCLKON;
  829. break;
  830. default:
  831. /*
  832. * For FIFO bypass mode:
  833. * Enable the FIFO bypass (Disable the FIFO use)
  834. * Set the BCLK as continuous
  835. */
  836. fifoctrl_a |= DAC33_FBYPAS;
  837. aictrl_b |= DAC33_BCLKON;
  838. break;
  839. }
  840. dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a);
  841. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  842. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
  843. /*
  844. * BCLK divide ratio
  845. * 0: 1.5
  846. * 1: 1
  847. * 2: 2
  848. * ...
  849. * 254: 254
  850. * 255: 255
  851. */
  852. if (dac33->fifo_mode)
  853. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C,
  854. dac33->burst_bclkdiv);
  855. else
  856. if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
  857. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32);
  858. else
  859. dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16);
  860. switch (dac33->fifo_mode) {
  861. case DAC33_FIFO_MODE1:
  862. dac33_write16(component, DAC33_ATHR_MSB,
  863. DAC33_THRREG(dac33->alarm_threshold));
  864. break;
  865. case DAC33_FIFO_MODE7:
  866. /*
  867. * Configure the threshold levels, and leave 10 sample space
  868. * at the bottom, and also at the top of the FIFO
  869. */
  870. dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
  871. dac33_write16(component, DAC33_LTHR_MSB,
  872. DAC33_THRREG(DAC33_MODE7_MARGIN));
  873. break;
  874. default:
  875. break;
  876. }
  877. mutex_unlock(&dac33->mutex);
  878. return 0;
  879. }
  880. static void dac33_calculate_times(struct snd_pcm_substream *substream,
  881. struct snd_soc_component *component)
  882. {
  883. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  884. unsigned int period_size = substream->runtime->period_size;
  885. unsigned int rate = substream->runtime->rate;
  886. unsigned int nsample_limit;
  887. /* In bypass mode we don't need to calculate */
  888. if (!dac33->fifo_mode)
  889. return;
  890. switch (dac33->fifo_mode) {
  891. case DAC33_FIFO_MODE1:
  892. /* Number of samples under i2c latency */
  893. dac33->alarm_threshold = US_TO_SAMPLES(rate,
  894. dac33->mode1_latency);
  895. nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
  896. if (period_size <= dac33->alarm_threshold)
  897. /*
  898. * Configure nSamaple to number of periods,
  899. * which covers the latency requironment.
  900. */
  901. dac33->nsample = period_size *
  902. ((dac33->alarm_threshold / period_size) +
  903. (dac33->alarm_threshold % period_size ?
  904. 1 : 0));
  905. else if (period_size > nsample_limit)
  906. dac33->nsample = nsample_limit;
  907. else
  908. dac33->nsample = period_size;
  909. dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
  910. dac33->nsample);
  911. dac33->t_stamp1 = 0;
  912. dac33->t_stamp2 = 0;
  913. break;
  914. case DAC33_FIFO_MODE7:
  915. dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
  916. dac33->burst_rate) + 9;
  917. if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
  918. dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
  919. if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
  920. dac33->uthr = (DAC33_MODE7_MARGIN + 10);
  921. dac33->mode7_us_to_lthr =
  922. SAMPLES_TO_US(substream->runtime->rate,
  923. dac33->uthr - DAC33_MODE7_MARGIN + 1);
  924. dac33->t_stamp1 = 0;
  925. break;
  926. default:
  927. break;
  928. }
  929. }
  930. static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
  931. struct snd_soc_dai *dai)
  932. {
  933. struct snd_soc_component *component = dai->component;
  934. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  935. int ret = 0;
  936. switch (cmd) {
  937. case SNDRV_PCM_TRIGGER_START:
  938. case SNDRV_PCM_TRIGGER_RESUME:
  939. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  940. if (dac33->fifo_mode) {
  941. dac33->state = DAC33_PREFILL;
  942. schedule_work(&dac33->work);
  943. }
  944. break;
  945. case SNDRV_PCM_TRIGGER_STOP:
  946. case SNDRV_PCM_TRIGGER_SUSPEND:
  947. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  948. if (dac33->fifo_mode) {
  949. dac33->state = DAC33_FLUSH;
  950. schedule_work(&dac33->work);
  951. }
  952. break;
  953. default:
  954. ret = -EINVAL;
  955. }
  956. return ret;
  957. }
  958. static snd_pcm_sframes_t dac33_dai_delay(
  959. struct snd_pcm_substream *substream,
  960. struct snd_soc_dai *dai)
  961. {
  962. struct snd_soc_component *component = dai->component;
  963. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  964. unsigned long long t0, t1, t_now;
  965. unsigned int time_delta, uthr;
  966. int samples_out, samples_in, samples;
  967. snd_pcm_sframes_t delay = 0;
  968. unsigned long flags;
  969. switch (dac33->fifo_mode) {
  970. case DAC33_FIFO_BYPASS:
  971. break;
  972. case DAC33_FIFO_MODE1:
  973. spin_lock_irqsave(&dac33->lock, flags);
  974. t0 = dac33->t_stamp1;
  975. t1 = dac33->t_stamp2;
  976. spin_unlock_irqrestore(&dac33->lock, flags);
  977. t_now = ktime_to_us(ktime_get());
  978. /* We have not started to fill the FIFO yet, delay is 0 */
  979. if (!t1)
  980. goto out;
  981. if (t0 > t1) {
  982. /*
  983. * Phase 1:
  984. * After Alarm threshold, and before nSample write
  985. */
  986. time_delta = t_now - t0;
  987. samples_out = time_delta ? US_TO_SAMPLES(
  988. substream->runtime->rate,
  989. time_delta) : 0;
  990. if (likely(dac33->alarm_threshold > samples_out))
  991. delay = dac33->alarm_threshold - samples_out;
  992. else
  993. delay = 0;
  994. } else if ((t_now - t1) <= dac33->mode1_us_burst) {
  995. /*
  996. * Phase 2:
  997. * After nSample write (during burst operation)
  998. */
  999. time_delta = t_now - t0;
  1000. samples_out = time_delta ? US_TO_SAMPLES(
  1001. substream->runtime->rate,
  1002. time_delta) : 0;
  1003. time_delta = t_now - t1;
  1004. samples_in = time_delta ? US_TO_SAMPLES(
  1005. dac33->burst_rate,
  1006. time_delta) : 0;
  1007. samples = dac33->alarm_threshold;
  1008. samples += (samples_in - samples_out);
  1009. if (likely(samples > 0))
  1010. delay = samples;
  1011. else
  1012. delay = 0;
  1013. } else {
  1014. /*
  1015. * Phase 3:
  1016. * After burst operation, before next alarm threshold
  1017. */
  1018. time_delta = t_now - t0;
  1019. samples_out = time_delta ? US_TO_SAMPLES(
  1020. substream->runtime->rate,
  1021. time_delta) : 0;
  1022. samples_in = dac33->nsample;
  1023. samples = dac33->alarm_threshold;
  1024. samples += (samples_in - samples_out);
  1025. if (likely(samples > 0))
  1026. delay = samples > dac33->fifo_size ?
  1027. dac33->fifo_size : samples;
  1028. else
  1029. delay = 0;
  1030. }
  1031. break;
  1032. case DAC33_FIFO_MODE7:
  1033. spin_lock_irqsave(&dac33->lock, flags);
  1034. t0 = dac33->t_stamp1;
  1035. uthr = dac33->uthr;
  1036. spin_unlock_irqrestore(&dac33->lock, flags);
  1037. t_now = ktime_to_us(ktime_get());
  1038. /* We have not started to fill the FIFO yet, delay is 0 */
  1039. if (!t0)
  1040. goto out;
  1041. if (t_now <= t0) {
  1042. /*
  1043. * Either the timestamps are messed or equal. Report
  1044. * maximum delay
  1045. */
  1046. delay = uthr;
  1047. goto out;
  1048. }
  1049. time_delta = t_now - t0;
  1050. if (time_delta <= dac33->mode7_us_to_lthr) {
  1051. /*
  1052. * Phase 1:
  1053. * After burst (draining phase)
  1054. */
  1055. samples_out = US_TO_SAMPLES(
  1056. substream->runtime->rate,
  1057. time_delta);
  1058. if (likely(uthr > samples_out))
  1059. delay = uthr - samples_out;
  1060. else
  1061. delay = 0;
  1062. } else {
  1063. /*
  1064. * Phase 2:
  1065. * During burst operation
  1066. */
  1067. time_delta = time_delta - dac33->mode7_us_to_lthr;
  1068. samples_out = US_TO_SAMPLES(
  1069. substream->runtime->rate,
  1070. time_delta);
  1071. samples_in = US_TO_SAMPLES(
  1072. dac33->burst_rate,
  1073. time_delta);
  1074. delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
  1075. if (unlikely(delay > uthr))
  1076. delay = uthr;
  1077. }
  1078. break;
  1079. default:
  1080. dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
  1081. dac33->fifo_mode);
  1082. break;
  1083. }
  1084. out:
  1085. return delay;
  1086. }
  1087. static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1088. int clk_id, unsigned int freq, int dir)
  1089. {
  1090. struct snd_soc_component *component = codec_dai->component;
  1091. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  1092. u8 ioc_reg, asrcb_reg;
  1093. ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
  1094. asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B);
  1095. switch (clk_id) {
  1096. case TLV320DAC33_MCLK:
  1097. ioc_reg |= DAC33_REFSEL;
  1098. asrcb_reg |= DAC33_SRCREFSEL;
  1099. break;
  1100. case TLV320DAC33_SLEEPCLK:
  1101. ioc_reg &= ~DAC33_REFSEL;
  1102. asrcb_reg &= ~DAC33_SRCREFSEL;
  1103. break;
  1104. default:
  1105. dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id);
  1106. break;
  1107. }
  1108. dac33->refclk = freq;
  1109. dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg);
  1110. dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg);
  1111. return 0;
  1112. }
  1113. static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1114. unsigned int fmt)
  1115. {
  1116. struct snd_soc_component *component = codec_dai->component;
  1117. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  1118. u8 aictrl_a, aictrl_b;
  1119. aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
  1120. aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
  1121. /* set master/slave audio interface */
  1122. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1123. case SND_SOC_DAIFMT_CBM_CFM:
  1124. /* Codec Master */
  1125. aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
  1126. break;
  1127. case SND_SOC_DAIFMT_CBS_CFS:
  1128. /* Codec Slave */
  1129. if (dac33->fifo_mode) {
  1130. dev_err(component->dev, "FIFO mode requires master mode\n");
  1131. return -EINVAL;
  1132. } else
  1133. aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
  1134. break;
  1135. default:
  1136. return -EINVAL;
  1137. }
  1138. aictrl_a &= ~DAC33_AFMT_MASK;
  1139. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1140. case SND_SOC_DAIFMT_I2S:
  1141. aictrl_a |= DAC33_AFMT_I2S;
  1142. break;
  1143. case SND_SOC_DAIFMT_DSP_A:
  1144. aictrl_a |= DAC33_AFMT_DSP;
  1145. aictrl_b &= ~DAC33_DATA_DELAY_MASK;
  1146. aictrl_b |= DAC33_DATA_DELAY(0);
  1147. break;
  1148. case SND_SOC_DAIFMT_RIGHT_J:
  1149. aictrl_a |= DAC33_AFMT_RIGHT_J;
  1150. break;
  1151. case SND_SOC_DAIFMT_LEFT_J:
  1152. aictrl_a |= DAC33_AFMT_LEFT_J;
  1153. break;
  1154. default:
  1155. dev_err(component->dev, "Unsupported format (%u)\n",
  1156. fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1157. return -EINVAL;
  1158. }
  1159. dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
  1160. dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
  1161. return 0;
  1162. }
  1163. static int dac33_soc_probe(struct snd_soc_component *component)
  1164. {
  1165. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  1166. int ret = 0;
  1167. dac33->component = component;
  1168. /* Read the tlv320dac33 ID registers */
  1169. ret = dac33_hard_power(component, 1);
  1170. if (ret != 0) {
  1171. dev_err(component->dev, "Failed to power up component: %d\n", ret);
  1172. goto err_power;
  1173. }
  1174. ret = dac33_read_id(component);
  1175. dac33_hard_power(component, 0);
  1176. if (ret < 0) {
  1177. dev_err(component->dev, "Failed to read chip ID: %d\n", ret);
  1178. ret = -ENODEV;
  1179. goto err_power;
  1180. }
  1181. /* Check if the IRQ number is valid and request it */
  1182. if (dac33->irq >= 0) {
  1183. ret = request_irq(dac33->irq, dac33_interrupt_handler,
  1184. IRQF_TRIGGER_RISING,
  1185. component->name, component);
  1186. if (ret < 0) {
  1187. dev_err(component->dev, "Could not request IRQ%d (%d)\n",
  1188. dac33->irq, ret);
  1189. dac33->irq = -1;
  1190. }
  1191. if (dac33->irq != -1) {
  1192. INIT_WORK(&dac33->work, dac33_work);
  1193. }
  1194. }
  1195. /* Only add the FIFO controls, if we have valid IRQ number */
  1196. if (dac33->irq >= 0)
  1197. snd_soc_add_component_controls(component, dac33_mode_snd_controls,
  1198. ARRAY_SIZE(dac33_mode_snd_controls));
  1199. err_power:
  1200. return ret;
  1201. }
  1202. static void dac33_soc_remove(struct snd_soc_component *component)
  1203. {
  1204. struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
  1205. if (dac33->irq >= 0) {
  1206. free_irq(dac33->irq, dac33->component);
  1207. flush_work(&dac33->work);
  1208. }
  1209. }
  1210. static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = {
  1211. .read = dac33_read_reg_cache,
  1212. .write = dac33_write_locked,
  1213. .set_bias_level = dac33_set_bias_level,
  1214. .probe = dac33_soc_probe,
  1215. .remove = dac33_soc_remove,
  1216. .controls = dac33_snd_controls,
  1217. .num_controls = ARRAY_SIZE(dac33_snd_controls),
  1218. .dapm_widgets = dac33_dapm_widgets,
  1219. .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets),
  1220. .dapm_routes = audio_map,
  1221. .num_dapm_routes = ARRAY_SIZE(audio_map),
  1222. .use_pmdown_time = 1,
  1223. .endianness = 1,
  1224. .non_legacy_dai_naming = 1,
  1225. };
  1226. #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
  1227. SNDRV_PCM_RATE_48000)
  1228. #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1229. static const struct snd_soc_dai_ops dac33_dai_ops = {
  1230. .startup = dac33_startup,
  1231. .shutdown = dac33_shutdown,
  1232. .hw_params = dac33_hw_params,
  1233. .trigger = dac33_pcm_trigger,
  1234. .delay = dac33_dai_delay,
  1235. .set_sysclk = dac33_set_dai_sysclk,
  1236. .set_fmt = dac33_set_dai_fmt,
  1237. };
  1238. static struct snd_soc_dai_driver dac33_dai = {
  1239. .name = "tlv320dac33-hifi",
  1240. .playback = {
  1241. .stream_name = "Playback",
  1242. .channels_min = 2,
  1243. .channels_max = 2,
  1244. .rates = DAC33_RATES,
  1245. .formats = DAC33_FORMATS,
  1246. .sig_bits = 24,
  1247. },
  1248. .ops = &dac33_dai_ops,
  1249. };
  1250. static int dac33_i2c_probe(struct i2c_client *client,
  1251. const struct i2c_device_id *id)
  1252. {
  1253. struct tlv320dac33_platform_data *pdata;
  1254. struct tlv320dac33_priv *dac33;
  1255. int ret, i;
  1256. if (client->dev.platform_data == NULL) {
  1257. dev_err(&client->dev, "Platform data not set\n");
  1258. return -ENODEV;
  1259. }
  1260. pdata = client->dev.platform_data;
  1261. dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
  1262. GFP_KERNEL);
  1263. if (dac33 == NULL)
  1264. return -ENOMEM;
  1265. dac33->reg_cache = devm_kmemdup(&client->dev,
  1266. dac33_reg,
  1267. ARRAY_SIZE(dac33_reg) * sizeof(u8),
  1268. GFP_KERNEL);
  1269. if (!dac33->reg_cache)
  1270. return -ENOMEM;
  1271. dac33->i2c = client;
  1272. mutex_init(&dac33->mutex);
  1273. spin_lock_init(&dac33->lock);
  1274. i2c_set_clientdata(client, dac33);
  1275. dac33->power_gpio = pdata->power_gpio;
  1276. dac33->burst_bclkdiv = pdata->burst_bclkdiv;
  1277. dac33->keep_bclk = pdata->keep_bclk;
  1278. dac33->mode1_latency = pdata->mode1_latency;
  1279. if (!dac33->mode1_latency)
  1280. dac33->mode1_latency = 10000; /* 10ms */
  1281. dac33->irq = client->irq;
  1282. /* Disable FIFO use by default */
  1283. dac33->fifo_mode = DAC33_FIFO_BYPASS;
  1284. /* Check if the reset GPIO number is valid and request it */
  1285. if (dac33->power_gpio >= 0) {
  1286. ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
  1287. if (ret < 0) {
  1288. dev_err(&client->dev,
  1289. "Failed to request reset GPIO (%d)\n",
  1290. dac33->power_gpio);
  1291. goto err_gpio;
  1292. }
  1293. gpio_direction_output(dac33->power_gpio, 0);
  1294. }
  1295. for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
  1296. dac33->supplies[i].supply = dac33_supply_names[i];
  1297. ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
  1298. dac33->supplies);
  1299. if (ret != 0) {
  1300. dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
  1301. goto err_get;
  1302. }
  1303. ret = devm_snd_soc_register_component(&client->dev,
  1304. &soc_component_dev_tlv320dac33, &dac33_dai, 1);
  1305. if (ret < 0)
  1306. goto err_get;
  1307. return ret;
  1308. err_get:
  1309. if (dac33->power_gpio >= 0)
  1310. gpio_free(dac33->power_gpio);
  1311. err_gpio:
  1312. return ret;
  1313. }
  1314. static int dac33_i2c_remove(struct i2c_client *client)
  1315. {
  1316. struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
  1317. if (unlikely(dac33->chip_power))
  1318. dac33_hard_power(dac33->component, 0);
  1319. if (dac33->power_gpio >= 0)
  1320. gpio_free(dac33->power_gpio);
  1321. return 0;
  1322. }
  1323. static const struct i2c_device_id tlv320dac33_i2c_id[] = {
  1324. {
  1325. .name = "tlv320dac33",
  1326. .driver_data = 0,
  1327. },
  1328. { },
  1329. };
  1330. MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
  1331. static struct i2c_driver tlv320dac33_i2c_driver = {
  1332. .driver = {
  1333. .name = "tlv320dac33-codec",
  1334. },
  1335. .probe = dac33_i2c_probe,
  1336. .remove = dac33_i2c_remove,
  1337. .id_table = tlv320dac33_i2c_id,
  1338. };
  1339. module_i2c_driver(tlv320dac33_i2c_driver);
  1340. MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
  1341. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  1342. MODULE_LICENSE("GPL");