tlv320aic3x.h 8.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ALSA SoC TLV320AIC3X codec driver
  4. *
  5. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  6. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  7. */
  8. #ifndef _AIC3X_H
  9. #define _AIC3X_H
  10. /* AIC3X register space */
  11. #define AIC3X_CACHEREGNUM 110
  12. /* Page select register */
  13. #define AIC3X_PAGE_SELECT 0
  14. /* Software reset register */
  15. #define AIC3X_RESET 1
  16. /* Codec Sample rate select register */
  17. #define AIC3X_SAMPLE_RATE_SEL_REG 2
  18. /* PLL progrramming register A */
  19. #define AIC3X_PLL_PROGA_REG 3
  20. /* PLL progrramming register B */
  21. #define AIC3X_PLL_PROGB_REG 4
  22. /* PLL progrramming register C */
  23. #define AIC3X_PLL_PROGC_REG 5
  24. /* PLL progrramming register D */
  25. #define AIC3X_PLL_PROGD_REG 6
  26. /* Codec datapath setup register */
  27. #define AIC3X_CODEC_DATAPATH_REG 7
  28. /* Audio serial data interface control register A */
  29. #define AIC3X_ASD_INTF_CTRLA 8
  30. /* Audio serial data interface control register B */
  31. #define AIC3X_ASD_INTF_CTRLB 9
  32. /* Audio serial data interface control register C */
  33. #define AIC3X_ASD_INTF_CTRLC 10
  34. /* Audio overflow status and PLL R value programming register */
  35. #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
  36. /* Audio codec digital filter control register */
  37. #define AIC3X_CODEC_DFILT_CTRL 12
  38. /* Headset/button press detection register */
  39. #define AIC3X_HEADSET_DETECT_CTRL_A 13
  40. #define AIC3X_HEADSET_DETECT_CTRL_B 14
  41. /* ADC PGA Gain control registers */
  42. #define LADC_VOL 15
  43. #define RADC_VOL 16
  44. /* MIC3 control registers */
  45. #define MIC3LR_2_LADC_CTRL 17
  46. #define MIC3LR_2_RADC_CTRL 18
  47. /* Line1 Input control registers */
  48. #define LINE1L_2_LADC_CTRL 19
  49. #define LINE1R_2_LADC_CTRL 21
  50. #define LINE1R_2_RADC_CTRL 22
  51. #define LINE1L_2_RADC_CTRL 24
  52. /* Line2 Input control registers */
  53. #define LINE2L_2_LADC_CTRL 20
  54. #define LINE2R_2_RADC_CTRL 23
  55. /* MICBIAS Control Register */
  56. #define MICBIAS_CTRL 25
  57. /* AGC Control Registers A, B, C */
  58. #define LAGC_CTRL_A 26
  59. #define LAGC_CTRL_B 27
  60. #define LAGC_CTRL_C 28
  61. #define RAGC_CTRL_A 29
  62. #define RAGC_CTRL_B 30
  63. #define RAGC_CTRL_C 31
  64. /* DAC Power and Left High Power Output control registers */
  65. #define DAC_PWR 37
  66. #define HPLCOM_CFG 37
  67. /* Right High Power Output control registers */
  68. #define HPRCOM_CFG 38
  69. /* High Power Output Stage Control Register */
  70. #define HPOUT_SC 40
  71. /* DAC Output Switching control registers */
  72. #define DAC_LINE_MUX 41
  73. /* High Power Output Driver Pop Reduction registers */
  74. #define HPOUT_POP_REDUCTION 42
  75. /* DAC Digital control registers */
  76. #define LDAC_VOL 43
  77. #define RDAC_VOL 44
  78. /* Left High Power Output control registers */
  79. #define LINE2L_2_HPLOUT_VOL 45
  80. #define PGAL_2_HPLOUT_VOL 46
  81. #define DACL1_2_HPLOUT_VOL 47
  82. #define LINE2R_2_HPLOUT_VOL 48
  83. #define PGAR_2_HPLOUT_VOL 49
  84. #define DACR1_2_HPLOUT_VOL 50
  85. #define HPLOUT_CTRL 51
  86. /* Left High Power COM control registers */
  87. #define LINE2L_2_HPLCOM_VOL 52
  88. #define PGAL_2_HPLCOM_VOL 53
  89. #define DACL1_2_HPLCOM_VOL 54
  90. #define LINE2R_2_HPLCOM_VOL 55
  91. #define PGAR_2_HPLCOM_VOL 56
  92. #define DACR1_2_HPLCOM_VOL 57
  93. #define HPLCOM_CTRL 58
  94. /* Right High Power Output control registers */
  95. #define LINE2L_2_HPROUT_VOL 59
  96. #define PGAL_2_HPROUT_VOL 60
  97. #define DACL1_2_HPROUT_VOL 61
  98. #define LINE2R_2_HPROUT_VOL 62
  99. #define PGAR_2_HPROUT_VOL 63
  100. #define DACR1_2_HPROUT_VOL 64
  101. #define HPROUT_CTRL 65
  102. /* Right High Power COM control registers */
  103. #define LINE2L_2_HPRCOM_VOL 66
  104. #define PGAL_2_HPRCOM_VOL 67
  105. #define DACL1_2_HPRCOM_VOL 68
  106. #define LINE2R_2_HPRCOM_VOL 69
  107. #define PGAR_2_HPRCOM_VOL 70
  108. #define DACR1_2_HPRCOM_VOL 71
  109. #define HPRCOM_CTRL 72
  110. /* Mono Line Output Plus/Minus control registers */
  111. #define LINE2L_2_MONOLOPM_VOL 73
  112. #define PGAL_2_MONOLOPM_VOL 74
  113. #define DACL1_2_MONOLOPM_VOL 75
  114. #define LINE2R_2_MONOLOPM_VOL 76
  115. #define PGAR_2_MONOLOPM_VOL 77
  116. #define DACR1_2_MONOLOPM_VOL 78
  117. #define MONOLOPM_CTRL 79
  118. /* Class-D speaker driver on tlv320aic3007 */
  119. #define CLASSD_CTRL 73
  120. /* Left Line Output Plus/Minus control registers */
  121. #define LINE2L_2_LLOPM_VOL 80
  122. #define PGAL_2_LLOPM_VOL 81
  123. #define DACL1_2_LLOPM_VOL 82
  124. #define LINE2R_2_LLOPM_VOL 83
  125. #define PGAR_2_LLOPM_VOL 84
  126. #define DACR1_2_LLOPM_VOL 85
  127. #define LLOPM_CTRL 86
  128. /* Right Line Output Plus/Minus control registers */
  129. #define LINE2L_2_RLOPM_VOL 87
  130. #define PGAL_2_RLOPM_VOL 88
  131. #define DACL1_2_RLOPM_VOL 89
  132. #define LINE2R_2_RLOPM_VOL 90
  133. #define PGAR_2_RLOPM_VOL 91
  134. #define DACR1_2_RLOPM_VOL 92
  135. #define RLOPM_CTRL 93
  136. /* GPIO/IRQ registers */
  137. #define AIC3X_STICKY_IRQ_FLAGS_REG 96
  138. #define AIC3X_RT_IRQ_FLAGS_REG 97
  139. #define AIC3X_GPIO1_REG 98
  140. #define AIC3X_GPIO2_REG 99
  141. #define AIC3X_GPIOA_REG 100
  142. #define AIC3X_GPIOB_REG 101
  143. /* Clock generation control register */
  144. #define AIC3X_CLKGEN_CTRL_REG 102
  145. /* New AGC registers */
  146. #define LAGCN_ATTACK 103
  147. #define LAGCN_DECAY 104
  148. #define RAGCN_ATTACK 105
  149. #define RAGCN_DECAY 106
  150. /* New Programmable ADC Digital Path and I2C Bus Condition Register */
  151. #define NEW_ADC_DIGITALPATH 107
  152. /* Passive Analog Signal Bypass Selection During Powerdown Register */
  153. #define PASSIVE_BYPASS 108
  154. /* DAC Quiescent Current Adjustment Register */
  155. #define DAC_ICC_ADJ 109
  156. /* Page select register bits */
  157. #define PAGE0_SELECT 0
  158. #define PAGE1_SELECT 1
  159. /* Audio serial data interface control register A bits */
  160. #define BIT_CLK_MASTER 0x80
  161. #define WORD_CLK_MASTER 0x40
  162. #define DOUT_TRISTATE 0x20
  163. /* Codec Datapath setup register 7 */
  164. #define FSREF_44100 (1 << 7)
  165. #define FSREF_48000 (0 << 7)
  166. #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
  167. #define LDAC2LCH (0x1 << 3)
  168. #define RDAC2RCH (0x1 << 1)
  169. #define LDAC2RCH (0x2 << 3)
  170. #define RDAC2LCH (0x2 << 1)
  171. #define LDAC2MONOMIX (0x3 << 3)
  172. #define RDAC2MONOMIX (0x3 << 1)
  173. /* PLL registers bitfields */
  174. #define PLLP_SHIFT 0
  175. #define PLLP_MASK 7
  176. #define PLLQ_SHIFT 3
  177. #define PLLR_SHIFT 0
  178. #define PLLJ_SHIFT 2
  179. #define PLLD_MSB_SHIFT 0
  180. #define PLLD_LSB_SHIFT 2
  181. /* Clock generation register bits */
  182. #define CODEC_CLKIN_PLLDIV 0
  183. #define CODEC_CLKIN_CLKDIV 1
  184. #define PLL_CLKIN_SHIFT 4
  185. #define MCLK_SOURCE 0x0
  186. #define PLL_CLKDIV_SHIFT 0
  187. #define PLLCLK_IN_MASK 0x30
  188. #define PLLCLK_IN_SHIFT 4
  189. #define CLKDIV_IN_MASK 0xc0
  190. #define CLKDIV_IN_SHIFT 6
  191. /* clock in source */
  192. #define CLKIN_MCLK 0
  193. #define CLKIN_GPIO2 1
  194. #define CLKIN_BCLK 2
  195. /* Software reset register bits */
  196. #define SOFT_RESET 0x80
  197. /* PLL progrramming register A bits */
  198. #define PLL_ENABLE 0x80
  199. /* Route bits */
  200. #define ROUTE_ON 0x80
  201. /* Mute bits */
  202. #define UNMUTE 0x08
  203. #define MUTE_ON 0x80
  204. /* Power bits */
  205. #define LADC_PWR_ON 0x04
  206. #define RADC_PWR_ON 0x04
  207. #define LDAC_PWR_ON 0x80
  208. #define RDAC_PWR_ON 0x40
  209. #define HPLOUT_PWR_ON 0x01
  210. #define HPROUT_PWR_ON 0x01
  211. #define HPLCOM_PWR_ON 0x01
  212. #define HPRCOM_PWR_ON 0x01
  213. #define MONOLOPM_PWR_ON 0x01
  214. #define LLOPM_PWR_ON 0x01
  215. #define RLOPM_PWR_ON 0x01
  216. #define INVERT_VOL(val) (0x7f - val)
  217. /* Default output volume (inverted) */
  218. #define DEFAULT_VOL INVERT_VOL(0x50)
  219. /* Default input volume */
  220. #define DEFAULT_GAIN 0x20
  221. /* MICBIAS Control Register */
  222. #define MICBIAS_LEVEL_SHIFT (6)
  223. #define MICBIAS_LEVEL_MASK (3 << 6)
  224. /* HPOUT_SC */
  225. #define HPOUT_SC_OCMV_MASK (3 << 6)
  226. #define HPOUT_SC_OCMV_SHIFT (6)
  227. #define HPOUT_SC_OCMV_1_35V 0
  228. #define HPOUT_SC_OCMV_1_5V 1
  229. #define HPOUT_SC_OCMV_1_65V 2
  230. #define HPOUT_SC_OCMV_1_8V 3
  231. /* headset detection / button API */
  232. /* The AIC3x supports detection of stereo headsets (GND + left + right signal)
  233. * and cellular headsets (GND + speaker output + microphone input).
  234. * It is recommended to enable MIC bias for this function to work properly.
  235. * For more information, please refer to the datasheet. */
  236. enum {
  237. AIC3X_HEADSET_DETECT_OFF = 0,
  238. AIC3X_HEADSET_DETECT_STEREO = 1,
  239. AIC3X_HEADSET_DETECT_CELLULAR = 2,
  240. AIC3X_HEADSET_DETECT_BOTH = 3
  241. };
  242. enum {
  243. AIC3X_HEADSET_DEBOUNCE_16MS = 0,
  244. AIC3X_HEADSET_DEBOUNCE_32MS = 1,
  245. AIC3X_HEADSET_DEBOUNCE_64MS = 2,
  246. AIC3X_HEADSET_DEBOUNCE_128MS = 3,
  247. AIC3X_HEADSET_DEBOUNCE_256MS = 4,
  248. AIC3X_HEADSET_DEBOUNCE_512MS = 5
  249. };
  250. enum {
  251. AIC3X_BUTTON_DEBOUNCE_0MS = 0,
  252. AIC3X_BUTTON_DEBOUNCE_8MS = 1,
  253. AIC3X_BUTTON_DEBOUNCE_16MS = 2,
  254. AIC3X_BUTTON_DEBOUNCE_32MS = 3
  255. };
  256. #define AIC3X_HEADSET_DETECT_ENABLED 0x80
  257. #define AIC3X_HEADSET_DETECT_SHIFT 5
  258. #define AIC3X_HEADSET_DETECT_MASK 3
  259. #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
  260. #define AIC3X_HEADSET_DEBOUNCE_MASK 7
  261. #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
  262. #define AIC3X_BUTTON_DEBOUNCE_MASK 3
  263. #endif /* _AIC3X_H */