tlv320aic3x.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ALSA SoC TLV320AIC3X codec driver
  4. *
  5. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  6. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  7. *
  8. * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
  9. *
  10. * Notes:
  11. * The AIC3X is a driver for a low power stereo audio
  12. * codecs aic31, aic32, aic33, aic3007.
  13. *
  14. * It supports full aic33 codec functionality.
  15. * The compatibility with aic32, aic31 and aic3007 is as follows:
  16. * aic32/aic3007 | aic31
  17. * ---------------------------------------
  18. * MONO_LOUT -> N/A | MONO_LOUT -> N/A
  19. * | IN1L -> LINE1L
  20. * | IN1R -> LINE1R
  21. * | IN2L -> LINE2L
  22. * | IN2R -> LINE2R
  23. * | MIC3L/R -> N/A
  24. * truncated internal functionality in
  25. * accordance with documentation
  26. * ---------------------------------------
  27. *
  28. * Hence the machine layer should disable unsupported inputs/outputs by
  29. * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
  30. */
  31. #include <linux/module.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/init.h>
  34. #include <linux/delay.h>
  35. #include <linux/pm.h>
  36. #include <linux/i2c.h>
  37. #include <linux/gpio.h>
  38. #include <linux/regulator/consumer.h>
  39. #include <linux/of.h>
  40. #include <linux/of_gpio.h>
  41. #include <linux/slab.h>
  42. #include <sound/core.h>
  43. #include <sound/pcm.h>
  44. #include <sound/pcm_params.h>
  45. #include <sound/soc.h>
  46. #include <sound/initval.h>
  47. #include <sound/tlv.h>
  48. #include <sound/tlv320aic3x.h>
  49. #include "tlv320aic3x.h"
  50. #define AIC3X_NUM_SUPPLIES 4
  51. static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
  52. "IOVDD", /* I/O Voltage */
  53. "DVDD", /* Digital Core Voltage */
  54. "AVDD", /* Analog DAC Voltage */
  55. "DRVDD", /* ADC Analog and Output Driver Voltage */
  56. };
  57. static LIST_HEAD(reset_list);
  58. struct aic3x_priv;
  59. struct aic3x_disable_nb {
  60. struct notifier_block nb;
  61. struct aic3x_priv *aic3x;
  62. };
  63. /* codec private data */
  64. struct aic3x_priv {
  65. struct snd_soc_component *component;
  66. struct regmap *regmap;
  67. struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
  68. struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
  69. struct aic3x_setup_data *setup;
  70. unsigned int sysclk;
  71. unsigned int dai_fmt;
  72. unsigned int tdm_delay;
  73. unsigned int slot_width;
  74. struct list_head list;
  75. int master;
  76. int gpio_reset;
  77. int power;
  78. #define AIC3X_MODEL_3X 0
  79. #define AIC3X_MODEL_33 1
  80. #define AIC3X_MODEL_3007 2
  81. #define AIC3X_MODEL_3104 3
  82. u16 model;
  83. /* Selects the micbias voltage */
  84. enum aic3x_micbias_voltage micbias_vg;
  85. /* Output Common-Mode Voltage */
  86. u8 ocmv;
  87. };
  88. static const struct reg_default aic3x_reg[] = {
  89. { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
  90. { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
  91. { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
  92. { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
  93. { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
  94. { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
  95. { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
  96. { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
  97. { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
  98. { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
  99. { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
  100. { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
  101. { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
  102. { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
  103. { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
  104. { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
  105. { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
  106. { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
  107. { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
  108. { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
  109. { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
  110. { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
  111. { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
  112. { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
  113. { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
  114. { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
  115. { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
  116. { 108, 0x00 }, { 109, 0x00 },
  117. };
  118. static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
  119. {
  120. switch (reg) {
  121. case AIC3X_RESET:
  122. return true;
  123. default:
  124. return false;
  125. }
  126. }
  127. static const struct regmap_config aic3x_regmap = {
  128. .reg_bits = 8,
  129. .val_bits = 8,
  130. .max_register = DAC_ICC_ADJ,
  131. .reg_defaults = aic3x_reg,
  132. .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
  133. .volatile_reg = aic3x_volatile_reg,
  134. .cache_type = REGCACHE_RBTREE,
  135. };
  136. #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
  137. SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
  138. snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
  139. /*
  140. * All input lines are connected when !0xf and disconnected with 0xf bit field,
  141. * so we have to use specific dapm_put call for input mixer
  142. */
  143. static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
  144. struct snd_ctl_elem_value *ucontrol)
  145. {
  146. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  147. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  148. struct soc_mixer_control *mc =
  149. (struct soc_mixer_control *)kcontrol->private_value;
  150. unsigned int reg = mc->reg;
  151. unsigned int shift = mc->shift;
  152. int max = mc->max;
  153. unsigned int mask = (1 << fls(max)) - 1;
  154. unsigned int invert = mc->invert;
  155. unsigned short val;
  156. struct snd_soc_dapm_update update = {};
  157. int connect, change;
  158. val = (ucontrol->value.integer.value[0] & mask);
  159. mask = 0xf;
  160. if (val)
  161. val = mask;
  162. connect = !!val;
  163. if (invert)
  164. val = mask - val;
  165. mask <<= shift;
  166. val <<= shift;
  167. change = snd_soc_component_test_bits(component, reg, mask, val);
  168. if (change) {
  169. update.kcontrol = kcontrol;
  170. update.reg = reg;
  171. update.mask = mask;
  172. update.val = val;
  173. snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
  174. &update);
  175. }
  176. return change;
  177. }
  178. /*
  179. * mic bias power on/off share the same register bits with
  180. * output voltage of mic bias. when power on mic bias, we
  181. * need reclaim it to voltage value.
  182. * 0x0 = Powered off
  183. * 0x1 = MICBIAS output is powered to 2.0V,
  184. * 0x2 = MICBIAS output is powered to 2.5V
  185. * 0x3 = MICBIAS output is connected to AVDD
  186. */
  187. static int mic_bias_event(struct snd_soc_dapm_widget *w,
  188. struct snd_kcontrol *kcontrol, int event)
  189. {
  190. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  191. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  192. switch (event) {
  193. case SND_SOC_DAPM_POST_PMU:
  194. /* change mic bias voltage to user defined */
  195. snd_soc_component_update_bits(component, MICBIAS_CTRL,
  196. MICBIAS_LEVEL_MASK,
  197. aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
  198. break;
  199. case SND_SOC_DAPM_PRE_PMD:
  200. snd_soc_component_update_bits(component, MICBIAS_CTRL,
  201. MICBIAS_LEVEL_MASK, 0);
  202. break;
  203. }
  204. return 0;
  205. }
  206. static const char * const aic3x_left_dac_mux[] = {
  207. "DAC_L1", "DAC_L3", "DAC_L2" };
  208. static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
  209. aic3x_left_dac_mux);
  210. static const char * const aic3x_right_dac_mux[] = {
  211. "DAC_R1", "DAC_R3", "DAC_R2" };
  212. static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
  213. aic3x_right_dac_mux);
  214. static const char * const aic3x_left_hpcom_mux[] = {
  215. "differential of HPLOUT", "constant VCM", "single-ended" };
  216. static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
  217. aic3x_left_hpcom_mux);
  218. static const char * const aic3x_right_hpcom_mux[] = {
  219. "differential of HPROUT", "constant VCM", "single-ended",
  220. "differential of HPLCOM", "external feedback" };
  221. static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
  222. aic3x_right_hpcom_mux);
  223. static const char * const aic3x_linein_mode_mux[] = {
  224. "single-ended", "differential" };
  225. static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
  226. aic3x_linein_mode_mux);
  227. static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
  228. aic3x_linein_mode_mux);
  229. static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
  230. aic3x_linein_mode_mux);
  231. static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
  232. aic3x_linein_mode_mux);
  233. static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
  234. aic3x_linein_mode_mux);
  235. static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
  236. aic3x_linein_mode_mux);
  237. static const char * const aic3x_adc_hpf[] = {
  238. "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
  239. static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
  240. aic3x_adc_hpf);
  241. static const char * const aic3x_agc_level[] = {
  242. "-5.5dB", "-8dB", "-10dB", "-12dB",
  243. "-14dB", "-17dB", "-20dB", "-24dB" };
  244. static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
  245. aic3x_agc_level);
  246. static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
  247. aic3x_agc_level);
  248. static const char * const aic3x_agc_attack[] = {
  249. "8ms", "11ms", "16ms", "20ms" };
  250. static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
  251. aic3x_agc_attack);
  252. static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
  253. aic3x_agc_attack);
  254. static const char * const aic3x_agc_decay[] = {
  255. "100ms", "200ms", "400ms", "500ms" };
  256. static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
  257. aic3x_agc_decay);
  258. static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
  259. aic3x_agc_decay);
  260. static const char * const aic3x_poweron_time[] = {
  261. "0us", "10us", "100us", "1ms", "10ms", "50ms",
  262. "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
  263. static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
  264. aic3x_poweron_time);
  265. static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
  266. static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
  267. aic3x_rampup_step);
  268. /*
  269. * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
  270. */
  271. static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
  272. /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
  273. static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
  274. /*
  275. * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
  276. * Step size is approximately 0.5 dB over most of the scale but increasing
  277. * near the very low levels.
  278. * Define dB scale so that it is mostly correct for range about -55 to 0 dB
  279. * but having increasing dB difference below that (and where it doesn't count
  280. * so much). This setting shows -50 dB (actual is -50.3 dB) for register
  281. * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
  282. */
  283. static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
  284. /* Output volumes. From 0 to 9 dB in 1 dB steps */
  285. static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0);
  286. static const struct snd_kcontrol_new aic3x_snd_controls[] = {
  287. /* Output */
  288. SOC_DOUBLE_R_TLV("PCM Playback Volume",
  289. LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
  290. /*
  291. * Output controls that map to output mixer switches. Note these are
  292. * only for swapped L-to-R and R-to-L routes. See below stereo controls
  293. * for direct L-to-L and R-to-R routes.
  294. */
  295. SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
  296. PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  297. SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
  298. DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  299. SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
  300. PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  301. SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
  302. DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  303. SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
  304. PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  305. SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
  306. DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  307. SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
  308. PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  309. SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
  310. DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  311. SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
  312. PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  313. SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
  314. DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  315. SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
  316. PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  317. SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
  318. DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  319. /* Stereo output controls for direct L-to-L and R-to-R routes */
  320. SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
  321. PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
  322. 0, 118, 1, output_stage_tlv),
  323. SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
  324. DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
  325. 0, 118, 1, output_stage_tlv),
  326. SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
  327. PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
  328. 0, 118, 1, output_stage_tlv),
  329. SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
  330. DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
  331. 0, 118, 1, output_stage_tlv),
  332. SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
  333. PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
  334. 0, 118, 1, output_stage_tlv),
  335. SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
  336. DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
  337. 0, 118, 1, output_stage_tlv),
  338. /* Output pin controls */
  339. SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
  340. 9, 0, out_tlv),
  341. SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
  342. 0x01, 0),
  343. SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
  344. 9, 0, out_tlv),
  345. SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
  346. 0x01, 0),
  347. SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL,
  348. 4, 9, 0, out_tlv),
  349. SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
  350. 0x01, 0),
  351. /*
  352. * Note: enable Automatic input Gain Controller with care. It can
  353. * adjust PGA to max value when ADC is on and will never go back.
  354. */
  355. SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
  356. SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
  357. SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
  358. SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
  359. SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
  360. SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
  361. SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
  362. /* De-emphasis */
  363. SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
  364. /* Input */
  365. SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
  366. 0, 119, 0, adc_tlv),
  367. SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
  368. SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
  369. /* Pop reduction */
  370. SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
  371. SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
  372. };
  373. /* For other than tlv320aic3104 */
  374. static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
  375. /*
  376. * Output controls that map to output mixer switches. Note these are
  377. * only for swapped L-to-R and R-to-L routes. See below stereo controls
  378. * for direct L-to-L and R-to-R routes.
  379. */
  380. SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
  381. LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  382. SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
  383. LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  384. SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
  385. LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  386. SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
  387. LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  388. SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
  389. LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  390. SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
  391. LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  392. /* Stereo output controls for direct L-to-L and R-to-R routes */
  393. SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
  394. LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
  395. 0, 118, 1, output_stage_tlv),
  396. SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
  397. LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
  398. 0, 118, 1, output_stage_tlv),
  399. SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
  400. LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
  401. 0, 118, 1, output_stage_tlv),
  402. };
  403. static const struct snd_kcontrol_new aic3x_mono_controls[] = {
  404. SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
  405. LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
  406. 0, 118, 1, output_stage_tlv),
  407. SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
  408. PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
  409. 0, 118, 1, output_stage_tlv),
  410. SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
  411. DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
  412. 0, 118, 1, output_stage_tlv),
  413. SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
  414. SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
  415. out_tlv),
  416. };
  417. /*
  418. * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
  419. */
  420. static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
  421. static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
  422. SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
  423. /* Left DAC Mux */
  424. static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
  425. SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
  426. /* Right DAC Mux */
  427. static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
  428. SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
  429. /* Left HPCOM Mux */
  430. static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
  431. SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
  432. /* Right HPCOM Mux */
  433. static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
  434. SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
  435. /* Left Line Mixer */
  436. static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
  437. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
  438. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
  439. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
  440. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
  441. /* Not on tlv320aic3104 */
  442. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
  443. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
  444. };
  445. /* Right Line Mixer */
  446. static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
  447. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
  448. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
  449. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
  450. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
  451. /* Not on tlv320aic3104 */
  452. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
  453. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
  454. };
  455. /* Mono Mixer */
  456. static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
  457. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
  458. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
  459. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
  460. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
  461. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
  462. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
  463. };
  464. /* Left HP Mixer */
  465. static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
  466. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
  467. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
  468. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
  469. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
  470. /* Not on tlv320aic3104 */
  471. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
  472. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
  473. };
  474. /* Right HP Mixer */
  475. static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
  476. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
  477. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
  478. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
  479. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
  480. /* Not on tlv320aic3104 */
  481. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
  482. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
  483. };
  484. /* Left HPCOM Mixer */
  485. static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
  486. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
  487. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
  488. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
  489. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
  490. /* Not on tlv320aic3104 */
  491. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
  492. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
  493. };
  494. /* Right HPCOM Mixer */
  495. static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
  496. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
  497. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
  498. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
  499. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
  500. /* Not on tlv320aic3104 */
  501. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
  502. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
  503. };
  504. /* Left PGA Mixer */
  505. static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
  506. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
  507. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
  508. SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
  509. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
  510. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
  511. };
  512. /* Right PGA Mixer */
  513. static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
  514. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
  515. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
  516. SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
  517. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
  518. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
  519. };
  520. /* Left PGA Mixer for tlv320aic3104 */
  521. static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
  522. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
  523. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
  524. SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
  525. SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
  526. };
  527. /* Right PGA Mixer for tlv320aic3104 */
  528. static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
  529. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
  530. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
  531. SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
  532. SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
  533. };
  534. /* Left Line1 Mux */
  535. static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
  536. SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
  537. static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
  538. SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
  539. /* Right Line1 Mux */
  540. static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
  541. SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
  542. static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
  543. SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
  544. /* Left Line2 Mux */
  545. static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
  546. SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
  547. /* Right Line2 Mux */
  548. static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
  549. SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
  550. static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
  551. /* Left DAC to Left Outputs */
  552. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
  553. SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
  554. &aic3x_left_dac_mux_controls),
  555. SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
  556. &aic3x_left_hpcom_mux_controls),
  557. SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
  558. SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
  559. SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
  560. /* Right DAC to Right Outputs */
  561. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
  562. SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
  563. &aic3x_right_dac_mux_controls),
  564. SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
  565. &aic3x_right_hpcom_mux_controls),
  566. SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
  567. SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
  568. SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
  569. /* Inputs to Left ADC */
  570. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
  571. SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
  572. &aic3x_left_line1l_mux_controls),
  573. SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
  574. &aic3x_left_line1r_mux_controls),
  575. /* Inputs to Right ADC */
  576. SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
  577. LINE1R_2_RADC_CTRL, 2, 0),
  578. SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
  579. &aic3x_right_line1l_mux_controls),
  580. SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
  581. &aic3x_right_line1r_mux_controls),
  582. /* Mic Bias */
  583. SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
  584. mic_bias_event,
  585. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  586. SND_SOC_DAPM_OUTPUT("LLOUT"),
  587. SND_SOC_DAPM_OUTPUT("RLOUT"),
  588. SND_SOC_DAPM_OUTPUT("HPLOUT"),
  589. SND_SOC_DAPM_OUTPUT("HPROUT"),
  590. SND_SOC_DAPM_OUTPUT("HPLCOM"),
  591. SND_SOC_DAPM_OUTPUT("HPRCOM"),
  592. SND_SOC_DAPM_INPUT("LINE1L"),
  593. SND_SOC_DAPM_INPUT("LINE1R"),
  594. /*
  595. * Virtual output pin to detection block inside codec. This can be
  596. * used to keep codec bias on if gpio or detection features are needed.
  597. * Force pin on or construct a path with an input jack and mic bias
  598. * widgets.
  599. */
  600. SND_SOC_DAPM_OUTPUT("Detection"),
  601. };
  602. /* For other than tlv320aic3104 */
  603. static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
  604. /* Inputs to Left ADC */
  605. SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
  606. &aic3x_left_pga_mixer_controls[0],
  607. ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
  608. SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
  609. &aic3x_left_line2_mux_controls),
  610. /* Inputs to Right ADC */
  611. SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
  612. &aic3x_right_pga_mixer_controls[0],
  613. ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
  614. SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
  615. &aic3x_right_line2_mux_controls),
  616. /*
  617. * Not a real mic bias widget but similar function. This is for dynamic
  618. * control of GPIO1 digital mic modulator clock output function when
  619. * using digital mic.
  620. */
  621. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
  622. AIC3X_GPIO1_REG, 4, 0xf,
  623. AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
  624. AIC3X_GPIO1_FUNC_DISABLED),
  625. /*
  626. * Also similar function like mic bias. Selects digital mic with
  627. * configurable oversampling rate instead of ADC converter.
  628. */
  629. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
  630. AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
  631. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
  632. AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
  633. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
  634. AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
  635. /* Output mixers */
  636. SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
  637. &aic3x_left_line_mixer_controls[0],
  638. ARRAY_SIZE(aic3x_left_line_mixer_controls)),
  639. SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
  640. &aic3x_right_line_mixer_controls[0],
  641. ARRAY_SIZE(aic3x_right_line_mixer_controls)),
  642. SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
  643. &aic3x_left_hp_mixer_controls[0],
  644. ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
  645. SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
  646. &aic3x_right_hp_mixer_controls[0],
  647. ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
  648. SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  649. &aic3x_left_hpcom_mixer_controls[0],
  650. ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
  651. SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  652. &aic3x_right_hpcom_mixer_controls[0],
  653. ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
  654. SND_SOC_DAPM_INPUT("MIC3L"),
  655. SND_SOC_DAPM_INPUT("MIC3R"),
  656. SND_SOC_DAPM_INPUT("LINE2L"),
  657. SND_SOC_DAPM_INPUT("LINE2R"),
  658. };
  659. /* For tlv320aic3104 */
  660. static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
  661. /* Inputs to Left ADC */
  662. SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
  663. &aic3104_left_pga_mixer_controls[0],
  664. ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
  665. /* Inputs to Right ADC */
  666. SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
  667. &aic3104_right_pga_mixer_controls[0],
  668. ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
  669. /* Output mixers */
  670. SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
  671. &aic3x_left_line_mixer_controls[0],
  672. ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
  673. SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
  674. &aic3x_right_line_mixer_controls[0],
  675. ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
  676. SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
  677. &aic3x_left_hp_mixer_controls[0],
  678. ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
  679. SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
  680. &aic3x_right_hp_mixer_controls[0],
  681. ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
  682. SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  683. &aic3x_left_hpcom_mixer_controls[0],
  684. ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
  685. SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  686. &aic3x_right_hpcom_mixer_controls[0],
  687. ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
  688. SND_SOC_DAPM_INPUT("MIC2L"),
  689. SND_SOC_DAPM_INPUT("MIC2R"),
  690. };
  691. static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
  692. /* Mono Output */
  693. SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
  694. SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
  695. &aic3x_mono_mixer_controls[0],
  696. ARRAY_SIZE(aic3x_mono_mixer_controls)),
  697. SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
  698. };
  699. static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
  700. /* Class-D outputs */
  701. SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
  702. SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
  703. SND_SOC_DAPM_OUTPUT("SPOP"),
  704. SND_SOC_DAPM_OUTPUT("SPOM"),
  705. };
  706. static const struct snd_soc_dapm_route intercon[] = {
  707. /* Left Input */
  708. {"Left Line1L Mux", "single-ended", "LINE1L"},
  709. {"Left Line1L Mux", "differential", "LINE1L"},
  710. {"Left Line1R Mux", "single-ended", "LINE1R"},
  711. {"Left Line1R Mux", "differential", "LINE1R"},
  712. {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
  713. {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
  714. {"Left ADC", NULL, "Left PGA Mixer"},
  715. /* Right Input */
  716. {"Right Line1R Mux", "single-ended", "LINE1R"},
  717. {"Right Line1R Mux", "differential", "LINE1R"},
  718. {"Right Line1L Mux", "single-ended", "LINE1L"},
  719. {"Right Line1L Mux", "differential", "LINE1L"},
  720. {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
  721. {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
  722. {"Right ADC", NULL, "Right PGA Mixer"},
  723. /* Left DAC Output */
  724. {"Left DAC Mux", "DAC_L1", "Left DAC"},
  725. {"Left DAC Mux", "DAC_L2", "Left DAC"},
  726. {"Left DAC Mux", "DAC_L3", "Left DAC"},
  727. /* Right DAC Output */
  728. {"Right DAC Mux", "DAC_R1", "Right DAC"},
  729. {"Right DAC Mux", "DAC_R2", "Right DAC"},
  730. {"Right DAC Mux", "DAC_R3", "Right DAC"},
  731. /* Left Line Output */
  732. {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  733. {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
  734. {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  735. {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
  736. {"Left Line Out", NULL, "Left Line Mixer"},
  737. {"Left Line Out", NULL, "Left DAC Mux"},
  738. {"LLOUT", NULL, "Left Line Out"},
  739. /* Right Line Output */
  740. {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  741. {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
  742. {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  743. {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
  744. {"Right Line Out", NULL, "Right Line Mixer"},
  745. {"Right Line Out", NULL, "Right DAC Mux"},
  746. {"RLOUT", NULL, "Right Line Out"},
  747. /* Left HP Output */
  748. {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  749. {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
  750. {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  751. {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
  752. {"Left HP Out", NULL, "Left HP Mixer"},
  753. {"Left HP Out", NULL, "Left DAC Mux"},
  754. {"HPLOUT", NULL, "Left HP Out"},
  755. /* Right HP Output */
  756. {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  757. {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
  758. {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  759. {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
  760. {"Right HP Out", NULL, "Right HP Mixer"},
  761. {"Right HP Out", NULL, "Right DAC Mux"},
  762. {"HPROUT", NULL, "Right HP Out"},
  763. /* Left HPCOM Output */
  764. {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  765. {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
  766. {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  767. {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
  768. {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
  769. {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
  770. {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
  771. {"Left HP Com", NULL, "Left HPCOM Mux"},
  772. {"HPLCOM", NULL, "Left HP Com"},
  773. /* Right HPCOM Output */
  774. {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  775. {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
  776. {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  777. {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
  778. {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
  779. {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
  780. {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
  781. {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
  782. {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
  783. {"Right HP Com", NULL, "Right HPCOM Mux"},
  784. {"HPRCOM", NULL, "Right HP Com"},
  785. };
  786. /* For other than tlv320aic3104 */
  787. static const struct snd_soc_dapm_route intercon_extra[] = {
  788. /* Left Input */
  789. {"Left Line2L Mux", "single-ended", "LINE2L"},
  790. {"Left Line2L Mux", "differential", "LINE2L"},
  791. {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
  792. {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
  793. {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
  794. {"Left ADC", NULL, "GPIO1 dmic modclk"},
  795. /* Right Input */
  796. {"Right Line2R Mux", "single-ended", "LINE2R"},
  797. {"Right Line2R Mux", "differential", "LINE2R"},
  798. {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
  799. {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
  800. {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
  801. {"Right ADC", NULL, "GPIO1 dmic modclk"},
  802. /*
  803. * Logical path between digital mic enable and GPIO1 modulator clock
  804. * output function
  805. */
  806. {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
  807. {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
  808. {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
  809. /* Left Line Output */
  810. {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  811. {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  812. /* Right Line Output */
  813. {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  814. {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  815. /* Left HP Output */
  816. {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  817. {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  818. /* Right HP Output */
  819. {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  820. {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  821. /* Left HPCOM Output */
  822. {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  823. {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  824. /* Right HPCOM Output */
  825. {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  826. {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  827. };
  828. /* For tlv320aic3104 */
  829. static const struct snd_soc_dapm_route intercon_extra_3104[] = {
  830. /* Left Input */
  831. {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
  832. {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
  833. /* Right Input */
  834. {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
  835. {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
  836. };
  837. static const struct snd_soc_dapm_route intercon_mono[] = {
  838. /* Mono Output */
  839. {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  840. {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  841. {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
  842. {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  843. {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  844. {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
  845. {"Mono Out", NULL, "Mono Mixer"},
  846. {"MONO_LOUT", NULL, "Mono Out"},
  847. };
  848. static const struct snd_soc_dapm_route intercon_3007[] = {
  849. /* Class-D outputs */
  850. {"Left Class-D Out", NULL, "Left Line Out"},
  851. {"Right Class-D Out", NULL, "Left Line Out"},
  852. {"SPOP", NULL, "Left Class-D Out"},
  853. {"SPOM", NULL, "Right Class-D Out"},
  854. };
  855. static int aic3x_add_widgets(struct snd_soc_component *component)
  856. {
  857. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  858. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  859. switch (aic3x->model) {
  860. case AIC3X_MODEL_3X:
  861. case AIC3X_MODEL_33:
  862. snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
  863. ARRAY_SIZE(aic3x_extra_dapm_widgets));
  864. snd_soc_dapm_add_routes(dapm, intercon_extra,
  865. ARRAY_SIZE(intercon_extra));
  866. snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
  867. ARRAY_SIZE(aic3x_dapm_mono_widgets));
  868. snd_soc_dapm_add_routes(dapm, intercon_mono,
  869. ARRAY_SIZE(intercon_mono));
  870. break;
  871. case AIC3X_MODEL_3007:
  872. snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
  873. ARRAY_SIZE(aic3x_extra_dapm_widgets));
  874. snd_soc_dapm_add_routes(dapm, intercon_extra,
  875. ARRAY_SIZE(intercon_extra));
  876. snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
  877. ARRAY_SIZE(aic3007_dapm_widgets));
  878. snd_soc_dapm_add_routes(dapm, intercon_3007,
  879. ARRAY_SIZE(intercon_3007));
  880. break;
  881. case AIC3X_MODEL_3104:
  882. snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
  883. ARRAY_SIZE(aic3104_extra_dapm_widgets));
  884. snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
  885. ARRAY_SIZE(intercon_extra_3104));
  886. break;
  887. }
  888. return 0;
  889. }
  890. static int aic3x_hw_params(struct snd_pcm_substream *substream,
  891. struct snd_pcm_hw_params *params,
  892. struct snd_soc_dai *dai)
  893. {
  894. struct snd_soc_component *component = dai->component;
  895. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  896. int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
  897. u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
  898. u16 d, pll_d = 1;
  899. int clk;
  900. int width = aic3x->slot_width;
  901. if (!width)
  902. width = params_width(params);
  903. /* select data word length */
  904. data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
  905. switch (width) {
  906. case 16:
  907. break;
  908. case 20:
  909. data |= (0x01 << 4);
  910. break;
  911. case 24:
  912. data |= (0x02 << 4);
  913. break;
  914. case 32:
  915. data |= (0x03 << 4);
  916. break;
  917. }
  918. snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
  919. /* Fsref can be 44100 or 48000 */
  920. fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
  921. /* Try to find a value for Q which allows us to bypass the PLL and
  922. * generate CODEC_CLK directly. */
  923. for (pll_q = 2; pll_q < 18; pll_q++)
  924. if (aic3x->sysclk / (128 * pll_q) == fsref) {
  925. bypass_pll = 1;
  926. break;
  927. }
  928. if (bypass_pll) {
  929. pll_q &= 0xf;
  930. snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
  931. snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
  932. /* disable PLL if it is bypassed */
  933. snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
  934. } else {
  935. snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
  936. /* enable PLL when it is used */
  937. snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
  938. PLL_ENABLE, PLL_ENABLE);
  939. }
  940. /* Route Left DAC to left channel input and
  941. * right DAC to right channel input */
  942. data = (LDAC2LCH | RDAC2RCH);
  943. data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
  944. if (params_rate(params) >= 64000)
  945. data |= DUAL_RATE_MODE;
  946. snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
  947. /* codec sample rate select */
  948. data = (fsref * 20) / params_rate(params);
  949. if (params_rate(params) < 64000)
  950. data /= 2;
  951. data /= 5;
  952. data -= 2;
  953. data |= (data << 4);
  954. snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
  955. if (bypass_pll)
  956. return 0;
  957. /* Use PLL, compute appropriate setup for j, d, r and p, the closest
  958. * one wins the game. Try with d==0 first, next with d!=0.
  959. * Constraints for j are according to the datasheet.
  960. * The sysclk is divided by 1000 to prevent integer overflows.
  961. */
  962. codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
  963. for (r = 1; r <= 16; r++)
  964. for (p = 1; p <= 8; p++) {
  965. for (j = 4; j <= 55; j++) {
  966. /* This is actually 1000*((j+(d/10000))*r)/p
  967. * The term had to be converted to get
  968. * rid of the division by 10000; d = 0 here
  969. */
  970. int tmp_clk = (1000 * j * r) / p;
  971. /* Check whether this values get closer than
  972. * the best ones we had before
  973. */
  974. if (abs(codec_clk - tmp_clk) <
  975. abs(codec_clk - last_clk)) {
  976. pll_j = j; pll_d = 0;
  977. pll_r = r; pll_p = p;
  978. last_clk = tmp_clk;
  979. }
  980. /* Early exit for exact matches */
  981. if (tmp_clk == codec_clk)
  982. goto found;
  983. }
  984. }
  985. /* try with d != 0 */
  986. for (p = 1; p <= 8; p++) {
  987. j = codec_clk * p / 1000;
  988. if (j < 4 || j > 11)
  989. continue;
  990. /* do not use codec_clk here since we'd loose precision */
  991. d = ((2048 * p * fsref) - j * aic3x->sysclk)
  992. * 100 / (aic3x->sysclk/100);
  993. clk = (10000 * j + d) / (10 * p);
  994. /* check whether this values get closer than the best
  995. * ones we had before */
  996. if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
  997. pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
  998. last_clk = clk;
  999. }
  1000. /* Early exit for exact matches */
  1001. if (clk == codec_clk)
  1002. goto found;
  1003. }
  1004. if (last_clk == 0) {
  1005. printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
  1006. return -EINVAL;
  1007. }
  1008. found:
  1009. snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
  1010. snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
  1011. pll_r << PLLR_SHIFT);
  1012. snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
  1013. snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
  1014. (pll_d >> 6) << PLLD_MSB_SHIFT);
  1015. snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
  1016. (pll_d & 0x3F) << PLLD_LSB_SHIFT);
  1017. return 0;
  1018. }
  1019. static int aic3x_prepare(struct snd_pcm_substream *substream,
  1020. struct snd_soc_dai *dai)
  1021. {
  1022. struct snd_soc_component *component = dai->component;
  1023. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1024. int delay = 0;
  1025. int width = aic3x->slot_width;
  1026. if (!width)
  1027. width = substream->runtime->sample_bits;
  1028. /* TDM slot selection only valid in DSP_A/_B mode */
  1029. if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
  1030. delay += (aic3x->tdm_delay*width + 1);
  1031. else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
  1032. delay += aic3x->tdm_delay*width;
  1033. /* Configure data delay */
  1034. snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
  1035. return 0;
  1036. }
  1037. static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction)
  1038. {
  1039. struct snd_soc_component *component = dai->component;
  1040. u8 ldac_reg = snd_soc_component_read(component, LDAC_VOL) & ~MUTE_ON;
  1041. u8 rdac_reg = snd_soc_component_read(component, RDAC_VOL) & ~MUTE_ON;
  1042. if (mute) {
  1043. snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
  1044. snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
  1045. } else {
  1046. snd_soc_component_write(component, LDAC_VOL, ldac_reg);
  1047. snd_soc_component_write(component, RDAC_VOL, rdac_reg);
  1048. }
  1049. return 0;
  1050. }
  1051. static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1052. int clk_id, unsigned int freq, int dir)
  1053. {
  1054. struct snd_soc_component *component = codec_dai->component;
  1055. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1056. /* set clock on MCLK or GPIO2 or BCLK */
  1057. snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
  1058. clk_id << PLLCLK_IN_SHIFT);
  1059. snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
  1060. clk_id << CLKDIV_IN_SHIFT);
  1061. aic3x->sysclk = freq;
  1062. return 0;
  1063. }
  1064. static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1065. unsigned int fmt)
  1066. {
  1067. struct snd_soc_component *component = codec_dai->component;
  1068. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1069. u8 iface_areg, iface_breg;
  1070. iface_areg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
  1071. iface_breg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
  1072. /* set master/slave audio interface */
  1073. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1074. case SND_SOC_DAIFMT_CBM_CFM:
  1075. aic3x->master = 1;
  1076. iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
  1077. break;
  1078. case SND_SOC_DAIFMT_CBS_CFS:
  1079. aic3x->master = 0;
  1080. iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
  1081. break;
  1082. case SND_SOC_DAIFMT_CBM_CFS:
  1083. aic3x->master = 1;
  1084. iface_areg |= BIT_CLK_MASTER;
  1085. iface_areg &= ~WORD_CLK_MASTER;
  1086. break;
  1087. case SND_SOC_DAIFMT_CBS_CFM:
  1088. aic3x->master = 1;
  1089. iface_areg |= WORD_CLK_MASTER;
  1090. iface_areg &= ~BIT_CLK_MASTER;
  1091. break;
  1092. default:
  1093. return -EINVAL;
  1094. }
  1095. /*
  1096. * match both interface format and signal polarities since they
  1097. * are fixed
  1098. */
  1099. switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
  1100. SND_SOC_DAIFMT_INV_MASK)) {
  1101. case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
  1102. break;
  1103. case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
  1104. case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
  1105. iface_breg |= (0x01 << 6);
  1106. break;
  1107. case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
  1108. iface_breg |= (0x02 << 6);
  1109. break;
  1110. case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
  1111. iface_breg |= (0x03 << 6);
  1112. break;
  1113. default:
  1114. return -EINVAL;
  1115. }
  1116. aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  1117. /* set iface */
  1118. snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
  1119. snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
  1120. return 0;
  1121. }
  1122. static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
  1123. unsigned int tx_mask, unsigned int rx_mask,
  1124. int slots, int slot_width)
  1125. {
  1126. struct snd_soc_component *component = codec_dai->component;
  1127. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1128. unsigned int lsb;
  1129. if (tx_mask != rx_mask) {
  1130. dev_err(component->dev, "tx and rx masks must be symmetric\n");
  1131. return -EINVAL;
  1132. }
  1133. if (unlikely(!tx_mask)) {
  1134. dev_err(component->dev, "tx and rx masks need to be non 0\n");
  1135. return -EINVAL;
  1136. }
  1137. /* TDM based on DSP mode requires slots to be adjacent */
  1138. lsb = __ffs(tx_mask);
  1139. if ((lsb + 1) != __fls(tx_mask)) {
  1140. dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
  1141. return -EINVAL;
  1142. }
  1143. switch (slot_width) {
  1144. case 16:
  1145. case 20:
  1146. case 24:
  1147. case 32:
  1148. break;
  1149. default:
  1150. dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
  1151. return -EINVAL;
  1152. }
  1153. aic3x->tdm_delay = lsb;
  1154. aic3x->slot_width = slot_width;
  1155. /* DOUT in high-impedance on inactive bit clocks */
  1156. snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
  1157. DOUT_TRISTATE, DOUT_TRISTATE);
  1158. return 0;
  1159. }
  1160. static int aic3x_regulator_event(struct notifier_block *nb,
  1161. unsigned long event, void *data)
  1162. {
  1163. struct aic3x_disable_nb *disable_nb =
  1164. container_of(nb, struct aic3x_disable_nb, nb);
  1165. struct aic3x_priv *aic3x = disable_nb->aic3x;
  1166. if (event & REGULATOR_EVENT_DISABLE) {
  1167. /*
  1168. * Put codec to reset and require cache sync as at least one
  1169. * of the supplies was disabled
  1170. */
  1171. if (gpio_is_valid(aic3x->gpio_reset))
  1172. gpio_set_value(aic3x->gpio_reset, 0);
  1173. regcache_mark_dirty(aic3x->regmap);
  1174. }
  1175. return 0;
  1176. }
  1177. static int aic3x_set_power(struct snd_soc_component *component, int power)
  1178. {
  1179. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1180. unsigned int pll_c, pll_d;
  1181. int ret;
  1182. if (power) {
  1183. ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
  1184. aic3x->supplies);
  1185. if (ret)
  1186. goto out;
  1187. aic3x->power = 1;
  1188. if (gpio_is_valid(aic3x->gpio_reset)) {
  1189. udelay(1);
  1190. gpio_set_value(aic3x->gpio_reset, 1);
  1191. }
  1192. /* Sync reg_cache with the hardware */
  1193. regcache_cache_only(aic3x->regmap, false);
  1194. regcache_sync(aic3x->regmap);
  1195. /* Rewrite paired PLL D registers in case cached sync skipped
  1196. * writing one of them and thus caused other one also not
  1197. * being written
  1198. */
  1199. pll_c = snd_soc_component_read(component, AIC3X_PLL_PROGC_REG);
  1200. pll_d = snd_soc_component_read(component, AIC3X_PLL_PROGD_REG);
  1201. if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
  1202. pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
  1203. snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
  1204. snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
  1205. }
  1206. /*
  1207. * Delay is needed to reduce pop-noise after syncing back the
  1208. * registers
  1209. */
  1210. mdelay(50);
  1211. } else {
  1212. /*
  1213. * Do soft reset to this codec instance in order to clear
  1214. * possible VDD leakage currents in case the supply regulators
  1215. * remain on
  1216. */
  1217. snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
  1218. regcache_mark_dirty(aic3x->regmap);
  1219. aic3x->power = 0;
  1220. /* HW writes are needless when bias is off */
  1221. regcache_cache_only(aic3x->regmap, true);
  1222. ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
  1223. aic3x->supplies);
  1224. }
  1225. out:
  1226. return ret;
  1227. }
  1228. static int aic3x_set_bias_level(struct snd_soc_component *component,
  1229. enum snd_soc_bias_level level)
  1230. {
  1231. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1232. switch (level) {
  1233. case SND_SOC_BIAS_ON:
  1234. break;
  1235. case SND_SOC_BIAS_PREPARE:
  1236. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&
  1237. aic3x->master) {
  1238. /* enable pll */
  1239. snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
  1240. PLL_ENABLE, PLL_ENABLE);
  1241. }
  1242. break;
  1243. case SND_SOC_BIAS_STANDBY:
  1244. if (!aic3x->power)
  1245. aic3x_set_power(component, 1);
  1246. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&
  1247. aic3x->master) {
  1248. /* disable pll */
  1249. snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
  1250. PLL_ENABLE, 0);
  1251. }
  1252. break;
  1253. case SND_SOC_BIAS_OFF:
  1254. if (aic3x->power)
  1255. aic3x_set_power(component, 0);
  1256. break;
  1257. }
  1258. return 0;
  1259. }
  1260. #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
  1261. #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1262. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
  1263. SNDRV_PCM_FMTBIT_S32_LE)
  1264. static const struct snd_soc_dai_ops aic3x_dai_ops = {
  1265. .hw_params = aic3x_hw_params,
  1266. .prepare = aic3x_prepare,
  1267. .mute_stream = aic3x_mute,
  1268. .set_sysclk = aic3x_set_dai_sysclk,
  1269. .set_fmt = aic3x_set_dai_fmt,
  1270. .set_tdm_slot = aic3x_set_dai_tdm_slot,
  1271. .no_capture_mute = 1,
  1272. };
  1273. static struct snd_soc_dai_driver aic3x_dai = {
  1274. .name = "tlv320aic3x-hifi",
  1275. .playback = {
  1276. .stream_name = "Playback",
  1277. .channels_min = 2,
  1278. .channels_max = 2,
  1279. .rates = AIC3X_RATES,
  1280. .formats = AIC3X_FORMATS,},
  1281. .capture = {
  1282. .stream_name = "Capture",
  1283. .channels_min = 2,
  1284. .channels_max = 2,
  1285. .rates = AIC3X_RATES,
  1286. .formats = AIC3X_FORMATS,},
  1287. .ops = &aic3x_dai_ops,
  1288. .symmetric_rates = 1,
  1289. };
  1290. static void aic3x_mono_init(struct snd_soc_component *component)
  1291. {
  1292. /* DAC to Mono Line Out default volume and route to Output mixer */
  1293. snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1294. snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1295. /* unmute all outputs */
  1296. snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
  1297. /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
  1298. snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
  1299. snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
  1300. /* Line2 to Mono Out default volume, disconnect from Output Mixer */
  1301. snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
  1302. snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
  1303. }
  1304. /*
  1305. * initialise the AIC3X driver
  1306. * register the mixer and dsp interfaces with the kernel
  1307. */
  1308. static int aic3x_init(struct snd_soc_component *component)
  1309. {
  1310. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1311. snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
  1312. snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
  1313. /* DAC default volume and mute */
  1314. snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1315. snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1316. /* DAC to HP default volume and route to Output mixer */
  1317. snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1318. snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1319. snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1320. snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1321. /* DAC to Line Out default volume and route to Output mixer */
  1322. snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1323. snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1324. /* unmute all outputs */
  1325. snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
  1326. snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
  1327. snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
  1328. snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
  1329. snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
  1330. snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
  1331. /* ADC default volume and unmute */
  1332. snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
  1333. snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
  1334. /* By default route Line1 to ADC PGA mixer */
  1335. snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
  1336. snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
  1337. /* PGA to HP Bypass default volume, disconnect from Output Mixer */
  1338. snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
  1339. snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
  1340. snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
  1341. snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
  1342. /* PGA to Line Out default volume, disconnect from Output Mixer */
  1343. snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
  1344. snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
  1345. /* On tlv320aic3104, these registers are reserved and must not be written */
  1346. if (aic3x->model != AIC3X_MODEL_3104) {
  1347. /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
  1348. snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
  1349. snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
  1350. snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
  1351. snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
  1352. /* Line2 Line Out default volume, disconnect from Output Mixer */
  1353. snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
  1354. snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
  1355. }
  1356. switch (aic3x->model) {
  1357. case AIC3X_MODEL_3X:
  1358. case AIC3X_MODEL_33:
  1359. aic3x_mono_init(component);
  1360. break;
  1361. case AIC3X_MODEL_3007:
  1362. snd_soc_component_write(component, CLASSD_CTRL, 0);
  1363. break;
  1364. }
  1365. /* Output common-mode voltage = 1.5 V */
  1366. snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
  1367. aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
  1368. return 0;
  1369. }
  1370. static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
  1371. {
  1372. struct aic3x_priv *a;
  1373. list_for_each_entry(a, &reset_list, list) {
  1374. if (gpio_is_valid(aic3x->gpio_reset) &&
  1375. aic3x->gpio_reset == a->gpio_reset)
  1376. return true;
  1377. }
  1378. return false;
  1379. }
  1380. static int aic3x_probe(struct snd_soc_component *component)
  1381. {
  1382. struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
  1383. int ret, i;
  1384. aic3x->component = component;
  1385. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
  1386. aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
  1387. aic3x->disable_nb[i].aic3x = aic3x;
  1388. ret = devm_regulator_register_notifier(
  1389. aic3x->supplies[i].consumer,
  1390. &aic3x->disable_nb[i].nb);
  1391. if (ret) {
  1392. dev_err(component->dev,
  1393. "Failed to request regulator notifier: %d\n",
  1394. ret);
  1395. return ret;
  1396. }
  1397. }
  1398. regcache_mark_dirty(aic3x->regmap);
  1399. aic3x_init(component);
  1400. if (aic3x->setup) {
  1401. if (aic3x->model != AIC3X_MODEL_3104) {
  1402. /* setup GPIO functions */
  1403. snd_soc_component_write(component, AIC3X_GPIO1_REG,
  1404. (aic3x->setup->gpio_func[0] & 0xf) << 4);
  1405. snd_soc_component_write(component, AIC3X_GPIO2_REG,
  1406. (aic3x->setup->gpio_func[1] & 0xf) << 4);
  1407. } else {
  1408. dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
  1409. }
  1410. }
  1411. switch (aic3x->model) {
  1412. case AIC3X_MODEL_3X:
  1413. case AIC3X_MODEL_33:
  1414. snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
  1415. ARRAY_SIZE(aic3x_extra_snd_controls));
  1416. snd_soc_add_component_controls(component, aic3x_mono_controls,
  1417. ARRAY_SIZE(aic3x_mono_controls));
  1418. break;
  1419. case AIC3X_MODEL_3007:
  1420. snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
  1421. ARRAY_SIZE(aic3x_extra_snd_controls));
  1422. snd_soc_add_component_controls(component,
  1423. &aic3x_classd_amp_gain_ctrl, 1);
  1424. break;
  1425. case AIC3X_MODEL_3104:
  1426. break;
  1427. }
  1428. /* set mic bias voltage */
  1429. switch (aic3x->micbias_vg) {
  1430. case AIC3X_MICBIAS_2_0V:
  1431. case AIC3X_MICBIAS_2_5V:
  1432. case AIC3X_MICBIAS_AVDDV:
  1433. snd_soc_component_update_bits(component, MICBIAS_CTRL,
  1434. MICBIAS_LEVEL_MASK,
  1435. (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
  1436. break;
  1437. case AIC3X_MICBIAS_OFF:
  1438. /*
  1439. * noting to do. target won't enter here. This is just to avoid
  1440. * compile time warning "warning: enumeration value
  1441. * 'AIC3X_MICBIAS_OFF' not handled in switch"
  1442. */
  1443. break;
  1444. }
  1445. aic3x_add_widgets(component);
  1446. return 0;
  1447. }
  1448. static const struct snd_soc_component_driver soc_component_dev_aic3x = {
  1449. .set_bias_level = aic3x_set_bias_level,
  1450. .probe = aic3x_probe,
  1451. .controls = aic3x_snd_controls,
  1452. .num_controls = ARRAY_SIZE(aic3x_snd_controls),
  1453. .dapm_widgets = aic3x_dapm_widgets,
  1454. .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
  1455. .dapm_routes = intercon,
  1456. .num_dapm_routes = ARRAY_SIZE(intercon),
  1457. .use_pmdown_time = 1,
  1458. .endianness = 1,
  1459. .non_legacy_dai_naming = 1,
  1460. };
  1461. static void aic3x_configure_ocmv(struct i2c_client *client)
  1462. {
  1463. struct device_node *np = client->dev.of_node;
  1464. struct aic3x_priv *aic3x = i2c_get_clientdata(client);
  1465. u32 value;
  1466. int dvdd, avdd;
  1467. if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
  1468. /* OCMV setting is forced by DT */
  1469. if (value <= 3) {
  1470. aic3x->ocmv = value;
  1471. return;
  1472. }
  1473. }
  1474. dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
  1475. avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
  1476. if (avdd > 3600000 || dvdd > 1950000) {
  1477. dev_warn(&client->dev,
  1478. "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
  1479. avdd, dvdd);
  1480. } else if (avdd == 3600000 && dvdd == 1950000) {
  1481. aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
  1482. } else if (avdd > 3300000 && dvdd > 1800000) {
  1483. aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
  1484. } else if (avdd > 3000000 && dvdd > 1650000) {
  1485. aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
  1486. } else if (avdd >= 2700000 && dvdd >= 1525000) {
  1487. aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
  1488. } else {
  1489. dev_warn(&client->dev,
  1490. "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
  1491. avdd, dvdd);
  1492. }
  1493. }
  1494. /*
  1495. * AIC3X 2 wire address can be up to 4 devices with device addresses
  1496. * 0x18, 0x19, 0x1A, 0x1B
  1497. */
  1498. static const struct i2c_device_id aic3x_i2c_id[] = {
  1499. { "tlv320aic3x", AIC3X_MODEL_3X },
  1500. { "tlv320aic33", AIC3X_MODEL_33 },
  1501. { "tlv320aic3007", AIC3X_MODEL_3007 },
  1502. { "tlv320aic3106", AIC3X_MODEL_3X },
  1503. { "tlv320aic3104", AIC3X_MODEL_3104 },
  1504. { }
  1505. };
  1506. MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
  1507. static const struct reg_sequence aic3007_class_d[] = {
  1508. /* Class-D speaker driver init; datasheet p. 46 */
  1509. { AIC3X_PAGE_SELECT, 0x0D },
  1510. { 0xD, 0x0D },
  1511. { 0x8, 0x5C },
  1512. { 0x8, 0x5D },
  1513. { 0x8, 0x5C },
  1514. { AIC3X_PAGE_SELECT, 0x00 },
  1515. };
  1516. /*
  1517. * If the i2c layer weren't so broken, we could pass this kind of data
  1518. * around
  1519. */
  1520. static int aic3x_i2c_probe(struct i2c_client *i2c,
  1521. const struct i2c_device_id *id)
  1522. {
  1523. struct aic3x_pdata *pdata = i2c->dev.platform_data;
  1524. struct aic3x_priv *aic3x;
  1525. struct aic3x_setup_data *ai3x_setup;
  1526. struct device_node *np = i2c->dev.of_node;
  1527. int ret, i;
  1528. u32 value;
  1529. aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
  1530. if (!aic3x)
  1531. return -ENOMEM;
  1532. aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
  1533. if (IS_ERR(aic3x->regmap)) {
  1534. ret = PTR_ERR(aic3x->regmap);
  1535. return ret;
  1536. }
  1537. regcache_cache_only(aic3x->regmap, true);
  1538. i2c_set_clientdata(i2c, aic3x);
  1539. if (pdata) {
  1540. aic3x->gpio_reset = pdata->gpio_reset;
  1541. aic3x->setup = pdata->setup;
  1542. aic3x->micbias_vg = pdata->micbias_vg;
  1543. } else if (np) {
  1544. ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
  1545. GFP_KERNEL);
  1546. if (!ai3x_setup)
  1547. return -ENOMEM;
  1548. ret = of_get_named_gpio(np, "reset-gpios", 0);
  1549. if (ret >= 0) {
  1550. aic3x->gpio_reset = ret;
  1551. } else {
  1552. ret = of_get_named_gpio(np, "gpio-reset", 0);
  1553. if (ret > 0) {
  1554. dev_warn(&i2c->dev, "Using deprecated property \"gpio-reset\", please update your DT");
  1555. aic3x->gpio_reset = ret;
  1556. } else {
  1557. aic3x->gpio_reset = -1;
  1558. }
  1559. }
  1560. if (of_property_read_u32_array(np, "ai3x-gpio-func",
  1561. ai3x_setup->gpio_func, 2) >= 0) {
  1562. aic3x->setup = ai3x_setup;
  1563. }
  1564. if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
  1565. switch (value) {
  1566. case 1 :
  1567. aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
  1568. break;
  1569. case 2 :
  1570. aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
  1571. break;
  1572. case 3 :
  1573. aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
  1574. break;
  1575. default :
  1576. aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
  1577. dev_err(&i2c->dev, "Unsuitable MicBias voltage "
  1578. "found in DT\n");
  1579. }
  1580. } else {
  1581. aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
  1582. }
  1583. } else {
  1584. aic3x->gpio_reset = -1;
  1585. }
  1586. aic3x->model = id->driver_data;
  1587. if (gpio_is_valid(aic3x->gpio_reset) &&
  1588. !aic3x_is_shared_reset(aic3x)) {
  1589. ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
  1590. if (ret != 0)
  1591. goto err;
  1592. gpio_direction_output(aic3x->gpio_reset, 0);
  1593. }
  1594. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
  1595. aic3x->supplies[i].supply = aic3x_supply_names[i];
  1596. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
  1597. aic3x->supplies);
  1598. if (ret != 0) {
  1599. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  1600. goto err_gpio;
  1601. }
  1602. aic3x_configure_ocmv(i2c);
  1603. if (aic3x->model == AIC3X_MODEL_3007) {
  1604. ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
  1605. ARRAY_SIZE(aic3007_class_d));
  1606. if (ret != 0)
  1607. dev_err(&i2c->dev, "Failed to init class D: %d\n",
  1608. ret);
  1609. }
  1610. ret = devm_snd_soc_register_component(&i2c->dev,
  1611. &soc_component_dev_aic3x, &aic3x_dai, 1);
  1612. if (ret != 0)
  1613. goto err_gpio;
  1614. INIT_LIST_HEAD(&aic3x->list);
  1615. list_add(&aic3x->list, &reset_list);
  1616. return 0;
  1617. err_gpio:
  1618. if (gpio_is_valid(aic3x->gpio_reset) &&
  1619. !aic3x_is_shared_reset(aic3x))
  1620. gpio_free(aic3x->gpio_reset);
  1621. err:
  1622. return ret;
  1623. }
  1624. static int aic3x_i2c_remove(struct i2c_client *client)
  1625. {
  1626. struct aic3x_priv *aic3x = i2c_get_clientdata(client);
  1627. list_del(&aic3x->list);
  1628. if (gpio_is_valid(aic3x->gpio_reset) &&
  1629. !aic3x_is_shared_reset(aic3x)) {
  1630. gpio_set_value(aic3x->gpio_reset, 0);
  1631. gpio_free(aic3x->gpio_reset);
  1632. }
  1633. return 0;
  1634. }
  1635. #if defined(CONFIG_OF)
  1636. static const struct of_device_id tlv320aic3x_of_match[] = {
  1637. { .compatible = "ti,tlv320aic3x", },
  1638. { .compatible = "ti,tlv320aic33" },
  1639. { .compatible = "ti,tlv320aic3007" },
  1640. { .compatible = "ti,tlv320aic3106" },
  1641. { .compatible = "ti,tlv320aic3104" },
  1642. {},
  1643. };
  1644. MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
  1645. #endif
  1646. /* machine i2c codec control layer */
  1647. static struct i2c_driver aic3x_i2c_driver = {
  1648. .driver = {
  1649. .name = "tlv320aic3x-codec",
  1650. .of_match_table = of_match_ptr(tlv320aic3x_of_match),
  1651. },
  1652. .probe = aic3x_i2c_probe,
  1653. .remove = aic3x_i2c_remove,
  1654. .id_table = aic3x_i2c_id,
  1655. };
  1656. module_i2c_driver(aic3x_i2c_driver);
  1657. MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
  1658. MODULE_AUTHOR("Vladimir Barinov");
  1659. MODULE_LICENSE("GPL");