tlv320aic32x4.h 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * tlv320aic32x4.h
  4. */
  5. #ifndef _TLV320AIC32X4_H
  6. #define _TLV320AIC32X4_H
  7. struct device;
  8. struct regmap_config;
  9. extern const struct regmap_config aic32x4_regmap_config;
  10. int aic32x4_probe(struct device *dev, struct regmap *regmap);
  11. int aic32x4_remove(struct device *dev);
  12. int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
  13. /* tlv320aic32x4 register space (in decimal to match datasheet) */
  14. #define AIC32X4_REG(page, reg) ((page * 128) + reg)
  15. #define AIC32X4_PSEL AIC32X4_REG(0, 0)
  16. #define AIC32X4_RESET AIC32X4_REG(0, 1)
  17. #define AIC32X4_CLKMUX AIC32X4_REG(0, 4)
  18. #define AIC32X4_PLLPR AIC32X4_REG(0, 5)
  19. #define AIC32X4_PLLJ AIC32X4_REG(0, 6)
  20. #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7)
  21. #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8)
  22. #define AIC32X4_NDAC AIC32X4_REG(0, 11)
  23. #define AIC32X4_MDAC AIC32X4_REG(0, 12)
  24. #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13)
  25. #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14)
  26. #define AIC32X4_NADC AIC32X4_REG(0, 18)
  27. #define AIC32X4_MADC AIC32X4_REG(0, 19)
  28. #define AIC32X4_AOSR AIC32X4_REG(0, 20)
  29. #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25)
  30. #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26)
  31. #define AIC32X4_IFACE1 AIC32X4_REG(0, 27)
  32. #define AIC32X4_IFACE2 AIC32X4_REG(0, 28)
  33. #define AIC32X4_IFACE3 AIC32X4_REG(0, 29)
  34. #define AIC32X4_BCLKN AIC32X4_REG(0, 30)
  35. #define AIC32X4_IFACE4 AIC32X4_REG(0, 31)
  36. #define AIC32X4_IFACE5 AIC32X4_REG(0, 32)
  37. #define AIC32X4_IFACE6 AIC32X4_REG(0, 33)
  38. #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52)
  39. #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53)
  40. #define AIC32X4_DINCTL AIC32X4_REG(0, 54)
  41. #define AIC32X4_MISOCTL AIC32X4_REG(0, 55)
  42. #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56)
  43. #define AIC32X4_DACSPB AIC32X4_REG(0, 60)
  44. #define AIC32X4_ADCSPB AIC32X4_REG(0, 61)
  45. #define AIC32X4_DACSETUP AIC32X4_REG(0, 63)
  46. #define AIC32X4_DACMUTE AIC32X4_REG(0, 64)
  47. #define AIC32X4_LDACVOL AIC32X4_REG(0, 65)
  48. #define AIC32X4_RDACVOL AIC32X4_REG(0, 66)
  49. #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81)
  50. #define AIC32X4_ADCFGA AIC32X4_REG(0, 82)
  51. #define AIC32X4_LADCVOL AIC32X4_REG(0, 83)
  52. #define AIC32X4_RADCVOL AIC32X4_REG(0, 84)
  53. #define AIC32X4_LAGC1 AIC32X4_REG(0, 86)
  54. #define AIC32X4_LAGC2 AIC32X4_REG(0, 87)
  55. #define AIC32X4_LAGC3 AIC32X4_REG(0, 88)
  56. #define AIC32X4_LAGC4 AIC32X4_REG(0, 89)
  57. #define AIC32X4_LAGC5 AIC32X4_REG(0, 90)
  58. #define AIC32X4_LAGC6 AIC32X4_REG(0, 91)
  59. #define AIC32X4_LAGC7 AIC32X4_REG(0, 92)
  60. #define AIC32X4_RAGC1 AIC32X4_REG(0, 94)
  61. #define AIC32X4_RAGC2 AIC32X4_REG(0, 95)
  62. #define AIC32X4_RAGC3 AIC32X4_REG(0, 96)
  63. #define AIC32X4_RAGC4 AIC32X4_REG(0, 97)
  64. #define AIC32X4_RAGC5 AIC32X4_REG(0, 98)
  65. #define AIC32X4_RAGC6 AIC32X4_REG(0, 99)
  66. #define AIC32X4_RAGC7 AIC32X4_REG(0, 100)
  67. #define AIC32X4_PWRCFG AIC32X4_REG(1, 1)
  68. #define AIC32X4_LDOCTL AIC32X4_REG(1, 2)
  69. #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3)
  70. #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4)
  71. #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9)
  72. #define AIC32X4_CMMODE AIC32X4_REG(1, 10)
  73. #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12)
  74. #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13)
  75. #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14)
  76. #define AIC32X4_LORROUTE AIC32X4_REG(1, 15)
  77. #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16)
  78. #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17)
  79. #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18)
  80. #define AIC32X4_LORGAIN AIC32X4_REG(1, 19)
  81. #define AIC32X4_HEADSTART AIC32X4_REG(1, 20)
  82. #define AIC32X4_MICBIAS AIC32X4_REG(1, 51)
  83. #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52)
  84. #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54)
  85. #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55)
  86. #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57)
  87. #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58)
  88. #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59)
  89. #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60)
  90. #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123)
  91. /* Bits, masks, and shifts */
  92. /* AIC32X4_CLKMUX */
  93. #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2)
  94. #define AIC32X4_PLL_CLKIN_SHIFT (2)
  95. #define AIC32X4_PLL_CLKIN_MCLK (0x00)
  96. #define AIC32X4_PLL_CLKIN_BCKL (0x01)
  97. #define AIC32X4_PLL_CLKIN_GPIO1 (0x02)
  98. #define AIC32X4_PLL_CLKIN_DIN (0x03)
  99. #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0)
  100. #define AIC32X4_CODEC_CLKIN_SHIFT (0)
  101. #define AIC32X4_CODEC_CLKIN_MCLK (0x00)
  102. #define AIC32X4_CODEC_CLKIN_BCLK (0x01)
  103. #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02)
  104. #define AIC32X4_CODEC_CLKIN_PLL (0x03)
  105. /* AIC32X4_PLLPR */
  106. #define AIC32X4_PLLEN BIT(7)
  107. #define AIC32X4_PLL_P_MASK GENMASK(6, 4)
  108. #define AIC32X4_PLL_P_SHIFT (4)
  109. #define AIC32X4_PLL_R_MASK GENMASK(3, 0)
  110. /* AIC32X4_NDAC */
  111. #define AIC32X4_NDACEN BIT(7)
  112. #define AIC32X4_NDAC_MASK GENMASK(6, 0)
  113. /* AIC32X4_MDAC */
  114. #define AIC32X4_MDACEN BIT(7)
  115. #define AIC32X4_MDAC_MASK GENMASK(6, 0)
  116. /* AIC32X4_NADC */
  117. #define AIC32X4_NADCEN BIT(7)
  118. #define AIC32X4_NADC_MASK GENMASK(6, 0)
  119. /* AIC32X4_MADC */
  120. #define AIC32X4_MADCEN BIT(7)
  121. #define AIC32X4_MADC_MASK GENMASK(6, 0)
  122. /* AIC32X4_BCLKN */
  123. #define AIC32X4_BCLKEN BIT(7)
  124. #define AIC32X4_BCLK_MASK GENMASK(6, 0)
  125. /* AIC32X4_IFACE1 */
  126. #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6)
  127. #define AIC32X4_IFACE1_DATATYPE_SHIFT (6)
  128. #define AIC32X4_I2S_MODE (0x00)
  129. #define AIC32X4_DSP_MODE (0x01)
  130. #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02)
  131. #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03)
  132. #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4)
  133. #define AIC32X4_IFACE1_DATALEN_SHIFT (4)
  134. #define AIC32X4_WORD_LEN_16BITS (0x00)
  135. #define AIC32X4_WORD_LEN_20BITS (0x01)
  136. #define AIC32X4_WORD_LEN_24BITS (0x02)
  137. #define AIC32X4_WORD_LEN_32BITS (0x03)
  138. #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2)
  139. #define AIC32X4_BCLKMASTER BIT(2)
  140. #define AIC32X4_WCLKMASTER BIT(3)
  141. /* AIC32X4_IFACE2 */
  142. #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0)
  143. /* AIC32X4_IFACE3 */
  144. #define AIC32X4_BCLKINV_MASK BIT(3)
  145. #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0)
  146. #define AIC32X4_BDIVCLK_SHIFT (0)
  147. #define AIC32X4_DAC2BCLK (0x00)
  148. #define AIC32X4_DACMOD2BCLK (0x01)
  149. #define AIC32X4_ADC2BCLK (0x02)
  150. #define AIC32X4_ADCMOD2BCLK (0x03)
  151. /* AIC32X4_DACSETUP */
  152. #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2)
  153. #define AIC32X4_LDAC2RCHN BIT(5)
  154. #define AIC32X4_LDAC2LCHN BIT(4)
  155. #define AIC32X4_RDAC2LCHN BIT(3)
  156. #define AIC32X4_RDAC2RCHN BIT(2)
  157. /* AIC32X4_DACMUTE */
  158. #define AIC32X4_MUTEON 0x0C
  159. /* AIC32X4_ADCSETUP */
  160. #define AIC32X4_LADC_EN BIT(7)
  161. #define AIC32X4_RADC_EN BIT(6)
  162. /* AIC32X4_PWRCFG */
  163. #define AIC32X4_AVDDWEAKDISABLE BIT(3)
  164. /* AIC32X4_LDOCTL */
  165. #define AIC32X4_LDOCTLEN BIT(0)
  166. /* AIC32X4_CMMODE */
  167. #define AIC32X4_LDOIN_18_36 BIT(0)
  168. #define AIC32X4_LDOIN2HP BIT(1)
  169. /* AIC32X4_MICBIAS */
  170. #define AIC32X4_MICBIAS_LDOIN BIT(3)
  171. #define AIC32X4_MICBIAS_2075V 0x60
  172. #define AIC32x4_MICBIAS_MASK GENMASK(6, 3)
  173. /* AIC32X4_LMICPGANIN */
  174. #define AIC32X4_LMICPGANIN_IN2R_10K 0x10
  175. #define AIC32X4_LMICPGANIN_CM1L_10K 0x40
  176. /* AIC32X4_RMICPGANIN */
  177. #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
  178. #define AIC32X4_RMICPGANIN_CM1R_10K 0x40
  179. /* AIC32X4_REFPOWERUP */
  180. #define AIC32X4_REFPOWERUP_SLOW 0x04
  181. #define AIC32X4_REFPOWERUP_40MS 0x05
  182. #define AIC32X4_REFPOWERUP_80MS 0x06
  183. #define AIC32X4_REFPOWERUP_120MS 0x07
  184. /* Common mask and enable for all of the dividers */
  185. #define AIC32X4_DIVEN BIT(7)
  186. #define AIC32X4_DIV_MASK GENMASK(6, 0)
  187. /* Clock Limits */
  188. #define AIC32X4_MAX_DOSR_FREQ 6200000
  189. #define AIC32X4_MIN_DOSR_FREQ 2800000
  190. #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000
  191. #define AIC32X4_MAX_PLL_CLKIN 20000000
  192. #endif /* _TLV320AIC32X4_H */