tlv320aic32x4-clk.c 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Clock Tree for the Texas Instruments TLV320AIC32x4
  4. *
  5. * Copyright 2019 Annaliese McDermond
  6. *
  7. * Author: Annaliese McDermond <nh6z@nh6z.net>
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/regmap.h>
  12. #include <linux/device.h>
  13. #include "tlv320aic32x4.h"
  14. #define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
  15. struct clk_aic32x4 {
  16. struct clk_hw hw;
  17. struct device *dev;
  18. struct regmap *regmap;
  19. unsigned int reg;
  20. };
  21. /*
  22. * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
  23. * @p: Divider
  24. * @r: first multiplier
  25. * @j: integer part of second multiplier
  26. * @d: decimal part of second multiplier
  27. */
  28. struct clk_aic32x4_pll_muldiv {
  29. u8 p;
  30. u16 r;
  31. u8 j;
  32. u16 d;
  33. };
  34. struct aic32x4_clkdesc {
  35. const char *name;
  36. const char * const *parent_names;
  37. unsigned int num_parents;
  38. const struct clk_ops *ops;
  39. unsigned int reg;
  40. };
  41. static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
  42. {
  43. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  44. return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
  45. AIC32X4_PLLEN, AIC32X4_PLLEN);
  46. }
  47. static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
  48. {
  49. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  50. regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
  51. AIC32X4_PLLEN, 0);
  52. }
  53. static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
  54. {
  55. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  56. unsigned int val;
  57. int ret;
  58. ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
  59. if (ret < 0)
  60. return ret;
  61. return !!(val & AIC32X4_PLLEN);
  62. }
  63. static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
  64. struct clk_aic32x4_pll_muldiv *settings)
  65. {
  66. /* Change to use regmap_bulk_read? */
  67. unsigned int val;
  68. int ret;
  69. ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
  70. if (ret < 0)
  71. return ret;
  72. settings->r = val & AIC32X4_PLL_R_MASK;
  73. settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
  74. ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
  75. if (ret < 0)
  76. return ret;
  77. settings->j = val;
  78. ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
  79. if (ret < 0)
  80. return ret;
  81. settings->d = val << 8;
  82. ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
  83. if (ret < 0)
  84. return ret;
  85. settings->d |= val;
  86. return 0;
  87. }
  88. static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
  89. struct clk_aic32x4_pll_muldiv *settings)
  90. {
  91. int ret;
  92. /* Change to use regmap_bulk_write for some if not all? */
  93. ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
  94. AIC32X4_PLL_R_MASK, settings->r);
  95. if (ret < 0)
  96. return ret;
  97. ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
  98. AIC32X4_PLL_P_MASK,
  99. settings->p << AIC32X4_PLL_P_SHIFT);
  100. if (ret < 0)
  101. return ret;
  102. ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
  103. if (ret < 0)
  104. return ret;
  105. ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
  106. if (ret < 0)
  107. return ret;
  108. ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
  109. if (ret < 0)
  110. return ret;
  111. return 0;
  112. }
  113. static unsigned long clk_aic32x4_pll_calc_rate(
  114. struct clk_aic32x4_pll_muldiv *settings,
  115. unsigned long parent_rate)
  116. {
  117. u64 rate;
  118. /*
  119. * We scale j by 10000 to account for the decimal part of P and divide
  120. * it back out later.
  121. */
  122. rate = (u64) parent_rate * settings->r *
  123. ((settings->j * 10000) + settings->d);
  124. return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
  125. }
  126. static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
  127. unsigned long rate, unsigned long parent_rate)
  128. {
  129. u64 multiplier;
  130. settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
  131. if (settings->p > 8)
  132. return -1;
  133. /*
  134. * We scale this figure by 10000 so that we can get the decimal part
  135. * of the multiplier. This is because we can't do floating point
  136. * math in the kernel.
  137. */
  138. multiplier = (u64) rate * settings->p * 10000;
  139. do_div(multiplier, parent_rate);
  140. /*
  141. * J can't be over 64, so R can scale this.
  142. * R can't be greater than 4.
  143. */
  144. settings->r = ((u32) multiplier / 640000) + 1;
  145. if (settings->r > 4)
  146. return -1;
  147. do_div(multiplier, settings->r);
  148. /*
  149. * J can't be < 1.
  150. */
  151. if (multiplier < 10000)
  152. return -1;
  153. /* Figure out the integer part, J, and the fractional part, D. */
  154. settings->j = (u32) multiplier / 10000;
  155. settings->d = (u32) multiplier % 10000;
  156. return 0;
  157. }
  158. static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
  159. unsigned long parent_rate)
  160. {
  161. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  162. struct clk_aic32x4_pll_muldiv settings;
  163. int ret;
  164. ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
  165. if (ret < 0)
  166. return 0;
  167. return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
  168. }
  169. static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
  170. unsigned long rate,
  171. unsigned long *parent_rate)
  172. {
  173. struct clk_aic32x4_pll_muldiv settings;
  174. int ret;
  175. ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
  176. if (ret < 0)
  177. return 0;
  178. return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
  179. }
  180. static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
  181. unsigned long rate,
  182. unsigned long parent_rate)
  183. {
  184. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  185. struct clk_aic32x4_pll_muldiv settings;
  186. int ret;
  187. ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
  188. if (ret < 0)
  189. return -EINVAL;
  190. ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
  191. if (ret)
  192. return ret;
  193. /* 10ms is the delay to wait before the clocks are stable */
  194. msleep(10);
  195. return 0;
  196. }
  197. static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
  198. {
  199. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  200. return regmap_update_bits(pll->regmap,
  201. AIC32X4_CLKMUX,
  202. AIC32X4_PLL_CLKIN_MASK,
  203. index << AIC32X4_PLL_CLKIN_SHIFT);
  204. }
  205. static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
  206. {
  207. struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  208. unsigned int val;
  209. regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
  210. return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
  211. }
  212. static const struct clk_ops aic32x4_pll_ops = {
  213. .prepare = clk_aic32x4_pll_prepare,
  214. .unprepare = clk_aic32x4_pll_unprepare,
  215. .is_prepared = clk_aic32x4_pll_is_prepared,
  216. .recalc_rate = clk_aic32x4_pll_recalc_rate,
  217. .round_rate = clk_aic32x4_pll_round_rate,
  218. .set_rate = clk_aic32x4_pll_set_rate,
  219. .set_parent = clk_aic32x4_pll_set_parent,
  220. .get_parent = clk_aic32x4_pll_get_parent,
  221. };
  222. static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
  223. {
  224. struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  225. return regmap_update_bits(mux->regmap,
  226. AIC32X4_CLKMUX,
  227. AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
  228. }
  229. static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
  230. {
  231. struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  232. unsigned int val;
  233. regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
  234. return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
  235. }
  236. static const struct clk_ops aic32x4_codec_clkin_ops = {
  237. .set_parent = clk_aic32x4_codec_clkin_set_parent,
  238. .get_parent = clk_aic32x4_codec_clkin_get_parent,
  239. };
  240. static int clk_aic32x4_div_prepare(struct clk_hw *hw)
  241. {
  242. struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  243. return regmap_update_bits(div->regmap, div->reg,
  244. AIC32X4_DIVEN, AIC32X4_DIVEN);
  245. }
  246. static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
  247. {
  248. struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  249. regmap_update_bits(div->regmap, div->reg,
  250. AIC32X4_DIVEN, 0);
  251. }
  252. static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
  253. unsigned long parent_rate)
  254. {
  255. struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  256. u8 divisor;
  257. divisor = DIV_ROUND_UP(parent_rate, rate);
  258. if (divisor > 128)
  259. return -EINVAL;
  260. return regmap_update_bits(div->regmap, div->reg,
  261. AIC32X4_DIV_MASK, divisor);
  262. }
  263. static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate,
  264. unsigned long *parent_rate)
  265. {
  266. unsigned long divisor;
  267. divisor = DIV_ROUND_UP(*parent_rate, rate);
  268. if (divisor > 128)
  269. return -EINVAL;
  270. return DIV_ROUND_UP(*parent_rate, divisor);
  271. }
  272. static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
  273. unsigned long parent_rate)
  274. {
  275. struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  276. unsigned int val;
  277. regmap_read(div->regmap, div->reg, &val);
  278. return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
  279. }
  280. static const struct clk_ops aic32x4_div_ops = {
  281. .prepare = clk_aic32x4_div_prepare,
  282. .unprepare = clk_aic32x4_div_unprepare,
  283. .set_rate = clk_aic32x4_div_set_rate,
  284. .round_rate = clk_aic32x4_div_round_rate,
  285. .recalc_rate = clk_aic32x4_div_recalc_rate,
  286. };
  287. static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
  288. {
  289. struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  290. return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
  291. AIC32X4_BDIVCLK_MASK, index);
  292. }
  293. static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
  294. {
  295. struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  296. unsigned int val;
  297. regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
  298. return val & AIC32X4_BDIVCLK_MASK;
  299. }
  300. static const struct clk_ops aic32x4_bdiv_ops = {
  301. .prepare = clk_aic32x4_div_prepare,
  302. .unprepare = clk_aic32x4_div_unprepare,
  303. .set_parent = clk_aic32x4_bdiv_set_parent,
  304. .get_parent = clk_aic32x4_bdiv_get_parent,
  305. .set_rate = clk_aic32x4_div_set_rate,
  306. .round_rate = clk_aic32x4_div_round_rate,
  307. .recalc_rate = clk_aic32x4_div_recalc_rate,
  308. };
  309. static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
  310. {
  311. .name = "pll",
  312. .parent_names =
  313. (const char* []) { "mclk", "bclk", "gpio", "din" },
  314. .num_parents = 4,
  315. .ops = &aic32x4_pll_ops,
  316. .reg = 0,
  317. },
  318. {
  319. .name = "codec_clkin",
  320. .parent_names =
  321. (const char *[]) { "mclk", "bclk", "gpio", "pll" },
  322. .num_parents = 4,
  323. .ops = &aic32x4_codec_clkin_ops,
  324. .reg = 0,
  325. },
  326. {
  327. .name = "ndac",
  328. .parent_names = (const char * []) { "codec_clkin" },
  329. .num_parents = 1,
  330. .ops = &aic32x4_div_ops,
  331. .reg = AIC32X4_NDAC,
  332. },
  333. {
  334. .name = "mdac",
  335. .parent_names = (const char * []) { "ndac" },
  336. .num_parents = 1,
  337. .ops = &aic32x4_div_ops,
  338. .reg = AIC32X4_MDAC,
  339. },
  340. {
  341. .name = "nadc",
  342. .parent_names = (const char * []) { "codec_clkin" },
  343. .num_parents = 1,
  344. .ops = &aic32x4_div_ops,
  345. .reg = AIC32X4_NADC,
  346. },
  347. {
  348. .name = "madc",
  349. .parent_names = (const char * []) { "nadc" },
  350. .num_parents = 1,
  351. .ops = &aic32x4_div_ops,
  352. .reg = AIC32X4_MADC,
  353. },
  354. {
  355. .name = "bdiv",
  356. .parent_names =
  357. (const char *[]) { "ndac", "mdac", "nadc", "madc" },
  358. .num_parents = 4,
  359. .ops = &aic32x4_bdiv_ops,
  360. .reg = AIC32X4_BCLKN,
  361. },
  362. };
  363. static struct clk *aic32x4_register_clk(struct device *dev,
  364. struct aic32x4_clkdesc *desc)
  365. {
  366. struct clk_init_data init;
  367. struct clk_aic32x4 *priv;
  368. const char *devname = dev_name(dev);
  369. init.ops = desc->ops;
  370. init.name = desc->name;
  371. init.parent_names = desc->parent_names;
  372. init.num_parents = desc->num_parents;
  373. init.flags = 0;
  374. priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
  375. if (priv == NULL)
  376. return (struct clk *) -ENOMEM;
  377. priv->dev = dev;
  378. priv->hw.init = &init;
  379. priv->regmap = dev_get_regmap(dev, NULL);
  380. priv->reg = desc->reg;
  381. clk_hw_register_clkdev(&priv->hw, desc->name, devname);
  382. return devm_clk_register(dev, &priv->hw);
  383. }
  384. int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
  385. {
  386. int i;
  387. /*
  388. * These lines are here to preserve the current functionality of
  389. * the driver with regard to the DT. These should eventually be set
  390. * by DT nodes so that the connections can be set up in configuration
  391. * rather than code.
  392. */
  393. aic32x4_clkdesc_array[0].parent_names =
  394. (const char* []) { mclk_name, "bclk", "gpio", "din" };
  395. aic32x4_clkdesc_array[1].parent_names =
  396. (const char *[]) { mclk_name, "bclk", "gpio", "pll" };
  397. for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
  398. aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
  399. return 0;
  400. }
  401. EXPORT_SYMBOL_GPL(aic32x4_register_clocks);