tlv320aic31xx.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ALSA SoC TLV320AIC31xx CODEC Driver
  4. *
  5. * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
  6. * Jyri Sarha <jsarha@ti.com>
  7. *
  8. * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
  9. *
  10. * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
  11. * high performance codecs which provides a stereo DAC, a mono ADC,
  12. * and mono/stereo Class-D speaker driver.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/pm.h>
  19. #include <linux/i2c.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/acpi.h>
  23. #include <linux/of.h>
  24. #include <linux/of_gpio.h>
  25. #include <linux/slab.h>
  26. #include <sound/core.h>
  27. #include <sound/jack.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/soc.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
  34. #include "tlv320aic31xx.h"
  35. static int aic31xx_set_jack(struct snd_soc_component *component,
  36. struct snd_soc_jack *jack, void *data);
  37. static const struct reg_default aic31xx_reg_defaults[] = {
  38. { AIC31XX_CLKMUX, 0x00 },
  39. { AIC31XX_PLLPR, 0x11 },
  40. { AIC31XX_PLLJ, 0x04 },
  41. { AIC31XX_PLLDMSB, 0x00 },
  42. { AIC31XX_PLLDLSB, 0x00 },
  43. { AIC31XX_NDAC, 0x01 },
  44. { AIC31XX_MDAC, 0x01 },
  45. { AIC31XX_DOSRMSB, 0x00 },
  46. { AIC31XX_DOSRLSB, 0x80 },
  47. { AIC31XX_NADC, 0x01 },
  48. { AIC31XX_MADC, 0x01 },
  49. { AIC31XX_AOSR, 0x80 },
  50. { AIC31XX_IFACE1, 0x00 },
  51. { AIC31XX_DATA_OFFSET, 0x00 },
  52. { AIC31XX_IFACE2, 0x00 },
  53. { AIC31XX_BCLKN, 0x01 },
  54. { AIC31XX_DACSETUP, 0x14 },
  55. { AIC31XX_DACMUTE, 0x0c },
  56. { AIC31XX_LDACVOL, 0x00 },
  57. { AIC31XX_RDACVOL, 0x00 },
  58. { AIC31XX_ADCSETUP, 0x00 },
  59. { AIC31XX_ADCFGA, 0x80 },
  60. { AIC31XX_ADCVOL, 0x00 },
  61. { AIC31XX_HPDRIVER, 0x04 },
  62. { AIC31XX_SPKAMP, 0x06 },
  63. { AIC31XX_DACMIXERROUTE, 0x00 },
  64. { AIC31XX_LANALOGHPL, 0x7f },
  65. { AIC31XX_RANALOGHPR, 0x7f },
  66. { AIC31XX_LANALOGSPL, 0x7f },
  67. { AIC31XX_RANALOGSPR, 0x7f },
  68. { AIC31XX_HPLGAIN, 0x02 },
  69. { AIC31XX_HPRGAIN, 0x02 },
  70. { AIC31XX_SPLGAIN, 0x00 },
  71. { AIC31XX_SPRGAIN, 0x00 },
  72. { AIC31XX_MICBIAS, 0x00 },
  73. { AIC31XX_MICPGA, 0x80 },
  74. { AIC31XX_MICPGAPI, 0x00 },
  75. { AIC31XX_MICPGAMI, 0x00 },
  76. };
  77. static bool aic31xx_volatile(struct device *dev, unsigned int reg)
  78. {
  79. switch (reg) {
  80. case AIC31XX_PAGECTL: /* regmap implementation requires this */
  81. case AIC31XX_RESET: /* always clears after write */
  82. case AIC31XX_OT_FLAG:
  83. case AIC31XX_ADCFLAG:
  84. case AIC31XX_DACFLAG1:
  85. case AIC31XX_DACFLAG2:
  86. case AIC31XX_OFFLAG: /* Sticky interrupt flags */
  87. case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
  88. case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
  89. case AIC31XX_INTRDACFLAG2:
  90. case AIC31XX_INTRADCFLAG2:
  91. case AIC31XX_HSDETECT:
  92. return true;
  93. }
  94. return false;
  95. }
  96. static bool aic31xx_writeable(struct device *dev, unsigned int reg)
  97. {
  98. switch (reg) {
  99. case AIC31XX_OT_FLAG:
  100. case AIC31XX_ADCFLAG:
  101. case AIC31XX_DACFLAG1:
  102. case AIC31XX_DACFLAG2:
  103. case AIC31XX_OFFLAG: /* Sticky interrupt flags */
  104. case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
  105. case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
  106. case AIC31XX_INTRDACFLAG2:
  107. case AIC31XX_INTRADCFLAG2:
  108. return false;
  109. }
  110. return true;
  111. }
  112. static const struct regmap_range_cfg aic31xx_ranges[] = {
  113. {
  114. .range_min = 0,
  115. .range_max = 12 * 128,
  116. .selector_reg = AIC31XX_PAGECTL,
  117. .selector_mask = 0xff,
  118. .selector_shift = 0,
  119. .window_start = 0,
  120. .window_len = 128,
  121. },
  122. };
  123. static const struct regmap_config aic31xx_i2c_regmap = {
  124. .reg_bits = 8,
  125. .val_bits = 8,
  126. .writeable_reg = aic31xx_writeable,
  127. .volatile_reg = aic31xx_volatile,
  128. .reg_defaults = aic31xx_reg_defaults,
  129. .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
  130. .cache_type = REGCACHE_RBTREE,
  131. .ranges = aic31xx_ranges,
  132. .num_ranges = ARRAY_SIZE(aic31xx_ranges),
  133. .max_register = 12 * 128,
  134. };
  135. static const char * const aic31xx_supply_names[] = {
  136. "HPVDD",
  137. "SPRVDD",
  138. "SPLVDD",
  139. "AVDD",
  140. "IOVDD",
  141. "DVDD",
  142. };
  143. #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
  144. struct aic31xx_disable_nb {
  145. struct notifier_block nb;
  146. struct aic31xx_priv *aic31xx;
  147. };
  148. struct aic31xx_priv {
  149. struct snd_soc_component *component;
  150. u8 i2c_regs_status;
  151. struct device *dev;
  152. struct regmap *regmap;
  153. enum aic31xx_type codec_type;
  154. struct gpio_desc *gpio_reset;
  155. int micbias_vg;
  156. struct aic31xx_pdata pdata;
  157. struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
  158. struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
  159. struct snd_soc_jack *jack;
  160. unsigned int sysclk;
  161. u8 p_div;
  162. int rate_div_line;
  163. bool master_dapm_route_applied;
  164. int irq;
  165. u8 ocmv; /* output common-mode voltage */
  166. };
  167. struct aic31xx_rate_divs {
  168. u32 mclk_p;
  169. u32 rate;
  170. u8 pll_j;
  171. u16 pll_d;
  172. u16 dosr;
  173. u8 ndac;
  174. u8 mdac;
  175. u8 aosr;
  176. u8 nadc;
  177. u8 madc;
  178. };
  179. /* ADC dividers can be disabled by configuring them to 0 */
  180. static const struct aic31xx_rate_divs aic31xx_divs[] = {
  181. /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
  182. /* 8k rate */
  183. {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
  184. {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
  185. {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
  186. /* 11.025k rate */
  187. {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
  188. {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
  189. {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
  190. /* 16k rate */
  191. {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
  192. {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
  193. {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
  194. /* 22.05k rate */
  195. {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
  196. {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
  197. {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
  198. /* 32k rate */
  199. {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
  200. {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
  201. {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
  202. /* 44.1k rate */
  203. {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
  204. {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
  205. {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
  206. /* 48k rate */
  207. {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
  208. {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
  209. {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
  210. /* 88.2k rate */
  211. {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
  212. {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
  213. {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
  214. /* 96k rate */
  215. {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
  216. {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
  217. {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
  218. /* 176.4k rate */
  219. {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
  220. {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
  221. {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
  222. /* 192k rate */
  223. {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
  224. {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
  225. {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
  226. };
  227. static const char * const ldac_in_text[] = {
  228. "Off", "Left Data", "Right Data", "Mono"
  229. };
  230. static const char * const rdac_in_text[] = {
  231. "Off", "Right Data", "Left Data", "Mono"
  232. };
  233. static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
  234. static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
  235. static const char * const mic_select_text[] = {
  236. "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
  237. };
  238. static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
  239. mic_select_text);
  240. static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
  241. mic_select_text);
  242. static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
  243. mic_select_text);
  244. static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
  245. mic_select_text);
  246. static const char * const hp_poweron_time_text[] = {
  247. "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
  248. "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };
  249. static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,
  250. hp_poweron_time_text);
  251. static const char * const hp_rampup_step_text[] = {
  252. "0ms", "0.98ms", "1.95ms", "3.9ms" };
  253. static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,
  254. hp_rampup_step_text);
  255. static const char * const vol_soft_step_mode_text[] = {
  256. "fast", "slow", "disabled" };
  257. static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
  258. vol_soft_step_mode_text);
  259. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
  260. static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
  261. static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
  262. static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
  263. static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
  264. static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
  265. static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
  266. static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
  267. /*
  268. * controls to be exported to the user space
  269. */
  270. static const struct snd_kcontrol_new common31xx_snd_controls[] = {
  271. SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
  272. AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
  273. SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
  274. AIC31XX_HPRGAIN, 2, 1, 0),
  275. SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
  276. AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
  277. SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
  278. AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
  279. /* HP de-pop control: apply power not immediately but via ramp
  280. * function with these psarameters. Note that power up sequence
  281. * has to wait for this to complete; this is implemented by
  282. * polling HP driver status in aic31xx_dapm_power_event()
  283. */
  284. SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
  285. SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
  286. SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),
  287. };
  288. static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
  289. SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
  290. adc_fgain_tlv),
  291. SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
  292. SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
  293. 0, -24, 40, 6, 0, adc_cgain_tlv),
  294. SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
  295. 119, 0, mic_pga_tlv),
  296. };
  297. static const struct snd_kcontrol_new aic311x_snd_controls[] = {
  298. SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
  299. AIC31XX_SPRGAIN, 2, 1, 0),
  300. SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
  301. AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
  302. SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
  303. AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
  304. };
  305. static const struct snd_kcontrol_new aic310x_snd_controls[] = {
  306. SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
  307. 2, 1, 0),
  308. SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
  309. 3, 3, 0, class_D_drv_tlv),
  310. SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
  311. 0, 0x7F, 1, sp_vol_tlv),
  312. };
  313. static const struct snd_kcontrol_new ldac_in_control =
  314. SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
  315. static const struct snd_kcontrol_new rdac_in_control =
  316. SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
  317. static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
  318. unsigned int mask, unsigned int wbits, int sleep,
  319. int count)
  320. {
  321. unsigned int bits;
  322. int counter = count;
  323. int ret = regmap_read(aic31xx->regmap, reg, &bits);
  324. while ((bits & mask) != wbits && counter && !ret) {
  325. usleep_range(sleep, sleep * 2);
  326. ret = regmap_read(aic31xx->regmap, reg, &bits);
  327. counter--;
  328. }
  329. if ((bits & mask) != wbits) {
  330. dev_err(aic31xx->dev,
  331. "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
  332. __func__, reg, bits, wbits, ret, mask,
  333. (count - counter) * sleep);
  334. ret = -1;
  335. }
  336. return ret;
  337. }
  338. #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
  339. static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
  340. struct snd_kcontrol *kcontrol, int event)
  341. {
  342. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  343. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  344. unsigned int reg = AIC31XX_DACFLAG1;
  345. unsigned int mask;
  346. unsigned int timeout = 500 * USEC_PER_MSEC;
  347. switch (WIDGET_BIT(w->reg, w->shift)) {
  348. case WIDGET_BIT(AIC31XX_DACSETUP, 7):
  349. mask = AIC31XX_LDACPWRSTATUS_MASK;
  350. break;
  351. case WIDGET_BIT(AIC31XX_DACSETUP, 6):
  352. mask = AIC31XX_RDACPWRSTATUS_MASK;
  353. break;
  354. case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
  355. mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
  356. if (event == SND_SOC_DAPM_POST_PMU)
  357. timeout = 7 * USEC_PER_SEC;
  358. break;
  359. case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
  360. mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
  361. if (event == SND_SOC_DAPM_POST_PMU)
  362. timeout = 7 * USEC_PER_SEC;
  363. break;
  364. case WIDGET_BIT(AIC31XX_SPKAMP, 7):
  365. mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
  366. break;
  367. case WIDGET_BIT(AIC31XX_SPKAMP, 6):
  368. mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
  369. break;
  370. case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
  371. mask = AIC31XX_ADCPWRSTATUS_MASK;
  372. reg = AIC31XX_ADCFLAG;
  373. break;
  374. default:
  375. dev_err(component->dev, "Unknown widget '%s' calling %s\n",
  376. w->name, __func__);
  377. return -EINVAL;
  378. }
  379. switch (event) {
  380. case SND_SOC_DAPM_POST_PMU:
  381. return aic31xx_wait_bits(aic31xx, reg, mask, mask,
  382. 5000, timeout / 5000);
  383. case SND_SOC_DAPM_POST_PMD:
  384. return aic31xx_wait_bits(aic31xx, reg, mask, 0,
  385. 5000, timeout / 5000);
  386. default:
  387. dev_dbg(component->dev,
  388. "Unhandled dapm widget event %d from %s\n",
  389. event, w->name);
  390. }
  391. return 0;
  392. }
  393. static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
  394. SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
  395. SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
  396. SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
  397. };
  398. static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
  399. SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
  400. SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
  401. };
  402. static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
  403. SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
  404. SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
  405. SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
  406. };
  407. static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
  408. SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
  409. SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
  410. };
  411. static const struct snd_kcontrol_new p_term_mic1lp =
  412. SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
  413. static const struct snd_kcontrol_new p_term_mic1rp =
  414. SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
  415. static const struct snd_kcontrol_new p_term_mic1lm =
  416. SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
  417. static const struct snd_kcontrol_new m_term_mic1lm =
  418. SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
  419. static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
  420. SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
  421. static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
  422. SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
  423. static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
  424. SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
  425. static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
  426. SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
  427. static int mic_bias_event(struct snd_soc_dapm_widget *w,
  428. struct snd_kcontrol *kcontrol, int event)
  429. {
  430. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  431. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  432. switch (event) {
  433. case SND_SOC_DAPM_POST_PMU:
  434. /* change mic bias voltage to user defined */
  435. snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
  436. AIC31XX_MICBIAS_MASK,
  437. aic31xx->micbias_vg <<
  438. AIC31XX_MICBIAS_SHIFT);
  439. dev_dbg(component->dev, "%s: turned on\n", __func__);
  440. break;
  441. case SND_SOC_DAPM_PRE_PMD:
  442. /* turn mic bias off */
  443. snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
  444. AIC31XX_MICBIAS_MASK, 0);
  445. dev_dbg(component->dev, "%s: turned off\n", __func__);
  446. break;
  447. }
  448. return 0;
  449. }
  450. static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
  451. SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
  452. SND_SOC_DAPM_MUX("DAC Left Input",
  453. SND_SOC_NOPM, 0, 0, &ldac_in_control),
  454. SND_SOC_DAPM_MUX("DAC Right Input",
  455. SND_SOC_NOPM, 0, 0, &rdac_in_control),
  456. /* DACs */
  457. SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
  458. AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
  459. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  460. SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
  461. AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
  462. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  463. /* HP */
  464. SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
  465. &aic31xx_dapm_hpl_switch),
  466. SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
  467. &aic31xx_dapm_hpr_switch),
  468. /* Output drivers */
  469. SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
  470. NULL, 0, aic31xx_dapm_power_event,
  471. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
  472. SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
  473. NULL, 0, aic31xx_dapm_power_event,
  474. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
  475. /* Mic Bias */
  476. SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
  477. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  478. /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
  479. SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
  480. NULL, 0),
  481. /* Outputs */
  482. SND_SOC_DAPM_OUTPUT("HPL"),
  483. SND_SOC_DAPM_OUTPUT("HPR"),
  484. };
  485. static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
  486. /* Inputs */
  487. SND_SOC_DAPM_INPUT("AIN1"),
  488. SND_SOC_DAPM_INPUT("AIN2"),
  489. /* Output Mixers */
  490. SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
  491. dac31xx_left_output_switches,
  492. ARRAY_SIZE(dac31xx_left_output_switches)),
  493. SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
  494. dac31xx_right_output_switches,
  495. ARRAY_SIZE(dac31xx_right_output_switches)),
  496. };
  497. static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
  498. /* Inputs */
  499. SND_SOC_DAPM_INPUT("MIC1LP"),
  500. SND_SOC_DAPM_INPUT("MIC1RP"),
  501. SND_SOC_DAPM_INPUT("MIC1LM"),
  502. /* Input Selection to MIC_PGA */
  503. SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
  504. &p_term_mic1lp),
  505. SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
  506. &p_term_mic1rp),
  507. SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
  508. &p_term_mic1lm),
  509. /* ADC */
  510. SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
  511. aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
  512. SND_SOC_DAPM_POST_PMD),
  513. SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
  514. &m_term_mic1lm),
  515. /* Enabling & Disabling MIC Gain Ctl */
  516. SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
  517. 7, 1, NULL, 0),
  518. /* Output Mixers */
  519. SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
  520. aic31xx_left_output_switches,
  521. ARRAY_SIZE(aic31xx_left_output_switches)),
  522. SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
  523. aic31xx_right_output_switches,
  524. ARRAY_SIZE(aic31xx_right_output_switches)),
  525. SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
  526. };
  527. static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
  528. /* AIC3111 and AIC3110 have stereo class-D amplifier */
  529. SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
  530. aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
  531. SND_SOC_DAPM_POST_PMD),
  532. SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
  533. aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
  534. SND_SOC_DAPM_POST_PMD),
  535. SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
  536. &aic31xx_dapm_spl_switch),
  537. SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
  538. &aic31xx_dapm_spr_switch),
  539. SND_SOC_DAPM_OUTPUT("SPL"),
  540. SND_SOC_DAPM_OUTPUT("SPR"),
  541. };
  542. /* AIC3100 and AIC3120 have only mono class-D amplifier */
  543. static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
  544. SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
  545. aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
  546. SND_SOC_DAPM_POST_PMD),
  547. SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
  548. &aic31xx_dapm_spl_switch),
  549. SND_SOC_DAPM_OUTPUT("SPK"),
  550. };
  551. static const struct snd_soc_dapm_route
  552. common31xx_audio_map[] = {
  553. /* DAC Input Routing */
  554. {"DAC Left Input", "Left Data", "AIF IN"},
  555. {"DAC Left Input", "Right Data", "AIF IN"},
  556. {"DAC Left Input", "Mono", "AIF IN"},
  557. {"DAC Right Input", "Left Data", "AIF IN"},
  558. {"DAC Right Input", "Right Data", "AIF IN"},
  559. {"DAC Right Input", "Mono", "AIF IN"},
  560. {"DAC Left", NULL, "DAC Left Input"},
  561. {"DAC Right", NULL, "DAC Right Input"},
  562. /* HPL path */
  563. {"HP Left", "Switch", "Output Left"},
  564. {"HPL Driver", NULL, "HP Left"},
  565. {"HPL", NULL, "HPL Driver"},
  566. /* HPR path */
  567. {"HP Right", "Switch", "Output Right"},
  568. {"HPR Driver", NULL, "HP Right"},
  569. {"HPR", NULL, "HPR Driver"},
  570. };
  571. static const struct snd_soc_dapm_route
  572. dac31xx_audio_map[] = {
  573. /* Left Output */
  574. {"Output Left", "From Left DAC", "DAC Left"},
  575. {"Output Left", "From AIN1", "AIN1"},
  576. {"Output Left", "From AIN2", "AIN2"},
  577. /* Right Output */
  578. {"Output Right", "From Right DAC", "DAC Right"},
  579. {"Output Right", "From AIN2", "AIN2"},
  580. };
  581. static const struct snd_soc_dapm_route
  582. aic31xx_audio_map[] = {
  583. /* Mic input */
  584. {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
  585. {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
  586. {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
  587. {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
  588. {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
  589. {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
  590. {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
  591. {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
  592. {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
  593. {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
  594. {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
  595. {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
  596. {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
  597. {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
  598. {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
  599. {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
  600. {"ADC", NULL, "MIC_GAIN_CTL"},
  601. {"AIF OUT", NULL, "ADC"},
  602. /* Left Output */
  603. {"Output Left", "From Left DAC", "DAC Left"},
  604. {"Output Left", "From MIC1LP", "MIC1LP"},
  605. {"Output Left", "From MIC1RP", "MIC1RP"},
  606. /* Right Output */
  607. {"Output Right", "From Right DAC", "DAC Right"},
  608. {"Output Right", "From MIC1RP", "MIC1RP"},
  609. };
  610. static const struct snd_soc_dapm_route
  611. aic311x_audio_map[] = {
  612. /* SP L path */
  613. {"Speaker Left", "Switch", "Output Left"},
  614. {"SPL ClassD", NULL, "Speaker Left"},
  615. {"SPL", NULL, "SPL ClassD"},
  616. /* SP R path */
  617. {"Speaker Right", "Switch", "Output Right"},
  618. {"SPR ClassD", NULL, "Speaker Right"},
  619. {"SPR", NULL, "SPR ClassD"},
  620. };
  621. static const struct snd_soc_dapm_route
  622. aic310x_audio_map[] = {
  623. /* SP L path */
  624. {"Speaker", "Switch", "Output Left"},
  625. {"SPK ClassD", NULL, "Speaker"},
  626. {"SPK", NULL, "SPK ClassD"},
  627. };
  628. /*
  629. * Always connected DAPM routes for codec clock master modes.
  630. * If the codec is the master on the I2S bus, we need to power up components
  631. * to have valid DAC_CLK.
  632. *
  633. * In order to have the I2S clocks on the bus either the DACs/ADC need to be
  634. * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
  635. *
  636. * Otherwise the codec will not generate clocks on the bus.
  637. */
  638. static const struct snd_soc_dapm_route
  639. common31xx_cm_audio_map[] = {
  640. {"HPL", NULL, "AIF IN"},
  641. {"HPR", NULL, "AIF IN"},
  642. {"AIF IN", NULL, "Activate I2S clocks"},
  643. };
  644. static const struct snd_soc_dapm_route
  645. aic31xx_cm_audio_map[] = {
  646. {"AIF OUT", NULL, "MIC1LP"},
  647. {"AIF OUT", NULL, "MIC1RP"},
  648. {"AIF OUT", NULL, "MIC1LM"},
  649. {"AIF OUT", NULL, "Activate I2S clocks"},
  650. };
  651. static int aic31xx_add_controls(struct snd_soc_component *component)
  652. {
  653. int ret = 0;
  654. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  655. if (!(aic31xx->codec_type & DAC31XX_BIT))
  656. ret = snd_soc_add_component_controls(
  657. component, aic31xx_snd_controls,
  658. ARRAY_SIZE(aic31xx_snd_controls));
  659. if (ret)
  660. return ret;
  661. if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
  662. ret = snd_soc_add_component_controls(
  663. component, aic311x_snd_controls,
  664. ARRAY_SIZE(aic311x_snd_controls));
  665. else
  666. ret = snd_soc_add_component_controls(
  667. component, aic310x_snd_controls,
  668. ARRAY_SIZE(aic310x_snd_controls));
  669. return ret;
  670. }
  671. static int aic31xx_add_widgets(struct snd_soc_component *component)
  672. {
  673. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  674. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  675. int ret = 0;
  676. if (aic31xx->codec_type & DAC31XX_BIT) {
  677. ret = snd_soc_dapm_new_controls(
  678. dapm, dac31xx_dapm_widgets,
  679. ARRAY_SIZE(dac31xx_dapm_widgets));
  680. if (ret)
  681. return ret;
  682. ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
  683. ARRAY_SIZE(dac31xx_audio_map));
  684. if (ret)
  685. return ret;
  686. } else {
  687. ret = snd_soc_dapm_new_controls(
  688. dapm, aic31xx_dapm_widgets,
  689. ARRAY_SIZE(aic31xx_dapm_widgets));
  690. if (ret)
  691. return ret;
  692. ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
  693. ARRAY_SIZE(aic31xx_audio_map));
  694. if (ret)
  695. return ret;
  696. }
  697. if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
  698. ret = snd_soc_dapm_new_controls(
  699. dapm, aic311x_dapm_widgets,
  700. ARRAY_SIZE(aic311x_dapm_widgets));
  701. if (ret)
  702. return ret;
  703. ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
  704. ARRAY_SIZE(aic311x_audio_map));
  705. if (ret)
  706. return ret;
  707. } else {
  708. ret = snd_soc_dapm_new_controls(
  709. dapm, aic310x_dapm_widgets,
  710. ARRAY_SIZE(aic310x_dapm_widgets));
  711. if (ret)
  712. return ret;
  713. ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
  714. ARRAY_SIZE(aic310x_audio_map));
  715. if (ret)
  716. return ret;
  717. }
  718. return 0;
  719. }
  720. static int aic31xx_setup_pll(struct snd_soc_component *component,
  721. struct snd_pcm_hw_params *params)
  722. {
  723. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  724. int bclk_score = snd_soc_params_to_frame_size(params);
  725. int mclk_p;
  726. int bclk_n = 0;
  727. int match = -1;
  728. int i;
  729. if (!aic31xx->sysclk || !aic31xx->p_div) {
  730. dev_err(component->dev, "Master clock not supplied\n");
  731. return -EINVAL;
  732. }
  733. mclk_p = aic31xx->sysclk / aic31xx->p_div;
  734. /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
  735. snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
  736. AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
  737. snd_soc_component_update_bits(component, AIC31XX_IFACE2,
  738. AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
  739. for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
  740. if (aic31xx_divs[i].rate == params_rate(params) &&
  741. aic31xx_divs[i].mclk_p == mclk_p) {
  742. int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
  743. snd_soc_params_to_frame_size(params);
  744. int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
  745. snd_soc_params_to_frame_size(params);
  746. if (s < bclk_score && bn > 0) {
  747. match = i;
  748. bclk_n = bn;
  749. bclk_score = s;
  750. }
  751. }
  752. }
  753. if (match == -1) {
  754. dev_err(component->dev,
  755. "%s: Sample rate (%u) and format not supported\n",
  756. __func__, params_rate(params));
  757. /* See bellow for details how fix this. */
  758. return -EINVAL;
  759. }
  760. if (bclk_score != 0) {
  761. dev_warn(component->dev, "Can not produce exact bitclock");
  762. /* This is fine if using dsp format, but if using i2s
  763. there may be trouble. To fix the issue edit the
  764. aic31xx_divs table for your mclk and sample
  765. rate. Details can be found from:
  766. https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
  767. Section: 5.6 CLOCK Generation and PLL
  768. */
  769. }
  770. i = match;
  771. /* PLL configuration */
  772. snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
  773. (aic31xx->p_div << 4) | 0x01);
  774. snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
  775. snd_soc_component_write(component, AIC31XX_PLLDMSB,
  776. aic31xx_divs[i].pll_d >> 8);
  777. snd_soc_component_write(component, AIC31XX_PLLDLSB,
  778. aic31xx_divs[i].pll_d & 0xff);
  779. /* DAC dividers configuration */
  780. snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
  781. aic31xx_divs[i].ndac);
  782. snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
  783. aic31xx_divs[i].mdac);
  784. snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
  785. snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
  786. /* ADC dividers configuration. Write reset value 1 if not used. */
  787. snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
  788. aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
  789. snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
  790. aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
  791. snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
  792. /* Bit clock divider configuration. */
  793. snd_soc_component_update_bits(component, AIC31XX_BCLKN,
  794. AIC31XX_PLL_MASK, bclk_n);
  795. aic31xx->rate_div_line = i;
  796. dev_dbg(component->dev,
  797. "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
  798. aic31xx_divs[i].pll_j,
  799. aic31xx_divs[i].pll_d,
  800. aic31xx->p_div,
  801. aic31xx_divs[i].dosr,
  802. aic31xx_divs[i].ndac,
  803. aic31xx_divs[i].mdac,
  804. aic31xx_divs[i].aosr,
  805. aic31xx_divs[i].nadc,
  806. aic31xx_divs[i].madc,
  807. bclk_n
  808. );
  809. return 0;
  810. }
  811. static int aic31xx_hw_params(struct snd_pcm_substream *substream,
  812. struct snd_pcm_hw_params *params,
  813. struct snd_soc_dai *dai)
  814. {
  815. struct snd_soc_component *component = dai->component;
  816. u8 data = 0;
  817. dev_dbg(component->dev, "## %s: width %d rate %d\n",
  818. __func__, params_width(params),
  819. params_rate(params));
  820. switch (params_width(params)) {
  821. case 16:
  822. break;
  823. case 20:
  824. data = (AIC31XX_WORD_LEN_20BITS <<
  825. AIC31XX_IFACE1_DATALEN_SHIFT);
  826. break;
  827. case 24:
  828. data = (AIC31XX_WORD_LEN_24BITS <<
  829. AIC31XX_IFACE1_DATALEN_SHIFT);
  830. break;
  831. case 32:
  832. data = (AIC31XX_WORD_LEN_32BITS <<
  833. AIC31XX_IFACE1_DATALEN_SHIFT);
  834. break;
  835. default:
  836. dev_err(component->dev, "%s: Unsupported width %d\n",
  837. __func__, params_width(params));
  838. return -EINVAL;
  839. }
  840. snd_soc_component_update_bits(component, AIC31XX_IFACE1,
  841. AIC31XX_IFACE1_DATALEN_MASK,
  842. data);
  843. return aic31xx_setup_pll(component, params);
  844. }
  845. static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute,
  846. int direction)
  847. {
  848. struct snd_soc_component *component = codec_dai->component;
  849. if (mute) {
  850. snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
  851. AIC31XX_DACMUTE_MASK,
  852. AIC31XX_DACMUTE_MASK);
  853. } else {
  854. snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
  855. AIC31XX_DACMUTE_MASK, 0x0);
  856. }
  857. return 0;
  858. }
  859. static int aic31xx_clock_master_routes(struct snd_soc_component *component,
  860. unsigned int fmt)
  861. {
  862. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  863. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  864. int ret;
  865. fmt &= SND_SOC_DAIFMT_MASTER_MASK;
  866. if (fmt == SND_SOC_DAIFMT_CBS_CFS &&
  867. aic31xx->master_dapm_route_applied) {
  868. /*
  869. * Remove the DAPM route(s) for codec clock master modes,
  870. * if applied
  871. */
  872. ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
  873. ARRAY_SIZE(common31xx_cm_audio_map));
  874. if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
  875. ret = snd_soc_dapm_del_routes(dapm,
  876. aic31xx_cm_audio_map,
  877. ARRAY_SIZE(aic31xx_cm_audio_map));
  878. if (ret)
  879. return ret;
  880. aic31xx->master_dapm_route_applied = false;
  881. } else if (fmt != SND_SOC_DAIFMT_CBS_CFS &&
  882. !aic31xx->master_dapm_route_applied) {
  883. /*
  884. * Add the needed DAPM route(s) for codec clock master modes,
  885. * if it is not done already
  886. */
  887. ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
  888. ARRAY_SIZE(common31xx_cm_audio_map));
  889. if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
  890. ret = snd_soc_dapm_add_routes(dapm,
  891. aic31xx_cm_audio_map,
  892. ARRAY_SIZE(aic31xx_cm_audio_map));
  893. if (ret)
  894. return ret;
  895. aic31xx->master_dapm_route_applied = true;
  896. }
  897. return 0;
  898. }
  899. static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
  900. unsigned int fmt)
  901. {
  902. struct snd_soc_component *component = codec_dai->component;
  903. u8 iface_reg1 = 0;
  904. u8 iface_reg2 = 0;
  905. u8 dsp_a_val = 0;
  906. dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
  907. /* set master/slave audio interface */
  908. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  909. case SND_SOC_DAIFMT_CBM_CFM:
  910. iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
  911. break;
  912. case SND_SOC_DAIFMT_CBS_CFM:
  913. iface_reg1 |= AIC31XX_WCLK_MASTER;
  914. break;
  915. case SND_SOC_DAIFMT_CBM_CFS:
  916. iface_reg1 |= AIC31XX_BCLK_MASTER;
  917. break;
  918. case SND_SOC_DAIFMT_CBS_CFS:
  919. break;
  920. default:
  921. dev_err(component->dev, "Invalid DAI master/slave interface\n");
  922. return -EINVAL;
  923. }
  924. /* signal polarity */
  925. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  926. case SND_SOC_DAIFMT_NB_NF:
  927. break;
  928. case SND_SOC_DAIFMT_IB_NF:
  929. iface_reg2 |= AIC31XX_BCLKINV_MASK;
  930. break;
  931. default:
  932. dev_err(component->dev, "Invalid DAI clock signal polarity\n");
  933. return -EINVAL;
  934. }
  935. /* interface format */
  936. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  937. case SND_SOC_DAIFMT_I2S:
  938. break;
  939. case SND_SOC_DAIFMT_DSP_A:
  940. dsp_a_val = 0x1;
  941. fallthrough;
  942. case SND_SOC_DAIFMT_DSP_B:
  943. /*
  944. * NOTE: This CODEC samples on the falling edge of BCLK in
  945. * DSP mode, this is inverted compared to what most DAIs
  946. * expect, so we invert for this mode
  947. */
  948. iface_reg2 ^= AIC31XX_BCLKINV_MASK;
  949. iface_reg1 |= (AIC31XX_DSP_MODE <<
  950. AIC31XX_IFACE1_DATATYPE_SHIFT);
  951. break;
  952. case SND_SOC_DAIFMT_RIGHT_J:
  953. iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
  954. AIC31XX_IFACE1_DATATYPE_SHIFT);
  955. break;
  956. case SND_SOC_DAIFMT_LEFT_J:
  957. iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
  958. AIC31XX_IFACE1_DATATYPE_SHIFT);
  959. break;
  960. default:
  961. dev_err(component->dev, "Invalid DAI interface format\n");
  962. return -EINVAL;
  963. }
  964. snd_soc_component_update_bits(component, AIC31XX_IFACE1,
  965. AIC31XX_IFACE1_DATATYPE_MASK |
  966. AIC31XX_IFACE1_MASTER_MASK,
  967. iface_reg1);
  968. snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
  969. AIC31XX_DATA_OFFSET_MASK,
  970. dsp_a_val);
  971. snd_soc_component_update_bits(component, AIC31XX_IFACE2,
  972. AIC31XX_BCLKINV_MASK,
  973. iface_reg2);
  974. return aic31xx_clock_master_routes(component, fmt);
  975. }
  976. static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  977. int clk_id, unsigned int freq, int dir)
  978. {
  979. struct snd_soc_component *component = codec_dai->component;
  980. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  981. int i;
  982. dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
  983. __func__, clk_id, freq, dir);
  984. for (i = 1; i < 8; i++)
  985. if (freq / i <= 20000000)
  986. break;
  987. if (freq/i > 20000000) {
  988. dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
  989. __func__, freq);
  990. return -EINVAL;
  991. }
  992. aic31xx->p_div = i;
  993. for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
  994. if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
  995. break;
  996. if (i == ARRAY_SIZE(aic31xx_divs)) {
  997. dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
  998. __func__, freq);
  999. return -EINVAL;
  1000. }
  1001. /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
  1002. snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
  1003. clk_id << AIC31XX_PLL_CLKIN_SHIFT);
  1004. aic31xx->sysclk = freq;
  1005. return 0;
  1006. }
  1007. static int aic31xx_regulator_event(struct notifier_block *nb,
  1008. unsigned long event, void *data)
  1009. {
  1010. struct aic31xx_disable_nb *disable_nb =
  1011. container_of(nb, struct aic31xx_disable_nb, nb);
  1012. struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
  1013. if (event & REGULATOR_EVENT_DISABLE) {
  1014. /*
  1015. * Put codec to reset and as at least one of the
  1016. * supplies was disabled.
  1017. */
  1018. if (aic31xx->gpio_reset)
  1019. gpiod_set_value(aic31xx->gpio_reset, 1);
  1020. regcache_mark_dirty(aic31xx->regmap);
  1021. dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
  1022. }
  1023. return 0;
  1024. }
  1025. static int aic31xx_reset(struct aic31xx_priv *aic31xx)
  1026. {
  1027. int ret = 0;
  1028. if (aic31xx->gpio_reset) {
  1029. gpiod_set_value(aic31xx->gpio_reset, 1);
  1030. ndelay(10); /* At least 10ns */
  1031. gpiod_set_value(aic31xx->gpio_reset, 0);
  1032. } else {
  1033. ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
  1034. }
  1035. mdelay(1); /* At least 1ms */
  1036. return ret;
  1037. }
  1038. static void aic31xx_clk_on(struct snd_soc_component *component)
  1039. {
  1040. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  1041. u8 mask = AIC31XX_PM_MASK;
  1042. u8 on = AIC31XX_PM_MASK;
  1043. dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
  1044. aic31xx_divs[aic31xx->rate_div_line].rate);
  1045. snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
  1046. mdelay(10);
  1047. snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
  1048. snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
  1049. if (aic31xx_divs[aic31xx->rate_div_line].nadc)
  1050. snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
  1051. if (aic31xx_divs[aic31xx->rate_div_line].madc)
  1052. snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
  1053. snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
  1054. }
  1055. static void aic31xx_clk_off(struct snd_soc_component *component)
  1056. {
  1057. u8 mask = AIC31XX_PM_MASK;
  1058. u8 off = 0;
  1059. dev_dbg(component->dev, "codec clock -> off\n");
  1060. snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
  1061. snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
  1062. snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
  1063. snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
  1064. snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
  1065. snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
  1066. }
  1067. static int aic31xx_power_on(struct snd_soc_component *component)
  1068. {
  1069. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  1070. int ret;
  1071. ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
  1072. aic31xx->supplies);
  1073. if (ret)
  1074. return ret;
  1075. regcache_cache_only(aic31xx->regmap, false);
  1076. /* Reset device registers for a consistent power-on like state */
  1077. ret = aic31xx_reset(aic31xx);
  1078. if (ret < 0)
  1079. dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
  1080. ret = regcache_sync(aic31xx->regmap);
  1081. if (ret) {
  1082. dev_err(component->dev,
  1083. "Failed to restore cache: %d\n", ret);
  1084. regcache_cache_only(aic31xx->regmap, true);
  1085. regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
  1086. aic31xx->supplies);
  1087. return ret;
  1088. }
  1089. /*
  1090. * The jack detection configuration is in the same register
  1091. * that is used to report jack detect status so is volatile
  1092. * and not covered by the cache sync, restore it separately.
  1093. */
  1094. aic31xx_set_jack(component, aic31xx->jack, NULL);
  1095. return 0;
  1096. }
  1097. static void aic31xx_power_off(struct snd_soc_component *component)
  1098. {
  1099. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  1100. regcache_cache_only(aic31xx->regmap, true);
  1101. regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
  1102. aic31xx->supplies);
  1103. }
  1104. static int aic31xx_set_bias_level(struct snd_soc_component *component,
  1105. enum snd_soc_bias_level level)
  1106. {
  1107. dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
  1108. snd_soc_component_get_bias_level(component), level);
  1109. switch (level) {
  1110. case SND_SOC_BIAS_ON:
  1111. break;
  1112. case SND_SOC_BIAS_PREPARE:
  1113. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
  1114. aic31xx_clk_on(component);
  1115. break;
  1116. case SND_SOC_BIAS_STANDBY:
  1117. switch (snd_soc_component_get_bias_level(component)) {
  1118. case SND_SOC_BIAS_OFF:
  1119. aic31xx_power_on(component);
  1120. break;
  1121. case SND_SOC_BIAS_PREPARE:
  1122. aic31xx_clk_off(component);
  1123. break;
  1124. default:
  1125. BUG();
  1126. }
  1127. break;
  1128. case SND_SOC_BIAS_OFF:
  1129. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
  1130. aic31xx_power_off(component);
  1131. break;
  1132. }
  1133. return 0;
  1134. }
  1135. static int aic31xx_set_jack(struct snd_soc_component *component,
  1136. struct snd_soc_jack *jack, void *data)
  1137. {
  1138. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  1139. aic31xx->jack = jack;
  1140. /* Enable/Disable jack detection */
  1141. regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,
  1142. jack ? AIC31XX_HSD_ENABLE : 0);
  1143. return 0;
  1144. }
  1145. static int aic31xx_codec_probe(struct snd_soc_component *component)
  1146. {
  1147. struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
  1148. int i, ret;
  1149. dev_dbg(aic31xx->dev, "## %s\n", __func__);
  1150. aic31xx->component = component;
  1151. for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
  1152. aic31xx->disable_nb[i].nb.notifier_call =
  1153. aic31xx_regulator_event;
  1154. aic31xx->disable_nb[i].aic31xx = aic31xx;
  1155. ret = devm_regulator_register_notifier(
  1156. aic31xx->supplies[i].consumer,
  1157. &aic31xx->disable_nb[i].nb);
  1158. if (ret) {
  1159. dev_err(component->dev,
  1160. "Failed to request regulator notifier: %d\n",
  1161. ret);
  1162. return ret;
  1163. }
  1164. }
  1165. regcache_cache_only(aic31xx->regmap, true);
  1166. regcache_mark_dirty(aic31xx->regmap);
  1167. ret = aic31xx_add_controls(component);
  1168. if (ret)
  1169. return ret;
  1170. ret = aic31xx_add_widgets(component);
  1171. if (ret)
  1172. return ret;
  1173. /* set output common-mode voltage */
  1174. snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,
  1175. AIC31XX_HPD_OCMV_MASK,
  1176. aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);
  1177. return 0;
  1178. }
  1179. static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
  1180. .probe = aic31xx_codec_probe,
  1181. .set_jack = aic31xx_set_jack,
  1182. .set_bias_level = aic31xx_set_bias_level,
  1183. .controls = common31xx_snd_controls,
  1184. .num_controls = ARRAY_SIZE(common31xx_snd_controls),
  1185. .dapm_widgets = common31xx_dapm_widgets,
  1186. .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
  1187. .dapm_routes = common31xx_audio_map,
  1188. .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
  1189. .suspend_bias_off = 1,
  1190. .idle_bias_on = 1,
  1191. .use_pmdown_time = 1,
  1192. .endianness = 1,
  1193. .non_legacy_dai_naming = 1,
  1194. };
  1195. static const struct snd_soc_dai_ops aic31xx_dai_ops = {
  1196. .hw_params = aic31xx_hw_params,
  1197. .set_sysclk = aic31xx_set_dai_sysclk,
  1198. .set_fmt = aic31xx_set_dai_fmt,
  1199. .mute_stream = aic31xx_dac_mute,
  1200. .no_capture_mute = 1,
  1201. };
  1202. static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
  1203. {
  1204. .name = "tlv320dac31xx-hifi",
  1205. .playback = {
  1206. .stream_name = "Playback",
  1207. .channels_min = 2,
  1208. .channels_max = 2,
  1209. .rates = AIC31XX_RATES,
  1210. .formats = AIC31XX_FORMATS,
  1211. },
  1212. .ops = &aic31xx_dai_ops,
  1213. .symmetric_rates = 1,
  1214. }
  1215. };
  1216. static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
  1217. {
  1218. .name = "tlv320aic31xx-hifi",
  1219. .playback = {
  1220. .stream_name = "Playback",
  1221. .channels_min = 2,
  1222. .channels_max = 2,
  1223. .rates = AIC31XX_RATES,
  1224. .formats = AIC31XX_FORMATS,
  1225. },
  1226. .capture = {
  1227. .stream_name = "Capture",
  1228. .channels_min = 2,
  1229. .channels_max = 2,
  1230. .rates = AIC31XX_RATES,
  1231. .formats = AIC31XX_FORMATS,
  1232. },
  1233. .ops = &aic31xx_dai_ops,
  1234. .symmetric_rates = 1,
  1235. }
  1236. };
  1237. #if defined(CONFIG_OF)
  1238. static const struct of_device_id tlv320aic31xx_of_match[] = {
  1239. { .compatible = "ti,tlv320aic310x" },
  1240. { .compatible = "ti,tlv320aic311x" },
  1241. { .compatible = "ti,tlv320aic3100" },
  1242. { .compatible = "ti,tlv320aic3110" },
  1243. { .compatible = "ti,tlv320aic3120" },
  1244. { .compatible = "ti,tlv320aic3111" },
  1245. { .compatible = "ti,tlv320dac3100" },
  1246. { .compatible = "ti,tlv320dac3101" },
  1247. {},
  1248. };
  1249. MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
  1250. #endif /* CONFIG_OF */
  1251. #ifdef CONFIG_ACPI
  1252. static const struct acpi_device_id aic31xx_acpi_match[] = {
  1253. { "10TI3100", 0 },
  1254. { }
  1255. };
  1256. MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
  1257. #endif
  1258. static irqreturn_t aic31xx_irq(int irq, void *data)
  1259. {
  1260. struct aic31xx_priv *aic31xx = data;
  1261. struct device *dev = aic31xx->dev;
  1262. unsigned int value;
  1263. bool handled = false;
  1264. int ret;
  1265. ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);
  1266. if (ret) {
  1267. dev_err(dev, "Failed to read interrupt mask: %d\n", ret);
  1268. goto exit;
  1269. }
  1270. if (value)
  1271. handled = true;
  1272. else
  1273. goto read_overflow;
  1274. if (value & AIC31XX_HPLSCDETECT)
  1275. dev_err(dev, "Short circuit on Left output is detected\n");
  1276. if (value & AIC31XX_HPRSCDETECT)
  1277. dev_err(dev, "Short circuit on Right output is detected\n");
  1278. if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {
  1279. unsigned int val;
  1280. int status = 0;
  1281. ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,
  1282. &val);
  1283. if (ret) {
  1284. dev_err(dev, "Failed to read interrupt mask: %d\n",
  1285. ret);
  1286. goto exit;
  1287. }
  1288. if (val & AIC31XX_BUTTONPRESS)
  1289. status |= SND_JACK_BTN_0;
  1290. ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);
  1291. if (ret) {
  1292. dev_err(dev, "Failed to read headset type: %d\n", ret);
  1293. goto exit;
  1294. }
  1295. switch ((val & AIC31XX_HSD_TYPE_MASK) >>
  1296. AIC31XX_HSD_TYPE_SHIFT) {
  1297. case AIC31XX_HSD_HP:
  1298. status |= SND_JACK_HEADPHONE;
  1299. break;
  1300. case AIC31XX_HSD_HS:
  1301. status |= SND_JACK_HEADSET;
  1302. break;
  1303. default:
  1304. break;
  1305. }
  1306. if (aic31xx->jack)
  1307. snd_soc_jack_report(aic31xx->jack, status,
  1308. AIC31XX_JACK_MASK);
  1309. }
  1310. if (value & ~(AIC31XX_HPLSCDETECT |
  1311. AIC31XX_HPRSCDETECT |
  1312. AIC31XX_HSPLUG |
  1313. AIC31XX_BUTTONPRESS))
  1314. dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);
  1315. read_overflow:
  1316. ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);
  1317. if (ret) {
  1318. dev_err(dev, "Failed to read overflow flag: %d\n", ret);
  1319. goto exit;
  1320. }
  1321. if (value)
  1322. handled = true;
  1323. else
  1324. goto exit;
  1325. if (value & AIC31XX_DAC_OF_LEFT)
  1326. dev_warn(dev, "Left-channel DAC overflow has occurred\n");
  1327. if (value & AIC31XX_DAC_OF_RIGHT)
  1328. dev_warn(dev, "Right-channel DAC overflow has occurred\n");
  1329. if (value & AIC31XX_DAC_OF_SHIFTER)
  1330. dev_warn(dev, "DAC barrel shifter overflow has occurred\n");
  1331. if (value & AIC31XX_ADC_OF)
  1332. dev_warn(dev, "ADC overflow has occurred\n");
  1333. if (value & AIC31XX_ADC_OF_SHIFTER)
  1334. dev_warn(dev, "ADC barrel shifter overflow has occurred\n");
  1335. if (value & ~(AIC31XX_DAC_OF_LEFT |
  1336. AIC31XX_DAC_OF_RIGHT |
  1337. AIC31XX_DAC_OF_SHIFTER |
  1338. AIC31XX_ADC_OF |
  1339. AIC31XX_ADC_OF_SHIFTER))
  1340. dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);
  1341. exit:
  1342. if (handled)
  1343. return IRQ_HANDLED;
  1344. else
  1345. return IRQ_NONE;
  1346. }
  1347. static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)
  1348. {
  1349. struct device *dev = priv->dev;
  1350. int dvdd, avdd;
  1351. u32 value;
  1352. if (dev->fwnode &&
  1353. fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {
  1354. /* OCMV setting is forced by DT */
  1355. if (value <= 3) {
  1356. priv->ocmv = value;
  1357. return;
  1358. }
  1359. }
  1360. avdd = regulator_get_voltage(priv->supplies[3].consumer);
  1361. dvdd = regulator_get_voltage(priv->supplies[5].consumer);
  1362. if (avdd > 3600000 || dvdd > 1950000) {
  1363. dev_warn(dev,
  1364. "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
  1365. avdd, dvdd);
  1366. } else if (avdd == 3600000 && dvdd == 1950000) {
  1367. priv->ocmv = AIC31XX_HPD_OCMV_1_8V;
  1368. } else if (avdd >= 3300000 && dvdd >= 1800000) {
  1369. priv->ocmv = AIC31XX_HPD_OCMV_1_65V;
  1370. } else if (avdd >= 3000000 && dvdd >= 1650000) {
  1371. priv->ocmv = AIC31XX_HPD_OCMV_1_5V;
  1372. } else if (avdd >= 2700000 && dvdd >= 1525000) {
  1373. priv->ocmv = AIC31XX_HPD_OCMV_1_35V;
  1374. } else {
  1375. dev_warn(dev,
  1376. "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
  1377. avdd, dvdd);
  1378. }
  1379. }
  1380. static int aic31xx_i2c_probe(struct i2c_client *i2c,
  1381. const struct i2c_device_id *id)
  1382. {
  1383. struct aic31xx_priv *aic31xx;
  1384. unsigned int micbias_value = MICBIAS_2_0V;
  1385. int i, ret;
  1386. dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
  1387. id->name, (int)id->driver_data);
  1388. aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
  1389. if (!aic31xx)
  1390. return -ENOMEM;
  1391. aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
  1392. if (IS_ERR(aic31xx->regmap)) {
  1393. ret = PTR_ERR(aic31xx->regmap);
  1394. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1395. ret);
  1396. return ret;
  1397. }
  1398. aic31xx->dev = &i2c->dev;
  1399. aic31xx->irq = i2c->irq;
  1400. aic31xx->codec_type = id->driver_data;
  1401. dev_set_drvdata(aic31xx->dev, aic31xx);
  1402. fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
  1403. &micbias_value);
  1404. switch (micbias_value) {
  1405. case MICBIAS_2_0V:
  1406. case MICBIAS_2_5V:
  1407. case MICBIAS_AVDDV:
  1408. aic31xx->micbias_vg = micbias_value;
  1409. break;
  1410. default:
  1411. dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
  1412. micbias_value);
  1413. aic31xx->micbias_vg = MICBIAS_2_0V;
  1414. }
  1415. if (dev_get_platdata(aic31xx->dev)) {
  1416. memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
  1417. aic31xx->codec_type = aic31xx->pdata.codec_type;
  1418. aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
  1419. }
  1420. aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
  1421. GPIOD_OUT_LOW);
  1422. if (IS_ERR(aic31xx->gpio_reset)) {
  1423. if (PTR_ERR(aic31xx->gpio_reset) != -EPROBE_DEFER)
  1424. dev_err(aic31xx->dev, "not able to acquire gpio\n");
  1425. return PTR_ERR(aic31xx->gpio_reset);
  1426. }
  1427. for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
  1428. aic31xx->supplies[i].supply = aic31xx_supply_names[i];
  1429. ret = devm_regulator_bulk_get(aic31xx->dev,
  1430. ARRAY_SIZE(aic31xx->supplies),
  1431. aic31xx->supplies);
  1432. if (ret) {
  1433. if (ret != -EPROBE_DEFER)
  1434. dev_err(aic31xx->dev,
  1435. "Failed to request supplies: %d\n", ret);
  1436. return ret;
  1437. }
  1438. aic31xx_configure_ocmv(aic31xx);
  1439. if (aic31xx->irq > 0) {
  1440. regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
  1441. AIC31XX_GPIO1_FUNC_MASK,
  1442. AIC31XX_GPIO1_INT1 <<
  1443. AIC31XX_GPIO1_FUNC_SHIFT);
  1444. regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,
  1445. AIC31XX_HSPLUGDET |
  1446. AIC31XX_BUTTONPRESSDET |
  1447. AIC31XX_SC |
  1448. AIC31XX_ENGINE);
  1449. ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,
  1450. NULL, aic31xx_irq,
  1451. IRQF_ONESHOT, "aic31xx-irq",
  1452. aic31xx);
  1453. if (ret) {
  1454. dev_err(aic31xx->dev, "Unable to request IRQ\n");
  1455. return ret;
  1456. }
  1457. }
  1458. if (aic31xx->codec_type & DAC31XX_BIT)
  1459. return devm_snd_soc_register_component(&i2c->dev,
  1460. &soc_codec_driver_aic31xx,
  1461. dac31xx_dai_driver,
  1462. ARRAY_SIZE(dac31xx_dai_driver));
  1463. else
  1464. return devm_snd_soc_register_component(&i2c->dev,
  1465. &soc_codec_driver_aic31xx,
  1466. aic31xx_dai_driver,
  1467. ARRAY_SIZE(aic31xx_dai_driver));
  1468. }
  1469. static const struct i2c_device_id aic31xx_i2c_id[] = {
  1470. { "tlv320aic310x", AIC3100 },
  1471. { "tlv320aic311x", AIC3110 },
  1472. { "tlv320aic3100", AIC3100 },
  1473. { "tlv320aic3110", AIC3110 },
  1474. { "tlv320aic3120", AIC3120 },
  1475. { "tlv320aic3111", AIC3111 },
  1476. { "tlv320dac3100", DAC3100 },
  1477. { "tlv320dac3101", DAC3101 },
  1478. { }
  1479. };
  1480. MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
  1481. static struct i2c_driver aic31xx_i2c_driver = {
  1482. .driver = {
  1483. .name = "tlv320aic31xx-codec",
  1484. .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
  1485. .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
  1486. },
  1487. .probe = aic31xx_i2c_probe,
  1488. .id_table = aic31xx_i2c_id,
  1489. };
  1490. module_i2c_driver(aic31xx_i2c_driver);
  1491. MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
  1492. MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
  1493. MODULE_LICENSE("GPL v2");