tlv320adcx140.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // TLV320ADCX140 Sound driver
  3. // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  4. #include <linux/module.h>
  5. #include <linux/moduleparam.h>
  6. #include <linux/init.h>
  7. #include <linux/delay.h>
  8. #include <linux/pm.h>
  9. #include <linux/i2c.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/regulator/consumer.h>
  12. #include <linux/acpi.h>
  13. #include <linux/of.h>
  14. #include <linux/of_gpio.h>
  15. #include <linux/slab.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/soc.h>
  20. #include <sound/initval.h>
  21. #include <sound/tlv.h>
  22. #include "tlv320adcx140.h"
  23. struct adcx140_priv {
  24. struct snd_soc_component *component;
  25. struct regulator *supply_areg;
  26. struct gpio_desc *gpio_reset;
  27. struct regmap *regmap;
  28. struct device *dev;
  29. bool micbias_vg;
  30. unsigned int dai_fmt;
  31. unsigned int tdm_delay;
  32. unsigned int slot_width;
  33. };
  34. static const char * const gpo_config_names[] = {
  35. "ti,gpo-config-1",
  36. "ti,gpo-config-2",
  37. "ti,gpo-config-3",
  38. "ti,gpo-config-4",
  39. };
  40. static const struct reg_default adcx140_reg_defaults[] = {
  41. { ADCX140_PAGE_SELECT, 0x00 },
  42. { ADCX140_SW_RESET, 0x00 },
  43. { ADCX140_SLEEP_CFG, 0x00 },
  44. { ADCX140_SHDN_CFG, 0x05 },
  45. { ADCX140_ASI_CFG0, 0x30 },
  46. { ADCX140_ASI_CFG1, 0x00 },
  47. { ADCX140_ASI_CFG2, 0x00 },
  48. { ADCX140_ASI_CH1, 0x00 },
  49. { ADCX140_ASI_CH2, 0x01 },
  50. { ADCX140_ASI_CH3, 0x02 },
  51. { ADCX140_ASI_CH4, 0x03 },
  52. { ADCX140_ASI_CH5, 0x04 },
  53. { ADCX140_ASI_CH6, 0x05 },
  54. { ADCX140_ASI_CH7, 0x06 },
  55. { ADCX140_ASI_CH8, 0x07 },
  56. { ADCX140_MST_CFG0, 0x02 },
  57. { ADCX140_MST_CFG1, 0x48 },
  58. { ADCX140_ASI_STS, 0xff },
  59. { ADCX140_CLK_SRC, 0x10 },
  60. { ADCX140_PDMCLK_CFG, 0x40 },
  61. { ADCX140_PDM_CFG, 0x00 },
  62. { ADCX140_GPIO_CFG0, 0x22 },
  63. { ADCX140_GPO_CFG0, 0x00 },
  64. { ADCX140_GPO_CFG1, 0x00 },
  65. { ADCX140_GPO_CFG2, 0x00 },
  66. { ADCX140_GPO_CFG3, 0x00 },
  67. { ADCX140_GPO_VAL, 0x00 },
  68. { ADCX140_GPIO_MON, 0x00 },
  69. { ADCX140_GPI_CFG0, 0x00 },
  70. { ADCX140_GPI_CFG1, 0x00 },
  71. { ADCX140_GPI_MON, 0x00 },
  72. { ADCX140_INT_CFG, 0x00 },
  73. { ADCX140_INT_MASK0, 0xff },
  74. { ADCX140_INT_LTCH0, 0x00 },
  75. { ADCX140_BIAS_CFG, 0x00 },
  76. { ADCX140_CH1_CFG0, 0x00 },
  77. { ADCX140_CH1_CFG1, 0x00 },
  78. { ADCX140_CH1_CFG2, 0xc9 },
  79. { ADCX140_CH1_CFG3, 0x80 },
  80. { ADCX140_CH1_CFG4, 0x00 },
  81. { ADCX140_CH2_CFG0, 0x00 },
  82. { ADCX140_CH2_CFG1, 0x00 },
  83. { ADCX140_CH2_CFG2, 0xc9 },
  84. { ADCX140_CH2_CFG3, 0x80 },
  85. { ADCX140_CH2_CFG4, 0x00 },
  86. { ADCX140_CH3_CFG0, 0x00 },
  87. { ADCX140_CH3_CFG1, 0x00 },
  88. { ADCX140_CH3_CFG2, 0xc9 },
  89. { ADCX140_CH3_CFG3, 0x80 },
  90. { ADCX140_CH3_CFG4, 0x00 },
  91. { ADCX140_CH4_CFG0, 0x00 },
  92. { ADCX140_CH4_CFG1, 0x00 },
  93. { ADCX140_CH4_CFG2, 0xc9 },
  94. { ADCX140_CH4_CFG3, 0x80 },
  95. { ADCX140_CH4_CFG4, 0x00 },
  96. { ADCX140_CH5_CFG2, 0xc9 },
  97. { ADCX140_CH5_CFG3, 0x80 },
  98. { ADCX140_CH5_CFG4, 0x00 },
  99. { ADCX140_CH6_CFG2, 0xc9 },
  100. { ADCX140_CH6_CFG3, 0x80 },
  101. { ADCX140_CH6_CFG4, 0x00 },
  102. { ADCX140_CH7_CFG2, 0xc9 },
  103. { ADCX140_CH7_CFG3, 0x80 },
  104. { ADCX140_CH7_CFG4, 0x00 },
  105. { ADCX140_CH8_CFG2, 0xc9 },
  106. { ADCX140_CH8_CFG3, 0x80 },
  107. { ADCX140_CH8_CFG4, 0x00 },
  108. { ADCX140_DSP_CFG0, 0x01 },
  109. { ADCX140_DSP_CFG1, 0x40 },
  110. { ADCX140_DRE_CFG0, 0x7b },
  111. { ADCX140_AGC_CFG0, 0xe7 },
  112. { ADCX140_IN_CH_EN, 0xf0 },
  113. { ADCX140_ASI_OUT_CH_EN, 0x00 },
  114. { ADCX140_PWR_CFG, 0x00 },
  115. { ADCX140_DEV_STS0, 0x00 },
  116. { ADCX140_DEV_STS1, 0x80 },
  117. };
  118. static const struct regmap_range_cfg adcx140_ranges[] = {
  119. {
  120. .range_min = 0,
  121. .range_max = 12 * 128,
  122. .selector_reg = ADCX140_PAGE_SELECT,
  123. .selector_mask = 0xff,
  124. .selector_shift = 0,
  125. .window_start = 0,
  126. .window_len = 128,
  127. },
  128. };
  129. static bool adcx140_volatile(struct device *dev, unsigned int reg)
  130. {
  131. switch (reg) {
  132. case ADCX140_SW_RESET:
  133. case ADCX140_DEV_STS0:
  134. case ADCX140_DEV_STS1:
  135. case ADCX140_ASI_STS:
  136. return true;
  137. default:
  138. return false;
  139. }
  140. }
  141. static const struct regmap_config adcx140_i2c_regmap = {
  142. .reg_bits = 8,
  143. .val_bits = 8,
  144. .reg_defaults = adcx140_reg_defaults,
  145. .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
  146. .cache_type = REGCACHE_FLAT,
  147. .ranges = adcx140_ranges,
  148. .num_ranges = ARRAY_SIZE(adcx140_ranges),
  149. .max_register = 12 * 128,
  150. .volatile_reg = adcx140_volatile,
  151. };
  152. /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
  153. static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
  154. /* ADC gain. From 0 to 42 dB in 1 dB steps */
  155. static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
  156. /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
  157. static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
  158. /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
  159. static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
  160. /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
  161. static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
  162. /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
  163. static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
  164. static const char * const decimation_filter_text[] = {
  165. "Linear Phase", "Low Latency", "Ultra-low Latency"
  166. };
  167. static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
  168. decimation_filter_text);
  169. static const struct snd_kcontrol_new decimation_filter_controls[] = {
  170. SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
  171. };
  172. static const char * const pdmclk_text[] = {
  173. "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
  174. };
  175. static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
  176. pdmclk_text);
  177. static const struct snd_kcontrol_new pdmclk_div_controls[] = {
  178. SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
  179. };
  180. static const char * const resistor_text[] = {
  181. "2.5 kOhm", "10 kOhm", "20 kOhm"
  182. };
  183. static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
  184. resistor_text);
  185. static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
  186. resistor_text);
  187. static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
  188. resistor_text);
  189. static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
  190. resistor_text);
  191. static const struct snd_kcontrol_new in1_resistor_controls[] = {
  192. SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
  193. };
  194. static const struct snd_kcontrol_new in2_resistor_controls[] = {
  195. SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
  196. };
  197. static const struct snd_kcontrol_new in3_resistor_controls[] = {
  198. SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
  199. };
  200. static const struct snd_kcontrol_new in4_resistor_controls[] = {
  201. SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
  202. };
  203. /* Analog/Digital Selection */
  204. static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
  205. static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
  206. static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
  207. ADCX140_CH1_CFG0, 5,
  208. adcx140_mic_sel_text);
  209. static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
  210. SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
  211. static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
  212. ADCX140_CH1_CFG0, 7,
  213. adcx140_analog_sel_text);
  214. static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
  215. SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
  216. static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
  217. ADCX140_CH1_CFG0, 5,
  218. adcx140_mic_sel_text);
  219. static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
  220. SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
  221. static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
  222. ADCX140_CH2_CFG0, 5,
  223. adcx140_mic_sel_text);
  224. static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
  225. SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
  226. static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
  227. ADCX140_CH2_CFG0, 7,
  228. adcx140_analog_sel_text);
  229. static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
  230. SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
  231. static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
  232. ADCX140_CH2_CFG0, 5,
  233. adcx140_mic_sel_text);
  234. static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
  235. SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
  236. static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
  237. ADCX140_CH3_CFG0, 5,
  238. adcx140_mic_sel_text);
  239. static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
  240. SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
  241. static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
  242. ADCX140_CH3_CFG0, 7,
  243. adcx140_analog_sel_text);
  244. static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
  245. SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
  246. static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
  247. ADCX140_CH3_CFG0, 5,
  248. adcx140_mic_sel_text);
  249. static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
  250. SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
  251. static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
  252. ADCX140_CH4_CFG0, 5,
  253. adcx140_mic_sel_text);
  254. static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
  255. SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
  256. static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
  257. ADCX140_CH4_CFG0, 7,
  258. adcx140_analog_sel_text);
  259. static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
  260. SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
  261. static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
  262. ADCX140_CH4_CFG0, 5,
  263. adcx140_mic_sel_text);
  264. static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
  265. SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
  266. static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
  267. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
  268. static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
  269. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
  270. static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
  271. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
  272. static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
  273. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
  274. static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
  275. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
  276. static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
  277. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
  278. static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
  279. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
  280. static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
  281. SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
  282. static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
  283. SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
  284. static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
  285. SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
  286. static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
  287. SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
  288. static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
  289. SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
  290. static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
  291. SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
  292. /* Output Mixer */
  293. static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
  294. SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
  295. SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
  296. SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
  297. SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
  298. };
  299. static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
  300. /* Analog Differential Inputs */
  301. SND_SOC_DAPM_INPUT("MIC1P"),
  302. SND_SOC_DAPM_INPUT("MIC1M"),
  303. SND_SOC_DAPM_INPUT("MIC2P"),
  304. SND_SOC_DAPM_INPUT("MIC2M"),
  305. SND_SOC_DAPM_INPUT("MIC3P"),
  306. SND_SOC_DAPM_INPUT("MIC3M"),
  307. SND_SOC_DAPM_INPUT("MIC4P"),
  308. SND_SOC_DAPM_INPUT("MIC4M"),
  309. SND_SOC_DAPM_OUTPUT("CH1_OUT"),
  310. SND_SOC_DAPM_OUTPUT("CH2_OUT"),
  311. SND_SOC_DAPM_OUTPUT("CH3_OUT"),
  312. SND_SOC_DAPM_OUTPUT("CH4_OUT"),
  313. SND_SOC_DAPM_OUTPUT("CH5_OUT"),
  314. SND_SOC_DAPM_OUTPUT("CH6_OUT"),
  315. SND_SOC_DAPM_OUTPUT("CH7_OUT"),
  316. SND_SOC_DAPM_OUTPUT("CH8_OUT"),
  317. SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
  318. &adcx140_output_mixer_controls[0],
  319. ARRAY_SIZE(adcx140_output_mixer_controls)),
  320. /* Input Selection to MIC_PGA */
  321. SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
  322. &adcx140_dapm_mic1p_control),
  323. SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
  324. &adcx140_dapm_mic2p_control),
  325. SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
  326. &adcx140_dapm_mic3p_control),
  327. SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
  328. &adcx140_dapm_mic4p_control),
  329. /* Input Selection to MIC_PGA */
  330. SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
  331. &adcx140_dapm_mic1_analog_control),
  332. SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
  333. &adcx140_dapm_mic2_analog_control),
  334. SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
  335. &adcx140_dapm_mic3_analog_control),
  336. SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
  337. &adcx140_dapm_mic4_analog_control),
  338. SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
  339. &adcx140_dapm_mic1m_control),
  340. SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
  341. &adcx140_dapm_mic2m_control),
  342. SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
  343. &adcx140_dapm_mic3m_control),
  344. SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
  345. &adcx140_dapm_mic4m_control),
  346. SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
  347. SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
  348. SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
  349. SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
  350. SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
  351. SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
  352. SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
  353. SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
  354. SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
  355. SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
  356. SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
  357. SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
  358. SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
  359. SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
  360. SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
  361. SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
  362. SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
  363. &adcx140_dapm_ch1_en_switch),
  364. SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
  365. &adcx140_dapm_ch2_en_switch),
  366. SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
  367. &adcx140_dapm_ch3_en_switch),
  368. SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
  369. &adcx140_dapm_ch4_en_switch),
  370. SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
  371. &adcx140_dapm_ch5_en_switch),
  372. SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
  373. &adcx140_dapm_ch6_en_switch),
  374. SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
  375. &adcx140_dapm_ch7_en_switch),
  376. SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
  377. &adcx140_dapm_ch8_en_switch),
  378. SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
  379. &adcx140_dapm_dre_en_switch),
  380. SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
  381. &adcx140_dapm_ch1_dre_en_switch),
  382. SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
  383. &adcx140_dapm_ch2_dre_en_switch),
  384. SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
  385. &adcx140_dapm_ch3_dre_en_switch),
  386. SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
  387. &adcx140_dapm_ch4_dre_en_switch),
  388. SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
  389. in1_resistor_controls),
  390. SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
  391. in2_resistor_controls),
  392. SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
  393. in3_resistor_controls),
  394. SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
  395. in4_resistor_controls),
  396. SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
  397. pdmclk_div_controls),
  398. SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
  399. decimation_filter_controls),
  400. };
  401. static const struct snd_soc_dapm_route adcx140_audio_map[] = {
  402. /* Outputs */
  403. {"CH1_OUT", NULL, "Output Mixer"},
  404. {"CH2_OUT", NULL, "Output Mixer"},
  405. {"CH3_OUT", NULL, "Output Mixer"},
  406. {"CH4_OUT", NULL, "Output Mixer"},
  407. {"CH1_ASI_EN", "Switch", "CH1_ADC"},
  408. {"CH2_ASI_EN", "Switch", "CH2_ADC"},
  409. {"CH3_ASI_EN", "Switch", "CH3_ADC"},
  410. {"CH4_ASI_EN", "Switch", "CH4_ADC"},
  411. {"CH1_ASI_EN", "Switch", "CH1_DIG"},
  412. {"CH2_ASI_EN", "Switch", "CH2_DIG"},
  413. {"CH3_ASI_EN", "Switch", "CH3_DIG"},
  414. {"CH4_ASI_EN", "Switch", "CH4_DIG"},
  415. {"CH5_ASI_EN", "Switch", "CH5_DIG"},
  416. {"CH6_ASI_EN", "Switch", "CH6_DIG"},
  417. {"CH7_ASI_EN", "Switch", "CH7_DIG"},
  418. {"CH8_ASI_EN", "Switch", "CH8_DIG"},
  419. {"CH5_ASI_EN", "Switch", "CH5_OUT"},
  420. {"CH6_ASI_EN", "Switch", "CH6_OUT"},
  421. {"CH7_ASI_EN", "Switch", "CH7_OUT"},
  422. {"CH8_ASI_EN", "Switch", "CH8_OUT"},
  423. {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
  424. {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
  425. {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
  426. {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
  427. {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
  428. {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
  429. {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
  430. {"CH1_DRE_EN", "Switch", "CH1_ADC"},
  431. {"CH2_DRE_EN", "Switch", "CH2_ADC"},
  432. {"CH3_DRE_EN", "Switch", "CH3_ADC"},
  433. {"CH4_DRE_EN", "Switch", "CH4_ADC"},
  434. /* Mic input */
  435. {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
  436. {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
  437. {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
  438. {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
  439. {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
  440. {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
  441. {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
  442. {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
  443. {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
  444. {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
  445. {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
  446. {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
  447. {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
  448. {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
  449. {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
  450. {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
  451. {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
  452. {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
  453. {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
  454. {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
  455. {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
  456. {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
  457. {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
  458. {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
  459. {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
  460. {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
  461. {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
  462. {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
  463. {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
  464. {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
  465. {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
  466. {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
  467. {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
  468. {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
  469. {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
  470. {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
  471. {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
  472. {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
  473. {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
  474. {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
  475. {"MIC1P Input Mux", NULL, "CH1_DIG"},
  476. {"MIC1M Input Mux", NULL, "CH2_DIG"},
  477. {"MIC2P Input Mux", NULL, "CH3_DIG"},
  478. {"MIC2M Input Mux", NULL, "CH4_DIG"},
  479. {"MIC3P Input Mux", NULL, "CH5_DIG"},
  480. {"MIC3M Input Mux", NULL, "CH6_DIG"},
  481. {"MIC4P Input Mux", NULL, "CH7_DIG"},
  482. {"MIC4M Input Mux", NULL, "CH8_DIG"},
  483. {"MIC1 Analog Mux", "Line In", "MIC1P"},
  484. {"MIC2 Analog Mux", "Line In", "MIC2P"},
  485. {"MIC3 Analog Mux", "Line In", "MIC3P"},
  486. {"MIC4 Analog Mux", "Line In", "MIC4P"},
  487. {"MIC1P Input Mux", "Analog", "MIC1P"},
  488. {"MIC1M Input Mux", "Analog", "MIC1M"},
  489. {"MIC2P Input Mux", "Analog", "MIC2P"},
  490. {"MIC2M Input Mux", "Analog", "MIC2M"},
  491. {"MIC3P Input Mux", "Analog", "MIC3P"},
  492. {"MIC3M Input Mux", "Analog", "MIC3M"},
  493. {"MIC4P Input Mux", "Analog", "MIC4P"},
  494. {"MIC4M Input Mux", "Analog", "MIC4M"},
  495. {"MIC1P Input Mux", "Digital", "MIC1P"},
  496. {"MIC1M Input Mux", "Digital", "MIC1M"},
  497. {"MIC2P Input Mux", "Digital", "MIC2P"},
  498. {"MIC2M Input Mux", "Digital", "MIC2M"},
  499. {"MIC3P Input Mux", "Digital", "MIC3P"},
  500. {"MIC3M Input Mux", "Digital", "MIC3M"},
  501. {"MIC4P Input Mux", "Digital", "MIC4P"},
  502. {"MIC4M Input Mux", "Digital", "MIC4M"},
  503. };
  504. static const struct snd_kcontrol_new adcx140_snd_controls[] = {
  505. SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
  506. adc_tlv),
  507. SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
  508. adc_tlv),
  509. SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
  510. adc_tlv),
  511. SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
  512. adc_tlv),
  513. SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
  514. dre_thresh_tlv),
  515. SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
  516. dre_gain_tlv),
  517. SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
  518. agc_thresh_tlv),
  519. SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
  520. agc_gain_tlv),
  521. SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
  522. 0, 0xff, 0, dig_vol_tlv),
  523. SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
  524. 0, 0xff, 0, dig_vol_tlv),
  525. SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
  526. 0, 0xff, 0, dig_vol_tlv),
  527. SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
  528. 0, 0xff, 0, dig_vol_tlv),
  529. SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
  530. 0, 0xff, 0, dig_vol_tlv),
  531. SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
  532. 0, 0xff, 0, dig_vol_tlv),
  533. SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
  534. 0, 0xff, 0, dig_vol_tlv),
  535. SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
  536. 0, 0xff, 0, dig_vol_tlv),
  537. };
  538. static int adcx140_reset(struct adcx140_priv *adcx140)
  539. {
  540. int ret = 0;
  541. if (adcx140->gpio_reset) {
  542. gpiod_direction_output(adcx140->gpio_reset, 0);
  543. /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
  544. usleep_range(30000, 100000);
  545. gpiod_direction_output(adcx140->gpio_reset, 1);
  546. } else {
  547. ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
  548. ADCX140_RESET);
  549. }
  550. /* 8.4.2: wait >= 10 ms after entering sleep mode. */
  551. usleep_range(10000, 100000);
  552. return ret;
  553. }
  554. static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
  555. {
  556. int pwr_ctrl = 0;
  557. if (power_state)
  558. pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
  559. if (adcx140->micbias_vg && power_state)
  560. pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
  561. regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
  562. ADCX140_PWR_CTRL_MSK, pwr_ctrl);
  563. }
  564. static int adcx140_hw_params(struct snd_pcm_substream *substream,
  565. struct snd_pcm_hw_params *params,
  566. struct snd_soc_dai *dai)
  567. {
  568. struct snd_soc_component *component = dai->component;
  569. struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
  570. u8 data = 0;
  571. switch (params_width(params)) {
  572. case 16:
  573. data = ADCX140_16_BIT_WORD;
  574. break;
  575. case 20:
  576. data = ADCX140_20_BIT_WORD;
  577. break;
  578. case 24:
  579. data = ADCX140_24_BIT_WORD;
  580. break;
  581. case 32:
  582. data = ADCX140_32_BIT_WORD;
  583. break;
  584. default:
  585. dev_err(component->dev, "%s: Unsupported width %d\n",
  586. __func__, params_width(params));
  587. return -EINVAL;
  588. }
  589. adcx140_pwr_ctrl(adcx140, false);
  590. snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
  591. ADCX140_WORD_LEN_MSK, data);
  592. adcx140_pwr_ctrl(adcx140, true);
  593. return 0;
  594. }
  595. static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
  596. unsigned int fmt)
  597. {
  598. struct snd_soc_component *component = codec_dai->component;
  599. struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
  600. u8 iface_reg1 = 0;
  601. u8 iface_reg2 = 0;
  602. int offset = 0;
  603. bool inverted_bclk = false;
  604. /* set master/slave audio interface */
  605. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  606. case SND_SOC_DAIFMT_CBM_CFM:
  607. iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
  608. break;
  609. case SND_SOC_DAIFMT_CBS_CFS:
  610. break;
  611. case SND_SOC_DAIFMT_CBS_CFM:
  612. case SND_SOC_DAIFMT_CBM_CFS:
  613. default:
  614. dev_err(component->dev, "Invalid DAI master/slave interface\n");
  615. return -EINVAL;
  616. }
  617. /* interface format */
  618. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  619. case SND_SOC_DAIFMT_I2S:
  620. iface_reg1 |= ADCX140_I2S_MODE_BIT;
  621. break;
  622. case SND_SOC_DAIFMT_LEFT_J:
  623. iface_reg1 |= ADCX140_LEFT_JUST_BIT;
  624. break;
  625. case SND_SOC_DAIFMT_DSP_A:
  626. offset = 1;
  627. inverted_bclk = true;
  628. break;
  629. case SND_SOC_DAIFMT_DSP_B:
  630. inverted_bclk = true;
  631. break;
  632. default:
  633. dev_err(component->dev, "Invalid DAI interface format\n");
  634. return -EINVAL;
  635. }
  636. /* signal polarity */
  637. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  638. case SND_SOC_DAIFMT_IB_NF:
  639. case SND_SOC_DAIFMT_IB_IF:
  640. inverted_bclk = !inverted_bclk;
  641. break;
  642. case SND_SOC_DAIFMT_NB_IF:
  643. iface_reg1 |= ADCX140_FSYNCINV_BIT;
  644. break;
  645. case SND_SOC_DAIFMT_NB_NF:
  646. break;
  647. default:
  648. dev_err(component->dev, "Invalid DAI clock signal polarity\n");
  649. return -EINVAL;
  650. }
  651. if (inverted_bclk)
  652. iface_reg1 |= ADCX140_BCLKINV_BIT;
  653. adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  654. adcx140_pwr_ctrl(adcx140, false);
  655. snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
  656. ADCX140_FSYNCINV_BIT |
  657. ADCX140_BCLKINV_BIT |
  658. ADCX140_ASI_FORMAT_MSK,
  659. iface_reg1);
  660. snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
  661. ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
  662. /* Configure data offset */
  663. snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
  664. ADCX140_TX_OFFSET_MASK, offset);
  665. adcx140_pwr_ctrl(adcx140, true);
  666. return 0;
  667. }
  668. static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
  669. unsigned int tx_mask, unsigned int rx_mask,
  670. int slots, int slot_width)
  671. {
  672. struct snd_soc_component *component = codec_dai->component;
  673. struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
  674. unsigned int lsb;
  675. /* TDM based on DSP mode requires slots to be adjacent */
  676. lsb = __ffs(tx_mask);
  677. if ((lsb + 1) != __fls(tx_mask)) {
  678. dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
  679. return -EINVAL;
  680. }
  681. switch (slot_width) {
  682. case 16:
  683. case 20:
  684. case 24:
  685. case 32:
  686. break;
  687. default:
  688. dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
  689. return -EINVAL;
  690. }
  691. adcx140->tdm_delay = lsb;
  692. adcx140->slot_width = slot_width;
  693. return 0;
  694. }
  695. static const struct snd_soc_dai_ops adcx140_dai_ops = {
  696. .hw_params = adcx140_hw_params,
  697. .set_fmt = adcx140_set_dai_fmt,
  698. .set_tdm_slot = adcx140_set_dai_tdm_slot,
  699. };
  700. static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
  701. {
  702. u32 gpo_outputs[ADCX140_NUM_GPOS];
  703. u32 gpo_output_val = 0;
  704. int ret;
  705. int i;
  706. for (i = 0; i < ADCX140_NUM_GPOS; i++) {
  707. ret = device_property_read_u32_array(adcx140->dev,
  708. gpo_config_names[i],
  709. gpo_outputs,
  710. ADCX140_NUM_GPO_CFGS);
  711. if (ret)
  712. continue;
  713. if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
  714. dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
  715. return -EINVAL;
  716. }
  717. if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
  718. dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
  719. return -EINVAL;
  720. }
  721. gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
  722. gpo_outputs[1];
  723. ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
  724. gpo_output_val);
  725. if (ret)
  726. return ret;
  727. }
  728. return 0;
  729. }
  730. static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
  731. {
  732. int gpio_count = 0;
  733. u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
  734. u32 gpio_output_val = 0;
  735. int ret;
  736. gpio_count = device_property_count_u32(adcx140->dev,
  737. "ti,gpio-config");
  738. if (gpio_count == 0)
  739. return 0;
  740. if (gpio_count != ADCX140_NUM_GPIO_CFGS)
  741. return -EINVAL;
  742. ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
  743. gpio_outputs, gpio_count);
  744. if (ret)
  745. return ret;
  746. if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
  747. dev_err(adcx140->dev, "GPIO config out of range\n");
  748. return -EINVAL;
  749. }
  750. if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
  751. dev_err(adcx140->dev, "GPIO drive out of range\n");
  752. return -EINVAL;
  753. }
  754. gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
  755. | gpio_outputs[1];
  756. return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
  757. }
  758. static int adcx140_codec_probe(struct snd_soc_component *component)
  759. {
  760. struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
  761. int sleep_cfg_val = ADCX140_WAKE_DEV;
  762. u32 bias_source;
  763. u32 vref_source;
  764. u8 bias_cfg;
  765. int pdm_count;
  766. u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
  767. u32 pdm_edge_val = 0;
  768. int gpi_count;
  769. u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
  770. u32 gpi_input_val = 0;
  771. int i;
  772. int ret;
  773. bool tx_high_z;
  774. ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
  775. &bias_source);
  776. if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
  777. bias_source = ADCX140_MIC_BIAS_VAL_VREF;
  778. adcx140->micbias_vg = false;
  779. } else {
  780. adcx140->micbias_vg = true;
  781. }
  782. ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
  783. &vref_source);
  784. if (ret)
  785. vref_source = ADCX140_MIC_BIAS_VREF_275V;
  786. if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
  787. dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
  788. return -EINVAL;
  789. }
  790. bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
  791. ret = adcx140_reset(adcx140);
  792. if (ret)
  793. goto out;
  794. if (adcx140->supply_areg == NULL)
  795. sleep_cfg_val |= ADCX140_AREG_INTERNAL;
  796. ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
  797. if (ret) {
  798. dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
  799. goto out;
  800. }
  801. /* 8.4.3: Wait >= 1ms after entering active mode. */
  802. usleep_range(1000, 100000);
  803. pdm_count = device_property_count_u32(adcx140->dev,
  804. "ti,pdm-edge-select");
  805. if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
  806. ret = device_property_read_u32_array(adcx140->dev,
  807. "ti,pdm-edge-select",
  808. pdm_edges, pdm_count);
  809. if (ret)
  810. return ret;
  811. for (i = 0; i < pdm_count; i++)
  812. pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
  813. ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
  814. pdm_edge_val);
  815. if (ret)
  816. return ret;
  817. }
  818. gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
  819. if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
  820. ret = device_property_read_u32_array(adcx140->dev,
  821. "ti,gpi-config",
  822. gpi_inputs, gpi_count);
  823. if (ret)
  824. return ret;
  825. gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
  826. gpi_inputs[ADCX140_GPI2_INDEX];
  827. ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
  828. gpi_input_val);
  829. if (ret)
  830. return ret;
  831. gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
  832. gpi_inputs[ADCX140_GPI4_INDEX];
  833. ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
  834. gpi_input_val);
  835. if (ret)
  836. return ret;
  837. }
  838. ret = adcx140_configure_gpio(adcx140);
  839. if (ret)
  840. return ret;
  841. ret = adcx140_configure_gpo(adcx140);
  842. if (ret)
  843. goto out;
  844. ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
  845. ADCX140_MIC_BIAS_VAL_MSK |
  846. ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
  847. if (ret)
  848. dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
  849. tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
  850. if (tx_high_z) {
  851. ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
  852. ADCX140_TX_FILL, ADCX140_TX_FILL);
  853. if (ret) {
  854. dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
  855. goto out;
  856. }
  857. }
  858. adcx140_pwr_ctrl(adcx140, true);
  859. out:
  860. return ret;
  861. }
  862. static int adcx140_set_bias_level(struct snd_soc_component *component,
  863. enum snd_soc_bias_level level)
  864. {
  865. struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
  866. switch (level) {
  867. case SND_SOC_BIAS_ON:
  868. case SND_SOC_BIAS_PREPARE:
  869. case SND_SOC_BIAS_STANDBY:
  870. adcx140_pwr_ctrl(adcx140, true);
  871. break;
  872. case SND_SOC_BIAS_OFF:
  873. adcx140_pwr_ctrl(adcx140, false);
  874. break;
  875. }
  876. return 0;
  877. }
  878. static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
  879. .probe = adcx140_codec_probe,
  880. .set_bias_level = adcx140_set_bias_level,
  881. .controls = adcx140_snd_controls,
  882. .num_controls = ARRAY_SIZE(adcx140_snd_controls),
  883. .dapm_widgets = adcx140_dapm_widgets,
  884. .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
  885. .dapm_routes = adcx140_audio_map,
  886. .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
  887. .suspend_bias_off = 1,
  888. .idle_bias_on = 0,
  889. .use_pmdown_time = 1,
  890. .endianness = 1,
  891. .non_legacy_dai_naming = 1,
  892. };
  893. static struct snd_soc_dai_driver adcx140_dai_driver[] = {
  894. {
  895. .name = "tlv320adcx140-codec",
  896. .capture = {
  897. .stream_name = "Capture",
  898. .channels_min = 2,
  899. .channels_max = ADCX140_MAX_CHANNELS,
  900. .rates = ADCX140_RATES,
  901. .formats = ADCX140_FORMATS,
  902. },
  903. .ops = &adcx140_dai_ops,
  904. .symmetric_rates = 1,
  905. }
  906. };
  907. static const struct of_device_id tlv320adcx140_of_match[] = {
  908. { .compatible = "ti,tlv320adc3140" },
  909. { .compatible = "ti,tlv320adc5140" },
  910. { .compatible = "ti,tlv320adc6140" },
  911. {},
  912. };
  913. MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
  914. static int adcx140_i2c_probe(struct i2c_client *i2c,
  915. const struct i2c_device_id *id)
  916. {
  917. struct adcx140_priv *adcx140;
  918. int ret;
  919. adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
  920. if (!adcx140)
  921. return -ENOMEM;
  922. adcx140->dev = &i2c->dev;
  923. adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
  924. "reset", GPIOD_OUT_LOW);
  925. if (IS_ERR(adcx140->gpio_reset))
  926. dev_info(&i2c->dev, "Reset GPIO not defined\n");
  927. adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
  928. "areg");
  929. if (IS_ERR(adcx140->supply_areg)) {
  930. if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
  931. return -EPROBE_DEFER;
  932. adcx140->supply_areg = NULL;
  933. } else {
  934. ret = regulator_enable(adcx140->supply_areg);
  935. if (ret) {
  936. dev_err(adcx140->dev, "Failed to enable areg\n");
  937. return ret;
  938. }
  939. }
  940. adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
  941. if (IS_ERR(adcx140->regmap)) {
  942. ret = PTR_ERR(adcx140->regmap);
  943. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  944. ret);
  945. return ret;
  946. }
  947. i2c_set_clientdata(i2c, adcx140);
  948. return devm_snd_soc_register_component(&i2c->dev,
  949. &soc_codec_driver_adcx140,
  950. adcx140_dai_driver, 1);
  951. }
  952. static const struct i2c_device_id adcx140_i2c_id[] = {
  953. { "tlv320adc3140", 0 },
  954. { "tlv320adc5140", 1 },
  955. { "tlv320adc6140", 2 },
  956. {}
  957. };
  958. MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
  959. static struct i2c_driver adcx140_i2c_driver = {
  960. .driver = {
  961. .name = "tlv320adcx140-codec",
  962. .of_match_table = of_match_ptr(tlv320adcx140_of_match),
  963. },
  964. .probe = adcx140_i2c_probe,
  965. .id_table = adcx140_i2c_id,
  966. };
  967. module_i2c_driver(adcx140_i2c_driver);
  968. MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
  969. MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
  970. MODULE_LICENSE("GPL v2");