tas2764.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Driver for the Texas Instruments TAS2764 CODEC
  4. // Copyright (C) 2020 Texas Instruments Inc.
  5. #include <linux/module.h>
  6. #include <linux/moduleparam.h>
  7. #include <linux/err.h>
  8. #include <linux/init.h>
  9. #include <linux/delay.h>
  10. #include <linux/pm.h>
  11. #include <linux/i2c.h>
  12. #include <linux/gpio.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/regmap.h>
  16. #include <linux/of.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/slab.h>
  19. #include <sound/soc.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/initval.h>
  23. #include <sound/tlv.h>
  24. #include "tas2764.h"
  25. struct tas2764_priv {
  26. struct snd_soc_component *component;
  27. struct gpio_desc *reset_gpio;
  28. struct gpio_desc *sdz_gpio;
  29. struct regmap *regmap;
  30. struct device *dev;
  31. int v_sense_slot;
  32. int i_sense_slot;
  33. };
  34. static void tas2764_reset(struct tas2764_priv *tas2764)
  35. {
  36. if (tas2764->reset_gpio) {
  37. gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
  38. msleep(20);
  39. gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
  40. }
  41. snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
  42. TAS2764_RST);
  43. }
  44. static int tas2764_set_bias_level(struct snd_soc_component *component,
  45. enum snd_soc_bias_level level)
  46. {
  47. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  48. switch (level) {
  49. case SND_SOC_BIAS_ON:
  50. snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  51. TAS2764_PWR_CTRL_MASK,
  52. TAS2764_PWR_CTRL_ACTIVE);
  53. break;
  54. case SND_SOC_BIAS_STANDBY:
  55. case SND_SOC_BIAS_PREPARE:
  56. snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  57. TAS2764_PWR_CTRL_MASK,
  58. TAS2764_PWR_CTRL_MUTE);
  59. break;
  60. case SND_SOC_BIAS_OFF:
  61. snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  62. TAS2764_PWR_CTRL_MASK,
  63. TAS2764_PWR_CTRL_SHUTDOWN);
  64. break;
  65. default:
  66. dev_err(tas2764->dev,
  67. "wrong power level setting %d\n", level);
  68. return -EINVAL;
  69. }
  70. return 0;
  71. }
  72. #ifdef CONFIG_PM
  73. static int tas2764_codec_suspend(struct snd_soc_component *component)
  74. {
  75. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  76. int ret;
  77. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  78. TAS2764_PWR_CTRL_MASK,
  79. TAS2764_PWR_CTRL_SHUTDOWN);
  80. if (ret < 0)
  81. return ret;
  82. if (tas2764->sdz_gpio)
  83. gpiod_set_value_cansleep(tas2764->sdz_gpio, 0);
  84. regcache_cache_only(tas2764->regmap, true);
  85. regcache_mark_dirty(tas2764->regmap);
  86. return 0;
  87. }
  88. static int tas2764_codec_resume(struct snd_soc_component *component)
  89. {
  90. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  91. int ret;
  92. if (tas2764->sdz_gpio)
  93. gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
  94. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  95. TAS2764_PWR_CTRL_MASK,
  96. TAS2764_PWR_CTRL_ACTIVE);
  97. if (ret < 0)
  98. return ret;
  99. regcache_cache_only(tas2764->regmap, false);
  100. return regcache_sync(tas2764->regmap);
  101. }
  102. #else
  103. #define tas2764_codec_suspend NULL
  104. #define tas2764_codec_resume NULL
  105. #endif
  106. static const char * const tas2764_ASI1_src[] = {
  107. "I2C offset", "Left", "Right", "LeftRightDiv2",
  108. };
  109. static SOC_ENUM_SINGLE_DECL(
  110. tas2764_ASI1_src_enum, TAS2764_TDM_CFG2, 4, tas2764_ASI1_src);
  111. static const struct snd_kcontrol_new tas2764_asi1_mux =
  112. SOC_DAPM_ENUM("ASI1 Source", tas2764_ASI1_src_enum);
  113. static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
  114. struct snd_kcontrol *kcontrol, int event)
  115. {
  116. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  117. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  118. int ret;
  119. switch (event) {
  120. case SND_SOC_DAPM_POST_PMU:
  121. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  122. TAS2764_PWR_CTRL_MASK,
  123. TAS2764_PWR_CTRL_MUTE);
  124. break;
  125. case SND_SOC_DAPM_PRE_PMD:
  126. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  127. TAS2764_PWR_CTRL_MASK,
  128. TAS2764_PWR_CTRL_SHUTDOWN);
  129. break;
  130. default:
  131. dev_err(tas2764->dev, "Unsupported event\n");
  132. return -EINVAL;
  133. }
  134. if (ret < 0)
  135. return ret;
  136. return 0;
  137. }
  138. static const struct snd_kcontrol_new isense_switch =
  139. SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN, 1, 1);
  140. static const struct snd_kcontrol_new vsense_switch =
  141. SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN, 1, 1);
  142. static const struct snd_soc_dapm_widget tas2764_dapm_widgets[] = {
  143. SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
  144. SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2764_asi1_mux),
  145. SND_SOC_DAPM_SWITCH("ISENSE", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN,
  146. 1, &isense_switch),
  147. SND_SOC_DAPM_SWITCH("VSENSE", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN,
  148. 1, &vsense_switch),
  149. SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2764_dac_event,
  150. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  151. SND_SOC_DAPM_OUTPUT("OUT"),
  152. SND_SOC_DAPM_SIGGEN("VMON"),
  153. SND_SOC_DAPM_SIGGEN("IMON")
  154. };
  155. static const struct snd_soc_dapm_route tas2764_audio_map[] = {
  156. {"ASI1 Sel", "I2C offset", "ASI1"},
  157. {"ASI1 Sel", "Left", "ASI1"},
  158. {"ASI1 Sel", "Right", "ASI1"},
  159. {"ASI1 Sel", "LeftRightDiv2", "ASI1"},
  160. {"DAC", NULL, "ASI1 Sel"},
  161. {"OUT", NULL, "DAC"},
  162. {"ISENSE", "Switch", "IMON"},
  163. {"VSENSE", "Switch", "VMON"},
  164. };
  165. static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
  166. {
  167. struct snd_soc_component *component = dai->component;
  168. int ret;
  169. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  170. TAS2764_PWR_CTRL_MASK,
  171. mute ? TAS2764_PWR_CTRL_MUTE : 0);
  172. if (ret < 0)
  173. return ret;
  174. return 0;
  175. }
  176. static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
  177. {
  178. struct snd_soc_component *component = tas2764->component;
  179. int sense_en;
  180. int val;
  181. int ret;
  182. switch (bitwidth) {
  183. case SNDRV_PCM_FORMAT_S16_LE:
  184. ret = snd_soc_component_update_bits(component,
  185. TAS2764_TDM_CFG2,
  186. TAS2764_TDM_CFG2_RXW_MASK,
  187. TAS2764_TDM_CFG2_RXW_16BITS);
  188. break;
  189. case SNDRV_PCM_FORMAT_S24_LE:
  190. ret = snd_soc_component_update_bits(component,
  191. TAS2764_TDM_CFG2,
  192. TAS2764_TDM_CFG2_RXW_MASK,
  193. TAS2764_TDM_CFG2_RXW_24BITS);
  194. break;
  195. case SNDRV_PCM_FORMAT_S32_LE:
  196. ret = snd_soc_component_update_bits(component,
  197. TAS2764_TDM_CFG2,
  198. TAS2764_TDM_CFG2_RXW_MASK,
  199. TAS2764_TDM_CFG2_RXW_32BITS);
  200. break;
  201. default:
  202. return -EINVAL;
  203. }
  204. if (ret < 0)
  205. return ret;
  206. val = snd_soc_component_read(tas2764->component, TAS2764_PWR_CTRL);
  207. if (val < 0)
  208. return val;
  209. if (val & (1 << TAS2764_VSENSE_POWER_EN))
  210. sense_en = 0;
  211. else
  212. sense_en = TAS2764_TDM_CFG5_VSNS_ENABLE;
  213. ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
  214. TAS2764_TDM_CFG5_VSNS_ENABLE,
  215. sense_en);
  216. if (ret < 0)
  217. return ret;
  218. if (val & (1 << TAS2764_ISENSE_POWER_EN))
  219. sense_en = 0;
  220. else
  221. sense_en = TAS2764_TDM_CFG6_ISNS_ENABLE;
  222. ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
  223. TAS2764_TDM_CFG6_ISNS_ENABLE,
  224. sense_en);
  225. if (ret < 0)
  226. return ret;
  227. return 0;
  228. }
  229. static int tas2764_set_samplerate(struct tas2764_priv *tas2764, int samplerate)
  230. {
  231. struct snd_soc_component *component = tas2764->component;
  232. int ramp_rate_val;
  233. int ret;
  234. switch (samplerate) {
  235. case 48000:
  236. ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
  237. TAS2764_TDM_CFG0_44_1_48KHZ;
  238. break;
  239. case 44100:
  240. ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
  241. TAS2764_TDM_CFG0_44_1_48KHZ;
  242. break;
  243. case 96000:
  244. ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
  245. TAS2764_TDM_CFG0_88_2_96KHZ;
  246. break;
  247. case 88200:
  248. ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
  249. TAS2764_TDM_CFG0_88_2_96KHZ;
  250. break;
  251. default:
  252. return -EINVAL;
  253. }
  254. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0,
  255. TAS2764_TDM_CFG0_SMP_MASK |
  256. TAS2764_TDM_CFG0_MASK,
  257. ramp_rate_val);
  258. if (ret < 0)
  259. return ret;
  260. return 0;
  261. }
  262. static int tas2764_hw_params(struct snd_pcm_substream *substream,
  263. struct snd_pcm_hw_params *params,
  264. struct snd_soc_dai *dai)
  265. {
  266. struct snd_soc_component *component = dai->component;
  267. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  268. int ret;
  269. ret = tas2764_set_bitwidth(tas2764, params_format(params));
  270. if (ret < 0)
  271. return ret;
  272. return tas2764_set_samplerate(tas2764, params_rate(params));
  273. }
  274. static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  275. {
  276. struct snd_soc_component *component = dai->component;
  277. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  278. u8 tdm_rx_start_slot = 0, asi_cfg_1 = 0;
  279. int iface;
  280. int ret;
  281. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  282. case SND_SOC_DAIFMT_NB_NF:
  283. asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING;
  284. break;
  285. case SND_SOC_DAIFMT_IB_NF:
  286. asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING;
  287. break;
  288. default:
  289. dev_err(tas2764->dev, "ASI format Inverse is not found\n");
  290. return -EINVAL;
  291. }
  292. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
  293. TAS2764_TDM_CFG1_RX_MASK,
  294. asi_cfg_1);
  295. if (ret < 0)
  296. return ret;
  297. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  298. case SND_SOC_DAIFMT_I2S:
  299. case SND_SOC_DAIFMT_DSP_A:
  300. iface = TAS2764_TDM_CFG2_SCFG_I2S;
  301. tdm_rx_start_slot = 1;
  302. break;
  303. case SND_SOC_DAIFMT_DSP_B:
  304. case SND_SOC_DAIFMT_LEFT_J:
  305. iface = TAS2764_TDM_CFG2_SCFG_LEFT_J;
  306. tdm_rx_start_slot = 0;
  307. break;
  308. default:
  309. dev_err(tas2764->dev,
  310. "DAI Format is not found, fmt=0x%x\n", fmt);
  311. return -EINVAL;
  312. }
  313. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
  314. TAS2764_TDM_CFG1_MASK,
  315. (tdm_rx_start_slot << TAS2764_TDM_CFG1_51_SHIFT));
  316. if (ret < 0)
  317. return ret;
  318. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG2,
  319. TAS2764_TDM_CFG2_SCFG_MASK, iface);
  320. if (ret < 0)
  321. return ret;
  322. return 0;
  323. }
  324. static int tas2764_set_dai_tdm_slot(struct snd_soc_dai *dai,
  325. unsigned int tx_mask,
  326. unsigned int rx_mask,
  327. int slots, int slot_width)
  328. {
  329. struct snd_soc_component *component = dai->component;
  330. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  331. int left_slot, right_slot;
  332. int slots_cfg;
  333. int slot_size;
  334. int ret;
  335. if (tx_mask == 0 || rx_mask != 0)
  336. return -EINVAL;
  337. if (slots == 1) {
  338. if (tx_mask != 1)
  339. return -EINVAL;
  340. left_slot = 0;
  341. right_slot = 0;
  342. } else {
  343. left_slot = __ffs(tx_mask);
  344. tx_mask &= ~(1 << left_slot);
  345. if (tx_mask == 0) {
  346. right_slot = left_slot;
  347. } else {
  348. right_slot = __ffs(tx_mask);
  349. tx_mask &= ~(1 << right_slot);
  350. }
  351. }
  352. if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
  353. return -EINVAL;
  354. slots_cfg = (right_slot << TAS2764_TDM_CFG3_RXS_SHIFT) | left_slot;
  355. ret = snd_soc_component_write(component, TAS2764_TDM_CFG3, slots_cfg);
  356. if (ret)
  357. return ret;
  358. switch (slot_width) {
  359. case 16:
  360. slot_size = TAS2764_TDM_CFG2_RXS_16BITS;
  361. break;
  362. case 24:
  363. slot_size = TAS2764_TDM_CFG2_RXS_24BITS;
  364. break;
  365. case 32:
  366. slot_size = TAS2764_TDM_CFG2_RXS_32BITS;
  367. break;
  368. default:
  369. return -EINVAL;
  370. }
  371. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG2,
  372. TAS2764_TDM_CFG2_RXS_MASK,
  373. slot_size);
  374. if (ret < 0)
  375. return ret;
  376. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG5,
  377. TAS2764_TDM_CFG5_50_MASK,
  378. tas2764->v_sense_slot);
  379. if (ret < 0)
  380. return ret;
  381. ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG6,
  382. TAS2764_TDM_CFG6_50_MASK,
  383. tas2764->i_sense_slot);
  384. if (ret < 0)
  385. return ret;
  386. return 0;
  387. }
  388. static struct snd_soc_dai_ops tas2764_dai_ops = {
  389. .mute_stream = tas2764_mute,
  390. .hw_params = tas2764_hw_params,
  391. .set_fmt = tas2764_set_fmt,
  392. .set_tdm_slot = tas2764_set_dai_tdm_slot,
  393. .no_capture_mute = 1,
  394. };
  395. #define TAS2764_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  396. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  397. #define TAS2764_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  398. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200)
  399. static struct snd_soc_dai_driver tas2764_dai_driver[] = {
  400. {
  401. .name = "tas2764 ASI1",
  402. .id = 0,
  403. .playback = {
  404. .stream_name = "ASI1 Playback",
  405. .channels_min = 2,
  406. .channels_max = 2,
  407. .rates = TAS2764_RATES,
  408. .formats = TAS2764_FORMATS,
  409. },
  410. .capture = {
  411. .stream_name = "ASI1 Capture",
  412. .channels_min = 0,
  413. .channels_max = 2,
  414. .rates = TAS2764_RATES,
  415. .formats = TAS2764_FORMATS,
  416. },
  417. .ops = &tas2764_dai_ops,
  418. .symmetric_rates = 1,
  419. },
  420. };
  421. static int tas2764_codec_probe(struct snd_soc_component *component)
  422. {
  423. struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
  424. int ret;
  425. tas2764->component = component;
  426. if (tas2764->sdz_gpio)
  427. gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
  428. tas2764_reset(tas2764);
  429. ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
  430. TAS2764_TDM_CFG5_VSNS_ENABLE, 0);
  431. if (ret < 0)
  432. return ret;
  433. ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
  434. TAS2764_TDM_CFG6_ISNS_ENABLE, 0);
  435. if (ret < 0)
  436. return ret;
  437. ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
  438. TAS2764_PWR_CTRL_MASK,
  439. TAS2764_PWR_CTRL_MUTE);
  440. if (ret < 0)
  441. return ret;
  442. return 0;
  443. }
  444. static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0);
  445. static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10000, 50, 0);
  446. static const struct snd_kcontrol_new tas2764_snd_controls[] = {
  447. SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0,
  448. TAS2764_DVC_MAX, 1, tas2764_playback_volume),
  449. SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 0, 0x14, 0,
  450. tas2764_digital_tlv),
  451. };
  452. static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
  453. .probe = tas2764_codec_probe,
  454. .suspend = tas2764_codec_suspend,
  455. .resume = tas2764_codec_resume,
  456. .set_bias_level = tas2764_set_bias_level,
  457. .controls = tas2764_snd_controls,
  458. .num_controls = ARRAY_SIZE(tas2764_snd_controls),
  459. .dapm_widgets = tas2764_dapm_widgets,
  460. .num_dapm_widgets = ARRAY_SIZE(tas2764_dapm_widgets),
  461. .dapm_routes = tas2764_audio_map,
  462. .num_dapm_routes = ARRAY_SIZE(tas2764_audio_map),
  463. .idle_bias_on = 1,
  464. .endianness = 1,
  465. .non_legacy_dai_naming = 1,
  466. };
  467. static const struct reg_default tas2764_reg_defaults[] = {
  468. { TAS2764_PAGE, 0x00 },
  469. { TAS2764_SW_RST, 0x00 },
  470. { TAS2764_PWR_CTRL, 0x1a },
  471. { TAS2764_DVC, 0x00 },
  472. { TAS2764_CHNL_0, 0x00 },
  473. { TAS2764_TDM_CFG0, 0x09 },
  474. { TAS2764_TDM_CFG1, 0x02 },
  475. { TAS2764_TDM_CFG2, 0x0a },
  476. { TAS2764_TDM_CFG3, 0x10 },
  477. { TAS2764_TDM_CFG5, 0x42 },
  478. };
  479. static const struct regmap_range_cfg tas2764_regmap_ranges[] = {
  480. {
  481. .range_min = 0,
  482. .range_max = 1 * 128,
  483. .selector_reg = TAS2764_PAGE,
  484. .selector_mask = 0xff,
  485. .selector_shift = 0,
  486. .window_start = 0,
  487. .window_len = 128,
  488. },
  489. };
  490. static const struct regmap_config tas2764_i2c_regmap = {
  491. .reg_bits = 8,
  492. .val_bits = 8,
  493. .reg_defaults = tas2764_reg_defaults,
  494. .num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults),
  495. .cache_type = REGCACHE_RBTREE,
  496. .ranges = tas2764_regmap_ranges,
  497. .num_ranges = ARRAY_SIZE(tas2764_regmap_ranges),
  498. .max_register = 1 * 128,
  499. };
  500. static int tas2764_parse_dt(struct device *dev, struct tas2764_priv *tas2764)
  501. {
  502. int ret = 0;
  503. tas2764->reset_gpio = devm_gpiod_get_optional(tas2764->dev, "reset",
  504. GPIOD_OUT_HIGH);
  505. if (IS_ERR(tas2764->reset_gpio)) {
  506. if (PTR_ERR(tas2764->reset_gpio) == -EPROBE_DEFER) {
  507. tas2764->reset_gpio = NULL;
  508. return -EPROBE_DEFER;
  509. }
  510. }
  511. tas2764->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
  512. if (IS_ERR(tas2764->sdz_gpio)) {
  513. if (PTR_ERR(tas2764->sdz_gpio) == -EPROBE_DEFER)
  514. return -EPROBE_DEFER;
  515. tas2764->sdz_gpio = NULL;
  516. }
  517. ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
  518. &tas2764->i_sense_slot);
  519. if (ret)
  520. tas2764->i_sense_slot = 0;
  521. ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
  522. &tas2764->v_sense_slot);
  523. if (ret)
  524. tas2764->v_sense_slot = 2;
  525. return 0;
  526. }
  527. static int tas2764_i2c_probe(struct i2c_client *client,
  528. const struct i2c_device_id *id)
  529. {
  530. struct tas2764_priv *tas2764;
  531. int result;
  532. tas2764 = devm_kzalloc(&client->dev, sizeof(struct tas2764_priv),
  533. GFP_KERNEL);
  534. if (!tas2764)
  535. return -ENOMEM;
  536. tas2764->dev = &client->dev;
  537. i2c_set_clientdata(client, tas2764);
  538. dev_set_drvdata(&client->dev, tas2764);
  539. tas2764->regmap = devm_regmap_init_i2c(client, &tas2764_i2c_regmap);
  540. if (IS_ERR(tas2764->regmap)) {
  541. result = PTR_ERR(tas2764->regmap);
  542. dev_err(&client->dev, "Failed to allocate register map: %d\n",
  543. result);
  544. return result;
  545. }
  546. if (client->dev.of_node) {
  547. result = tas2764_parse_dt(&client->dev, tas2764);
  548. if (result) {
  549. dev_err(tas2764->dev, "%s: Failed to parse devicetree\n",
  550. __func__);
  551. return result;
  552. }
  553. }
  554. return devm_snd_soc_register_component(tas2764->dev,
  555. &soc_component_driver_tas2764,
  556. tas2764_dai_driver,
  557. ARRAY_SIZE(tas2764_dai_driver));
  558. }
  559. static const struct i2c_device_id tas2764_i2c_id[] = {
  560. { "tas2764", 0},
  561. { }
  562. };
  563. MODULE_DEVICE_TABLE(i2c, tas2764_i2c_id);
  564. #if defined(CONFIG_OF)
  565. static const struct of_device_id tas2764_of_match[] = {
  566. { .compatible = "ti,tas2764" },
  567. {},
  568. };
  569. MODULE_DEVICE_TABLE(of, tas2764_of_match);
  570. #endif
  571. static struct i2c_driver tas2764_i2c_driver = {
  572. .driver = {
  573. .name = "tas2764",
  574. .of_match_table = of_match_ptr(tas2764_of_match),
  575. },
  576. .probe = tas2764_i2c_probe,
  577. .id_table = tas2764_i2c_id,
  578. };
  579. module_i2c_driver(tas2764_i2c_driver);
  580. MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
  581. MODULE_DESCRIPTION("TAS2764 I2C Smart Amplifier driver");
  582. MODULE_LICENSE("GPL v2");