ssm2602.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * File: sound/soc/codecs/ssm2602.h
  4. * Author: Cliff Cai <Cliff.Cai@analog.com>
  5. *
  6. * Created: Tue June 06 2008
  7. *
  8. * Modified:
  9. * Copyright 2008 Analog Devices Inc.
  10. *
  11. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  12. */
  13. #ifndef _SSM2602_H
  14. #define _SSM2602_H
  15. #include <linux/regmap.h>
  16. struct device;
  17. enum ssm2602_type {
  18. SSM2602,
  19. SSM2604,
  20. };
  21. extern const struct regmap_config ssm2602_regmap_config;
  22. int ssm2602_probe(struct device *dev, enum ssm2602_type type,
  23. struct regmap *regmap);
  24. /* SSM2602 Codec Register definitions */
  25. #define SSM2602_LINVOL 0x00
  26. #define SSM2602_RINVOL 0x01
  27. #define SSM2602_LOUT1V 0x02
  28. #define SSM2602_ROUT1V 0x03
  29. #define SSM2602_APANA 0x04
  30. #define SSM2602_APDIGI 0x05
  31. #define SSM2602_PWR 0x06
  32. #define SSM2602_IFACE 0x07
  33. #define SSM2602_SRATE 0x08
  34. #define SSM2602_ACTIVE 0x09
  35. #define SSM2602_RESET 0x0f
  36. /*SSM2602 Codec Register Field definitions
  37. *(Mask value to extract the corresponding Register field)
  38. */
  39. /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
  40. #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control */
  41. #define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute */
  42. #define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update */
  43. /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
  44. #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control */
  45. #define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute */
  46. #define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update */
  47. /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
  48. #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control */
  49. #define LOUT1V_ENABLE_LZC 0x080 /* Left Channel Zero cross detect enable */
  50. #define LOUT1V_LRHP_BOTH 0x100 /* Left Channel Headphone volume update */
  51. /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
  52. #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control */
  53. #define ROUT1V_ENABLE_RZC 0x080 /* Right Channel Zero cross detect enable */
  54. #define ROUT1V_RLHP_BOTH 0x100 /* Right Channel Headphone volume update */
  55. /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
  56. #define APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */
  57. #define APANA_ENABLE_MIC_MUTE 0x002 /* Microphone Mute Control */
  58. #define APANA_ADC_IN_SELECT 0x004 /* Microphone/Line IN select to ADC (1=MIC, 0=Line In) */
  59. #define APANA_ENABLE_BYPASS 0x008 /* Line input bypass to line output */
  60. #define APANA_SELECT_DAC 0x010 /* Select DAC (1=Select DAC, 0=Don't Select DAC) */
  61. #define APANA_ENABLE_SIDETONE 0x020 /* Enable/Disable Side Tone */
  62. #define APANA_SIDETONE_ATTN 0x0C0 /* Side Tone Attenuation */
  63. #define APANA_ENABLE_MIC_BOOST2 0x100 /* Secondary Microphone Amplifier gain booster control */
  64. /*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/
  65. #define APDIGI_ENABLE_ADC_HPF 0x001 /* Enable/Disable ADC Highpass Filter */
  66. #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control */
  67. #define APDIGI_ENABLE_DAC_MUTE 0x008 /* DAC Mute Control */
  68. #define APDIGI_STORE_OFFSET 0x010 /* Store/Clear DC offset when HPF is disabled */
  69. /*Power Down Control (SSM2602_REG_POWER)
  70. *(1=Enable PowerDown, 0=Disable PowerDown)
  71. */
  72. #define PWR_LINE_IN_PDN 0x001 /* Line Input Power Down */
  73. #define PWR_MIC_PDN 0x002 /* Microphone Input & Bias Power Down */
  74. #define PWR_ADC_PDN 0x004 /* ADC Power Down */
  75. #define PWR_DAC_PDN 0x008 /* DAC Power Down */
  76. #define PWR_OUT_PDN 0x010 /* Outputs Power Down */
  77. #define PWR_OSC_PDN 0x020 /* Oscillator Power Down */
  78. #define PWR_CLK_OUT_PDN 0x040 /* CLKOUT Power Down */
  79. #define PWR_POWER_OFF 0x080 /* POWEROFF Mode */
  80. /*Digital Audio Interface Format (SSM2602_REG_DIGITAL_IFACE)*/
  81. #define IFACE_IFACE_FORMAT 0x003 /* Digital Audio input format control */
  82. #define IFACE_AUDIO_DATA_LEN 0x00C /* Audio Data word length control */
  83. #define IFACE_DAC_LR_POLARITY 0x010 /* Polarity Control for clocks in RJ,LJ and I2S modes */
  84. #define IFACE_DAC_LR_SWAP 0x020 /* Swap DAC data control */
  85. #define IFACE_ENABLE_MASTER 0x040 /* Enable/Disable Master Mode */
  86. #define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control */
  87. /*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/
  88. #define SRATE_ENABLE_USB_MODE 0x001 /* Enable/Disable USB Mode */
  89. #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate */
  90. #define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control) */
  91. #define SRATE_CORECLK_DIV2 0x040 /* Core Clock divider select */
  92. #define SRATE_CLKOUT_DIV2 0x080 /* Clock Out divider select */
  93. /*Active Control (SSM2602_REG_ACTIVE_CTRL)*/
  94. #define ACTIVE_ACTIVATE_CODEC 0x001 /* Activate Codec Digital Audio Interface */
  95. /*********************************************************************/
  96. #define SSM2602_CACHEREGNUM 10
  97. enum ssm2602_clk {
  98. SSM2602_SYSCLK,
  99. SSM2602_CLK_CLKOUT,
  100. SSM2602_CLK_XTO
  101. };
  102. #endif