ssm2518.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SSM2518 amplifier audio driver
  4. *
  5. * Copyright 2013 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/i2c.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/gpio.h>
  14. #include <linux/of_gpio.h>
  15. #include <linux/platform_data/ssm2518.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/soc.h>
  20. #include <sound/initval.h>
  21. #include <sound/tlv.h>
  22. #include "ssm2518.h"
  23. #define SSM2518_REG_POWER1 0x00
  24. #define SSM2518_REG_CLOCK 0x01
  25. #define SSM2518_REG_SAI_CTRL1 0x02
  26. #define SSM2518_REG_SAI_CTRL2 0x03
  27. #define SSM2518_REG_CHAN_MAP 0x04
  28. #define SSM2518_REG_LEFT_VOL 0x05
  29. #define SSM2518_REG_RIGHT_VOL 0x06
  30. #define SSM2518_REG_MUTE_CTRL 0x07
  31. #define SSM2518_REG_FAULT_CTRL 0x08
  32. #define SSM2518_REG_POWER2 0x09
  33. #define SSM2518_REG_DRC_1 0x0a
  34. #define SSM2518_REG_DRC_2 0x0b
  35. #define SSM2518_REG_DRC_3 0x0c
  36. #define SSM2518_REG_DRC_4 0x0d
  37. #define SSM2518_REG_DRC_5 0x0e
  38. #define SSM2518_REG_DRC_6 0x0f
  39. #define SSM2518_REG_DRC_7 0x10
  40. #define SSM2518_REG_DRC_8 0x11
  41. #define SSM2518_REG_DRC_9 0x12
  42. #define SSM2518_POWER1_RESET BIT(7)
  43. #define SSM2518_POWER1_NO_BCLK BIT(5)
  44. #define SSM2518_POWER1_MCS_MASK (0xf << 1)
  45. #define SSM2518_POWER1_MCS_64FS (0x0 << 1)
  46. #define SSM2518_POWER1_MCS_128FS (0x1 << 1)
  47. #define SSM2518_POWER1_MCS_256FS (0x2 << 1)
  48. #define SSM2518_POWER1_MCS_384FS (0x3 << 1)
  49. #define SSM2518_POWER1_MCS_512FS (0x4 << 1)
  50. #define SSM2518_POWER1_MCS_768FS (0x5 << 1)
  51. #define SSM2518_POWER1_MCS_100FS (0x6 << 1)
  52. #define SSM2518_POWER1_MCS_200FS (0x7 << 1)
  53. #define SSM2518_POWER1_MCS_400FS (0x8 << 1)
  54. #define SSM2518_POWER1_SPWDN BIT(0)
  55. #define SSM2518_CLOCK_ASR BIT(0)
  56. #define SSM2518_SAI_CTRL1_FMT_MASK (0x3 << 5)
  57. #define SSM2518_SAI_CTRL1_FMT_I2S (0x0 << 5)
  58. #define SSM2518_SAI_CTRL1_FMT_LJ (0x1 << 5)
  59. #define SSM2518_SAI_CTRL1_FMT_RJ_24BIT (0x2 << 5)
  60. #define SSM2518_SAI_CTRL1_FMT_RJ_16BIT (0x3 << 5)
  61. #define SSM2518_SAI_CTRL1_SAI_MASK (0x7 << 2)
  62. #define SSM2518_SAI_CTRL1_SAI_I2S (0x0 << 2)
  63. #define SSM2518_SAI_CTRL1_SAI_TDM_2 (0x1 << 2)
  64. #define SSM2518_SAI_CTRL1_SAI_TDM_4 (0x2 << 2)
  65. #define SSM2518_SAI_CTRL1_SAI_TDM_8 (0x3 << 2)
  66. #define SSM2518_SAI_CTRL1_SAI_TDM_16 (0x4 << 2)
  67. #define SSM2518_SAI_CTRL1_SAI_MONO (0x5 << 2)
  68. #define SSM2518_SAI_CTRL1_FS_MASK (0x3)
  69. #define SSM2518_SAI_CTRL1_FS_8000_12000 (0x0)
  70. #define SSM2518_SAI_CTRL1_FS_16000_24000 (0x1)
  71. #define SSM2518_SAI_CTRL1_FS_32000_48000 (0x2)
  72. #define SSM2518_SAI_CTRL1_FS_64000_96000 (0x3)
  73. #define SSM2518_SAI_CTRL2_BCLK_INTERAL BIT(7)
  74. #define SSM2518_SAI_CTRL2_LRCLK_PULSE BIT(6)
  75. #define SSM2518_SAI_CTRL2_LRCLK_INVERT BIT(5)
  76. #define SSM2518_SAI_CTRL2_MSB BIT(4)
  77. #define SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK (0x3 << 2)
  78. #define SSM2518_SAI_CTRL2_SLOT_WIDTH_32 (0x0 << 2)
  79. #define SSM2518_SAI_CTRL2_SLOT_WIDTH_24 (0x1 << 2)
  80. #define SSM2518_SAI_CTRL2_SLOT_WIDTH_16 (0x2 << 2)
  81. #define SSM2518_SAI_CTRL2_BCLK_INVERT BIT(1)
  82. #define SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET 4
  83. #define SSM2518_CHAN_MAP_RIGHT_SLOT_MASK 0xf0
  84. #define SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET 0
  85. #define SSM2518_CHAN_MAP_LEFT_SLOT_MASK 0x0f
  86. #define SSM2518_MUTE_CTRL_ANA_GAIN BIT(5)
  87. #define SSM2518_MUTE_CTRL_MUTE_MASTER BIT(0)
  88. #define SSM2518_POWER2_APWDN BIT(0)
  89. #define SSM2518_DAC_MUTE BIT(6)
  90. #define SSM2518_DAC_FS_MASK 0x07
  91. #define SSM2518_DAC_FS_8000 0x00
  92. #define SSM2518_DAC_FS_16000 0x01
  93. #define SSM2518_DAC_FS_32000 0x02
  94. #define SSM2518_DAC_FS_64000 0x03
  95. #define SSM2518_DAC_FS_128000 0x04
  96. struct ssm2518 {
  97. struct regmap *regmap;
  98. bool right_j;
  99. unsigned int sysclk;
  100. const struct snd_pcm_hw_constraint_list *constraints;
  101. int enable_gpio;
  102. };
  103. static const struct reg_default ssm2518_reg_defaults[] = {
  104. { 0x00, 0x05 },
  105. { 0x01, 0x00 },
  106. { 0x02, 0x02 },
  107. { 0x03, 0x00 },
  108. { 0x04, 0x10 },
  109. { 0x05, 0x40 },
  110. { 0x06, 0x40 },
  111. { 0x07, 0x81 },
  112. { 0x08, 0x0c },
  113. { 0x09, 0x99 },
  114. { 0x0a, 0x7c },
  115. { 0x0b, 0x5b },
  116. { 0x0c, 0x57 },
  117. { 0x0d, 0x89 },
  118. { 0x0e, 0x8c },
  119. { 0x0f, 0x77 },
  120. { 0x10, 0x26 },
  121. { 0x11, 0x1c },
  122. { 0x12, 0x97 },
  123. };
  124. static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
  125. static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
  126. static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
  127. static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
  128. static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
  129. static const DECLARE_TLV_DB_RANGE(ssm2518_limiter_tlv,
  130. 0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
  131. 7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
  132. );
  133. static const char * const ssm2518_drc_peak_detector_attack_time_text[] = {
  134. "0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
  135. "6 ms", "12 ms", "24 ms", "48 ms", "96 ms", "192 ms", "384 ms",
  136. "768 ms", "1536 ms",
  137. };
  138. static const char * const ssm2518_drc_peak_detector_release_time_text[] = {
  139. "0 ms", "1.5 ms", "3 ms", "6 ms", "12 ms", "24 ms", "48 ms", "96 ms",
  140. "192 ms", "384 ms", "768 ms", "1536 ms", "3072 ms", "6144 ms",
  141. "12288 ms", "24576 ms"
  142. };
  143. static const char * const ssm2518_drc_hold_time_text[] = {
  144. "0 ms", "0.67 ms", "1.33 ms", "2.67 ms", "5.33 ms", "10.66 ms",
  145. "21.32 ms", "42.64 ms", "85.28 ms", "170.56 ms", "341.12 ms",
  146. "682.24 ms", "1364 ms",
  147. };
  148. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_attack_time_enum,
  149. SSM2518_REG_DRC_2, 4, ssm2518_drc_peak_detector_attack_time_text);
  150. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_release_time_enum,
  151. SSM2518_REG_DRC_2, 0, ssm2518_drc_peak_detector_release_time_text);
  152. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_attack_time_enum,
  153. SSM2518_REG_DRC_6, 4, ssm2518_drc_peak_detector_attack_time_text);
  154. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_decay_time_enum,
  155. SSM2518_REG_DRC_6, 0, ssm2518_drc_peak_detector_release_time_text);
  156. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_hold_time_enum,
  157. SSM2518_REG_DRC_7, 4, ssm2518_drc_hold_time_text);
  158. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_noise_gate_hold_time_enum,
  159. SSM2518_REG_DRC_7, 0, ssm2518_drc_hold_time_text);
  160. static SOC_ENUM_SINGLE_DECL(ssm2518_drc_rms_averaging_time_enum,
  161. SSM2518_REG_DRC_9, 0, ssm2518_drc_peak_detector_release_time_text);
  162. static const struct snd_kcontrol_new ssm2518_snd_controls[] = {
  163. SOC_SINGLE("Playback De-emphasis Switch", SSM2518_REG_MUTE_CTRL,
  164. 4, 1, 0),
  165. SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2518_REG_LEFT_VOL,
  166. SSM2518_REG_RIGHT_VOL, 0, 0xff, 1, ssm2518_vol_tlv),
  167. SOC_DOUBLE("Master Playback Switch", SSM2518_REG_MUTE_CTRL, 2, 1, 1, 1),
  168. SOC_SINGLE("Amp Low Power Mode Switch", SSM2518_REG_POWER2, 4, 1, 0),
  169. SOC_SINGLE("DAC Low Power Mode Switch", SSM2518_REG_POWER2, 3, 1, 0),
  170. SOC_SINGLE("DRC Limiter Switch", SSM2518_REG_DRC_1, 5, 1, 0),
  171. SOC_SINGLE("DRC Compressor Switch", SSM2518_REG_DRC_1, 4, 1, 0),
  172. SOC_SINGLE("DRC Expander Switch", SSM2518_REG_DRC_1, 3, 1, 0),
  173. SOC_SINGLE("DRC Noise Gate Switch", SSM2518_REG_DRC_1, 2, 1, 0),
  174. SOC_DOUBLE("DRC Switch", SSM2518_REG_DRC_1, 0, 1, 1, 0),
  175. SOC_SINGLE_TLV("DRC Limiter Threshold Volume",
  176. SSM2518_REG_DRC_3, 4, 15, 1, ssm2518_limiter_tlv),
  177. SOC_SINGLE_TLV("DRC Compressor Lower Threshold Volume",
  178. SSM2518_REG_DRC_3, 0, 15, 1, ssm2518_compressor_tlv),
  179. SOC_SINGLE_TLV("DRC Expander Upper Threshold Volume", SSM2518_REG_DRC_4,
  180. 4, 15, 1, ssm2518_expander_tlv),
  181. SOC_SINGLE_TLV("DRC Noise Gate Threshold Volume",
  182. SSM2518_REG_DRC_4, 0, 15, 1, ssm2518_noise_gate_tlv),
  183. SOC_SINGLE_TLV("DRC Upper Output Threshold Volume",
  184. SSM2518_REG_DRC_5, 4, 15, 1, ssm2518_limiter_tlv),
  185. SOC_SINGLE_TLV("DRC Lower Output Threshold Volume",
  186. SSM2518_REG_DRC_5, 0, 15, 1, ssm2518_noise_gate_tlv),
  187. SOC_SINGLE_TLV("DRC Post Volume", SSM2518_REG_DRC_8,
  188. 2, 15, 1, ssm2518_post_drc_tlv),
  189. SOC_ENUM("DRC Peak Detector Attack Time",
  190. ssm2518_drc_peak_detector_attack_time_enum),
  191. SOC_ENUM("DRC Peak Detector Release Time",
  192. ssm2518_drc_peak_detector_release_time_enum),
  193. SOC_ENUM("DRC Attack Time", ssm2518_drc_attack_time_enum),
  194. SOC_ENUM("DRC Decay Time", ssm2518_drc_decay_time_enum),
  195. SOC_ENUM("DRC Hold Time", ssm2518_drc_hold_time_enum),
  196. SOC_ENUM("DRC Noise Gate Hold Time",
  197. ssm2518_drc_noise_gate_hold_time_enum),
  198. SOC_ENUM("DRC RMS Averaging Time", ssm2518_drc_rms_averaging_time_enum),
  199. };
  200. static const struct snd_soc_dapm_widget ssm2518_dapm_widgets[] = {
  201. SND_SOC_DAPM_DAC("DACL", "HiFi Playback", SSM2518_REG_POWER2, 1, 1),
  202. SND_SOC_DAPM_DAC("DACR", "HiFi Playback", SSM2518_REG_POWER2, 2, 1),
  203. SND_SOC_DAPM_OUTPUT("OUTL"),
  204. SND_SOC_DAPM_OUTPUT("OUTR"),
  205. };
  206. static const struct snd_soc_dapm_route ssm2518_routes[] = {
  207. { "OUTL", NULL, "DACL" },
  208. { "OUTR", NULL, "DACR" },
  209. };
  210. struct ssm2518_mcs_lut {
  211. unsigned int rate;
  212. const unsigned int *sysclks;
  213. };
  214. static const unsigned int ssm2518_sysclks_2048000[] = {
  215. 2048000, 4096000, 8192000, 12288000, 16384000, 24576000,
  216. 3200000, 6400000, 12800000, 0
  217. };
  218. static const unsigned int ssm2518_sysclks_2822000[] = {
  219. 2822000, 5644800, 11289600, 16934400, 22579200, 33868800,
  220. 4410000, 8820000, 17640000, 0
  221. };
  222. static const unsigned int ssm2518_sysclks_3072000[] = {
  223. 3072000, 6144000, 12288000, 16384000, 24576000, 38864000,
  224. 4800000, 9600000, 19200000, 0
  225. };
  226. static const struct ssm2518_mcs_lut ssm2518_mcs_lut[] = {
  227. { 8000, ssm2518_sysclks_2048000, },
  228. { 11025, ssm2518_sysclks_2822000, },
  229. { 12000, ssm2518_sysclks_3072000, },
  230. { 16000, ssm2518_sysclks_2048000, },
  231. { 24000, ssm2518_sysclks_3072000, },
  232. { 22050, ssm2518_sysclks_2822000, },
  233. { 32000, ssm2518_sysclks_2048000, },
  234. { 44100, ssm2518_sysclks_2822000, },
  235. { 48000, ssm2518_sysclks_3072000, },
  236. { 96000, ssm2518_sysclks_3072000, },
  237. };
  238. static const unsigned int ssm2518_rates_2048000[] = {
  239. 8000, 16000, 32000,
  240. };
  241. static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2048000 = {
  242. .list = ssm2518_rates_2048000,
  243. .count = ARRAY_SIZE(ssm2518_rates_2048000),
  244. };
  245. static const unsigned int ssm2518_rates_2822000[] = {
  246. 11025, 22050, 44100,
  247. };
  248. static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2822000 = {
  249. .list = ssm2518_rates_2822000,
  250. .count = ARRAY_SIZE(ssm2518_rates_2822000),
  251. };
  252. static const unsigned int ssm2518_rates_3072000[] = {
  253. 12000, 24000, 48000, 96000,
  254. };
  255. static const struct snd_pcm_hw_constraint_list ssm2518_constraints_3072000 = {
  256. .list = ssm2518_rates_3072000,
  257. .count = ARRAY_SIZE(ssm2518_rates_3072000),
  258. };
  259. static const unsigned int ssm2518_rates_12288000[] = {
  260. 8000, 12000, 16000, 24000, 32000, 48000, 96000,
  261. };
  262. static const struct snd_pcm_hw_constraint_list ssm2518_constraints_12288000 = {
  263. .list = ssm2518_rates_12288000,
  264. .count = ARRAY_SIZE(ssm2518_rates_12288000),
  265. };
  266. static int ssm2518_lookup_mcs(struct ssm2518 *ssm2518,
  267. unsigned int rate)
  268. {
  269. const unsigned int *sysclks = NULL;
  270. int i;
  271. for (i = 0; i < ARRAY_SIZE(ssm2518_mcs_lut); i++) {
  272. if (ssm2518_mcs_lut[i].rate == rate) {
  273. sysclks = ssm2518_mcs_lut[i].sysclks;
  274. break;
  275. }
  276. }
  277. if (!sysclks)
  278. return -EINVAL;
  279. for (i = 0; sysclks[i]; i++) {
  280. if (sysclks[i] == ssm2518->sysclk)
  281. return i;
  282. }
  283. return -EINVAL;
  284. }
  285. static int ssm2518_hw_params(struct snd_pcm_substream *substream,
  286. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  287. {
  288. struct snd_soc_component *component = dai->component;
  289. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
  290. unsigned int rate = params_rate(params);
  291. unsigned int ctrl1, ctrl1_mask;
  292. int mcs;
  293. int ret;
  294. mcs = ssm2518_lookup_mcs(ssm2518, rate);
  295. if (mcs < 0)
  296. return mcs;
  297. ctrl1_mask = SSM2518_SAI_CTRL1_FS_MASK;
  298. if (rate >= 8000 && rate <= 12000)
  299. ctrl1 = SSM2518_SAI_CTRL1_FS_8000_12000;
  300. else if (rate >= 16000 && rate <= 24000)
  301. ctrl1 = SSM2518_SAI_CTRL1_FS_16000_24000;
  302. else if (rate >= 32000 && rate <= 48000)
  303. ctrl1 = SSM2518_SAI_CTRL1_FS_32000_48000;
  304. else if (rate >= 64000 && rate <= 96000)
  305. ctrl1 = SSM2518_SAI_CTRL1_FS_64000_96000;
  306. else
  307. return -EINVAL;
  308. if (ssm2518->right_j) {
  309. switch (params_width(params)) {
  310. case 16:
  311. ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_16BIT;
  312. break;
  313. case 24:
  314. ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
  315. break;
  316. default:
  317. return -EINVAL;
  318. }
  319. ctrl1_mask |= SSM2518_SAI_CTRL1_FMT_MASK;
  320. }
  321. /* Disable auto samplerate detection */
  322. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_CLOCK,
  323. SSM2518_CLOCK_ASR, SSM2518_CLOCK_ASR);
  324. if (ret < 0)
  325. return ret;
  326. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
  327. ctrl1_mask, ctrl1);
  328. if (ret < 0)
  329. return ret;
  330. return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
  331. SSM2518_POWER1_MCS_MASK, mcs << 1);
  332. }
  333. static int ssm2518_mute(struct snd_soc_dai *dai, int mute, int direction)
  334. {
  335. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
  336. unsigned int val;
  337. if (mute)
  338. val = SSM2518_MUTE_CTRL_MUTE_MASTER;
  339. else
  340. val = 0;
  341. return regmap_update_bits(ssm2518->regmap, SSM2518_REG_MUTE_CTRL,
  342. SSM2518_MUTE_CTRL_MUTE_MASTER, val);
  343. }
  344. static int ssm2518_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  345. {
  346. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
  347. unsigned int ctrl1 = 0, ctrl2 = 0;
  348. bool invert_fclk;
  349. int ret;
  350. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  351. case SND_SOC_DAIFMT_CBS_CFS:
  352. break;
  353. default:
  354. return -EINVAL;
  355. }
  356. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  357. case SND_SOC_DAIFMT_NB_NF:
  358. invert_fclk = false;
  359. break;
  360. case SND_SOC_DAIFMT_IB_NF:
  361. ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
  362. invert_fclk = false;
  363. break;
  364. case SND_SOC_DAIFMT_NB_IF:
  365. invert_fclk = true;
  366. break;
  367. case SND_SOC_DAIFMT_IB_IF:
  368. ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
  369. invert_fclk = true;
  370. break;
  371. default:
  372. return -EINVAL;
  373. }
  374. ssm2518->right_j = false;
  375. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  376. case SND_SOC_DAIFMT_I2S:
  377. ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
  378. break;
  379. case SND_SOC_DAIFMT_LEFT_J:
  380. ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
  381. invert_fclk = !invert_fclk;
  382. break;
  383. case SND_SOC_DAIFMT_RIGHT_J:
  384. ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
  385. ssm2518->right_j = true;
  386. invert_fclk = !invert_fclk;
  387. break;
  388. case SND_SOC_DAIFMT_DSP_A:
  389. ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
  390. ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
  391. invert_fclk = false;
  392. break;
  393. case SND_SOC_DAIFMT_DSP_B:
  394. ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
  395. ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
  396. invert_fclk = false;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. if (invert_fclk)
  402. ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_INVERT;
  403. ret = regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL1, ctrl1);
  404. if (ret)
  405. return ret;
  406. return regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL2, ctrl2);
  407. }
  408. static int ssm2518_set_power(struct ssm2518 *ssm2518, bool enable)
  409. {
  410. int ret = 0;
  411. if (!enable) {
  412. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
  413. SSM2518_POWER1_SPWDN, SSM2518_POWER1_SPWDN);
  414. regcache_mark_dirty(ssm2518->regmap);
  415. }
  416. if (gpio_is_valid(ssm2518->enable_gpio))
  417. gpio_set_value(ssm2518->enable_gpio, enable);
  418. regcache_cache_only(ssm2518->regmap, !enable);
  419. if (enable) {
  420. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
  421. SSM2518_POWER1_SPWDN | SSM2518_POWER1_RESET, 0x00);
  422. regcache_sync(ssm2518->regmap);
  423. }
  424. return ret;
  425. }
  426. static int ssm2518_set_bias_level(struct snd_soc_component *component,
  427. enum snd_soc_bias_level level)
  428. {
  429. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
  430. int ret = 0;
  431. switch (level) {
  432. case SND_SOC_BIAS_ON:
  433. break;
  434. case SND_SOC_BIAS_PREPARE:
  435. break;
  436. case SND_SOC_BIAS_STANDBY:
  437. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  438. ret = ssm2518_set_power(ssm2518, true);
  439. break;
  440. case SND_SOC_BIAS_OFF:
  441. ret = ssm2518_set_power(ssm2518, false);
  442. break;
  443. }
  444. return ret;
  445. }
  446. static int ssm2518_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  447. unsigned int rx_mask, int slots, int width)
  448. {
  449. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
  450. unsigned int ctrl1, ctrl2;
  451. int left_slot, right_slot;
  452. int ret;
  453. if (slots == 0)
  454. return regmap_update_bits(ssm2518->regmap,
  455. SSM2518_REG_SAI_CTRL1, SSM2518_SAI_CTRL1_SAI_MASK,
  456. SSM2518_SAI_CTRL1_SAI_I2S);
  457. if (tx_mask == 0 || rx_mask != 0)
  458. return -EINVAL;
  459. if (slots == 1) {
  460. if (tx_mask != 1)
  461. return -EINVAL;
  462. left_slot = 0;
  463. right_slot = 0;
  464. } else {
  465. /* We assume the left channel < right channel */
  466. left_slot = __ffs(tx_mask);
  467. tx_mask &= ~(1 << left_slot);
  468. if (tx_mask == 0) {
  469. right_slot = left_slot;
  470. } else {
  471. right_slot = __ffs(tx_mask);
  472. tx_mask &= ~(1 << right_slot);
  473. }
  474. }
  475. if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
  476. return -EINVAL;
  477. switch (width) {
  478. case 16:
  479. ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_16;
  480. break;
  481. case 24:
  482. ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_24;
  483. break;
  484. case 32:
  485. ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_32;
  486. break;
  487. default:
  488. return -EINVAL;
  489. }
  490. switch (slots) {
  491. case 1:
  492. ctrl1 = SSM2518_SAI_CTRL1_SAI_MONO;
  493. break;
  494. case 2:
  495. ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_2;
  496. break;
  497. case 4:
  498. ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_4;
  499. break;
  500. case 8:
  501. ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_8;
  502. break;
  503. case 16:
  504. ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_16;
  505. break;
  506. default:
  507. return -EINVAL;
  508. }
  509. ret = regmap_write(ssm2518->regmap, SSM2518_REG_CHAN_MAP,
  510. (left_slot << SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET) |
  511. (right_slot << SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET));
  512. if (ret)
  513. return ret;
  514. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
  515. SSM2518_SAI_CTRL1_SAI_MASK, ctrl1);
  516. if (ret)
  517. return ret;
  518. return regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL2,
  519. SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK, ctrl2);
  520. }
  521. static int ssm2518_startup(struct snd_pcm_substream *substream,
  522. struct snd_soc_dai *dai)
  523. {
  524. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
  525. if (ssm2518->constraints)
  526. snd_pcm_hw_constraint_list(substream->runtime, 0,
  527. SNDRV_PCM_HW_PARAM_RATE, ssm2518->constraints);
  528. return 0;
  529. }
  530. #define SSM2518_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  531. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32)
  532. static const struct snd_soc_dai_ops ssm2518_dai_ops = {
  533. .startup = ssm2518_startup,
  534. .hw_params = ssm2518_hw_params,
  535. .mute_stream = ssm2518_mute,
  536. .set_fmt = ssm2518_set_dai_fmt,
  537. .set_tdm_slot = ssm2518_set_tdm_slot,
  538. .no_capture_mute = 1,
  539. };
  540. static struct snd_soc_dai_driver ssm2518_dai = {
  541. .name = "ssm2518-hifi",
  542. .playback = {
  543. .stream_name = "Playback",
  544. .channels_min = 2,
  545. .channels_max = 2,
  546. .rates = SNDRV_PCM_RATE_8000_96000,
  547. .formats = SSM2518_FORMATS,
  548. },
  549. .ops = &ssm2518_dai_ops,
  550. };
  551. static int ssm2518_set_sysclk(struct snd_soc_component *component, int clk_id,
  552. int source, unsigned int freq, int dir)
  553. {
  554. struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
  555. unsigned int val;
  556. if (clk_id != SSM2518_SYSCLK)
  557. return -EINVAL;
  558. switch (source) {
  559. case SSM2518_SYSCLK_SRC_MCLK:
  560. val = 0;
  561. break;
  562. case SSM2518_SYSCLK_SRC_BCLK:
  563. /* In this case the bitclock is used as the system clock, and
  564. * the bitclock signal needs to be connected to the MCLK pin and
  565. * the BCLK pin is left unconnected */
  566. val = SSM2518_POWER1_NO_BCLK;
  567. break;
  568. default:
  569. return -EINVAL;
  570. }
  571. switch (freq) {
  572. case 0:
  573. ssm2518->constraints = NULL;
  574. break;
  575. case 2048000:
  576. case 4096000:
  577. case 8192000:
  578. case 3200000:
  579. case 6400000:
  580. case 12800000:
  581. ssm2518->constraints = &ssm2518_constraints_2048000;
  582. break;
  583. case 2822000:
  584. case 5644800:
  585. case 11289600:
  586. case 16934400:
  587. case 22579200:
  588. case 33868800:
  589. case 4410000:
  590. case 8820000:
  591. case 17640000:
  592. ssm2518->constraints = &ssm2518_constraints_2822000;
  593. break;
  594. case 3072000:
  595. case 6144000:
  596. case 38864000:
  597. case 4800000:
  598. case 9600000:
  599. case 19200000:
  600. ssm2518->constraints = &ssm2518_constraints_3072000;
  601. break;
  602. case 12288000:
  603. case 16384000:
  604. case 24576000:
  605. ssm2518->constraints = &ssm2518_constraints_12288000;
  606. break;
  607. default:
  608. return -EINVAL;
  609. }
  610. ssm2518->sysclk = freq;
  611. return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
  612. SSM2518_POWER1_NO_BCLK, val);
  613. }
  614. static const struct snd_soc_component_driver ssm2518_component_driver = {
  615. .set_bias_level = ssm2518_set_bias_level,
  616. .set_sysclk = ssm2518_set_sysclk,
  617. .controls = ssm2518_snd_controls,
  618. .num_controls = ARRAY_SIZE(ssm2518_snd_controls),
  619. .dapm_widgets = ssm2518_dapm_widgets,
  620. .num_dapm_widgets = ARRAY_SIZE(ssm2518_dapm_widgets),
  621. .dapm_routes = ssm2518_routes,
  622. .num_dapm_routes = ARRAY_SIZE(ssm2518_routes),
  623. .use_pmdown_time = 1,
  624. .endianness = 1,
  625. .non_legacy_dai_naming = 1,
  626. };
  627. static const struct regmap_config ssm2518_regmap_config = {
  628. .val_bits = 8,
  629. .reg_bits = 8,
  630. .max_register = SSM2518_REG_DRC_9,
  631. .cache_type = REGCACHE_RBTREE,
  632. .reg_defaults = ssm2518_reg_defaults,
  633. .num_reg_defaults = ARRAY_SIZE(ssm2518_reg_defaults),
  634. };
  635. static int ssm2518_i2c_probe(struct i2c_client *i2c,
  636. const struct i2c_device_id *id)
  637. {
  638. struct ssm2518_platform_data *pdata = i2c->dev.platform_data;
  639. struct ssm2518 *ssm2518;
  640. int ret;
  641. ssm2518 = devm_kzalloc(&i2c->dev, sizeof(*ssm2518), GFP_KERNEL);
  642. if (ssm2518 == NULL)
  643. return -ENOMEM;
  644. if (pdata) {
  645. ssm2518->enable_gpio = pdata->enable_gpio;
  646. } else if (i2c->dev.of_node) {
  647. ssm2518->enable_gpio = of_get_gpio(i2c->dev.of_node, 0);
  648. if (ssm2518->enable_gpio < 0 && ssm2518->enable_gpio != -ENOENT)
  649. return ssm2518->enable_gpio;
  650. } else {
  651. ssm2518->enable_gpio = -1;
  652. }
  653. if (gpio_is_valid(ssm2518->enable_gpio)) {
  654. ret = devm_gpio_request_one(&i2c->dev, ssm2518->enable_gpio,
  655. GPIOF_OUT_INIT_HIGH, "SSM2518 nSD");
  656. if (ret)
  657. return ret;
  658. }
  659. i2c_set_clientdata(i2c, ssm2518);
  660. ssm2518->regmap = devm_regmap_init_i2c(i2c, &ssm2518_regmap_config);
  661. if (IS_ERR(ssm2518->regmap))
  662. return PTR_ERR(ssm2518->regmap);
  663. /*
  664. * The reset bit is obviously volatile, but we need to be able to cache
  665. * the other bits in the register, so we can't just mark the whole
  666. * register as volatile. Since this is the only place where we'll ever
  667. * touch the reset bit just bypass the cache for this operation.
  668. */
  669. regcache_cache_bypass(ssm2518->regmap, true);
  670. ret = regmap_write(ssm2518->regmap, SSM2518_REG_POWER1,
  671. SSM2518_POWER1_RESET);
  672. regcache_cache_bypass(ssm2518->regmap, false);
  673. if (ret)
  674. return ret;
  675. ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER2,
  676. SSM2518_POWER2_APWDN, 0x00);
  677. if (ret)
  678. return ret;
  679. ret = ssm2518_set_power(ssm2518, false);
  680. if (ret)
  681. return ret;
  682. return devm_snd_soc_register_component(&i2c->dev,
  683. &ssm2518_component_driver,
  684. &ssm2518_dai, 1);
  685. }
  686. #ifdef CONFIG_OF
  687. static const struct of_device_id ssm2518_dt_ids[] = {
  688. { .compatible = "adi,ssm2518", },
  689. { }
  690. };
  691. MODULE_DEVICE_TABLE(of, ssm2518_dt_ids);
  692. #endif
  693. static const struct i2c_device_id ssm2518_i2c_ids[] = {
  694. { "ssm2518", 0 },
  695. { }
  696. };
  697. MODULE_DEVICE_TABLE(i2c, ssm2518_i2c_ids);
  698. static struct i2c_driver ssm2518_driver = {
  699. .driver = {
  700. .name = "ssm2518",
  701. .of_match_table = of_match_ptr(ssm2518_dt_ids),
  702. },
  703. .probe = ssm2518_i2c_probe,
  704. .id_table = ssm2518_i2c_ids,
  705. };
  706. module_i2c_driver(ssm2518_driver);
  707. MODULE_DESCRIPTION("ASoC SSM2518 driver");
  708. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  709. MODULE_LICENSE("GPL");