sgtl5000.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * sgtl5000.h - SGTL5000 audio codec interface
  4. *
  5. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef _SGTL5000_H
  8. #define _SGTL5000_H
  9. /*
  10. * Registers addresses
  11. */
  12. #define SGTL5000_CHIP_ID 0x0000
  13. #define SGTL5000_CHIP_DIG_POWER 0x0002
  14. #define SGTL5000_CHIP_CLK_CTRL 0x0004
  15. #define SGTL5000_CHIP_I2S_CTRL 0x0006
  16. #define SGTL5000_CHIP_SSS_CTRL 0x000a
  17. #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
  18. #define SGTL5000_CHIP_DAC_VOL 0x0010
  19. #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
  20. #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
  21. #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
  22. #define SGTL5000_CHIP_ANA_CTRL 0x0024
  23. #define SGTL5000_CHIP_LINREG_CTRL 0x0026
  24. #define SGTL5000_CHIP_REF_CTRL 0x0028
  25. #define SGTL5000_CHIP_MIC_CTRL 0x002a
  26. #define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c
  27. #define SGTL5000_CHIP_LINE_OUT_VOL 0x002e
  28. #define SGTL5000_CHIP_ANA_POWER 0x0030
  29. #define SGTL5000_CHIP_PLL_CTRL 0x0032
  30. #define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034
  31. #define SGTL5000_CHIP_ANA_STATUS 0x0036
  32. #define SGTL5000_CHIP_SHORT_CTRL 0x003c
  33. #define SGTL5000_CHIP_ANA_TEST2 0x003a
  34. #define SGTL5000_DAP_CTRL 0x0100
  35. #define SGTL5000_DAP_PEQ 0x0102
  36. #define SGTL5000_DAP_BASS_ENHANCE 0x0104
  37. #define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106
  38. #define SGTL5000_DAP_AUDIO_EQ 0x0108
  39. #define SGTL5000_DAP_SURROUND 0x010a
  40. #define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c
  41. #define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e
  42. #define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110
  43. #define SGTL5000_DAP_EQ_BASS_BAND0 0x0116
  44. #define SGTL5000_DAP_EQ_BASS_BAND1 0x0118
  45. #define SGTL5000_DAP_EQ_BASS_BAND2 0x011a
  46. #define SGTL5000_DAP_EQ_BASS_BAND3 0x011c
  47. #define SGTL5000_DAP_EQ_BASS_BAND4 0x011e
  48. #define SGTL5000_DAP_MAIN_CHAN 0x0120
  49. #define SGTL5000_DAP_MIX_CHAN 0x0122
  50. #define SGTL5000_DAP_AVC_CTRL 0x0124
  51. #define SGTL5000_DAP_AVC_THRESHOLD 0x0126
  52. #define SGTL5000_DAP_AVC_ATTACK 0x0128
  53. #define SGTL5000_DAP_AVC_DECAY 0x012a
  54. #define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c
  55. #define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e
  56. #define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130
  57. #define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132
  58. #define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134
  59. #define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136
  60. #define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138
  61. #define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a
  62. /*
  63. * Field Definitions.
  64. */
  65. /*
  66. * SGTL5000_CHIP_ID
  67. */
  68. #define SGTL5000_PARTID_MASK 0xff00
  69. #define SGTL5000_PARTID_SHIFT 8
  70. #define SGTL5000_PARTID_WIDTH 8
  71. #define SGTL5000_PARTID_PART_ID 0xa0
  72. #define SGTL5000_REVID_MASK 0x00ff
  73. #define SGTL5000_REVID_SHIFT 0
  74. #define SGTL5000_REVID_WIDTH 8
  75. /*
  76. * SGTL5000_CHIP_DIG_POWER
  77. */
  78. #define SGTL5000_ADC_EN 0x0040
  79. #define SGTL5000_DAC_EN 0x0020
  80. #define SGTL5000_DAP_POWERUP 0x0010
  81. #define SGTL5000_I2S_OUT_POWERUP 0x0002
  82. #define SGTL5000_I2S_IN_POWERUP 0x0001
  83. /*
  84. * SGTL5000_CHIP_CLK_CTRL
  85. */
  86. #define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x0008
  87. #define SGTL5000_RATE_MODE_MASK 0x0030
  88. #define SGTL5000_RATE_MODE_SHIFT 4
  89. #define SGTL5000_RATE_MODE_WIDTH 2
  90. #define SGTL5000_RATE_MODE_DIV_1 0
  91. #define SGTL5000_RATE_MODE_DIV_2 1
  92. #define SGTL5000_RATE_MODE_DIV_4 2
  93. #define SGTL5000_RATE_MODE_DIV_6 3
  94. #define SGTL5000_SYS_FS_MASK 0x000c
  95. #define SGTL5000_SYS_FS_SHIFT 2
  96. #define SGTL5000_SYS_FS_WIDTH 2
  97. #define SGTL5000_SYS_FS_32k 0x0
  98. #define SGTL5000_SYS_FS_44_1k 0x1
  99. #define SGTL5000_SYS_FS_48k 0x2
  100. #define SGTL5000_SYS_FS_96k 0x3
  101. #define SGTL5000_MCLK_FREQ_MASK 0x0003
  102. #define SGTL5000_MCLK_FREQ_SHIFT 0
  103. #define SGTL5000_MCLK_FREQ_WIDTH 2
  104. #define SGTL5000_MCLK_FREQ_256FS 0x0
  105. #define SGTL5000_MCLK_FREQ_384FS 0x1
  106. #define SGTL5000_MCLK_FREQ_512FS 0x2
  107. #define SGTL5000_MCLK_FREQ_PLL 0x3
  108. /*
  109. * SGTL5000_CHIP_I2S_CTRL
  110. */
  111. #define SGTL5000_I2S_SCLKFREQ_MASK 0x0100
  112. #define SGTL5000_I2S_SCLKFREQ_SHIFT 8
  113. #define SGTL5000_I2S_SCLKFREQ_WIDTH 1
  114. #define SGTL5000_I2S_SCLKFREQ_64FS 0x0
  115. #define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */
  116. #define SGTL5000_I2S_MASTER 0x0080
  117. #define SGTL5000_I2S_SCLK_INV 0x0040
  118. #define SGTL5000_I2S_DLEN_MASK 0x0030
  119. #define SGTL5000_I2S_DLEN_SHIFT 4
  120. #define SGTL5000_I2S_DLEN_WIDTH 2
  121. #define SGTL5000_I2S_DLEN_32 0x0
  122. #define SGTL5000_I2S_DLEN_24 0x1
  123. #define SGTL5000_I2S_DLEN_20 0x2
  124. #define SGTL5000_I2S_DLEN_16 0x3
  125. #define SGTL5000_I2S_MODE_MASK 0x000c
  126. #define SGTL5000_I2S_MODE_SHIFT 2
  127. #define SGTL5000_I2S_MODE_WIDTH 2
  128. #define SGTL5000_I2S_MODE_I2S_LJ 0x0
  129. #define SGTL5000_I2S_MODE_RJ 0x1
  130. #define SGTL5000_I2S_MODE_PCM 0x2
  131. #define SGTL5000_I2S_LRALIGN 0x0002
  132. #define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */
  133. /*
  134. * SGTL5000_CHIP_SSS_CTRL
  135. */
  136. #define SGTL5000_DAP_MIX_LRSWAP 0x4000
  137. #define SGTL5000_DAP_LRSWAP 0x2000
  138. #define SGTL5000_DAC_LRSWAP 0x1000
  139. #define SGTL5000_I2S_OUT_LRSWAP 0x0400
  140. #define SGTL5000_DAP_MIX_SEL_MASK 0x0300
  141. #define SGTL5000_DAP_MIX_SEL_SHIFT 8
  142. #define SGTL5000_DAP_MIX_SEL_WIDTH 2
  143. #define SGTL5000_DAP_MIX_SEL_ADC 0x0
  144. #define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1
  145. #define SGTL5000_DAP_SEL_MASK 0x00c0
  146. #define SGTL5000_DAP_SEL_SHIFT 6
  147. #define SGTL5000_DAP_SEL_WIDTH 2
  148. #define SGTL5000_DAP_SEL_ADC 0x0
  149. #define SGTL5000_DAP_SEL_I2S_IN 0x1
  150. #define SGTL5000_DAC_SEL_MASK 0x0030
  151. #define SGTL5000_DAC_SEL_SHIFT 4
  152. #define SGTL5000_DAC_SEL_WIDTH 2
  153. #define SGTL5000_DAC_SEL_ADC 0x0
  154. #define SGTL5000_DAC_SEL_I2S_IN 0x1
  155. #define SGTL5000_DAC_SEL_DAP 0x3
  156. #define SGTL5000_I2S_OUT_SEL_MASK 0x0003
  157. #define SGTL5000_I2S_OUT_SEL_SHIFT 0
  158. #define SGTL5000_I2S_OUT_SEL_WIDTH 2
  159. #define SGTL5000_I2S_OUT_SEL_ADC 0x0
  160. #define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1
  161. #define SGTL5000_I2S_OUT_SEL_DAP 0x3
  162. /*
  163. * SGTL5000_CHIP_ADCDAC_CTRL
  164. */
  165. #define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000
  166. #define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000
  167. #define SGTL5000_DAC_VOL_RAMP_EN 0x0200
  168. #define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100
  169. #define SGTL5000_DAC_MUTE_RIGHT 0x0008
  170. #define SGTL5000_DAC_MUTE_LEFT 0x0004
  171. #define SGTL5000_ADC_HPF_FREEZE 0x0002
  172. #define SGTL5000_ADC_HPF_BYPASS 0x0001
  173. /*
  174. * SGTL5000_CHIP_DAC_VOL
  175. */
  176. #define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00
  177. #define SGTL5000_DAC_VOL_RIGHT_SHIFT 8
  178. #define SGTL5000_DAC_VOL_RIGHT_WIDTH 8
  179. #define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff
  180. #define SGTL5000_DAC_VOL_LEFT_SHIFT 0
  181. #define SGTL5000_DAC_VOL_LEFT_WIDTH 8
  182. /*
  183. * SGTL5000_CHIP_PAD_STRENGTH
  184. */
  185. #define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300
  186. #define SGTL5000_PAD_I2S_LRCLK_SHIFT 8
  187. #define SGTL5000_PAD_I2S_LRCLK_WIDTH 2
  188. #define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0
  189. #define SGTL5000_PAD_I2S_SCLK_SHIFT 6
  190. #define SGTL5000_PAD_I2S_SCLK_WIDTH 2
  191. #define SGTL5000_PAD_I2S_DOUT_MASK 0x0030
  192. #define SGTL5000_PAD_I2S_DOUT_SHIFT 4
  193. #define SGTL5000_PAD_I2S_DOUT_WIDTH 2
  194. #define SGTL5000_PAD_I2C_SDA_MASK 0x000c
  195. #define SGTL5000_PAD_I2C_SDA_SHIFT 2
  196. #define SGTL5000_PAD_I2C_SDA_WIDTH 2
  197. #define SGTL5000_PAD_I2C_SCL_MASK 0x0003
  198. #define SGTL5000_PAD_I2C_SCL_SHIFT 0
  199. #define SGTL5000_PAD_I2C_SCL_WIDTH 2
  200. /*
  201. * SGTL5000_CHIP_ANA_ADC_CTRL
  202. */
  203. #define SGTL5000_ADC_VOL_M6DB 0x0100
  204. #define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0
  205. #define SGTL5000_ADC_VOL_RIGHT_SHIFT 4
  206. #define SGTL5000_ADC_VOL_RIGHT_WIDTH 4
  207. #define SGTL5000_ADC_VOL_LEFT_MASK 0x000f
  208. #define SGTL5000_ADC_VOL_LEFT_SHIFT 0
  209. #define SGTL5000_ADC_VOL_LEFT_WIDTH 4
  210. /*
  211. * SGTL5000_CHIP_ANA_HP_CTRL
  212. */
  213. #define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00
  214. #define SGTL5000_HP_VOL_RIGHT_SHIFT 8
  215. #define SGTL5000_HP_VOL_RIGHT_WIDTH 7
  216. #define SGTL5000_HP_VOL_LEFT_MASK 0x007f
  217. #define SGTL5000_HP_VOL_LEFT_SHIFT 0
  218. #define SGTL5000_HP_VOL_LEFT_WIDTH 7
  219. /*
  220. * SGTL5000_CHIP_ANA_CTRL
  221. */
  222. #define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133
  223. #define SGTL5000_LINE_OUT_MUTE 0x0100
  224. #define SGTL5000_HP_SEL_MASK 0x0040
  225. #define SGTL5000_HP_SEL_SHIFT 6
  226. #define SGTL5000_HP_SEL_WIDTH 1
  227. #define SGTL5000_HP_SEL_DAC 0x0
  228. #define SGTL5000_HP_SEL_LINE_IN 0x1
  229. #define SGTL5000_HP_ZCD_EN 0x0020
  230. #define SGTL5000_HP_MUTE 0x0010
  231. #define SGTL5000_ADC_SEL_MASK 0x0004
  232. #define SGTL5000_ADC_SEL_SHIFT 2
  233. #define SGTL5000_ADC_SEL_WIDTH 1
  234. #define SGTL5000_ADC_SEL_MIC 0x0
  235. #define SGTL5000_ADC_SEL_LINE_IN 0x1
  236. #define SGTL5000_ADC_ZCD_EN 0x0002
  237. #define SGTL5000_ADC_MUTE 0x0001
  238. /*
  239. * SGTL5000_CHIP_LINREG_CTRL
  240. */
  241. #define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040
  242. #define SGTL5000_VDDC_MAN_ASSN_SHIFT 6
  243. #define SGTL5000_VDDC_MAN_ASSN_WIDTH 1
  244. #define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0
  245. #define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1
  246. #define SGTL5000_VDDC_ASSN_OVRD 0x0020
  247. #define SGTL5000_LINREG_VDDD_MASK 0x000f
  248. #define SGTL5000_LINREG_VDDD_SHIFT 0
  249. #define SGTL5000_LINREG_VDDD_WIDTH 4
  250. /*
  251. * SGTL5000_CHIP_REF_CTRL
  252. */
  253. #define SGTL5000_ANA_GND_MASK 0x01f0
  254. #define SGTL5000_ANA_GND_SHIFT 4
  255. #define SGTL5000_ANA_GND_WIDTH 5
  256. #define SGTL5000_ANA_GND_BASE 800 /* mv */
  257. #define SGTL5000_ANA_GND_STP 25 /*mv */
  258. #define SGTL5000_BIAS_CTRL_MASK 0x000e
  259. #define SGTL5000_BIAS_CTRL_SHIFT 1
  260. #define SGTL5000_BIAS_CTRL_WIDTH 3
  261. #define SGTL5000_SMALL_POP 0x0001
  262. /*
  263. * SGTL5000_CHIP_MIC_CTRL
  264. */
  265. #define SGTL5000_BIAS_R_MASK 0x0300
  266. #define SGTL5000_BIAS_R_SHIFT 8
  267. #define SGTL5000_BIAS_R_WIDTH 2
  268. #define SGTL5000_BIAS_R_off 0x0
  269. #define SGTL5000_BIAS_R_2K 0x1
  270. #define SGTL5000_BIAS_R_4k 0x2
  271. #define SGTL5000_BIAS_R_8k 0x3
  272. #define SGTL5000_BIAS_VOLT_MASK 0x0070
  273. #define SGTL5000_BIAS_VOLT_SHIFT 4
  274. #define SGTL5000_BIAS_VOLT_WIDTH 3
  275. #define SGTL5000_MIC_GAIN_MASK 0x0003
  276. #define SGTL5000_MIC_GAIN_SHIFT 0
  277. #define SGTL5000_MIC_GAIN_WIDTH 2
  278. /*
  279. * SGTL5000_CHIP_LINE_OUT_CTRL
  280. */
  281. #define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00
  282. #define SGTL5000_LINE_OUT_CURRENT_SHIFT 8
  283. #define SGTL5000_LINE_OUT_CURRENT_WIDTH 4
  284. #define SGTL5000_LINE_OUT_CURRENT_180u 0x0
  285. #define SGTL5000_LINE_OUT_CURRENT_270u 0x1
  286. #define SGTL5000_LINE_OUT_CURRENT_360u 0x3
  287. #define SGTL5000_LINE_OUT_CURRENT_450u 0x7
  288. #define SGTL5000_LINE_OUT_CURRENT_540u 0xf
  289. #define SGTL5000_LINE_OUT_GND_MASK 0x003f
  290. #define SGTL5000_LINE_OUT_GND_SHIFT 0
  291. #define SGTL5000_LINE_OUT_GND_WIDTH 6
  292. #define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */
  293. #define SGTL5000_LINE_OUT_GND_STP 25
  294. #define SGTL5000_LINE_OUT_GND_MAX 0x23
  295. /*
  296. * SGTL5000_CHIP_LINE_OUT_VOL
  297. */
  298. #define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00
  299. #define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8
  300. #define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5
  301. #define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f
  302. #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0
  303. #define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5
  304. /*
  305. * SGTL5000_CHIP_ANA_POWER
  306. */
  307. #define SGTL5000_ANA_POWER_DEFAULT 0x7060
  308. #define SGTL5000_DAC_STEREO 0x4000
  309. #define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000
  310. #define SGTL5000_STARTUP_POWERUP 0x1000
  311. #define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800
  312. #define SGTL5000_PLL_POWERUP 0x0400
  313. #define SGTL5000_LINEREG_D_POWERUP 0x0200
  314. #define SGTL5000_VCOAMP_POWERUP 0x0100
  315. #define SGTL5000_VAG_POWERUP 0x0080
  316. #define SGTL5000_ADC_STEREO 0x0040
  317. #define SGTL5000_REFTOP_POWERUP 0x0020
  318. #define SGTL5000_HP_POWERUP 0x0010
  319. #define SGTL5000_DAC_POWERUP 0x0008
  320. #define SGTL5000_CAPLESS_HP_POWERUP 0x0004
  321. #define SGTL5000_ADC_POWERUP 0x0002
  322. #define SGTL5000_LINE_OUT_POWERUP 0x0001
  323. /*
  324. * SGTL5000_CHIP_PLL_CTRL
  325. */
  326. #define SGTL5000_PLL_INT_DIV_MASK 0xf800
  327. #define SGTL5000_PLL_INT_DIV_SHIFT 11
  328. #define SGTL5000_PLL_INT_DIV_WIDTH 5
  329. #define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
  330. #define SGTL5000_PLL_FRAC_DIV_SHIFT 0
  331. #define SGTL5000_PLL_FRAC_DIV_WIDTH 11
  332. /*
  333. * SGTL5000_CHIP_CLK_TOP_CTRL
  334. */
  335. #define SGTL5000_INT_OSC_EN 0x0800
  336. #define SGTL5000_INPUT_FREQ_DIV2 0x0008
  337. /*
  338. * SGTL5000_CHIP_ANA_STATUS
  339. */
  340. #define SGTL5000_HP_LRSHORT 0x0200
  341. #define SGTL5000_CAPLESS_SHORT 0x0100
  342. #define SGTL5000_PLL_LOCKED 0x0010
  343. /*
  344. * SGTL5000_CHIP_SHORT_CTRL
  345. */
  346. #define SGTL5000_LVLADJR_MASK 0x7000
  347. #define SGTL5000_LVLADJR_SHIFT 12
  348. #define SGTL5000_LVLADJR_WIDTH 3
  349. #define SGTL5000_LVLADJL_MASK 0x0700
  350. #define SGTL5000_LVLADJL_SHIFT 8
  351. #define SGTL5000_LVLADJL_WIDTH 3
  352. #define SGTL5000_LVLADJC_MASK 0x0070
  353. #define SGTL5000_LVLADJC_SHIFT 4
  354. #define SGTL5000_LVLADJC_WIDTH 3
  355. #define SGTL5000_LR_SHORT_MOD_MASK 0x000c
  356. #define SGTL5000_LR_SHORT_MOD_SHIFT 2
  357. #define SGTL5000_LR_SHORT_MOD_WIDTH 2
  358. #define SGTL5000_CM_SHORT_MOD_MASK 0x0003
  359. #define SGTL5000_CM_SHORT_MOD_SHIFT 0
  360. #define SGTL5000_CM_SHORT_MOD_WIDTH 2
  361. /*
  362. *SGTL5000_CHIP_ANA_TEST2
  363. */
  364. #define SGTL5000_MONO_DAC 0x1000
  365. /*
  366. * SGTL5000_DAP_CTRL
  367. */
  368. #define SGTL5000_DAP_MIX_EN 0x0010
  369. #define SGTL5000_DAP_EN 0x0001
  370. #define SGTL5000_SYSCLK 0x00
  371. #define SGTL5000_LRCLK 0x01
  372. /*
  373. * SGTL5000_DAP_AUDIO_EQ
  374. */
  375. #define SGTL5000_DAP_SEL_PEQ 1
  376. #define SGTL5000_DAP_SEL_TONE_CTRL 2
  377. #define SGTL5000_DAP_SEL_GEQ 3
  378. #endif