rt715.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * rt715.c -- rt715 ALSA SoC audio driver
  4. *
  5. * Copyright(c) 2019 Realtek Semiconductor Corp.
  6. *
  7. * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
  8. *
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/i2c.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/pm.h>
  17. #include <linux/soundwire/sdw.h>
  18. #include <linux/gpio.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/gpio/consumer.h>
  24. #include <linux/of.h>
  25. #include <linux/of_gpio.h>
  26. #include <linux/of_device.h>
  27. #include <sound/core.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include <sound/soc.h>
  31. #include <sound/soc-dapm.h>
  32. #include <sound/initval.h>
  33. #include <sound/tlv.h>
  34. #include <sound/hda_verbs.h>
  35. #include "rt715.h"
  36. static int rt715_index_write(struct regmap *regmap, unsigned int reg,
  37. unsigned int value)
  38. {
  39. int ret;
  40. unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
  41. ret = regmap_write(regmap, addr, value);
  42. if (ret < 0) {
  43. pr_err("Failed to set private value: %08x <= %04x %d\n", ret,
  44. addr, value);
  45. }
  46. return ret;
  47. }
  48. static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
  49. unsigned int addr_l, unsigned int val_h,
  50. unsigned int *r_val, unsigned int *l_val)
  51. {
  52. int ret;
  53. /* R Channel */
  54. *r_val = (val_h << 8);
  55. ret = regmap_read(rt715->regmap, addr_l, r_val);
  56. if (ret < 0)
  57. pr_err("Failed to get R channel gain.\n");
  58. /* L Channel */
  59. val_h |= 0x20;
  60. *l_val = (val_h << 8);
  61. ret = regmap_read(rt715->regmap, addr_h, l_val);
  62. if (ret < 0)
  63. pr_err("Failed to get L channel gain.\n");
  64. }
  65. /* For Verb-Set Amplifier Gain (Verb ID = 3h) */
  66. static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
  67. struct snd_ctl_elem_value *ucontrol)
  68. {
  69. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  70. struct snd_soc_dapm_context *dapm =
  71. snd_soc_component_get_dapm(component);
  72. struct soc_mixer_control *mc =
  73. (struct soc_mixer_control *)kcontrol->private_value;
  74. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  75. unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
  76. unsigned int read_ll, read_rl;
  77. int i;
  78. /* Can't use update bit function, so read the original value first */
  79. addr_h = mc->reg;
  80. addr_l = mc->rreg;
  81. if (mc->shift == RT715_DIR_OUT_SFT) /* output */
  82. val_h = 0x80;
  83. else /* input */
  84. val_h = 0x0;
  85. rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
  86. /* L Channel */
  87. if (mc->invert) {
  88. /* for mute */
  89. val_ll = (mc->max - ucontrol->value.integer.value[0]) << 7;
  90. /* keep gain */
  91. read_ll = read_ll & 0x7f;
  92. val_ll |= read_ll;
  93. } else {
  94. /* for gain */
  95. val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
  96. if (val_ll > mc->max)
  97. val_ll = mc->max;
  98. /* keep mute status */
  99. read_ll = read_ll & 0x80;
  100. val_ll |= read_ll;
  101. }
  102. /* R Channel */
  103. if (mc->invert) {
  104. regmap_write(rt715->regmap,
  105. RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
  106. /* for mute */
  107. val_lr = (mc->max - ucontrol->value.integer.value[1]) << 7;
  108. /* keep gain */
  109. read_rl = read_rl & 0x7f;
  110. val_lr |= read_rl;
  111. } else {
  112. /* for gain */
  113. val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
  114. if (val_lr > mc->max)
  115. val_lr = mc->max;
  116. /* keep mute status */
  117. read_rl = read_rl & 0x80;
  118. val_lr |= read_rl;
  119. }
  120. for (i = 0; i < 3; i++) { /* retry 3 times at most */
  121. if (val_ll == val_lr) {
  122. /* Set both L/R channels at the same time */
  123. val_h = (1 << mc->shift) | (3 << 4);
  124. regmap_write(rt715->regmap, addr_h,
  125. (val_h << 8 | val_ll));
  126. regmap_write(rt715->regmap, addr_l,
  127. (val_h << 8 | val_ll));
  128. } else {
  129. /* Lch*/
  130. val_h = (1 << mc->shift) | (1 << 5);
  131. regmap_write(rt715->regmap, addr_h,
  132. (val_h << 8 | val_ll));
  133. /* Rch */
  134. val_h = (1 << mc->shift) | (1 << 4);
  135. regmap_write(rt715->regmap, addr_l,
  136. (val_h << 8 | val_lr));
  137. }
  138. /* check result */
  139. if (mc->shift == RT715_DIR_OUT_SFT) /* output */
  140. val_h = 0x80;
  141. else /* input */
  142. val_h = 0x0;
  143. rt715_get_gain(rt715, addr_h, addr_l, val_h,
  144. &read_rl, &read_ll);
  145. if (read_rl == val_lr && read_ll == val_ll)
  146. break;
  147. }
  148. /* D0:power on state, D3: power saving mode */
  149. if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
  150. regmap_write(rt715->regmap,
  151. RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
  152. return 0;
  153. }
  154. static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
  155. struct snd_ctl_elem_value *ucontrol)
  156. {
  157. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  158. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  159. struct soc_mixer_control *mc =
  160. (struct soc_mixer_control *)kcontrol->private_value;
  161. unsigned int addr_h, addr_l, val_h;
  162. unsigned int read_ll, read_rl;
  163. addr_h = mc->reg;
  164. addr_l = mc->rreg;
  165. if (mc->shift == RT715_DIR_OUT_SFT) /* output */
  166. val_h = 0x80;
  167. else /* input */
  168. val_h = 0x0;
  169. rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
  170. if (mc->invert) {
  171. /* for mute status */
  172. read_ll = !((read_ll & 0x80) >> RT715_MUTE_SFT);
  173. read_rl = !((read_rl & 0x80) >> RT715_MUTE_SFT);
  174. } else {
  175. /* for gain */
  176. read_ll = read_ll & 0x7f;
  177. read_rl = read_rl & 0x7f;
  178. }
  179. ucontrol->value.integer.value[0] = read_ll;
  180. ucontrol->value.integer.value[1] = read_rl;
  181. return 0;
  182. }
  183. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
  184. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  185. #define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
  186. xhandler_get, xhandler_put) \
  187. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  188. .info = snd_soc_info_volsw, \
  189. .get = xhandler_get, .put = xhandler_put, \
  190. .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
  191. xmax, xinvert) }
  192. static const struct snd_kcontrol_new rt715_snd_controls[] = {
  193. /* Capture switch */
  194. SOC_DOUBLE_R_EXT("ADC 07 Capture Switch", RT715_SET_GAIN_MIC_ADC_H,
  195. RT715_SET_GAIN_MIC_ADC_L, RT715_DIR_IN_SFT, 1, 1,
  196. rt715_set_amp_gain_get, rt715_set_amp_gain_put),
  197. SOC_DOUBLE_R_EXT("ADC 08 Capture Switch", RT715_SET_GAIN_LINE_ADC_H,
  198. RT715_SET_GAIN_LINE_ADC_L, RT715_DIR_IN_SFT, 1, 1,
  199. rt715_set_amp_gain_get, rt715_set_amp_gain_put),
  200. SOC_DOUBLE_R_EXT("ADC 09 Capture Switch", RT715_SET_GAIN_MIX_ADC_H,
  201. RT715_SET_GAIN_MIX_ADC_L, RT715_DIR_IN_SFT, 1, 1,
  202. rt715_set_amp_gain_get, rt715_set_amp_gain_put),
  203. SOC_DOUBLE_R_EXT("ADC 27 Capture Switch", RT715_SET_GAIN_MIX_ADC2_H,
  204. RT715_SET_GAIN_MIX_ADC2_L, RT715_DIR_IN_SFT, 1, 1,
  205. rt715_set_amp_gain_get, rt715_set_amp_gain_put),
  206. /* Volume Control */
  207. SOC_DOUBLE_R_EXT_TLV("ADC 07 Capture Volume", RT715_SET_GAIN_MIC_ADC_H,
  208. RT715_SET_GAIN_MIC_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
  209. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  210. in_vol_tlv),
  211. SOC_DOUBLE_R_EXT_TLV("ADC 08 Capture Volume", RT715_SET_GAIN_LINE_ADC_H,
  212. RT715_SET_GAIN_LINE_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
  213. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  214. in_vol_tlv),
  215. SOC_DOUBLE_R_EXT_TLV("ADC 09 Capture Volume", RT715_SET_GAIN_MIX_ADC_H,
  216. RT715_SET_GAIN_MIX_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
  217. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  218. in_vol_tlv),
  219. SOC_DOUBLE_R_EXT_TLV("ADC 27 Capture Volume", RT715_SET_GAIN_MIX_ADC2_H,
  220. RT715_SET_GAIN_MIX_ADC2_L, RT715_DIR_IN_SFT, 0x3f, 0,
  221. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  222. in_vol_tlv),
  223. /* MIC Boost Control */
  224. SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
  225. RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
  226. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  227. mic_vol_tlv),
  228. SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
  229. RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
  230. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  231. mic_vol_tlv),
  232. SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
  233. RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
  234. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  235. mic_vol_tlv),
  236. SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
  237. RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
  238. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  239. mic_vol_tlv),
  240. SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
  241. RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
  242. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  243. mic_vol_tlv),
  244. SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
  245. RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
  246. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  247. mic_vol_tlv),
  248. SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
  249. RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
  250. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  251. mic_vol_tlv),
  252. SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
  253. RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
  254. rt715_set_amp_gain_get, rt715_set_amp_gain_put,
  255. mic_vol_tlv),
  256. };
  257. static int rt715_mux_get(struct snd_kcontrol *kcontrol,
  258. struct snd_ctl_elem_value *ucontrol)
  259. {
  260. struct snd_soc_component *component =
  261. snd_soc_dapm_kcontrol_component(kcontrol);
  262. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  263. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  264. unsigned int reg, val;
  265. int ret;
  266. /* nid = e->reg, vid = 0xf01 */
  267. reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
  268. ret = regmap_read(rt715->regmap, reg, &val);
  269. if (ret < 0) {
  270. dev_err(component->dev, "%s: sdw read failed: %d\n",
  271. __func__, ret);
  272. return ret;
  273. }
  274. /*
  275. * The first two indices of ADC Mux 24/25 are routed to the same
  276. * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
  277. * To have a unique set of inputs, we skip the index1 of the muxes.
  278. */
  279. if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
  280. val -= 1;
  281. ucontrol->value.enumerated.item[0] = val;
  282. return 0;
  283. }
  284. static int rt715_mux_put(struct snd_kcontrol *kcontrol,
  285. struct snd_ctl_elem_value *ucontrol)
  286. {
  287. struct snd_soc_component *component =
  288. snd_soc_dapm_kcontrol_component(kcontrol);
  289. struct snd_soc_dapm_context *dapm =
  290. snd_soc_dapm_kcontrol_dapm(kcontrol);
  291. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  292. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  293. unsigned int *item = ucontrol->value.enumerated.item;
  294. unsigned int val, val2 = 0, change, reg;
  295. int ret;
  296. if (item[0] >= e->items)
  297. return -EINVAL;
  298. /* Verb ID = 0x701h, nid = e->reg */
  299. val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
  300. reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
  301. ret = regmap_read(rt715->regmap, reg, &val2);
  302. if (ret < 0) {
  303. dev_err(component->dev, "%s: sdw read failed: %d\n",
  304. __func__, ret);
  305. return ret;
  306. }
  307. if (val == val2)
  308. change = 0;
  309. else
  310. change = 1;
  311. if (change) {
  312. reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
  313. regmap_write(rt715->regmap, reg, val);
  314. }
  315. snd_soc_dapm_mux_update_power(dapm, kcontrol,
  316. item[0], e, NULL);
  317. return change;
  318. }
  319. static const char * const adc_22_23_mux_text[] = {
  320. "MIC1",
  321. "MIC2",
  322. "LINE1",
  323. "LINE2",
  324. "DMIC1",
  325. "DMIC2",
  326. "DMIC3",
  327. "DMIC4",
  328. };
  329. /*
  330. * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
  331. * 1 will be connected to the same dmic source, therefore we skip index 1 to
  332. * avoid misunderstanding on usage of dapm routing.
  333. */
  334. static const unsigned int rt715_adc_24_25_values[] = {
  335. 0,
  336. 2,
  337. 3,
  338. 4,
  339. 5,
  340. };
  341. static const char * const adc_24_mux_text[] = {
  342. "MIC2",
  343. "DMIC1",
  344. "DMIC2",
  345. "DMIC3",
  346. "DMIC4",
  347. };
  348. static const char * const adc_25_mux_text[] = {
  349. "MIC1",
  350. "DMIC1",
  351. "DMIC2",
  352. "DMIC3",
  353. "DMIC4",
  354. };
  355. static SOC_ENUM_SINGLE_DECL(
  356. rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
  357. static SOC_ENUM_SINGLE_DECL(
  358. rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
  359. static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
  360. RT715_MUX_IN3, 0, 0xf,
  361. adc_24_mux_text, rt715_adc_24_25_values);
  362. static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
  363. RT715_MUX_IN4, 0, 0xf,
  364. adc_25_mux_text, rt715_adc_24_25_values);
  365. static const struct snd_kcontrol_new rt715_adc22_mux =
  366. SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
  367. rt715_mux_get, rt715_mux_put);
  368. static const struct snd_kcontrol_new rt715_adc23_mux =
  369. SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
  370. rt715_mux_get, rt715_mux_put);
  371. static const struct snd_kcontrol_new rt715_adc24_mux =
  372. SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
  373. rt715_mux_get, rt715_mux_put);
  374. static const struct snd_kcontrol_new rt715_adc25_mux =
  375. SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
  376. rt715_mux_get, rt715_mux_put);
  377. static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
  378. SND_SOC_DAPM_INPUT("DMIC1"),
  379. SND_SOC_DAPM_INPUT("DMIC2"),
  380. SND_SOC_DAPM_INPUT("DMIC3"),
  381. SND_SOC_DAPM_INPUT("DMIC4"),
  382. SND_SOC_DAPM_INPUT("MIC1"),
  383. SND_SOC_DAPM_INPUT("MIC2"),
  384. SND_SOC_DAPM_INPUT("LINE1"),
  385. SND_SOC_DAPM_INPUT("LINE2"),
  386. SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
  387. SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
  388. SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
  389. SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
  390. SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
  391. &rt715_adc22_mux),
  392. SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
  393. &rt715_adc23_mux),
  394. SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
  395. &rt715_adc24_mux),
  396. SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
  397. &rt715_adc25_mux),
  398. SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
  399. SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
  400. };
  401. static const struct snd_soc_dapm_route rt715_audio_map[] = {
  402. {"DP6TX", NULL, "ADC 09"},
  403. {"DP6TX", NULL, "ADC 08"},
  404. {"DP4TX", NULL, "ADC 07"},
  405. {"DP4TX", NULL, "ADC 27"},
  406. {"ADC 09", NULL, "ADC 22 Mux"},
  407. {"ADC 08", NULL, "ADC 23 Mux"},
  408. {"ADC 07", NULL, "ADC 24 Mux"},
  409. {"ADC 27", NULL, "ADC 25 Mux"},
  410. {"ADC 22 Mux", "MIC1", "MIC1"},
  411. {"ADC 22 Mux", "MIC2", "MIC2"},
  412. {"ADC 22 Mux", "LINE1", "LINE1"},
  413. {"ADC 22 Mux", "LINE2", "LINE2"},
  414. {"ADC 22 Mux", "DMIC1", "DMIC1"},
  415. {"ADC 22 Mux", "DMIC2", "DMIC2"},
  416. {"ADC 22 Mux", "DMIC3", "DMIC3"},
  417. {"ADC 22 Mux", "DMIC4", "DMIC4"},
  418. {"ADC 23 Mux", "MIC1", "MIC1"},
  419. {"ADC 23 Mux", "MIC2", "MIC2"},
  420. {"ADC 23 Mux", "LINE1", "LINE1"},
  421. {"ADC 23 Mux", "LINE2", "LINE2"},
  422. {"ADC 23 Mux", "DMIC1", "DMIC1"},
  423. {"ADC 23 Mux", "DMIC2", "DMIC2"},
  424. {"ADC 23 Mux", "DMIC3", "DMIC3"},
  425. {"ADC 23 Mux", "DMIC4", "DMIC4"},
  426. {"ADC 24 Mux", "MIC2", "MIC2"},
  427. {"ADC 24 Mux", "DMIC1", "DMIC1"},
  428. {"ADC 24 Mux", "DMIC2", "DMIC2"},
  429. {"ADC 24 Mux", "DMIC3", "DMIC3"},
  430. {"ADC 24 Mux", "DMIC4", "DMIC4"},
  431. {"ADC 25 Mux", "MIC1", "MIC1"},
  432. {"ADC 25 Mux", "DMIC1", "DMIC1"},
  433. {"ADC 25 Mux", "DMIC2", "DMIC2"},
  434. {"ADC 25 Mux", "DMIC3", "DMIC3"},
  435. {"ADC 25 Mux", "DMIC4", "DMIC4"},
  436. };
  437. static int rt715_set_bias_level(struct snd_soc_component *component,
  438. enum snd_soc_bias_level level)
  439. {
  440. struct snd_soc_dapm_context *dapm =
  441. snd_soc_component_get_dapm(component);
  442. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  443. switch (level) {
  444. case SND_SOC_BIAS_PREPARE:
  445. if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
  446. regmap_write(rt715->regmap,
  447. RT715_SET_AUDIO_POWER_STATE,
  448. AC_PWRST_D0);
  449. msleep(RT715_POWER_UP_DELAY_MS);
  450. }
  451. break;
  452. case SND_SOC_BIAS_STANDBY:
  453. regmap_write(rt715->regmap,
  454. RT715_SET_AUDIO_POWER_STATE,
  455. AC_PWRST_D3);
  456. break;
  457. default:
  458. break;
  459. }
  460. dapm->bias_level = level;
  461. return 0;
  462. }
  463. static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
  464. .set_bias_level = rt715_set_bias_level,
  465. .controls = rt715_snd_controls,
  466. .num_controls = ARRAY_SIZE(rt715_snd_controls),
  467. .dapm_widgets = rt715_dapm_widgets,
  468. .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
  469. .dapm_routes = rt715_audio_map,
  470. .num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
  471. };
  472. static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
  473. int direction)
  474. {
  475. struct sdw_stream_data *stream;
  476. if (!sdw_stream)
  477. return 0;
  478. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  479. if (!stream)
  480. return -ENOMEM;
  481. stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream;
  482. /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
  483. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  484. dai->playback_dma_data = stream;
  485. else
  486. dai->capture_dma_data = stream;
  487. return 0;
  488. }
  489. static void rt715_shutdown(struct snd_pcm_substream *substream,
  490. struct snd_soc_dai *dai)
  491. {
  492. struct sdw_stream_data *stream;
  493. stream = snd_soc_dai_get_dma_data(dai, substream);
  494. snd_soc_dai_set_dma_data(dai, substream, NULL);
  495. kfree(stream);
  496. }
  497. static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
  498. struct snd_pcm_hw_params *params,
  499. struct snd_soc_dai *dai)
  500. {
  501. struct snd_soc_component *component = dai->component;
  502. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  503. struct sdw_stream_config stream_config;
  504. struct sdw_port_config port_config;
  505. enum sdw_data_direction direction;
  506. struct sdw_stream_data *stream;
  507. int retval, port, num_channels;
  508. unsigned int val = 0;
  509. stream = snd_soc_dai_get_dma_data(dai, substream);
  510. if (!stream)
  511. return -EINVAL;
  512. if (!rt715->slave)
  513. return -EINVAL;
  514. switch (dai->id) {
  515. case RT715_AIF1:
  516. direction = SDW_DATA_DIR_TX;
  517. port = 6;
  518. rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
  519. break;
  520. case RT715_AIF2:
  521. direction = SDW_DATA_DIR_TX;
  522. port = 4;
  523. rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
  524. break;
  525. default:
  526. dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
  527. return -EINVAL;
  528. }
  529. stream_config.frame_rate = params_rate(params);
  530. stream_config.ch_count = params_channels(params);
  531. stream_config.bps = snd_pcm_format_width(params_format(params));
  532. stream_config.direction = direction;
  533. num_channels = params_channels(params);
  534. port_config.ch_mask = (1 << (num_channels)) - 1;
  535. port_config.num = port;
  536. retval = sdw_stream_add_slave(rt715->slave, &stream_config,
  537. &port_config, 1, stream->sdw_stream);
  538. if (retval) {
  539. dev_err(dai->dev, "Unable to configure port\n");
  540. return retval;
  541. }
  542. switch (params_rate(params)) {
  543. /* bit 14 0:48K 1:44.1K */
  544. /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
  545. case 44100:
  546. val |= 0x40 << 8;
  547. break;
  548. case 48000:
  549. val |= 0x0 << 8;
  550. break;
  551. default:
  552. dev_err(component->dev, "Unsupported sample rate %d\n",
  553. params_rate(params));
  554. return -EINVAL;
  555. }
  556. if (params_channels(params) <= 16) {
  557. /* bit 3:0 Number of Channel */
  558. val |= (params_channels(params) - 1);
  559. } else {
  560. dev_err(component->dev, "Unsupported channels %d\n",
  561. params_channels(params));
  562. return -EINVAL;
  563. }
  564. switch (params_width(params)) {
  565. /* bit 6:4 Bits per Sample */
  566. case 8:
  567. break;
  568. case 16:
  569. val |= (0x1 << 4);
  570. break;
  571. case 20:
  572. val |= (0x2 << 4);
  573. break;
  574. case 24:
  575. val |= (0x3 << 4);
  576. break;
  577. case 32:
  578. val |= (0x4 << 4);
  579. break;
  580. default:
  581. return -EINVAL;
  582. }
  583. regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
  584. regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
  585. regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
  586. regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
  587. return retval;
  588. }
  589. static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
  590. struct snd_soc_dai *dai)
  591. {
  592. struct snd_soc_component *component = dai->component;
  593. struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
  594. struct sdw_stream_data *stream =
  595. snd_soc_dai_get_dma_data(dai, substream);
  596. if (!rt715->slave)
  597. return -EINVAL;
  598. sdw_stream_remove_slave(rt715->slave, stream->sdw_stream);
  599. return 0;
  600. }
  601. #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  602. #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  603. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  604. static struct snd_soc_dai_ops rt715_ops = {
  605. .hw_params = rt715_pcm_hw_params,
  606. .hw_free = rt715_pcm_hw_free,
  607. .set_sdw_stream = rt715_set_sdw_stream,
  608. .shutdown = rt715_shutdown,
  609. };
  610. static struct snd_soc_dai_driver rt715_dai[] = {
  611. {
  612. .name = "rt715-aif1",
  613. .id = RT715_AIF1,
  614. .capture = {
  615. .stream_name = "DP6 Capture",
  616. .channels_min = 1,
  617. .channels_max = 2,
  618. .rates = RT715_STEREO_RATES,
  619. .formats = RT715_FORMATS,
  620. },
  621. .ops = &rt715_ops,
  622. },
  623. {
  624. .name = "rt715-aif2",
  625. .id = RT715_AIF2,
  626. .capture = {
  627. .stream_name = "DP4 Capture",
  628. .channels_min = 1,
  629. .channels_max = 2,
  630. .rates = RT715_STEREO_RATES,
  631. .formats = RT715_FORMATS,
  632. },
  633. .ops = &rt715_ops,
  634. },
  635. };
  636. /* Bus clock frequency */
  637. #define RT715_CLK_FREQ_9600000HZ 9600000
  638. #define RT715_CLK_FREQ_12000000HZ 12000000
  639. #define RT715_CLK_FREQ_6000000HZ 6000000
  640. #define RT715_CLK_FREQ_4800000HZ 4800000
  641. #define RT715_CLK_FREQ_2400000HZ 2400000
  642. #define RT715_CLK_FREQ_12288000HZ 12288000
  643. int rt715_clock_config(struct device *dev)
  644. {
  645. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  646. unsigned int clk_freq, value;
  647. clk_freq = (rt715->params.curr_dr_freq >> 1);
  648. switch (clk_freq) {
  649. case RT715_CLK_FREQ_12000000HZ:
  650. value = 0x0;
  651. break;
  652. case RT715_CLK_FREQ_6000000HZ:
  653. value = 0x1;
  654. break;
  655. case RT715_CLK_FREQ_9600000HZ:
  656. value = 0x2;
  657. break;
  658. case RT715_CLK_FREQ_4800000HZ:
  659. value = 0x3;
  660. break;
  661. case RT715_CLK_FREQ_2400000HZ:
  662. value = 0x4;
  663. break;
  664. case RT715_CLK_FREQ_12288000HZ:
  665. value = 0x5;
  666. break;
  667. default:
  668. return -EINVAL;
  669. }
  670. regmap_write(rt715->regmap, 0xe0, value);
  671. regmap_write(rt715->regmap, 0xf0, value);
  672. return 0;
  673. }
  674. int rt715_init(struct device *dev, struct regmap *sdw_regmap,
  675. struct regmap *regmap, struct sdw_slave *slave)
  676. {
  677. struct rt715_priv *rt715;
  678. int ret;
  679. rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
  680. if (!rt715)
  681. return -ENOMEM;
  682. dev_set_drvdata(dev, rt715);
  683. rt715->slave = slave;
  684. rt715->regmap = regmap;
  685. rt715->sdw_regmap = sdw_regmap;
  686. /*
  687. * Mark hw_init to false
  688. * HW init will be performed when device reports present
  689. */
  690. rt715->hw_init = false;
  691. rt715->first_hw_init = false;
  692. ret = devm_snd_soc_register_component(dev,
  693. &soc_codec_dev_rt715,
  694. rt715_dai,
  695. ARRAY_SIZE(rt715_dai));
  696. return ret;
  697. }
  698. int rt715_io_init(struct device *dev, struct sdw_slave *slave)
  699. {
  700. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  701. if (rt715->hw_init)
  702. return 0;
  703. /*
  704. * PM runtime is only enabled when a Slave reports as Attached
  705. */
  706. if (!rt715->first_hw_init) {
  707. /* set autosuspend parameters */
  708. pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
  709. pm_runtime_use_autosuspend(&slave->dev);
  710. /* update count of parent 'active' children */
  711. pm_runtime_set_active(&slave->dev);
  712. /* make sure the device does not suspend immediately */
  713. pm_runtime_mark_last_busy(&slave->dev);
  714. pm_runtime_enable(&slave->dev);
  715. }
  716. pm_runtime_get_noresume(&slave->dev);
  717. /* Mute nid=08h/09h */
  718. regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
  719. regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
  720. /* Mute nid=07h/27h */
  721. regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
  722. regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
  723. /* Set Pin Widget */
  724. regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
  725. regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
  726. regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
  727. regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
  728. /* Set Converter Stream */
  729. regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
  730. regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
  731. regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
  732. regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
  733. /* Set Configuration Default */
  734. regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
  735. regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
  736. regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
  737. regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
  738. regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
  739. regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
  740. regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
  741. regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
  742. regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
  743. regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
  744. regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
  745. regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
  746. regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
  747. regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
  748. regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
  749. regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
  750. /* Finish Initial Settings, set power to D3 */
  751. regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
  752. if (rt715->first_hw_init)
  753. regcache_mark_dirty(rt715->regmap);
  754. else
  755. rt715->first_hw_init = true;
  756. /* Mark Slave initialization complete */
  757. rt715->hw_init = true;
  758. pm_runtime_mark_last_busy(&slave->dev);
  759. pm_runtime_put_autosuspend(&slave->dev);
  760. return 0;
  761. }
  762. MODULE_DESCRIPTION("ASoC rt715 driver");
  763. MODULE_DESCRIPTION("ASoC rt715 driver SDW");
  764. MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
  765. MODULE_LICENSE("GPL v2");