rt715-sdw.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * rt715-sdw.c -- rt715 ALSA SoC audio driver
  4. *
  5. * Copyright(c) 2019 Realtek Semiconductor Corp.
  6. *
  7. * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
  8. *
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/mod_devicetable.h>
  13. #include <linux/soundwire/sdw.h>
  14. #include <linux/soundwire/sdw_type.h>
  15. #include <linux/soundwire/sdw_registers.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/regmap.h>
  19. #include <sound/soc.h>
  20. #include "rt715.h"
  21. #include "rt715-sdw.h"
  22. static bool rt715_readable_register(struct device *dev, unsigned int reg)
  23. {
  24. switch (reg) {
  25. case 0x00e0 ... 0x00e5:
  26. case 0x00ee ... 0x00ef:
  27. case 0x00f0 ... 0x00f5:
  28. case 0x00fe ... 0x00ff:
  29. case 0x02e0:
  30. case 0x02f0:
  31. case 0x04e0:
  32. case 0x04f0:
  33. case 0x06e0:
  34. case 0x06f0:
  35. case 0x2000 ... 0x2016:
  36. case 0x201a ... 0x2027:
  37. case 0x2029 ... 0x202a:
  38. case 0x202d ... 0x2034:
  39. case 0x2200 ... 0x2204:
  40. case 0x2206 ... 0x2212:
  41. case 0x2220 ... 0x2223:
  42. case 0x2230 ... 0x2239:
  43. case 0x22f0 ... 0x22f3:
  44. case 0x3122:
  45. case 0x3123:
  46. case 0x3124:
  47. case 0x3125:
  48. case 0x3607:
  49. case 0x3608:
  50. case 0x3609:
  51. case 0x3610:
  52. case 0x3611:
  53. case 0x3627:
  54. case 0x3712:
  55. case 0x3713:
  56. case 0x3718:
  57. case 0x3719:
  58. case 0x371a:
  59. case 0x371b:
  60. case 0x371d:
  61. case 0x3729:
  62. case 0x385e:
  63. case 0x3859:
  64. case 0x4c12:
  65. case 0x4c13:
  66. case 0x4c1d:
  67. case 0x4c29:
  68. case 0x4d12:
  69. case 0x4d13:
  70. case 0x4d1d:
  71. case 0x4d29:
  72. case 0x4e12:
  73. case 0x4e13:
  74. case 0x4e1d:
  75. case 0x4e29:
  76. case 0x4f12:
  77. case 0x4f13:
  78. case 0x4f1d:
  79. case 0x4f29:
  80. case 0x7207:
  81. case 0x7208:
  82. case 0x7209:
  83. case 0x7227:
  84. case 0x7307:
  85. case 0x7308:
  86. case 0x7309:
  87. case 0x7312:
  88. case 0x7313:
  89. case 0x7318:
  90. case 0x7319:
  91. case 0x731a:
  92. case 0x731b:
  93. case 0x731d:
  94. case 0x7327:
  95. case 0x7329:
  96. case 0x8287:
  97. case 0x8288:
  98. case 0x8289:
  99. case 0x82a7:
  100. case 0x8387:
  101. case 0x8388:
  102. case 0x8389:
  103. case 0x8392:
  104. case 0x8393:
  105. case 0x8398:
  106. case 0x8399:
  107. case 0x839a:
  108. case 0x839b:
  109. case 0x839d:
  110. case 0x83a7:
  111. case 0x83a9:
  112. case 0x752039:
  113. return true;
  114. default:
  115. return false;
  116. }
  117. }
  118. static bool rt715_volatile_register(struct device *dev, unsigned int reg)
  119. {
  120. switch (reg) {
  121. case 0x00e5:
  122. case 0x00f0:
  123. case 0x00f3:
  124. case 0x00f5:
  125. case 0x2009:
  126. case 0x2016:
  127. case 0x201b:
  128. case 0x201c:
  129. case 0x201d:
  130. case 0x201f:
  131. case 0x2023:
  132. case 0x2230:
  133. case 0x200b ... 0x200e: /* i2c read */
  134. case 0x2012 ... 0x2015: /* HD-A read */
  135. case 0x202d ... 0x202f: /* BRA */
  136. case 0x2201 ... 0x2212: /* i2c debug */
  137. case 0x2220 ... 0x2223: /* decoded HD-A */
  138. return true;
  139. default:
  140. return false;
  141. }
  142. }
  143. static int rt715_sdw_read(void *context, unsigned int reg, unsigned int *val)
  144. {
  145. struct device *dev = context;
  146. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  147. unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
  148. unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
  149. unsigned int is_hda_reg = 1, is_index_reg = 0;
  150. int ret;
  151. if (reg > 0xffff)
  152. is_index_reg = 1;
  153. mask = reg & 0xf000;
  154. if (is_index_reg) { /* index registers */
  155. val2 = reg & 0xff;
  156. reg = reg >> 8;
  157. nid = reg & 0xff;
  158. ret = regmap_write(rt715->sdw_regmap, reg, 0);
  159. if (ret < 0)
  160. return ret;
  161. reg2 = reg + 0x1000;
  162. reg2 |= 0x80;
  163. ret = regmap_write(rt715->sdw_regmap, reg2, val2);
  164. if (ret < 0)
  165. return ret;
  166. reg3 = RT715_PRIV_DATA_R_H | nid;
  167. ret = regmap_write(rt715->sdw_regmap, reg3,
  168. ((*val >> 8) & 0xff));
  169. if (ret < 0)
  170. return ret;
  171. reg4 = reg3 + 0x1000;
  172. reg4 |= 0x80;
  173. ret = regmap_write(rt715->sdw_regmap, reg4, (*val & 0xff));
  174. if (ret < 0)
  175. return ret;
  176. } else if (mask == 0x3000) {
  177. reg += 0x8000;
  178. ret = regmap_write(rt715->sdw_regmap, reg, *val);
  179. if (ret < 0)
  180. return ret;
  181. } else if (mask == 0x7000) {
  182. reg += 0x2000;
  183. reg |= 0x800;
  184. ret = regmap_write(rt715->sdw_regmap, reg,
  185. ((*val >> 8) & 0xff));
  186. if (ret < 0)
  187. return ret;
  188. reg2 = reg + 0x1000;
  189. reg2 |= 0x80;
  190. ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
  191. if (ret < 0)
  192. return ret;
  193. } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
  194. reg2 = reg - 0x1000;
  195. reg2 &= ~0x80;
  196. ret = regmap_write(rt715->sdw_regmap, reg2,
  197. ((*val >> 8) & 0xff));
  198. if (ret < 0)
  199. return ret;
  200. ret = regmap_write(rt715->sdw_regmap, reg, (*val & 0xff));
  201. if (ret < 0)
  202. return ret;
  203. } else if (mask == 0x9000) {
  204. ret = regmap_write(rt715->sdw_regmap, reg,
  205. ((*val >> 8) & 0xff));
  206. if (ret < 0)
  207. return ret;
  208. reg2 = reg + 0x1000;
  209. reg2 |= 0x80;
  210. ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
  211. if (ret < 0)
  212. return ret;
  213. } else if (mask == 0xb000) {
  214. ret = regmap_write(rt715->sdw_regmap, reg, *val);
  215. if (ret < 0)
  216. return ret;
  217. } else {
  218. ret = regmap_read(rt715->sdw_regmap, reg, val);
  219. if (ret < 0)
  220. return ret;
  221. is_hda_reg = 0;
  222. }
  223. if (is_hda_reg || is_index_reg) {
  224. sdw_data_3 = 0;
  225. sdw_data_2 = 0;
  226. sdw_data_1 = 0;
  227. sdw_data_0 = 0;
  228. ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_3,
  229. &sdw_data_3);
  230. if (ret < 0)
  231. return ret;
  232. ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_2,
  233. &sdw_data_2);
  234. if (ret < 0)
  235. return ret;
  236. ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_1,
  237. &sdw_data_1);
  238. if (ret < 0)
  239. return ret;
  240. ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_0,
  241. &sdw_data_0);
  242. if (ret < 0)
  243. return ret;
  244. *val = ((sdw_data_3 & 0xff) << 24) |
  245. ((sdw_data_2 & 0xff) << 16) |
  246. ((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
  247. }
  248. if (is_hda_reg == 0)
  249. dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
  250. else if (is_index_reg)
  251. dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n", __func__,
  252. reg, reg2, reg3, reg4, *val);
  253. else
  254. dev_dbg(dev, "[%s] %04x %04x => %08x\n",
  255. __func__, reg, reg2, *val);
  256. return 0;
  257. }
  258. static int rt715_sdw_write(void *context, unsigned int reg, unsigned int val)
  259. {
  260. struct device *dev = context;
  261. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  262. unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
  263. unsigned int is_index_reg = 0;
  264. int ret;
  265. if (reg > 0xffff)
  266. is_index_reg = 1;
  267. mask = reg & 0xf000;
  268. if (is_index_reg) { /* index registers */
  269. val2 = reg & 0xff;
  270. reg = reg >> 8;
  271. nid = reg & 0xff;
  272. ret = regmap_write(rt715->sdw_regmap, reg, 0);
  273. if (ret < 0)
  274. return ret;
  275. reg2 = reg + 0x1000;
  276. reg2 |= 0x80;
  277. ret = regmap_write(rt715->sdw_regmap, reg2, val2);
  278. if (ret < 0)
  279. return ret;
  280. reg3 = RT715_PRIV_DATA_W_H | nid;
  281. ret = regmap_write(rt715->sdw_regmap, reg3,
  282. ((val >> 8) & 0xff));
  283. if (ret < 0)
  284. return ret;
  285. reg4 = reg3 + 0x1000;
  286. reg4 |= 0x80;
  287. ret = regmap_write(rt715->sdw_regmap, reg4, (val & 0xff));
  288. if (ret < 0)
  289. return ret;
  290. is_index_reg = 1;
  291. } else if (reg < 0x4fff) {
  292. ret = regmap_write(rt715->sdw_regmap, reg, val);
  293. if (ret < 0)
  294. return ret;
  295. } else if (reg == RT715_FUNC_RESET) {
  296. ret = regmap_write(rt715->sdw_regmap, reg, val);
  297. if (ret < 0)
  298. return ret;
  299. } else if (mask == 0x7000) {
  300. ret = regmap_write(rt715->sdw_regmap, reg,
  301. ((val >> 8) & 0xff));
  302. if (ret < 0)
  303. return ret;
  304. reg2 = reg + 0x1000;
  305. reg2 |= 0x80;
  306. ret = regmap_write(rt715->sdw_regmap, reg2, (val & 0xff));
  307. if (ret < 0)
  308. return ret;
  309. } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
  310. reg2 = reg - 0x1000;
  311. reg2 &= ~0x80;
  312. ret = regmap_write(rt715->sdw_regmap, reg2,
  313. ((val >> 8) & 0xff));
  314. if (ret < 0)
  315. return ret;
  316. ret = regmap_write(rt715->sdw_regmap, reg, (val & 0xff));
  317. if (ret < 0)
  318. return ret;
  319. }
  320. if (reg2 == 0)
  321. dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
  322. else if (is_index_reg)
  323. dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
  324. __func__, reg, reg2, reg3, reg4, val2, val);
  325. else
  326. dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
  327. __func__, reg, reg2, val);
  328. return 0;
  329. }
  330. static const struct regmap_config rt715_regmap = {
  331. .reg_bits = 24,
  332. .val_bits = 32,
  333. .readable_reg = rt715_readable_register, /* Readable registers */
  334. .volatile_reg = rt715_volatile_register, /* volatile register */
  335. .max_register = 0x752039, /* Maximum number of register */
  336. .reg_defaults = rt715_reg_defaults, /* Defaults */
  337. .num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults),
  338. .cache_type = REGCACHE_RBTREE,
  339. .use_single_read = true,
  340. .use_single_write = true,
  341. .reg_read = rt715_sdw_read,
  342. .reg_write = rt715_sdw_write,
  343. };
  344. static const struct regmap_config rt715_sdw_regmap = {
  345. .name = "sdw",
  346. .reg_bits = 32, /* Total register space for SDW */
  347. .val_bits = 8, /* Total number of bits in register */
  348. .max_register = 0xff01, /* Maximum number of register */
  349. .cache_type = REGCACHE_NONE,
  350. .use_single_read = true,
  351. .use_single_write = true,
  352. };
  353. int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
  354. unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
  355. unsigned int *sdw_addr_l, unsigned int *sdw_data_l)
  356. {
  357. unsigned int offset_h, offset_l, e_verb;
  358. if (((verb & 0xff) != 0) || verb == 0xf00) { /* 12 bits command */
  359. if (verb == 0x7ff) /* special case */
  360. offset_h = 0;
  361. else
  362. offset_h = 0x3000;
  363. if (verb & 0x800) /* get command */
  364. e_verb = (verb - 0xf00) | 0x80;
  365. else /* set command */
  366. e_verb = (verb - 0x700);
  367. *sdw_data_h = payload; /* 7 bits payload */
  368. *sdw_addr_l = *sdw_data_l = 0;
  369. } else { /* 4 bits command */
  370. if ((verb & 0x800) == 0x800) { /* read */
  371. offset_h = 0x9000;
  372. offset_l = 0xa000;
  373. } else { /* write */
  374. offset_h = 0x7000;
  375. offset_l = 0x8000;
  376. }
  377. e_verb = verb >> 8;
  378. *sdw_data_h = (payload >> 8); /* 16 bits payload [15:8] */
  379. *sdw_addr_l = (e_verb << 8) | nid | 0x80; /* 0x80: valid bit */
  380. *sdw_addr_l += offset_l;
  381. *sdw_data_l = payload & 0xff;
  382. }
  383. *sdw_addr_h = (e_verb << 8) | nid;
  384. *sdw_addr_h += offset_h;
  385. return 0;
  386. }
  387. EXPORT_SYMBOL(hda_to_sdw);
  388. static int rt715_update_status(struct sdw_slave *slave,
  389. enum sdw_slave_status status)
  390. {
  391. struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
  392. /* Update the status */
  393. rt715->status = status;
  394. /*
  395. * Perform initialization only if slave status is present and
  396. * hw_init flag is false
  397. */
  398. if (rt715->hw_init || rt715->status != SDW_SLAVE_ATTACHED)
  399. return 0;
  400. /* perform I/O transfers required for Slave initialization */
  401. return rt715_io_init(&slave->dev, slave);
  402. }
  403. static int rt715_read_prop(struct sdw_slave *slave)
  404. {
  405. struct sdw_slave_prop *prop = &slave->prop;
  406. int nval, i;
  407. u32 bit;
  408. unsigned long addr;
  409. struct sdw_dpn_prop *dpn;
  410. prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
  411. SDW_SCP_INT1_PARITY;
  412. prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
  413. prop->paging_support = false;
  414. /* first we need to allocate memory for set bits in port lists */
  415. prop->source_ports = 0x50;/* BITMAP: 01010000 */
  416. prop->sink_ports = 0x0; /* BITMAP: 00000000 */
  417. nval = hweight32(prop->source_ports);
  418. prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
  419. sizeof(*prop->src_dpn_prop),
  420. GFP_KERNEL);
  421. if (!prop->src_dpn_prop)
  422. return -ENOMEM;
  423. dpn = prop->src_dpn_prop;
  424. i = 0;
  425. addr = prop->source_ports;
  426. for_each_set_bit(bit, &addr, 32) {
  427. dpn[i].num = bit;
  428. dpn[i].simple_ch_prep_sm = true;
  429. dpn[i].ch_prep_timeout = 10;
  430. i++;
  431. }
  432. /* set the timeout values */
  433. prop->clk_stop_timeout = 20;
  434. /* wake-up event */
  435. prop->wake_capable = 1;
  436. return 0;
  437. }
  438. static int rt715_bus_config(struct sdw_slave *slave,
  439. struct sdw_bus_params *params)
  440. {
  441. struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
  442. int ret;
  443. memcpy(&rt715->params, params, sizeof(*params));
  444. ret = rt715_clock_config(&slave->dev);
  445. if (ret < 0)
  446. dev_err(&slave->dev, "Invalid clk config");
  447. return 0;
  448. }
  449. static struct sdw_slave_ops rt715_slave_ops = {
  450. .read_prop = rt715_read_prop,
  451. .update_status = rt715_update_status,
  452. .bus_config = rt715_bus_config,
  453. };
  454. static int rt715_sdw_probe(struct sdw_slave *slave,
  455. const struct sdw_device_id *id)
  456. {
  457. struct regmap *sdw_regmap, *regmap;
  458. /* Regmap Initialization */
  459. sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap);
  460. if (IS_ERR(sdw_regmap))
  461. return PTR_ERR(sdw_regmap);
  462. regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev,
  463. &rt715_regmap);
  464. if (IS_ERR(regmap))
  465. return PTR_ERR(regmap);
  466. rt715_init(&slave->dev, sdw_regmap, regmap, slave);
  467. return 0;
  468. }
  469. static const struct sdw_device_id rt715_id[] = {
  470. SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x2, 0, 0),
  471. SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x2, 0, 0),
  472. {},
  473. };
  474. MODULE_DEVICE_TABLE(sdw, rt715_id);
  475. static int __maybe_unused rt715_dev_suspend(struct device *dev)
  476. {
  477. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  478. if (!rt715->hw_init)
  479. return 0;
  480. regcache_cache_only(rt715->regmap, true);
  481. return 0;
  482. }
  483. #define RT715_PROBE_TIMEOUT 2000
  484. static int __maybe_unused rt715_dev_resume(struct device *dev)
  485. {
  486. struct sdw_slave *slave = dev_to_sdw_dev(dev);
  487. struct rt715_priv *rt715 = dev_get_drvdata(dev);
  488. unsigned long time;
  489. if (!rt715->first_hw_init)
  490. return 0;
  491. if (!slave->unattach_request)
  492. goto regmap_sync;
  493. time = wait_for_completion_timeout(&slave->initialization_complete,
  494. msecs_to_jiffies(RT715_PROBE_TIMEOUT));
  495. if (!time) {
  496. dev_err(&slave->dev, "Initialization not complete, timed out\n");
  497. return -ETIMEDOUT;
  498. }
  499. regmap_sync:
  500. slave->unattach_request = 0;
  501. regcache_cache_only(rt715->regmap, false);
  502. regcache_sync_region(rt715->regmap, 0x3000, 0x8fff);
  503. regcache_sync_region(rt715->regmap, 0x752039, 0x752039);
  504. return 0;
  505. }
  506. static const struct dev_pm_ops rt715_pm = {
  507. SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
  508. SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
  509. };
  510. static struct sdw_driver rt715_sdw_driver = {
  511. .driver = {
  512. .name = "rt715",
  513. .owner = THIS_MODULE,
  514. .pm = &rt715_pm,
  515. },
  516. .probe = rt715_sdw_probe,
  517. .ops = &rt715_slave_ops,
  518. .id_table = rt715_id,
  519. };
  520. module_sdw_driver(rt715_sdw_driver);
  521. MODULE_DESCRIPTION("ASoC RT715 driver SDW");
  522. MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
  523. MODULE_LICENSE("GPL v2");