rt5682.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // rt5682.c -- RT5682 ALSA SoC audio component driver
  4. //
  5. // Copyright 2018 Realtek Semiconductor Corp.
  6. // Author: Bard Liao <bardliao@realtek.com>
  7. //
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/acpi.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/mutex.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/jack.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/rt5682.h>
  29. #include "rl6231.h"
  30. #include "rt5682.h"
  31. const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  32. "AVDD",
  33. "MICVDD",
  34. "VBAT",
  35. };
  36. EXPORT_SYMBOL_GPL(rt5682_supply_names);
  37. static const struct reg_sequence patch_list[] = {
  38. {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  39. {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  40. {RT5682_I2C_CTRL, 0x000f},
  41. {RT5682_PLL2_INTERNAL, 0x8266},
  42. {RT5682_SAR_IL_CMD_3, 0x8365},
  43. {RT5682_SAR_IL_CMD_6, 0x0180},
  44. };
  45. void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  46. {
  47. int ret;
  48. ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  49. ARRAY_SIZE(patch_list));
  50. if (ret)
  51. dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  52. }
  53. EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  54. const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  55. {0x0002, 0x8080},
  56. {0x0003, 0x8000},
  57. {0x0005, 0x0000},
  58. {0x0006, 0x0000},
  59. {0x0008, 0x800f},
  60. {0x000b, 0x0000},
  61. {0x0010, 0x4040},
  62. {0x0011, 0x0000},
  63. {0x0012, 0x1404},
  64. {0x0013, 0x1000},
  65. {0x0014, 0xa00a},
  66. {0x0015, 0x0404},
  67. {0x0016, 0x0404},
  68. {0x0019, 0xafaf},
  69. {0x001c, 0x2f2f},
  70. {0x001f, 0x0000},
  71. {0x0022, 0x5757},
  72. {0x0023, 0x0039},
  73. {0x0024, 0x000b},
  74. {0x0026, 0xc0c4},
  75. {0x0029, 0x8080},
  76. {0x002a, 0xa0a0},
  77. {0x002b, 0x0300},
  78. {0x0030, 0x0000},
  79. {0x003c, 0x0080},
  80. {0x0044, 0x0c0c},
  81. {0x0049, 0x0000},
  82. {0x0061, 0x0000},
  83. {0x0062, 0x0000},
  84. {0x0063, 0x003f},
  85. {0x0064, 0x0000},
  86. {0x0065, 0x0000},
  87. {0x0066, 0x0030},
  88. {0x0067, 0x0000},
  89. {0x006b, 0x0000},
  90. {0x006c, 0x0000},
  91. {0x006d, 0x2200},
  92. {0x006e, 0x0a10},
  93. {0x0070, 0x8000},
  94. {0x0071, 0x8000},
  95. {0x0073, 0x0000},
  96. {0x0074, 0x0000},
  97. {0x0075, 0x0002},
  98. {0x0076, 0x0001},
  99. {0x0079, 0x0000},
  100. {0x007a, 0x0000},
  101. {0x007b, 0x0000},
  102. {0x007c, 0x0100},
  103. {0x007e, 0x0000},
  104. {0x0080, 0x0000},
  105. {0x0081, 0x0000},
  106. {0x0082, 0x0000},
  107. {0x0083, 0x0000},
  108. {0x0084, 0x0000},
  109. {0x0085, 0x0000},
  110. {0x0086, 0x0005},
  111. {0x0087, 0x0000},
  112. {0x0088, 0x0000},
  113. {0x008c, 0x0003},
  114. {0x008d, 0x0000},
  115. {0x008e, 0x0060},
  116. {0x008f, 0x1000},
  117. {0x0091, 0x0c26},
  118. {0x0092, 0x0073},
  119. {0x0093, 0x0000},
  120. {0x0094, 0x0080},
  121. {0x0098, 0x0000},
  122. {0x009a, 0x0000},
  123. {0x009b, 0x0000},
  124. {0x009c, 0x0000},
  125. {0x009d, 0x0000},
  126. {0x009e, 0x100c},
  127. {0x009f, 0x0000},
  128. {0x00a0, 0x0000},
  129. {0x00a3, 0x0002},
  130. {0x00a4, 0x0001},
  131. {0x00ae, 0x2040},
  132. {0x00af, 0x0000},
  133. {0x00b6, 0x0000},
  134. {0x00b7, 0x0000},
  135. {0x00b8, 0x0000},
  136. {0x00b9, 0x0002},
  137. {0x00be, 0x0000},
  138. {0x00c0, 0x0160},
  139. {0x00c1, 0x82a0},
  140. {0x00c2, 0x0000},
  141. {0x00d0, 0x0000},
  142. {0x00d1, 0x2244},
  143. {0x00d2, 0x3300},
  144. {0x00d3, 0x2200},
  145. {0x00d4, 0x0000},
  146. {0x00d9, 0x0009},
  147. {0x00da, 0x0000},
  148. {0x00db, 0x0000},
  149. {0x00dc, 0x00c0},
  150. {0x00dd, 0x2220},
  151. {0x00de, 0x3131},
  152. {0x00df, 0x3131},
  153. {0x00e0, 0x3131},
  154. {0x00e2, 0x0000},
  155. {0x00e3, 0x4000},
  156. {0x00e4, 0x0aa0},
  157. {0x00e5, 0x3131},
  158. {0x00e6, 0x3131},
  159. {0x00e7, 0x3131},
  160. {0x00e8, 0x3131},
  161. {0x00ea, 0xb320},
  162. {0x00eb, 0x0000},
  163. {0x00f0, 0x0000},
  164. {0x00f1, 0x00d0},
  165. {0x00f2, 0x00d0},
  166. {0x00f6, 0x0000},
  167. {0x00fa, 0x0000},
  168. {0x00fb, 0x0000},
  169. {0x00fc, 0x0000},
  170. {0x00fd, 0x0000},
  171. {0x00fe, 0x10ec},
  172. {0x00ff, 0x6530},
  173. {0x0100, 0xa0a0},
  174. {0x010b, 0x0000},
  175. {0x010c, 0xae00},
  176. {0x010d, 0xaaa0},
  177. {0x010e, 0x8aa2},
  178. {0x010f, 0x02a2},
  179. {0x0110, 0xc000},
  180. {0x0111, 0x04a2},
  181. {0x0112, 0x2800},
  182. {0x0113, 0x0000},
  183. {0x0117, 0x0100},
  184. {0x0125, 0x0410},
  185. {0x0132, 0x6026},
  186. {0x0136, 0x5555},
  187. {0x0138, 0x3700},
  188. {0x013a, 0x2000},
  189. {0x013b, 0x2000},
  190. {0x013c, 0x2005},
  191. {0x013f, 0x0000},
  192. {0x0142, 0x0000},
  193. {0x0145, 0x0002},
  194. {0x0146, 0x0000},
  195. {0x0147, 0x0000},
  196. {0x0148, 0x0000},
  197. {0x0149, 0x0000},
  198. {0x0150, 0x79a1},
  199. {0x0156, 0xaaaa},
  200. {0x0160, 0x4ec0},
  201. {0x0161, 0x0080},
  202. {0x0162, 0x0200},
  203. {0x0163, 0x0800},
  204. {0x0164, 0x0000},
  205. {0x0165, 0x0000},
  206. {0x0166, 0x0000},
  207. {0x0167, 0x000f},
  208. {0x0168, 0x000f},
  209. {0x0169, 0x0021},
  210. {0x0190, 0x413d},
  211. {0x0194, 0x0000},
  212. {0x0195, 0x0000},
  213. {0x0197, 0x0022},
  214. {0x0198, 0x0000},
  215. {0x0199, 0x0000},
  216. {0x01af, 0x0000},
  217. {0x01b0, 0x0400},
  218. {0x01b1, 0x0000},
  219. {0x01b2, 0x0000},
  220. {0x01b3, 0x0000},
  221. {0x01b4, 0x0000},
  222. {0x01b5, 0x0000},
  223. {0x01b6, 0x01c3},
  224. {0x01b7, 0x02a0},
  225. {0x01b8, 0x03e9},
  226. {0x01b9, 0x1389},
  227. {0x01ba, 0xc351},
  228. {0x01bb, 0x0009},
  229. {0x01bc, 0x0018},
  230. {0x01bd, 0x002a},
  231. {0x01be, 0x004c},
  232. {0x01bf, 0x0097},
  233. {0x01c0, 0x433d},
  234. {0x01c2, 0x0000},
  235. {0x01c3, 0x0000},
  236. {0x01c4, 0x0000},
  237. {0x01c5, 0x0000},
  238. {0x01c6, 0x0000},
  239. {0x01c7, 0x0000},
  240. {0x01c8, 0x40af},
  241. {0x01c9, 0x0702},
  242. {0x01ca, 0x0000},
  243. {0x01cb, 0x0000},
  244. {0x01cc, 0x5757},
  245. {0x01cd, 0x5757},
  246. {0x01ce, 0x5757},
  247. {0x01cf, 0x5757},
  248. {0x01d0, 0x5757},
  249. {0x01d1, 0x5757},
  250. {0x01d2, 0x5757},
  251. {0x01d3, 0x5757},
  252. {0x01d4, 0x5757},
  253. {0x01d5, 0x5757},
  254. {0x01d6, 0x0000},
  255. {0x01d7, 0x0008},
  256. {0x01d8, 0x0029},
  257. {0x01d9, 0x3333},
  258. {0x01da, 0x0000},
  259. {0x01db, 0x0004},
  260. {0x01dc, 0x0000},
  261. {0x01de, 0x7c00},
  262. {0x01df, 0x0320},
  263. {0x01e0, 0x06a1},
  264. {0x01e1, 0x0000},
  265. {0x01e2, 0x0000},
  266. {0x01e3, 0x0000},
  267. {0x01e4, 0x0000},
  268. {0x01e6, 0x0001},
  269. {0x01e7, 0x0000},
  270. {0x01e8, 0x0000},
  271. {0x01ea, 0x0000},
  272. {0x01eb, 0x0000},
  273. {0x01ec, 0x0000},
  274. {0x01ed, 0x0000},
  275. {0x01ee, 0x0000},
  276. {0x01ef, 0x0000},
  277. {0x01f0, 0x0000},
  278. {0x01f1, 0x0000},
  279. {0x01f2, 0x0000},
  280. {0x01f3, 0x0000},
  281. {0x01f4, 0x0000},
  282. {0x0210, 0x6297},
  283. {0x0211, 0xa005},
  284. {0x0212, 0x824c},
  285. {0x0213, 0xf7ff},
  286. {0x0214, 0xf24c},
  287. {0x0215, 0x0102},
  288. {0x0216, 0x00a3},
  289. {0x0217, 0x0048},
  290. {0x0218, 0xa2c0},
  291. {0x0219, 0x0400},
  292. {0x021a, 0x00c8},
  293. {0x021b, 0x00c0},
  294. {0x021c, 0x0000},
  295. {0x0250, 0x4500},
  296. {0x0251, 0x40b3},
  297. {0x0252, 0x0000},
  298. {0x0253, 0x0000},
  299. {0x0254, 0x0000},
  300. {0x0255, 0x0000},
  301. {0x0256, 0x0000},
  302. {0x0257, 0x0000},
  303. {0x0258, 0x0000},
  304. {0x0259, 0x0000},
  305. {0x025a, 0x0005},
  306. {0x0270, 0x0000},
  307. {0x02ff, 0x0110},
  308. {0x0300, 0x001f},
  309. {0x0301, 0x032c},
  310. {0x0302, 0x5f21},
  311. {0x0303, 0x4000},
  312. {0x0304, 0x4000},
  313. {0x0305, 0x06d5},
  314. {0x0306, 0x8000},
  315. {0x0307, 0x0700},
  316. {0x0310, 0x4560},
  317. {0x0311, 0xa4a8},
  318. {0x0312, 0x7418},
  319. {0x0313, 0x0000},
  320. {0x0314, 0x0006},
  321. {0x0315, 0xffff},
  322. {0x0316, 0xc400},
  323. {0x0317, 0x0000},
  324. {0x03c0, 0x7e00},
  325. {0x03c1, 0x8000},
  326. {0x03c2, 0x8000},
  327. {0x03c3, 0x8000},
  328. {0x03c4, 0x8000},
  329. {0x03c5, 0x8000},
  330. {0x03c6, 0x8000},
  331. {0x03c7, 0x8000},
  332. {0x03c8, 0x8000},
  333. {0x03c9, 0x8000},
  334. {0x03ca, 0x8000},
  335. {0x03cb, 0x8000},
  336. {0x03cc, 0x8000},
  337. {0x03d0, 0x0000},
  338. {0x03d1, 0x0000},
  339. {0x03d2, 0x0000},
  340. {0x03d3, 0x0000},
  341. {0x03d4, 0x2000},
  342. {0x03d5, 0x2000},
  343. {0x03d6, 0x0000},
  344. {0x03d7, 0x0000},
  345. {0x03d8, 0x2000},
  346. {0x03d9, 0x2000},
  347. {0x03da, 0x2000},
  348. {0x03db, 0x2000},
  349. {0x03dc, 0x0000},
  350. {0x03dd, 0x0000},
  351. {0x03de, 0x0000},
  352. {0x03df, 0x2000},
  353. {0x03e0, 0x0000},
  354. {0x03e1, 0x0000},
  355. {0x03e2, 0x0000},
  356. {0x03e3, 0x0000},
  357. {0x03e4, 0x0000},
  358. {0x03e5, 0x0000},
  359. {0x03e6, 0x0000},
  360. {0x03e7, 0x0000},
  361. {0x03e8, 0x0000},
  362. {0x03e9, 0x0000},
  363. {0x03ea, 0x0000},
  364. {0x03eb, 0x0000},
  365. {0x03ec, 0x0000},
  366. {0x03ed, 0x0000},
  367. {0x03ee, 0x0000},
  368. {0x03ef, 0x0000},
  369. {0x03f0, 0x0800},
  370. {0x03f1, 0x0800},
  371. {0x03f2, 0x0800},
  372. {0x03f3, 0x0800},
  373. };
  374. EXPORT_SYMBOL_GPL(rt5682_reg);
  375. bool rt5682_volatile_register(struct device *dev, unsigned int reg)
  376. {
  377. switch (reg) {
  378. case RT5682_RESET:
  379. case RT5682_CBJ_CTRL_2:
  380. case RT5682_INT_ST_1:
  381. case RT5682_4BTN_IL_CMD_1:
  382. case RT5682_AJD1_CTRL:
  383. case RT5682_HP_CALIB_CTRL_1:
  384. case RT5682_DEVICE_ID:
  385. case RT5682_I2C_MODE:
  386. case RT5682_HP_CALIB_CTRL_10:
  387. case RT5682_EFUSE_CTRL_2:
  388. case RT5682_JD_TOP_VC_VTRL:
  389. case RT5682_HP_IMP_SENS_CTRL_19:
  390. case RT5682_IL_CMD_1:
  391. case RT5682_SAR_IL_CMD_2:
  392. case RT5682_SAR_IL_CMD_4:
  393. case RT5682_SAR_IL_CMD_10:
  394. case RT5682_SAR_IL_CMD_11:
  395. case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
  396. case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
  397. return true;
  398. default:
  399. return false;
  400. }
  401. }
  402. EXPORT_SYMBOL_GPL(rt5682_volatile_register);
  403. bool rt5682_readable_register(struct device *dev, unsigned int reg)
  404. {
  405. switch (reg) {
  406. case RT5682_RESET:
  407. case RT5682_VERSION_ID:
  408. case RT5682_VENDOR_ID:
  409. case RT5682_DEVICE_ID:
  410. case RT5682_HP_CTRL_1:
  411. case RT5682_HP_CTRL_2:
  412. case RT5682_HPL_GAIN:
  413. case RT5682_HPR_GAIN:
  414. case RT5682_I2C_CTRL:
  415. case RT5682_CBJ_BST_CTRL:
  416. case RT5682_CBJ_CTRL_1:
  417. case RT5682_CBJ_CTRL_2:
  418. case RT5682_CBJ_CTRL_3:
  419. case RT5682_CBJ_CTRL_4:
  420. case RT5682_CBJ_CTRL_5:
  421. case RT5682_CBJ_CTRL_6:
  422. case RT5682_CBJ_CTRL_7:
  423. case RT5682_DAC1_DIG_VOL:
  424. case RT5682_STO1_ADC_DIG_VOL:
  425. case RT5682_STO1_ADC_BOOST:
  426. case RT5682_HP_IMP_GAIN_1:
  427. case RT5682_HP_IMP_GAIN_2:
  428. case RT5682_SIDETONE_CTRL:
  429. case RT5682_STO1_ADC_MIXER:
  430. case RT5682_AD_DA_MIXER:
  431. case RT5682_STO1_DAC_MIXER:
  432. case RT5682_A_DAC1_MUX:
  433. case RT5682_DIG_INF2_DATA:
  434. case RT5682_REC_MIXER:
  435. case RT5682_CAL_REC:
  436. case RT5682_ALC_BACK_GAIN:
  437. case RT5682_PWR_DIG_1:
  438. case RT5682_PWR_DIG_2:
  439. case RT5682_PWR_ANLG_1:
  440. case RT5682_PWR_ANLG_2:
  441. case RT5682_PWR_ANLG_3:
  442. case RT5682_PWR_MIXER:
  443. case RT5682_PWR_VOL:
  444. case RT5682_CLK_DET:
  445. case RT5682_RESET_LPF_CTRL:
  446. case RT5682_RESET_HPF_CTRL:
  447. case RT5682_DMIC_CTRL_1:
  448. case RT5682_I2S1_SDP:
  449. case RT5682_I2S2_SDP:
  450. case RT5682_ADDA_CLK_1:
  451. case RT5682_ADDA_CLK_2:
  452. case RT5682_I2S1_F_DIV_CTRL_1:
  453. case RT5682_I2S1_F_DIV_CTRL_2:
  454. case RT5682_TDM_CTRL:
  455. case RT5682_TDM_ADDA_CTRL_1:
  456. case RT5682_TDM_ADDA_CTRL_2:
  457. case RT5682_DATA_SEL_CTRL_1:
  458. case RT5682_TDM_TCON_CTRL:
  459. case RT5682_GLB_CLK:
  460. case RT5682_PLL_CTRL_1:
  461. case RT5682_PLL_CTRL_2:
  462. case RT5682_PLL_TRACK_1:
  463. case RT5682_PLL_TRACK_2:
  464. case RT5682_PLL_TRACK_3:
  465. case RT5682_PLL_TRACK_4:
  466. case RT5682_PLL_TRACK_5:
  467. case RT5682_PLL_TRACK_6:
  468. case RT5682_PLL_TRACK_11:
  469. case RT5682_SDW_REF_CLK:
  470. case RT5682_DEPOP_1:
  471. case RT5682_DEPOP_2:
  472. case RT5682_HP_CHARGE_PUMP_1:
  473. case RT5682_HP_CHARGE_PUMP_2:
  474. case RT5682_MICBIAS_1:
  475. case RT5682_MICBIAS_2:
  476. case RT5682_PLL_TRACK_12:
  477. case RT5682_PLL_TRACK_14:
  478. case RT5682_PLL2_CTRL_1:
  479. case RT5682_PLL2_CTRL_2:
  480. case RT5682_PLL2_CTRL_3:
  481. case RT5682_PLL2_CTRL_4:
  482. case RT5682_RC_CLK_CTRL:
  483. case RT5682_I2S_M_CLK_CTRL_1:
  484. case RT5682_I2S2_F_DIV_CTRL_1:
  485. case RT5682_I2S2_F_DIV_CTRL_2:
  486. case RT5682_EQ_CTRL_1:
  487. case RT5682_EQ_CTRL_2:
  488. case RT5682_IRQ_CTRL_1:
  489. case RT5682_IRQ_CTRL_2:
  490. case RT5682_IRQ_CTRL_3:
  491. case RT5682_IRQ_CTRL_4:
  492. case RT5682_INT_ST_1:
  493. case RT5682_GPIO_CTRL_1:
  494. case RT5682_GPIO_CTRL_2:
  495. case RT5682_GPIO_CTRL_3:
  496. case RT5682_HP_AMP_DET_CTRL_1:
  497. case RT5682_HP_AMP_DET_CTRL_2:
  498. case RT5682_MID_HP_AMP_DET:
  499. case RT5682_LOW_HP_AMP_DET:
  500. case RT5682_DELAY_BUF_CTRL:
  501. case RT5682_SV_ZCD_1:
  502. case RT5682_SV_ZCD_2:
  503. case RT5682_IL_CMD_1:
  504. case RT5682_IL_CMD_2:
  505. case RT5682_IL_CMD_3:
  506. case RT5682_IL_CMD_4:
  507. case RT5682_IL_CMD_5:
  508. case RT5682_IL_CMD_6:
  509. case RT5682_4BTN_IL_CMD_1:
  510. case RT5682_4BTN_IL_CMD_2:
  511. case RT5682_4BTN_IL_CMD_3:
  512. case RT5682_4BTN_IL_CMD_4:
  513. case RT5682_4BTN_IL_CMD_5:
  514. case RT5682_4BTN_IL_CMD_6:
  515. case RT5682_4BTN_IL_CMD_7:
  516. case RT5682_ADC_STO1_HP_CTRL_1:
  517. case RT5682_ADC_STO1_HP_CTRL_2:
  518. case RT5682_AJD1_CTRL:
  519. case RT5682_JD1_THD:
  520. case RT5682_JD2_THD:
  521. case RT5682_JD_CTRL_1:
  522. case RT5682_DUMMY_1:
  523. case RT5682_DUMMY_2:
  524. case RT5682_DUMMY_3:
  525. case RT5682_DAC_ADC_DIG_VOL1:
  526. case RT5682_BIAS_CUR_CTRL_2:
  527. case RT5682_BIAS_CUR_CTRL_3:
  528. case RT5682_BIAS_CUR_CTRL_4:
  529. case RT5682_BIAS_CUR_CTRL_5:
  530. case RT5682_BIAS_CUR_CTRL_6:
  531. case RT5682_BIAS_CUR_CTRL_7:
  532. case RT5682_BIAS_CUR_CTRL_8:
  533. case RT5682_BIAS_CUR_CTRL_9:
  534. case RT5682_BIAS_CUR_CTRL_10:
  535. case RT5682_VREF_REC_OP_FB_CAP_CTRL:
  536. case RT5682_CHARGE_PUMP_1:
  537. case RT5682_DIG_IN_CTRL_1:
  538. case RT5682_PAD_DRIVING_CTRL:
  539. case RT5682_SOFT_RAMP_DEPOP:
  540. case RT5682_CHOP_DAC:
  541. case RT5682_CHOP_ADC:
  542. case RT5682_CALIB_ADC_CTRL:
  543. case RT5682_VOL_TEST:
  544. case RT5682_SPKVDD_DET_STA:
  545. case RT5682_TEST_MODE_CTRL_1:
  546. case RT5682_TEST_MODE_CTRL_2:
  547. case RT5682_TEST_MODE_CTRL_3:
  548. case RT5682_TEST_MODE_CTRL_4:
  549. case RT5682_TEST_MODE_CTRL_5:
  550. case RT5682_PLL1_INTERNAL:
  551. case RT5682_PLL2_INTERNAL:
  552. case RT5682_STO_NG2_CTRL_1:
  553. case RT5682_STO_NG2_CTRL_2:
  554. case RT5682_STO_NG2_CTRL_3:
  555. case RT5682_STO_NG2_CTRL_4:
  556. case RT5682_STO_NG2_CTRL_5:
  557. case RT5682_STO_NG2_CTRL_6:
  558. case RT5682_STO_NG2_CTRL_7:
  559. case RT5682_STO_NG2_CTRL_8:
  560. case RT5682_STO_NG2_CTRL_9:
  561. case RT5682_STO_NG2_CTRL_10:
  562. case RT5682_STO1_DAC_SIL_DET:
  563. case RT5682_SIL_PSV_CTRL1:
  564. case RT5682_SIL_PSV_CTRL2:
  565. case RT5682_SIL_PSV_CTRL3:
  566. case RT5682_SIL_PSV_CTRL4:
  567. case RT5682_SIL_PSV_CTRL5:
  568. case RT5682_HP_IMP_SENS_CTRL_01:
  569. case RT5682_HP_IMP_SENS_CTRL_02:
  570. case RT5682_HP_IMP_SENS_CTRL_03:
  571. case RT5682_HP_IMP_SENS_CTRL_04:
  572. case RT5682_HP_IMP_SENS_CTRL_05:
  573. case RT5682_HP_IMP_SENS_CTRL_06:
  574. case RT5682_HP_IMP_SENS_CTRL_07:
  575. case RT5682_HP_IMP_SENS_CTRL_08:
  576. case RT5682_HP_IMP_SENS_CTRL_09:
  577. case RT5682_HP_IMP_SENS_CTRL_10:
  578. case RT5682_HP_IMP_SENS_CTRL_11:
  579. case RT5682_HP_IMP_SENS_CTRL_12:
  580. case RT5682_HP_IMP_SENS_CTRL_13:
  581. case RT5682_HP_IMP_SENS_CTRL_14:
  582. case RT5682_HP_IMP_SENS_CTRL_15:
  583. case RT5682_HP_IMP_SENS_CTRL_16:
  584. case RT5682_HP_IMP_SENS_CTRL_17:
  585. case RT5682_HP_IMP_SENS_CTRL_18:
  586. case RT5682_HP_IMP_SENS_CTRL_19:
  587. case RT5682_HP_IMP_SENS_CTRL_20:
  588. case RT5682_HP_IMP_SENS_CTRL_21:
  589. case RT5682_HP_IMP_SENS_CTRL_22:
  590. case RT5682_HP_IMP_SENS_CTRL_23:
  591. case RT5682_HP_IMP_SENS_CTRL_24:
  592. case RT5682_HP_IMP_SENS_CTRL_25:
  593. case RT5682_HP_IMP_SENS_CTRL_26:
  594. case RT5682_HP_IMP_SENS_CTRL_27:
  595. case RT5682_HP_IMP_SENS_CTRL_28:
  596. case RT5682_HP_IMP_SENS_CTRL_29:
  597. case RT5682_HP_IMP_SENS_CTRL_30:
  598. case RT5682_HP_IMP_SENS_CTRL_31:
  599. case RT5682_HP_IMP_SENS_CTRL_32:
  600. case RT5682_HP_IMP_SENS_CTRL_33:
  601. case RT5682_HP_IMP_SENS_CTRL_34:
  602. case RT5682_HP_IMP_SENS_CTRL_35:
  603. case RT5682_HP_IMP_SENS_CTRL_36:
  604. case RT5682_HP_IMP_SENS_CTRL_37:
  605. case RT5682_HP_IMP_SENS_CTRL_38:
  606. case RT5682_HP_IMP_SENS_CTRL_39:
  607. case RT5682_HP_IMP_SENS_CTRL_40:
  608. case RT5682_HP_IMP_SENS_CTRL_41:
  609. case RT5682_HP_IMP_SENS_CTRL_42:
  610. case RT5682_HP_IMP_SENS_CTRL_43:
  611. case RT5682_HP_LOGIC_CTRL_1:
  612. case RT5682_HP_LOGIC_CTRL_2:
  613. case RT5682_HP_LOGIC_CTRL_3:
  614. case RT5682_HP_CALIB_CTRL_1:
  615. case RT5682_HP_CALIB_CTRL_2:
  616. case RT5682_HP_CALIB_CTRL_3:
  617. case RT5682_HP_CALIB_CTRL_4:
  618. case RT5682_HP_CALIB_CTRL_5:
  619. case RT5682_HP_CALIB_CTRL_6:
  620. case RT5682_HP_CALIB_CTRL_7:
  621. case RT5682_HP_CALIB_CTRL_9:
  622. case RT5682_HP_CALIB_CTRL_10:
  623. case RT5682_HP_CALIB_CTRL_11:
  624. case RT5682_HP_CALIB_STA_1:
  625. case RT5682_HP_CALIB_STA_2:
  626. case RT5682_HP_CALIB_STA_3:
  627. case RT5682_HP_CALIB_STA_4:
  628. case RT5682_HP_CALIB_STA_5:
  629. case RT5682_HP_CALIB_STA_6:
  630. case RT5682_HP_CALIB_STA_7:
  631. case RT5682_HP_CALIB_STA_8:
  632. case RT5682_HP_CALIB_STA_9:
  633. case RT5682_HP_CALIB_STA_10:
  634. case RT5682_HP_CALIB_STA_11:
  635. case RT5682_SAR_IL_CMD_1:
  636. case RT5682_SAR_IL_CMD_2:
  637. case RT5682_SAR_IL_CMD_3:
  638. case RT5682_SAR_IL_CMD_4:
  639. case RT5682_SAR_IL_CMD_5:
  640. case RT5682_SAR_IL_CMD_6:
  641. case RT5682_SAR_IL_CMD_7:
  642. case RT5682_SAR_IL_CMD_8:
  643. case RT5682_SAR_IL_CMD_9:
  644. case RT5682_SAR_IL_CMD_10:
  645. case RT5682_SAR_IL_CMD_11:
  646. case RT5682_SAR_IL_CMD_12:
  647. case RT5682_SAR_IL_CMD_13:
  648. case RT5682_EFUSE_CTRL_1:
  649. case RT5682_EFUSE_CTRL_2:
  650. case RT5682_EFUSE_CTRL_3:
  651. case RT5682_EFUSE_CTRL_4:
  652. case RT5682_EFUSE_CTRL_5:
  653. case RT5682_EFUSE_CTRL_6:
  654. case RT5682_EFUSE_CTRL_7:
  655. case RT5682_EFUSE_CTRL_8:
  656. case RT5682_EFUSE_CTRL_9:
  657. case RT5682_EFUSE_CTRL_10:
  658. case RT5682_EFUSE_CTRL_11:
  659. case RT5682_JD_TOP_VC_VTRL:
  660. case RT5682_DRC1_CTRL_0:
  661. case RT5682_DRC1_CTRL_1:
  662. case RT5682_DRC1_CTRL_2:
  663. case RT5682_DRC1_CTRL_3:
  664. case RT5682_DRC1_CTRL_4:
  665. case RT5682_DRC1_CTRL_5:
  666. case RT5682_DRC1_CTRL_6:
  667. case RT5682_DRC1_HARD_LMT_CTRL_1:
  668. case RT5682_DRC1_HARD_LMT_CTRL_2:
  669. case RT5682_DRC1_PRIV_1:
  670. case RT5682_DRC1_PRIV_2:
  671. case RT5682_DRC1_PRIV_3:
  672. case RT5682_DRC1_PRIV_4:
  673. case RT5682_DRC1_PRIV_5:
  674. case RT5682_DRC1_PRIV_6:
  675. case RT5682_DRC1_PRIV_7:
  676. case RT5682_DRC1_PRIV_8:
  677. case RT5682_EQ_AUTO_RCV_CTRL1:
  678. case RT5682_EQ_AUTO_RCV_CTRL2:
  679. case RT5682_EQ_AUTO_RCV_CTRL3:
  680. case RT5682_EQ_AUTO_RCV_CTRL4:
  681. case RT5682_EQ_AUTO_RCV_CTRL5:
  682. case RT5682_EQ_AUTO_RCV_CTRL6:
  683. case RT5682_EQ_AUTO_RCV_CTRL7:
  684. case RT5682_EQ_AUTO_RCV_CTRL8:
  685. case RT5682_EQ_AUTO_RCV_CTRL9:
  686. case RT5682_EQ_AUTO_RCV_CTRL10:
  687. case RT5682_EQ_AUTO_RCV_CTRL11:
  688. case RT5682_EQ_AUTO_RCV_CTRL12:
  689. case RT5682_EQ_AUTO_RCV_CTRL13:
  690. case RT5682_ADC_L_EQ_LPF1_A1:
  691. case RT5682_R_EQ_LPF1_A1:
  692. case RT5682_L_EQ_LPF1_H0:
  693. case RT5682_R_EQ_LPF1_H0:
  694. case RT5682_L_EQ_BPF1_A1:
  695. case RT5682_R_EQ_BPF1_A1:
  696. case RT5682_L_EQ_BPF1_A2:
  697. case RT5682_R_EQ_BPF1_A2:
  698. case RT5682_L_EQ_BPF1_H0:
  699. case RT5682_R_EQ_BPF1_H0:
  700. case RT5682_L_EQ_BPF2_A1:
  701. case RT5682_R_EQ_BPF2_A1:
  702. case RT5682_L_EQ_BPF2_A2:
  703. case RT5682_R_EQ_BPF2_A2:
  704. case RT5682_L_EQ_BPF2_H0:
  705. case RT5682_R_EQ_BPF2_H0:
  706. case RT5682_L_EQ_BPF3_A1:
  707. case RT5682_R_EQ_BPF3_A1:
  708. case RT5682_L_EQ_BPF3_A2:
  709. case RT5682_R_EQ_BPF3_A2:
  710. case RT5682_L_EQ_BPF3_H0:
  711. case RT5682_R_EQ_BPF3_H0:
  712. case RT5682_L_EQ_BPF4_A1:
  713. case RT5682_R_EQ_BPF4_A1:
  714. case RT5682_L_EQ_BPF4_A2:
  715. case RT5682_R_EQ_BPF4_A2:
  716. case RT5682_L_EQ_BPF4_H0:
  717. case RT5682_R_EQ_BPF4_H0:
  718. case RT5682_L_EQ_HPF1_A1:
  719. case RT5682_R_EQ_HPF1_A1:
  720. case RT5682_L_EQ_HPF1_H0:
  721. case RT5682_R_EQ_HPF1_H0:
  722. case RT5682_L_EQ_PRE_VOL:
  723. case RT5682_R_EQ_PRE_VOL:
  724. case RT5682_L_EQ_POST_VOL:
  725. case RT5682_R_EQ_POST_VOL:
  726. case RT5682_I2C_MODE:
  727. return true;
  728. default:
  729. return false;
  730. }
  731. }
  732. EXPORT_SYMBOL_GPL(rt5682_readable_register);
  733. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
  734. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
  735. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  736. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  737. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  738. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  739. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  740. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  741. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  742. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  743. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  744. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  745. );
  746. /* Interface data select */
  747. static const char * const rt5682_data_select[] = {
  748. "L/R", "R/L", "L/L", "R/R"
  749. };
  750. static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
  751. RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
  752. static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
  753. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
  754. static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
  755. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
  756. static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
  757. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
  758. static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
  759. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
  760. static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
  761. SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
  762. static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
  763. SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
  764. static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
  765. SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
  766. static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
  767. SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
  768. static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
  769. SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
  770. static const char * const rt5682_dac_select[] = {
  771. "IF1", "SOUND"
  772. };
  773. static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
  774. RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
  775. static const struct snd_kcontrol_new rt5682_dac_l_mux =
  776. SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
  777. static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
  778. RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
  779. static const struct snd_kcontrol_new rt5682_dac_r_mux =
  780. SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
  781. void rt5682_reset(struct rt5682_priv *rt5682)
  782. {
  783. regmap_write(rt5682->regmap, RT5682_RESET, 0);
  784. if (!rt5682->is_sdw)
  785. regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
  786. }
  787. EXPORT_SYMBOL_GPL(rt5682_reset);
  788. /**
  789. * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
  790. * @component: SoC audio component device.
  791. * @filter_mask: mask of filters.
  792. * @clk_src: clock source
  793. *
  794. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
  795. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  796. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  797. * ASRC function will track i2s clock and generate a corresponding system clock
  798. * for codec. This function provides an API to select the clock source for a
  799. * set of filters specified by the mask. And the component driver will turn on
  800. * ASRC for these filters if ASRC is selected as their clock source.
  801. */
  802. int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
  803. unsigned int filter_mask, unsigned int clk_src)
  804. {
  805. switch (clk_src) {
  806. case RT5682_CLK_SEL_SYS:
  807. case RT5682_CLK_SEL_I2S1_ASRC:
  808. case RT5682_CLK_SEL_I2S2_ASRC:
  809. break;
  810. default:
  811. return -EINVAL;
  812. }
  813. if (filter_mask & RT5682_DA_STEREO1_FILTER) {
  814. snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
  815. RT5682_FILTER_CLK_SEL_MASK,
  816. clk_src << RT5682_FILTER_CLK_SEL_SFT);
  817. }
  818. if (filter_mask & RT5682_AD_STEREO1_FILTER) {
  819. snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
  820. RT5682_FILTER_CLK_SEL_MASK,
  821. clk_src << RT5682_FILTER_CLK_SEL_SFT);
  822. }
  823. return 0;
  824. }
  825. EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
  826. static int rt5682_button_detect(struct snd_soc_component *component)
  827. {
  828. int btn_type, val;
  829. val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
  830. btn_type = val & 0xfff0;
  831. snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
  832. dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
  833. snd_soc_component_update_bits(component,
  834. RT5682_SAR_IL_CMD_2, 0x10, 0x10);
  835. return btn_type;
  836. }
  837. static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
  838. bool enable)
  839. {
  840. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  841. if (enable) {
  842. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  843. RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
  844. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
  845. RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
  846. snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
  847. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  848. RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
  849. RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
  850. if (rt5682->is_sdw)
  851. snd_soc_component_update_bits(component,
  852. RT5682_IRQ_CTRL_3,
  853. RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
  854. RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
  855. else
  856. snd_soc_component_update_bits(component,
  857. RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
  858. RT5682_IL_IRQ_EN);
  859. } else {
  860. snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
  861. RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
  862. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  863. RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
  864. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  865. RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
  866. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  867. RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
  868. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
  869. RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
  870. }
  871. }
  872. /**
  873. * rt5682_headset_detect - Detect headset.
  874. * @component: SoC audio component device.
  875. * @jack_insert: Jack insert or not.
  876. *
  877. * Detect whether is headset or not when jack inserted.
  878. *
  879. * Returns detect status.
  880. */
  881. int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
  882. {
  883. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  884. struct snd_soc_dapm_context *dapm = &component->dapm;
  885. unsigned int val, count;
  886. if (jack_insert) {
  887. snd_soc_dapm_mutex_lock(dapm);
  888. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  889. RT5682_PWR_VREF2 | RT5682_PWR_MB,
  890. RT5682_PWR_VREF2 | RT5682_PWR_MB);
  891. snd_soc_component_update_bits(component,
  892. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
  893. usleep_range(15000, 20000);
  894. snd_soc_component_update_bits(component,
  895. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
  896. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
  897. RT5682_PWR_CBJ, RT5682_PWR_CBJ);
  898. snd_soc_component_update_bits(component,
  899. RT5682_HP_CHARGE_PUMP_1,
  900. RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
  901. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  902. RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
  903. count = 0;
  904. val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
  905. & RT5682_JACK_TYPE_MASK;
  906. while (val == 0 && count < 50) {
  907. usleep_range(10000, 15000);
  908. val = snd_soc_component_read(component,
  909. RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
  910. count++;
  911. }
  912. switch (val) {
  913. case 0x1:
  914. case 0x2:
  915. rt5682->jack_type = SND_JACK_HEADSET;
  916. rt5682_enable_push_button_irq(component, true);
  917. break;
  918. default:
  919. rt5682->jack_type = SND_JACK_HEADPHONE;
  920. break;
  921. }
  922. snd_soc_component_update_bits(component,
  923. RT5682_HP_CHARGE_PUMP_1,
  924. RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
  925. RT5682_OSW_L_EN | RT5682_OSW_R_EN);
  926. snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
  927. RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
  928. RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
  929. snd_soc_dapm_mutex_unlock(dapm);
  930. } else {
  931. rt5682_enable_push_button_irq(component, false);
  932. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  933. RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
  934. if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
  935. !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
  936. !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
  937. snd_soc_component_update_bits(component,
  938. RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
  939. if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
  940. !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
  941. !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
  942. snd_soc_component_update_bits(component,
  943. RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
  944. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
  945. RT5682_PWR_CBJ, 0);
  946. snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
  947. RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
  948. RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
  949. rt5682->jack_type = 0;
  950. }
  951. dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
  952. return rt5682->jack_type;
  953. }
  954. EXPORT_SYMBOL_GPL(rt5682_headset_detect);
  955. static int rt5682_set_jack_detect(struct snd_soc_component *component,
  956. struct snd_soc_jack *hs_jack, void *data)
  957. {
  958. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  959. rt5682->hs_jack = hs_jack;
  960. if (!hs_jack) {
  961. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  962. RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
  963. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  964. RT5682_POW_JDH | RT5682_POW_JDL, 0);
  965. cancel_delayed_work_sync(&rt5682->jack_detect_work);
  966. return 0;
  967. }
  968. if (!rt5682->is_sdw) {
  969. switch (rt5682->pdata.jd_src) {
  970. case RT5682_JD1:
  971. snd_soc_component_update_bits(component,
  972. RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
  973. RT5682_EXT_JD_SRC_MANUAL);
  974. snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
  975. 0xd042);
  976. snd_soc_component_update_bits(component,
  977. RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
  978. RT5682_CBJ_IN_BUF_EN);
  979. snd_soc_component_update_bits(component,
  980. RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
  981. RT5682_SAR_POW_EN);
  982. regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
  983. RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
  984. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  985. RT5682_POW_IRQ | RT5682_POW_JDH |
  986. RT5682_POW_ANA, RT5682_POW_IRQ |
  987. RT5682_POW_JDH | RT5682_POW_ANA);
  988. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
  989. RT5682_PWR_JDH, RT5682_PWR_JDH);
  990. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  991. RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
  992. RT5682_JD1_EN | RT5682_JD1_POL_NOR);
  993. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
  994. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  995. rt5682->pdata.btndet_delay));
  996. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
  997. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  998. rt5682->pdata.btndet_delay));
  999. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
  1000. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1001. rt5682->pdata.btndet_delay));
  1002. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
  1003. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1004. rt5682->pdata.btndet_delay));
  1005. mod_delayed_work(system_power_efficient_wq,
  1006. &rt5682->jack_detect_work,
  1007. msecs_to_jiffies(250));
  1008. break;
  1009. case RT5682_JD_NULL:
  1010. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  1011. RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
  1012. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  1013. RT5682_POW_JDH | RT5682_POW_JDL, 0);
  1014. break;
  1015. default:
  1016. dev_warn(component->dev, "Wrong JD source\n");
  1017. break;
  1018. }
  1019. }
  1020. return 0;
  1021. }
  1022. void rt5682_jack_detect_handler(struct work_struct *work)
  1023. {
  1024. struct rt5682_priv *rt5682 =
  1025. container_of(work, struct rt5682_priv, jack_detect_work.work);
  1026. int val, btn_type;
  1027. if (!rt5682->component || !rt5682->component->card ||
  1028. !rt5682->component->card->instantiated) {
  1029. /* card not yet ready, try later */
  1030. mod_delayed_work(system_power_efficient_wq,
  1031. &rt5682->jack_detect_work, msecs_to_jiffies(15));
  1032. return;
  1033. }
  1034. mutex_lock(&rt5682->calibrate_mutex);
  1035. val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
  1036. & RT5682_JDH_RS_MASK;
  1037. if (!val) {
  1038. /* jack in */
  1039. if (rt5682->jack_type == 0) {
  1040. /* jack was out, report jack type */
  1041. rt5682->jack_type =
  1042. rt5682_headset_detect(rt5682->component, 1);
  1043. } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
  1044. SND_JACK_HEADSET) {
  1045. /* jack is already in, report button event */
  1046. rt5682->jack_type = SND_JACK_HEADSET;
  1047. btn_type = rt5682_button_detect(rt5682->component);
  1048. /**
  1049. * rt5682 can report three kinds of button behavior,
  1050. * one click, double click and hold. However,
  1051. * currently we will report button pressed/released
  1052. * event. So all the three button behaviors are
  1053. * treated as button pressed.
  1054. */
  1055. switch (btn_type) {
  1056. case 0x8000:
  1057. case 0x4000:
  1058. case 0x2000:
  1059. rt5682->jack_type |= SND_JACK_BTN_0;
  1060. break;
  1061. case 0x1000:
  1062. case 0x0800:
  1063. case 0x0400:
  1064. rt5682->jack_type |= SND_JACK_BTN_1;
  1065. break;
  1066. case 0x0200:
  1067. case 0x0100:
  1068. case 0x0080:
  1069. rt5682->jack_type |= SND_JACK_BTN_2;
  1070. break;
  1071. case 0x0040:
  1072. case 0x0020:
  1073. case 0x0010:
  1074. rt5682->jack_type |= SND_JACK_BTN_3;
  1075. break;
  1076. case 0x0000: /* unpressed */
  1077. break;
  1078. default:
  1079. dev_err(rt5682->component->dev,
  1080. "Unexpected button code 0x%04x\n",
  1081. btn_type);
  1082. break;
  1083. }
  1084. }
  1085. } else {
  1086. /* jack out */
  1087. rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
  1088. }
  1089. snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
  1090. SND_JACK_HEADSET |
  1091. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1092. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  1093. if (!rt5682->is_sdw) {
  1094. if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1095. SND_JACK_BTN_2 | SND_JACK_BTN_3))
  1096. schedule_delayed_work(&rt5682->jd_check_work, 0);
  1097. else
  1098. cancel_delayed_work_sync(&rt5682->jd_check_work);
  1099. }
  1100. mutex_unlock(&rt5682->calibrate_mutex);
  1101. }
  1102. EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
  1103. static const struct snd_kcontrol_new rt5682_snd_controls[] = {
  1104. /* DAC Digital Volume */
  1105. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
  1106. RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
  1107. /* IN Boost Volume */
  1108. SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
  1109. RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
  1110. /* ADC Digital Volume Control */
  1111. SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
  1112. RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
  1113. SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
  1114. RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
  1115. /* ADC Boost Volume Control */
  1116. SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
  1117. RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
  1118. 3, 0, adc_bst_tlv),
  1119. };
  1120. static int rt5682_div_sel(struct rt5682_priv *rt5682,
  1121. int target, const int div[], int size)
  1122. {
  1123. int i;
  1124. if (rt5682->sysclk < target) {
  1125. dev_err(rt5682->component->dev,
  1126. "sysclk rate %d is too low\n", rt5682->sysclk);
  1127. return 0;
  1128. }
  1129. for (i = 0; i < size - 1; i++) {
  1130. dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
  1131. if (target * div[i] == rt5682->sysclk)
  1132. return i;
  1133. if (target * div[i + 1] > rt5682->sysclk) {
  1134. dev_dbg(rt5682->component->dev,
  1135. "can't find div for sysclk %d\n",
  1136. rt5682->sysclk);
  1137. return i;
  1138. }
  1139. }
  1140. if (target * div[i] < rt5682->sysclk)
  1141. dev_err(rt5682->component->dev,
  1142. "sysclk rate %d is too high\n", rt5682->sysclk);
  1143. return size - 1;
  1144. }
  1145. /**
  1146. * set_dmic_clk - Set parameter of dmic.
  1147. *
  1148. * @w: DAPM widget.
  1149. * @kcontrol: The kcontrol of this widget.
  1150. * @event: Event id.
  1151. *
  1152. * Choose dmic clock between 1MHz and 3MHz.
  1153. * It is better for clock to approximate 3MHz.
  1154. */
  1155. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  1156. struct snd_kcontrol *kcontrol, int event)
  1157. {
  1158. struct snd_soc_component *component =
  1159. snd_soc_dapm_to_component(w->dapm);
  1160. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1161. int idx = -EINVAL, dmic_clk_rate = 3072000;
  1162. static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
  1163. if (rt5682->pdata.dmic_clk_rate)
  1164. dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
  1165. idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
  1166. snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
  1167. RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
  1168. return 0;
  1169. }
  1170. static int set_filter_clk(struct snd_soc_dapm_widget *w,
  1171. struct snd_kcontrol *kcontrol, int event)
  1172. {
  1173. struct snd_soc_component *component =
  1174. snd_soc_dapm_to_component(w->dapm);
  1175. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1176. int ref, val, reg, idx = -EINVAL;
  1177. static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
  1178. static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
  1179. if (rt5682->is_sdw)
  1180. return 0;
  1181. val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
  1182. RT5682_GP4_PIN_MASK;
  1183. if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
  1184. val == RT5682_GP4_PIN_ADCDAT2)
  1185. ref = 256 * rt5682->lrck[RT5682_AIF2];
  1186. else
  1187. ref = 256 * rt5682->lrck[RT5682_AIF1];
  1188. idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
  1189. if (w->shift == RT5682_PWR_ADC_S1F_BIT)
  1190. reg = RT5682_PLL_TRACK_3;
  1191. else
  1192. reg = RT5682_PLL_TRACK_2;
  1193. snd_soc_component_update_bits(component, reg,
  1194. RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
  1195. /* select over sample rate */
  1196. for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
  1197. if (rt5682->sysclk <= 12288000 * div_o[idx])
  1198. break;
  1199. }
  1200. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
  1201. RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
  1202. (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
  1203. return 0;
  1204. }
  1205. static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
  1206. struct snd_soc_dapm_widget *sink)
  1207. {
  1208. unsigned int val;
  1209. struct snd_soc_component *component =
  1210. snd_soc_dapm_to_component(w->dapm);
  1211. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1212. val &= RT5682_SCLK_SRC_MASK;
  1213. if (val == RT5682_SCLK_SRC_PLL1)
  1214. return 1;
  1215. else
  1216. return 0;
  1217. }
  1218. static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
  1219. struct snd_soc_dapm_widget *sink)
  1220. {
  1221. unsigned int val;
  1222. struct snd_soc_component *component =
  1223. snd_soc_dapm_to_component(w->dapm);
  1224. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1225. val &= RT5682_SCLK_SRC_MASK;
  1226. if (val == RT5682_SCLK_SRC_PLL2)
  1227. return 1;
  1228. else
  1229. return 0;
  1230. }
  1231. static int is_using_asrc(struct snd_soc_dapm_widget *w,
  1232. struct snd_soc_dapm_widget *sink)
  1233. {
  1234. unsigned int reg, shift, val;
  1235. struct snd_soc_component *component =
  1236. snd_soc_dapm_to_component(w->dapm);
  1237. switch (w->shift) {
  1238. case RT5682_ADC_STO1_ASRC_SFT:
  1239. reg = RT5682_PLL_TRACK_3;
  1240. shift = RT5682_FILTER_CLK_SEL_SFT;
  1241. break;
  1242. case RT5682_DAC_STO1_ASRC_SFT:
  1243. reg = RT5682_PLL_TRACK_2;
  1244. shift = RT5682_FILTER_CLK_SEL_SFT;
  1245. break;
  1246. default:
  1247. return 0;
  1248. }
  1249. val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
  1250. switch (val) {
  1251. case RT5682_CLK_SEL_I2S1_ASRC:
  1252. case RT5682_CLK_SEL_I2S2_ASRC:
  1253. return 1;
  1254. default:
  1255. return 0;
  1256. }
  1257. }
  1258. /* Digital Mixer */
  1259. static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
  1260. SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
  1261. RT5682_M_STO1_ADC_L1_SFT, 1, 1),
  1262. SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
  1263. RT5682_M_STO1_ADC_L2_SFT, 1, 1),
  1264. };
  1265. static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
  1266. SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
  1267. RT5682_M_STO1_ADC_R1_SFT, 1, 1),
  1268. SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
  1269. RT5682_M_STO1_ADC_R2_SFT, 1, 1),
  1270. };
  1271. static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
  1272. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
  1273. RT5682_M_ADCMIX_L_SFT, 1, 1),
  1274. SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
  1275. RT5682_M_DAC1_L_SFT, 1, 1),
  1276. };
  1277. static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
  1278. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
  1279. RT5682_M_ADCMIX_R_SFT, 1, 1),
  1280. SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
  1281. RT5682_M_DAC1_R_SFT, 1, 1),
  1282. };
  1283. static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
  1284. SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
  1285. RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
  1286. SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
  1287. RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
  1288. };
  1289. static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
  1290. SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
  1291. RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
  1292. SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
  1293. RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
  1294. };
  1295. /* Analog Input Mixer */
  1296. static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
  1297. SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
  1298. RT5682_M_CBJ_RM1_L_SFT, 1, 1),
  1299. };
  1300. /* STO1 ADC1 Source */
  1301. /* MX-26 [13] [5] */
  1302. static const char * const rt5682_sto1_adc1_src[] = {
  1303. "DAC MIX", "ADC"
  1304. };
  1305. static SOC_ENUM_SINGLE_DECL(
  1306. rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
  1307. RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
  1308. static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
  1309. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
  1310. static SOC_ENUM_SINGLE_DECL(
  1311. rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
  1312. RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
  1313. static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
  1314. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
  1315. /* STO1 ADC Source */
  1316. /* MX-26 [11:10] [3:2] */
  1317. static const char * const rt5682_sto1_adc_src[] = {
  1318. "ADC1 L", "ADC1 R"
  1319. };
  1320. static SOC_ENUM_SINGLE_DECL(
  1321. rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
  1322. RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
  1323. static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
  1324. SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
  1325. static SOC_ENUM_SINGLE_DECL(
  1326. rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
  1327. RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
  1328. static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
  1329. SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
  1330. /* STO1 ADC2 Source */
  1331. /* MX-26 [12] [4] */
  1332. static const char * const rt5682_sto1_adc2_src[] = {
  1333. "DAC MIX", "DMIC"
  1334. };
  1335. static SOC_ENUM_SINGLE_DECL(
  1336. rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
  1337. RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
  1338. static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
  1339. SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
  1340. static SOC_ENUM_SINGLE_DECL(
  1341. rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
  1342. RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
  1343. static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
  1344. SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
  1345. /* MX-79 [6:4] I2S1 ADC data location */
  1346. static const unsigned int rt5682_if1_adc_slot_values[] = {
  1347. 0,
  1348. 2,
  1349. 4,
  1350. 6,
  1351. };
  1352. static const char * const rt5682_if1_adc_slot_src[] = {
  1353. "Slot 0", "Slot 2", "Slot 4", "Slot 6"
  1354. };
  1355. static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
  1356. RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
  1357. rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
  1358. static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
  1359. SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
  1360. /* Analog DAC L1 Source, Analog DAC R1 Source*/
  1361. /* MX-2B [4], MX-2B [0]*/
  1362. static const char * const rt5682_alg_dac1_src[] = {
  1363. "Stereo1 DAC Mixer", "DAC1"
  1364. };
  1365. static SOC_ENUM_SINGLE_DECL(
  1366. rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
  1367. RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
  1368. static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
  1369. SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
  1370. static SOC_ENUM_SINGLE_DECL(
  1371. rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
  1372. RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
  1373. static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
  1374. SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
  1375. /* Out Switch */
  1376. static const struct snd_kcontrol_new hpol_switch =
  1377. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
  1378. RT5682_L_MUTE_SFT, 1, 1);
  1379. static const struct snd_kcontrol_new hpor_switch =
  1380. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
  1381. RT5682_R_MUTE_SFT, 1, 1);
  1382. static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
  1383. struct snd_kcontrol *kcontrol, int event)
  1384. {
  1385. struct snd_soc_component *component =
  1386. snd_soc_dapm_to_component(w->dapm);
  1387. switch (event) {
  1388. case SND_SOC_DAPM_PRE_PMU:
  1389. snd_soc_component_write(component,
  1390. RT5682_HP_LOGIC_CTRL_2, 0x0012);
  1391. snd_soc_component_write(component,
  1392. RT5682_HP_CTRL_2, 0x6000);
  1393. snd_soc_component_update_bits(component,
  1394. RT5682_DEPOP_1, 0x60, 0x60);
  1395. snd_soc_component_update_bits(component,
  1396. RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
  1397. break;
  1398. case SND_SOC_DAPM_POST_PMD:
  1399. snd_soc_component_update_bits(component,
  1400. RT5682_DEPOP_1, 0x60, 0x0);
  1401. snd_soc_component_write(component,
  1402. RT5682_HP_CTRL_2, 0x0000);
  1403. snd_soc_component_update_bits(component,
  1404. RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
  1405. break;
  1406. }
  1407. return 0;
  1408. }
  1409. static int set_dmic_power(struct snd_soc_dapm_widget *w,
  1410. struct snd_kcontrol *kcontrol, int event)
  1411. {
  1412. struct snd_soc_component *component =
  1413. snd_soc_dapm_to_component(w->dapm);
  1414. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1415. unsigned int delay = 50, val;
  1416. if (rt5682->pdata.dmic_delay)
  1417. delay = rt5682->pdata.dmic_delay;
  1418. switch (event) {
  1419. case SND_SOC_DAPM_POST_PMU:
  1420. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1421. val &= RT5682_SCLK_SRC_MASK;
  1422. if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
  1423. snd_soc_component_update_bits(component,
  1424. RT5682_PWR_ANLG_1,
  1425. RT5682_PWR_VREF2 | RT5682_PWR_MB,
  1426. RT5682_PWR_VREF2 | RT5682_PWR_MB);
  1427. /*Add delay to avoid pop noise*/
  1428. msleep(delay);
  1429. break;
  1430. case SND_SOC_DAPM_POST_PMD:
  1431. if (!rt5682->jack_type) {
  1432. if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
  1433. snd_soc_component_update_bits(component,
  1434. RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
  1435. if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
  1436. snd_soc_component_update_bits(component,
  1437. RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
  1438. }
  1439. break;
  1440. }
  1441. return 0;
  1442. }
  1443. static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
  1444. struct snd_kcontrol *kcontrol, int event)
  1445. {
  1446. struct snd_soc_component *component =
  1447. snd_soc_dapm_to_component(w->dapm);
  1448. switch (event) {
  1449. case SND_SOC_DAPM_PRE_PMU:
  1450. switch (w->shift) {
  1451. case RT5682_PWR_VREF1_BIT:
  1452. snd_soc_component_update_bits(component,
  1453. RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
  1454. break;
  1455. case RT5682_PWR_VREF2_BIT:
  1456. snd_soc_component_update_bits(component,
  1457. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
  1458. break;
  1459. }
  1460. break;
  1461. case SND_SOC_DAPM_POST_PMU:
  1462. usleep_range(15000, 20000);
  1463. switch (w->shift) {
  1464. case RT5682_PWR_VREF1_BIT:
  1465. snd_soc_component_update_bits(component,
  1466. RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
  1467. RT5682_PWR_FV1);
  1468. break;
  1469. case RT5682_PWR_VREF2_BIT:
  1470. snd_soc_component_update_bits(component,
  1471. RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
  1472. RT5682_PWR_FV2);
  1473. break;
  1474. }
  1475. break;
  1476. }
  1477. return 0;
  1478. }
  1479. static const unsigned int rt5682_adcdat_pin_values[] = {
  1480. 1,
  1481. 3,
  1482. };
  1483. static const char * const rt5682_adcdat_pin_select[] = {
  1484. "ADCDAT1",
  1485. "ADCDAT2",
  1486. };
  1487. static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
  1488. RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
  1489. rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
  1490. static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
  1491. SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
  1492. static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
  1493. SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
  1494. 0, NULL, 0),
  1495. SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
  1496. 0, NULL, 0),
  1497. SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
  1498. 0, NULL, 0),
  1499. SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
  1500. 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
  1501. SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
  1502. rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1503. SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1504. SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
  1505. /* ASRC */
  1506. SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
  1507. RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
  1508. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
  1509. RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
  1510. SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
  1511. RT5682_AD_ASRC_SFT, 0, NULL, 0),
  1512. SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
  1513. RT5682_DA_ASRC_SFT, 0, NULL, 0),
  1514. SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
  1515. RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
  1516. /* Input Side */
  1517. SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
  1518. 0, NULL, 0),
  1519. SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
  1520. 0, NULL, 0),
  1521. /* Input Lines */
  1522. SND_SOC_DAPM_INPUT("DMIC L1"),
  1523. SND_SOC_DAPM_INPUT("DMIC R1"),
  1524. SND_SOC_DAPM_INPUT("IN1P"),
  1525. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  1526. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  1527. SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
  1528. RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
  1529. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1530. /* Boost */
  1531. SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
  1532. 0, 0, NULL, 0),
  1533. /* REC Mixer */
  1534. SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
  1535. ARRAY_SIZE(rt5682_rec1_l_mix)),
  1536. SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
  1537. RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
  1538. /* ADCs */
  1539. SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
  1540. SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
  1541. SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
  1542. RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
  1543. SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
  1544. RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
  1545. SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
  1546. RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
  1547. /* ADC Mux */
  1548. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  1549. &rt5682_sto1_adc1l_mux),
  1550. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  1551. &rt5682_sto1_adc1r_mux),
  1552. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  1553. &rt5682_sto1_adc2l_mux),
  1554. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  1555. &rt5682_sto1_adc2r_mux),
  1556. SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
  1557. &rt5682_sto1_adcl_mux),
  1558. SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
  1559. &rt5682_sto1_adcr_mux),
  1560. SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
  1561. &rt5682_if1_adc_slot_mux),
  1562. /* ADC Mixer */
  1563. SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
  1564. RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
  1565. SND_SOC_DAPM_PRE_PMU),
  1566. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
  1567. RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
  1568. ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
  1569. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
  1570. RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
  1571. ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
  1572. SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
  1573. 14, 1, NULL, 0),
  1574. /* ADC PGA */
  1575. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  1576. /* Digital Interface */
  1577. SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
  1578. 0, NULL, 0),
  1579. SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
  1580. 0, NULL, 0),
  1581. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1582. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1583. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1584. SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1585. SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1586. /* Digital Interface Select */
  1587. SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1588. &rt5682_if1_01_adc_swap_mux),
  1589. SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1590. &rt5682_if1_23_adc_swap_mux),
  1591. SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1592. &rt5682_if1_45_adc_swap_mux),
  1593. SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1594. &rt5682_if1_67_adc_swap_mux),
  1595. SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1596. &rt5682_if2_adc_swap_mux),
  1597. SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
  1598. &rt5682_adcdat_pin_ctrl),
  1599. SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
  1600. &rt5682_dac_l_mux),
  1601. SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
  1602. &rt5682_dac_r_mux),
  1603. /* Audio Interface */
  1604. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
  1605. RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
  1606. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
  1607. RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
  1608. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  1609. SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
  1610. SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
  1611. /* Output Side */
  1612. /* DAC mixer before sound effect */
  1613. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  1614. rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
  1615. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  1616. rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
  1617. /* DAC channel Mux */
  1618. SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
  1619. &rt5682_alg_dac_l1_mux),
  1620. SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
  1621. &rt5682_alg_dac_r1_mux),
  1622. /* DAC Mixer */
  1623. SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
  1624. RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
  1625. SND_SOC_DAPM_PRE_PMU),
  1626. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
  1627. rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
  1628. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
  1629. rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
  1630. /* DACs */
  1631. SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
  1632. RT5682_PWR_DAC_L1_BIT, 0),
  1633. SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
  1634. RT5682_PWR_DAC_R1_BIT, 0),
  1635. SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
  1636. RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
  1637. /* HPO */
  1638. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
  1639. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
  1640. SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
  1641. RT5682_PWR_HA_L_BIT, 0, NULL, 0),
  1642. SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
  1643. RT5682_PWR_HA_R_BIT, 0, NULL, 0),
  1644. SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
  1645. RT5682_PUMP_EN_SFT, 0, NULL, 0),
  1646. SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
  1647. RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
  1648. SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
  1649. &hpol_switch),
  1650. SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
  1651. &hpor_switch),
  1652. /* CLK DET */
  1653. SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
  1654. RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
  1655. SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
  1656. RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
  1657. SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
  1658. RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
  1659. SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
  1660. RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
  1661. /* Output Lines */
  1662. SND_SOC_DAPM_OUTPUT("HPOL"),
  1663. SND_SOC_DAPM_OUTPUT("HPOR"),
  1664. };
  1665. static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
  1666. /*PLL*/
  1667. {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1668. {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
  1669. {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
  1670. {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1671. {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
  1672. {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
  1673. /*ASRC*/
  1674. {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
  1675. {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
  1676. {"ADC STO1 ASRC", NULL, "AD ASRC"},
  1677. {"ADC STO1 ASRC", NULL, "DA ASRC"},
  1678. {"ADC STO1 ASRC", NULL, "CLKDET"},
  1679. {"DAC STO1 ASRC", NULL, "AD ASRC"},
  1680. {"DAC STO1 ASRC", NULL, "DA ASRC"},
  1681. {"DAC STO1 ASRC", NULL, "CLKDET"},
  1682. /*Vref*/
  1683. {"MICBIAS1", NULL, "Vref1"},
  1684. {"MICBIAS2", NULL, "Vref1"},
  1685. {"CLKDET SYS", NULL, "CLKDET"},
  1686. {"IN1P", NULL, "LDO2"},
  1687. {"BST1 CBJ", NULL, "IN1P"},
  1688. {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
  1689. {"RECMIX1L", NULL, "RECMIX1L Power"},
  1690. {"ADC1 L", NULL, "RECMIX1L"},
  1691. {"ADC1 L", NULL, "ADC1 L Power"},
  1692. {"ADC1 L", NULL, "ADC1 clock"},
  1693. {"DMIC L1", NULL, "DMIC CLK"},
  1694. {"DMIC L1", NULL, "DMIC1 Power"},
  1695. {"DMIC R1", NULL, "DMIC CLK"},
  1696. {"DMIC R1", NULL, "DMIC1 Power"},
  1697. {"DMIC CLK", NULL, "DMIC ASRC"},
  1698. {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
  1699. {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
  1700. {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
  1701. {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
  1702. {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
  1703. {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1704. {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
  1705. {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1706. {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
  1707. {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1708. {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
  1709. {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1710. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  1711. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  1712. {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
  1713. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  1714. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  1715. {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
  1716. {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
  1717. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
  1718. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
  1719. {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1720. {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1721. {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1722. {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1723. {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1724. {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1725. {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1726. {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1727. {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1728. {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1729. {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1730. {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1731. {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1732. {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1733. {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1734. {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1735. {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
  1736. {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
  1737. {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
  1738. {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
  1739. {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
  1740. {"AIF1TX", NULL, "I2S1"},
  1741. {"AIF1TX", NULL, "ADCDAT Mux"},
  1742. {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1743. {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1744. {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1745. {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1746. {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
  1747. {"AIF2TX", NULL, "ADCDAT Mux"},
  1748. {"SDWTX", NULL, "PLL2B"},
  1749. {"SDWTX", NULL, "PLL2F"},
  1750. {"SDWTX", NULL, "ADCDAT Mux"},
  1751. {"IF1 DAC1 L", NULL, "AIF1RX"},
  1752. {"IF1 DAC1 L", NULL, "I2S1"},
  1753. {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
  1754. {"IF1 DAC1 R", NULL, "AIF1RX"},
  1755. {"IF1 DAC1 R", NULL, "I2S1"},
  1756. {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
  1757. {"SOUND DAC L", NULL, "SDWRX"},
  1758. {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
  1759. {"SOUND DAC L", NULL, "PLL2B"},
  1760. {"SOUND DAC L", NULL, "PLL2F"},
  1761. {"SOUND DAC R", NULL, "SDWRX"},
  1762. {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
  1763. {"SOUND DAC R", NULL, "PLL2B"},
  1764. {"SOUND DAC R", NULL, "PLL2F"},
  1765. {"DAC L Mux", "IF1", "IF1 DAC1 L"},
  1766. {"DAC L Mux", "SOUND", "SOUND DAC L"},
  1767. {"DAC R Mux", "IF1", "IF1 DAC1 R"},
  1768. {"DAC R Mux", "SOUND", "SOUND DAC R"},
  1769. {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  1770. {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
  1771. {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  1772. {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
  1773. {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  1774. {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
  1775. {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  1776. {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
  1777. {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
  1778. {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
  1779. {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
  1780. {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
  1781. {"DAC L1", NULL, "DAC L1 Source"},
  1782. {"DAC R1", NULL, "DAC R1 Source"},
  1783. {"DAC L1", NULL, "DAC 1 Clock"},
  1784. {"DAC R1", NULL, "DAC 1 Clock"},
  1785. {"HP Amp", NULL, "DAC L1"},
  1786. {"HP Amp", NULL, "DAC R1"},
  1787. {"HP Amp", NULL, "HP Amp L"},
  1788. {"HP Amp", NULL, "HP Amp R"},
  1789. {"HP Amp", NULL, "Capless"},
  1790. {"HP Amp", NULL, "Charge Pump"},
  1791. {"HP Amp", NULL, "CLKDET SYS"},
  1792. {"HP Amp", NULL, "Vref1"},
  1793. {"HPOL Playback", "Switch", "HP Amp"},
  1794. {"HPOR Playback", "Switch", "HP Amp"},
  1795. {"HPOL", NULL, "HPOL Playback"},
  1796. {"HPOR", NULL, "HPOR Playback"},
  1797. };
  1798. static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1799. unsigned int rx_mask, int slots, int slot_width)
  1800. {
  1801. struct snd_soc_component *component = dai->component;
  1802. unsigned int cl, val = 0;
  1803. if (tx_mask || rx_mask)
  1804. snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
  1805. RT5682_TDM_EN, RT5682_TDM_EN);
  1806. else
  1807. snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
  1808. RT5682_TDM_EN, 0);
  1809. switch (slots) {
  1810. case 4:
  1811. val |= RT5682_TDM_TX_CH_4;
  1812. val |= RT5682_TDM_RX_CH_4;
  1813. break;
  1814. case 6:
  1815. val |= RT5682_TDM_TX_CH_6;
  1816. val |= RT5682_TDM_RX_CH_6;
  1817. break;
  1818. case 8:
  1819. val |= RT5682_TDM_TX_CH_8;
  1820. val |= RT5682_TDM_RX_CH_8;
  1821. break;
  1822. case 2:
  1823. break;
  1824. default:
  1825. return -EINVAL;
  1826. }
  1827. snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
  1828. RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
  1829. switch (slot_width) {
  1830. case 8:
  1831. if (tx_mask || rx_mask)
  1832. return -EINVAL;
  1833. cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
  1834. break;
  1835. case 16:
  1836. val = RT5682_TDM_CL_16;
  1837. cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
  1838. break;
  1839. case 20:
  1840. val = RT5682_TDM_CL_20;
  1841. cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
  1842. break;
  1843. case 24:
  1844. val = RT5682_TDM_CL_24;
  1845. cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
  1846. break;
  1847. case 32:
  1848. val = RT5682_TDM_CL_32;
  1849. cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
  1850. break;
  1851. default:
  1852. return -EINVAL;
  1853. }
  1854. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  1855. RT5682_TDM_CL_MASK, val);
  1856. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  1857. RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
  1858. return 0;
  1859. }
  1860. static int rt5682_hw_params(struct snd_pcm_substream *substream,
  1861. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1862. {
  1863. struct snd_soc_component *component = dai->component;
  1864. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1865. unsigned int len_1 = 0, len_2 = 0;
  1866. int pre_div, frame_size;
  1867. rt5682->lrck[dai->id] = params_rate(params);
  1868. pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
  1869. frame_size = snd_soc_params_to_frame_size(params);
  1870. if (frame_size < 0) {
  1871. dev_err(component->dev, "Unsupported frame size: %d\n",
  1872. frame_size);
  1873. return -EINVAL;
  1874. }
  1875. dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  1876. rt5682->lrck[dai->id], pre_div, dai->id);
  1877. switch (params_width(params)) {
  1878. case 16:
  1879. break;
  1880. case 20:
  1881. len_1 |= RT5682_I2S1_DL_20;
  1882. len_2 |= RT5682_I2S2_DL_20;
  1883. break;
  1884. case 24:
  1885. len_1 |= RT5682_I2S1_DL_24;
  1886. len_2 |= RT5682_I2S2_DL_24;
  1887. break;
  1888. case 32:
  1889. len_1 |= RT5682_I2S1_DL_32;
  1890. len_2 |= RT5682_I2S2_DL_24;
  1891. break;
  1892. case 8:
  1893. len_1 |= RT5682_I2S2_DL_8;
  1894. len_2 |= RT5682_I2S2_DL_8;
  1895. break;
  1896. default:
  1897. return -EINVAL;
  1898. }
  1899. switch (dai->id) {
  1900. case RT5682_AIF1:
  1901. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  1902. RT5682_I2S1_DL_MASK, len_1);
  1903. if (rt5682->master[RT5682_AIF1]) {
  1904. snd_soc_component_update_bits(component,
  1905. RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
  1906. RT5682_I2S_CLK_SRC_MASK,
  1907. pre_div << RT5682_I2S_M_DIV_SFT |
  1908. (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
  1909. }
  1910. if (params_channels(params) == 1) /* mono mode */
  1911. snd_soc_component_update_bits(component,
  1912. RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
  1913. RT5682_I2S1_MONO_EN);
  1914. else
  1915. snd_soc_component_update_bits(component,
  1916. RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
  1917. RT5682_I2S1_MONO_DIS);
  1918. break;
  1919. case RT5682_AIF2:
  1920. snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
  1921. RT5682_I2S2_DL_MASK, len_2);
  1922. if (rt5682->master[RT5682_AIF2]) {
  1923. snd_soc_component_update_bits(component,
  1924. RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
  1925. pre_div << RT5682_I2S2_M_PD_SFT);
  1926. }
  1927. if (params_channels(params) == 1) /* mono mode */
  1928. snd_soc_component_update_bits(component,
  1929. RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
  1930. RT5682_I2S2_MONO_EN);
  1931. else
  1932. snd_soc_component_update_bits(component,
  1933. RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
  1934. RT5682_I2S2_MONO_DIS);
  1935. break;
  1936. default:
  1937. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  1938. return -EINVAL;
  1939. }
  1940. return 0;
  1941. }
  1942. static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1943. {
  1944. struct snd_soc_component *component = dai->component;
  1945. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1946. unsigned int reg_val = 0, tdm_ctrl = 0;
  1947. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1948. case SND_SOC_DAIFMT_CBM_CFM:
  1949. rt5682->master[dai->id] = 1;
  1950. break;
  1951. case SND_SOC_DAIFMT_CBS_CFS:
  1952. rt5682->master[dai->id] = 0;
  1953. break;
  1954. default:
  1955. return -EINVAL;
  1956. }
  1957. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1958. case SND_SOC_DAIFMT_NB_NF:
  1959. break;
  1960. case SND_SOC_DAIFMT_IB_NF:
  1961. reg_val |= RT5682_I2S_BP_INV;
  1962. tdm_ctrl |= RT5682_TDM_S_BP_INV;
  1963. break;
  1964. case SND_SOC_DAIFMT_NB_IF:
  1965. if (dai->id == RT5682_AIF1)
  1966. tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
  1967. else
  1968. return -EINVAL;
  1969. break;
  1970. case SND_SOC_DAIFMT_IB_IF:
  1971. if (dai->id == RT5682_AIF1)
  1972. tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
  1973. RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
  1974. else
  1975. return -EINVAL;
  1976. break;
  1977. default:
  1978. return -EINVAL;
  1979. }
  1980. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1981. case SND_SOC_DAIFMT_I2S:
  1982. break;
  1983. case SND_SOC_DAIFMT_LEFT_J:
  1984. reg_val |= RT5682_I2S_DF_LEFT;
  1985. tdm_ctrl |= RT5682_TDM_DF_LEFT;
  1986. break;
  1987. case SND_SOC_DAIFMT_DSP_A:
  1988. reg_val |= RT5682_I2S_DF_PCM_A;
  1989. tdm_ctrl |= RT5682_TDM_DF_PCM_A;
  1990. break;
  1991. case SND_SOC_DAIFMT_DSP_B:
  1992. reg_val |= RT5682_I2S_DF_PCM_B;
  1993. tdm_ctrl |= RT5682_TDM_DF_PCM_B;
  1994. break;
  1995. default:
  1996. return -EINVAL;
  1997. }
  1998. switch (dai->id) {
  1999. case RT5682_AIF1:
  2000. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  2001. RT5682_I2S_DF_MASK, reg_val);
  2002. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2003. RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
  2004. RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
  2005. RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
  2006. tdm_ctrl | rt5682->master[dai->id]);
  2007. break;
  2008. case RT5682_AIF2:
  2009. if (rt5682->master[dai->id] == 0)
  2010. reg_val |= RT5682_I2S2_MS_S;
  2011. snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
  2012. RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
  2013. RT5682_I2S_DF_MASK, reg_val);
  2014. break;
  2015. default:
  2016. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  2017. return -EINVAL;
  2018. }
  2019. return 0;
  2020. }
  2021. static int rt5682_set_component_sysclk(struct snd_soc_component *component,
  2022. int clk_id, int source, unsigned int freq, int dir)
  2023. {
  2024. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2025. unsigned int reg_val = 0, src = 0;
  2026. if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
  2027. return 0;
  2028. switch (clk_id) {
  2029. case RT5682_SCLK_S_MCLK:
  2030. reg_val |= RT5682_SCLK_SRC_MCLK;
  2031. src = RT5682_CLK_SRC_MCLK;
  2032. break;
  2033. case RT5682_SCLK_S_PLL1:
  2034. reg_val |= RT5682_SCLK_SRC_PLL1;
  2035. src = RT5682_CLK_SRC_PLL1;
  2036. break;
  2037. case RT5682_SCLK_S_PLL2:
  2038. reg_val |= RT5682_SCLK_SRC_PLL2;
  2039. src = RT5682_CLK_SRC_PLL2;
  2040. break;
  2041. case RT5682_SCLK_S_RCCLK:
  2042. reg_val |= RT5682_SCLK_SRC_RCCLK;
  2043. src = RT5682_CLK_SRC_RCCLK;
  2044. break;
  2045. default:
  2046. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  2047. return -EINVAL;
  2048. }
  2049. snd_soc_component_update_bits(component, RT5682_GLB_CLK,
  2050. RT5682_SCLK_SRC_MASK, reg_val);
  2051. if (rt5682->master[RT5682_AIF2]) {
  2052. snd_soc_component_update_bits(component,
  2053. RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
  2054. src << RT5682_I2S2_SRC_SFT);
  2055. }
  2056. rt5682->sysclk = freq;
  2057. rt5682->sysclk_src = clk_id;
  2058. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  2059. freq, clk_id);
  2060. return 0;
  2061. }
  2062. static int rt5682_set_component_pll(struct snd_soc_component *component,
  2063. int pll_id, int source, unsigned int freq_in,
  2064. unsigned int freq_out)
  2065. {
  2066. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2067. struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
  2068. unsigned int pll2_fout1, pll2_ps_val;
  2069. int ret;
  2070. if (source == rt5682->pll_src[pll_id] &&
  2071. freq_in == rt5682->pll_in[pll_id] &&
  2072. freq_out == rt5682->pll_out[pll_id])
  2073. return 0;
  2074. if (!freq_in || !freq_out) {
  2075. dev_dbg(component->dev, "PLL disabled\n");
  2076. rt5682->pll_in[pll_id] = 0;
  2077. rt5682->pll_out[pll_id] = 0;
  2078. snd_soc_component_update_bits(component, RT5682_GLB_CLK,
  2079. RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
  2080. return 0;
  2081. }
  2082. if (pll_id == RT5682_PLL2) {
  2083. switch (source) {
  2084. case RT5682_PLL2_S_MCLK:
  2085. snd_soc_component_update_bits(component,
  2086. RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
  2087. RT5682_PLL2_SRC_MCLK);
  2088. break;
  2089. default:
  2090. dev_err(component->dev, "Unknown PLL2 Source %d\n",
  2091. source);
  2092. return -EINVAL;
  2093. }
  2094. /**
  2095. * PLL2 concatenates 2 PLL units.
  2096. * We suggest the Fout of the front PLL is 3.84MHz.
  2097. */
  2098. pll2_fout1 = 3840000;
  2099. ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
  2100. if (ret < 0) {
  2101. dev_err(component->dev, "Unsupport input clock %d\n",
  2102. freq_in);
  2103. return ret;
  2104. }
  2105. dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
  2106. freq_in, pll2_fout1,
  2107. pll2f_code.m_bp,
  2108. (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
  2109. pll2f_code.n_code, pll2f_code.k_code);
  2110. ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
  2111. if (ret < 0) {
  2112. dev_err(component->dev, "Unsupport input clock %d\n",
  2113. pll2_fout1);
  2114. return ret;
  2115. }
  2116. dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
  2117. pll2_fout1, freq_out,
  2118. pll2b_code.m_bp,
  2119. (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
  2120. pll2b_code.n_code, pll2b_code.k_code);
  2121. snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
  2122. pll2f_code.k_code << RT5682_PLL2F_K_SFT |
  2123. pll2b_code.k_code << RT5682_PLL2B_K_SFT |
  2124. pll2b_code.m_code);
  2125. snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
  2126. pll2f_code.m_code << RT5682_PLL2F_M_SFT |
  2127. pll2b_code.n_code);
  2128. snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
  2129. pll2f_code.n_code << RT5682_PLL2F_N_SFT);
  2130. if (freq_out == 22579200)
  2131. pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
  2132. else
  2133. pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
  2134. snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
  2135. RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
  2136. RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
  2137. pll2_ps_val |
  2138. (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
  2139. (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
  2140. 0xf);
  2141. } else {
  2142. switch (source) {
  2143. case RT5682_PLL1_S_MCLK:
  2144. snd_soc_component_update_bits(component,
  2145. RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
  2146. RT5682_PLL1_SRC_MCLK);
  2147. break;
  2148. case RT5682_PLL1_S_BCLK1:
  2149. snd_soc_component_update_bits(component,
  2150. RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
  2151. RT5682_PLL1_SRC_BCLK1);
  2152. break;
  2153. default:
  2154. dev_err(component->dev, "Unknown PLL1 Source %d\n",
  2155. source);
  2156. return -EINVAL;
  2157. }
  2158. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  2159. if (ret < 0) {
  2160. dev_err(component->dev, "Unsupport input clock %d\n",
  2161. freq_in);
  2162. return ret;
  2163. }
  2164. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  2165. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  2166. pll_code.n_code, pll_code.k_code);
  2167. snd_soc_component_write(component, RT5682_PLL_CTRL_1,
  2168. pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
  2169. snd_soc_component_write(component, RT5682_PLL_CTRL_2,
  2170. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
  2171. pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
  2172. }
  2173. rt5682->pll_in[pll_id] = freq_in;
  2174. rt5682->pll_out[pll_id] = freq_out;
  2175. rt5682->pll_src[pll_id] = source;
  2176. return 0;
  2177. }
  2178. static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  2179. {
  2180. struct snd_soc_component *component = dai->component;
  2181. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2182. rt5682->bclk[dai->id] = ratio;
  2183. switch (ratio) {
  2184. case 256:
  2185. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2186. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
  2187. break;
  2188. case 128:
  2189. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2190. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
  2191. break;
  2192. case 64:
  2193. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2194. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
  2195. break;
  2196. case 32:
  2197. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2198. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
  2199. break;
  2200. default:
  2201. dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
  2202. return -EINVAL;
  2203. }
  2204. return 0;
  2205. }
  2206. static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  2207. {
  2208. struct snd_soc_component *component = dai->component;
  2209. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2210. rt5682->bclk[dai->id] = ratio;
  2211. switch (ratio) {
  2212. case 64:
  2213. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
  2214. RT5682_I2S2_BCLK_MS2_MASK,
  2215. RT5682_I2S2_BCLK_MS2_64);
  2216. break;
  2217. case 32:
  2218. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
  2219. RT5682_I2S2_BCLK_MS2_MASK,
  2220. RT5682_I2S2_BCLK_MS2_32);
  2221. break;
  2222. default:
  2223. dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
  2224. return -EINVAL;
  2225. }
  2226. return 0;
  2227. }
  2228. static int rt5682_set_bias_level(struct snd_soc_component *component,
  2229. enum snd_soc_bias_level level)
  2230. {
  2231. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2232. switch (level) {
  2233. case SND_SOC_BIAS_PREPARE:
  2234. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
  2235. RT5682_PWR_BG, RT5682_PWR_BG);
  2236. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2237. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
  2238. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
  2239. break;
  2240. case SND_SOC_BIAS_STANDBY:
  2241. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2242. RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
  2243. break;
  2244. case SND_SOC_BIAS_OFF:
  2245. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2246. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
  2247. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
  2248. RT5682_PWR_BG, 0);
  2249. break;
  2250. case SND_SOC_BIAS_ON:
  2251. break;
  2252. }
  2253. return 0;
  2254. }
  2255. #ifdef CONFIG_COMMON_CLK
  2256. #define CLK_PLL2_FIN 48000000
  2257. #define CLK_48 48000
  2258. #define CLK_44 44100
  2259. static bool rt5682_clk_check(struct rt5682_priv *rt5682)
  2260. {
  2261. if (!rt5682->master[RT5682_AIF1]) {
  2262. dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
  2263. return false;
  2264. }
  2265. return true;
  2266. }
  2267. static int rt5682_wclk_prepare(struct clk_hw *hw)
  2268. {
  2269. struct rt5682_priv *rt5682 =
  2270. container_of(hw, struct rt5682_priv,
  2271. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2272. struct snd_soc_component *component = rt5682->component;
  2273. struct snd_soc_dapm_context *dapm =
  2274. snd_soc_component_get_dapm(component);
  2275. if (!rt5682_clk_check(rt5682))
  2276. return -EINVAL;
  2277. snd_soc_dapm_mutex_lock(dapm);
  2278. snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
  2279. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2280. RT5682_PWR_MB, RT5682_PWR_MB);
  2281. snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
  2282. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2283. RT5682_PWR_VREF2 | RT5682_PWR_FV2,
  2284. RT5682_PWR_VREF2);
  2285. usleep_range(55000, 60000);
  2286. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2287. RT5682_PWR_FV2, RT5682_PWR_FV2);
  2288. snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
  2289. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
  2290. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
  2291. snd_soc_dapm_sync_unlocked(dapm);
  2292. snd_soc_dapm_mutex_unlock(dapm);
  2293. return 0;
  2294. }
  2295. static void rt5682_wclk_unprepare(struct clk_hw *hw)
  2296. {
  2297. struct rt5682_priv *rt5682 =
  2298. container_of(hw, struct rt5682_priv,
  2299. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2300. struct snd_soc_component *component = rt5682->component;
  2301. struct snd_soc_dapm_context *dapm =
  2302. snd_soc_component_get_dapm(component);
  2303. if (!rt5682_clk_check(rt5682))
  2304. return;
  2305. snd_soc_dapm_mutex_lock(dapm);
  2306. snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
  2307. snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
  2308. if (!rt5682->jack_type)
  2309. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2310. RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
  2311. RT5682_PWR_MB, 0);
  2312. snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
  2313. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
  2314. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
  2315. snd_soc_dapm_sync_unlocked(dapm);
  2316. snd_soc_dapm_mutex_unlock(dapm);
  2317. }
  2318. static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
  2319. unsigned long parent_rate)
  2320. {
  2321. struct rt5682_priv *rt5682 =
  2322. container_of(hw, struct rt5682_priv,
  2323. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2324. struct snd_soc_component *component = rt5682->component;
  2325. const char * const clk_name = clk_hw_get_name(hw);
  2326. if (!rt5682_clk_check(rt5682))
  2327. return 0;
  2328. /*
  2329. * Only accept to set wclk rate to 44.1k or 48kHz.
  2330. */
  2331. if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
  2332. rt5682->lrck[RT5682_AIF1] != CLK_44) {
  2333. dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
  2334. __func__, clk_name, CLK_44, CLK_48);
  2335. return 0;
  2336. }
  2337. return rt5682->lrck[RT5682_AIF1];
  2338. }
  2339. static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
  2340. unsigned long *parent_rate)
  2341. {
  2342. struct rt5682_priv *rt5682 =
  2343. container_of(hw, struct rt5682_priv,
  2344. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2345. struct snd_soc_component *component = rt5682->component;
  2346. const char * const clk_name = clk_hw_get_name(hw);
  2347. if (!rt5682_clk_check(rt5682))
  2348. return -EINVAL;
  2349. /*
  2350. * Only accept to set wclk rate to 44.1k or 48kHz.
  2351. * It will force to 48kHz if not both.
  2352. */
  2353. if (rate != CLK_48 && rate != CLK_44) {
  2354. dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
  2355. __func__, clk_name, CLK_44, CLK_48);
  2356. rate = CLK_48;
  2357. }
  2358. return rate;
  2359. }
  2360. static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
  2361. unsigned long parent_rate)
  2362. {
  2363. struct rt5682_priv *rt5682 =
  2364. container_of(hw, struct rt5682_priv,
  2365. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2366. struct snd_soc_component *component = rt5682->component;
  2367. struct clk *parent_clk;
  2368. const char * const clk_name = clk_hw_get_name(hw);
  2369. int pre_div;
  2370. unsigned int clk_pll2_out;
  2371. if (!rt5682_clk_check(rt5682))
  2372. return -EINVAL;
  2373. /*
  2374. * Whether the wclk's parent clk (mclk) exists or not, please ensure
  2375. * it is fixed or set to 48MHz before setting wclk rate. It's a
  2376. * temporary limitation. Only accept 48MHz clk as the clk provider.
  2377. *
  2378. * It will set the codec anyway by assuming mclk is 48MHz.
  2379. */
  2380. parent_clk = clk_get_parent(hw->clk);
  2381. if (!parent_clk)
  2382. dev_warn(component->dev,
  2383. "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
  2384. CLK_PLL2_FIN);
  2385. if (parent_rate != CLK_PLL2_FIN)
  2386. dev_warn(component->dev, "clk %s only support %d Hz input\n",
  2387. clk_name, CLK_PLL2_FIN);
  2388. /*
  2389. * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
  2390. * PLL2 is needed.
  2391. */
  2392. clk_pll2_out = rate * 512;
  2393. rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
  2394. CLK_PLL2_FIN, clk_pll2_out);
  2395. rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
  2396. clk_pll2_out, SND_SOC_CLOCK_IN);
  2397. rt5682->lrck[RT5682_AIF1] = rate;
  2398. pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
  2399. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
  2400. RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
  2401. pre_div << RT5682_I2S_M_DIV_SFT |
  2402. (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
  2403. return 0;
  2404. }
  2405. static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
  2406. unsigned long parent_rate)
  2407. {
  2408. struct rt5682_priv *rt5682 =
  2409. container_of(hw, struct rt5682_priv,
  2410. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2411. struct snd_soc_component *component = rt5682->component;
  2412. unsigned int bclks_per_wclk;
  2413. bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
  2414. switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
  2415. case RT5682_TDM_BCLK_MS1_256:
  2416. return parent_rate * 256;
  2417. case RT5682_TDM_BCLK_MS1_128:
  2418. return parent_rate * 128;
  2419. case RT5682_TDM_BCLK_MS1_64:
  2420. return parent_rate * 64;
  2421. case RT5682_TDM_BCLK_MS1_32:
  2422. return parent_rate * 32;
  2423. default:
  2424. return 0;
  2425. }
  2426. }
  2427. static unsigned long rt5682_bclk_get_factor(unsigned long rate,
  2428. unsigned long parent_rate)
  2429. {
  2430. unsigned long factor;
  2431. factor = rate / parent_rate;
  2432. if (factor < 64)
  2433. return 32;
  2434. else if (factor < 128)
  2435. return 64;
  2436. else if (factor < 256)
  2437. return 128;
  2438. else
  2439. return 256;
  2440. }
  2441. static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
  2442. unsigned long *parent_rate)
  2443. {
  2444. struct rt5682_priv *rt5682 =
  2445. container_of(hw, struct rt5682_priv,
  2446. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2447. unsigned long factor;
  2448. if (!*parent_rate || !rt5682_clk_check(rt5682))
  2449. return -EINVAL;
  2450. /*
  2451. * BCLK rates are set as a multiplier of WCLK in HW.
  2452. * We don't allow changing the parent WCLK. We just do
  2453. * some rounding down based on the parent WCLK rate
  2454. * and find the appropriate multiplier of BCLK to
  2455. * get the rounded down BCLK value.
  2456. */
  2457. factor = rt5682_bclk_get_factor(rate, *parent_rate);
  2458. return *parent_rate * factor;
  2459. }
  2460. static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
  2461. unsigned long parent_rate)
  2462. {
  2463. struct rt5682_priv *rt5682 =
  2464. container_of(hw, struct rt5682_priv,
  2465. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2466. struct snd_soc_component *component = rt5682->component;
  2467. struct snd_soc_dai *dai = NULL;
  2468. unsigned long factor;
  2469. if (!rt5682_clk_check(rt5682))
  2470. return -EINVAL;
  2471. factor = rt5682_bclk_get_factor(rate, parent_rate);
  2472. for_each_component_dais(component, dai)
  2473. if (dai->id == RT5682_AIF1)
  2474. break;
  2475. if (!dai) {
  2476. dev_err(component->dev, "dai %d not found in component\n",
  2477. RT5682_AIF1);
  2478. return -ENODEV;
  2479. }
  2480. return rt5682_set_bclk1_ratio(dai, factor);
  2481. }
  2482. static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
  2483. [RT5682_DAI_WCLK_IDX] = {
  2484. .prepare = rt5682_wclk_prepare,
  2485. .unprepare = rt5682_wclk_unprepare,
  2486. .recalc_rate = rt5682_wclk_recalc_rate,
  2487. .round_rate = rt5682_wclk_round_rate,
  2488. .set_rate = rt5682_wclk_set_rate,
  2489. },
  2490. [RT5682_DAI_BCLK_IDX] = {
  2491. .recalc_rate = rt5682_bclk_recalc_rate,
  2492. .round_rate = rt5682_bclk_round_rate,
  2493. .set_rate = rt5682_bclk_set_rate,
  2494. },
  2495. };
  2496. static int rt5682_register_dai_clks(struct snd_soc_component *component)
  2497. {
  2498. struct device *dev = component->dev;
  2499. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2500. struct rt5682_platform_data *pdata = &rt5682->pdata;
  2501. struct clk_hw *dai_clk_hw;
  2502. int i, ret;
  2503. for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
  2504. struct clk_init_data init = { };
  2505. struct clk_parent_data parent_data;
  2506. const struct clk_hw *parent;
  2507. dai_clk_hw = &rt5682->dai_clks_hw[i];
  2508. switch (i) {
  2509. case RT5682_DAI_WCLK_IDX:
  2510. /* Make MCLK the parent of WCLK */
  2511. if (rt5682->mclk) {
  2512. parent_data = (struct clk_parent_data){
  2513. .fw_name = "mclk",
  2514. };
  2515. init.parent_data = &parent_data;
  2516. init.num_parents = 1;
  2517. }
  2518. break;
  2519. case RT5682_DAI_BCLK_IDX:
  2520. /* Make WCLK the parent of BCLK */
  2521. parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
  2522. init.parent_hws = &parent;
  2523. init.num_parents = 1;
  2524. break;
  2525. default:
  2526. dev_err(dev, "Invalid clock index\n");
  2527. return -EINVAL;
  2528. }
  2529. init.name = pdata->dai_clk_names[i];
  2530. init.ops = &rt5682_dai_clk_ops[i];
  2531. init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
  2532. dai_clk_hw->init = &init;
  2533. ret = devm_clk_hw_register(dev, dai_clk_hw);
  2534. if (ret) {
  2535. dev_warn(dev, "Failed to register %s: %d\n",
  2536. init.name, ret);
  2537. return ret;
  2538. }
  2539. if (dev->of_node) {
  2540. devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
  2541. dai_clk_hw);
  2542. } else {
  2543. ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
  2544. init.name,
  2545. dev_name(dev));
  2546. if (ret)
  2547. return ret;
  2548. }
  2549. }
  2550. return 0;
  2551. }
  2552. #endif /* CONFIG_COMMON_CLK */
  2553. static int rt5682_probe(struct snd_soc_component *component)
  2554. {
  2555. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2556. struct sdw_slave *slave;
  2557. unsigned long time;
  2558. struct snd_soc_dapm_context *dapm = &component->dapm;
  2559. #ifdef CONFIG_COMMON_CLK
  2560. int ret;
  2561. #endif
  2562. rt5682->component = component;
  2563. if (rt5682->is_sdw) {
  2564. slave = rt5682->slave;
  2565. time = wait_for_completion_timeout(
  2566. &slave->initialization_complete,
  2567. msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
  2568. if (!time) {
  2569. dev_err(&slave->dev, "Initialization not complete, timed out\n");
  2570. return -ETIMEDOUT;
  2571. }
  2572. } else {
  2573. #ifdef CONFIG_COMMON_CLK
  2574. /* Check if MCLK provided */
  2575. rt5682->mclk = devm_clk_get(component->dev, "mclk");
  2576. if (IS_ERR(rt5682->mclk)) {
  2577. if (PTR_ERR(rt5682->mclk) != -ENOENT) {
  2578. ret = PTR_ERR(rt5682->mclk);
  2579. return ret;
  2580. }
  2581. rt5682->mclk = NULL;
  2582. }
  2583. /* Register CCF DAI clock control */
  2584. ret = rt5682_register_dai_clks(component);
  2585. if (ret)
  2586. return ret;
  2587. /* Initial setup for CCF */
  2588. rt5682->lrck[RT5682_AIF1] = CLK_48;
  2589. #endif
  2590. }
  2591. snd_soc_dapm_disable_pin(dapm, "MICBIAS");
  2592. snd_soc_dapm_disable_pin(dapm, "Vref2");
  2593. snd_soc_dapm_sync(dapm);
  2594. return 0;
  2595. }
  2596. static void rt5682_remove(struct snd_soc_component *component)
  2597. {
  2598. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2599. rt5682_reset(rt5682);
  2600. }
  2601. #ifdef CONFIG_PM
  2602. static int rt5682_suspend(struct snd_soc_component *component)
  2603. {
  2604. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2605. regcache_cache_only(rt5682->regmap, true);
  2606. regcache_mark_dirty(rt5682->regmap);
  2607. return 0;
  2608. }
  2609. static int rt5682_resume(struct snd_soc_component *component)
  2610. {
  2611. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2612. regcache_cache_only(rt5682->regmap, false);
  2613. regcache_sync(rt5682->regmap);
  2614. mod_delayed_work(system_power_efficient_wq,
  2615. &rt5682->jack_detect_work, msecs_to_jiffies(250));
  2616. return 0;
  2617. }
  2618. #else
  2619. #define rt5682_suspend NULL
  2620. #define rt5682_resume NULL
  2621. #endif
  2622. const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
  2623. .hw_params = rt5682_hw_params,
  2624. .set_fmt = rt5682_set_dai_fmt,
  2625. .set_tdm_slot = rt5682_set_tdm_slot,
  2626. .set_bclk_ratio = rt5682_set_bclk1_ratio,
  2627. };
  2628. EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
  2629. const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
  2630. .hw_params = rt5682_hw_params,
  2631. .set_fmt = rt5682_set_dai_fmt,
  2632. .set_bclk_ratio = rt5682_set_bclk2_ratio,
  2633. };
  2634. EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
  2635. const struct snd_soc_component_driver rt5682_soc_component_dev = {
  2636. .probe = rt5682_probe,
  2637. .remove = rt5682_remove,
  2638. .suspend = rt5682_suspend,
  2639. .resume = rt5682_resume,
  2640. .set_bias_level = rt5682_set_bias_level,
  2641. .controls = rt5682_snd_controls,
  2642. .num_controls = ARRAY_SIZE(rt5682_snd_controls),
  2643. .dapm_widgets = rt5682_dapm_widgets,
  2644. .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
  2645. .dapm_routes = rt5682_dapm_routes,
  2646. .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
  2647. .set_sysclk = rt5682_set_component_sysclk,
  2648. .set_pll = rt5682_set_component_pll,
  2649. .set_jack = rt5682_set_jack_detect,
  2650. .use_pmdown_time = 1,
  2651. .endianness = 1,
  2652. .non_legacy_dai_naming = 1,
  2653. };
  2654. EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
  2655. int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
  2656. {
  2657. device_property_read_u32(dev, "realtek,dmic1-data-pin",
  2658. &rt5682->pdata.dmic1_data_pin);
  2659. device_property_read_u32(dev, "realtek,dmic1-clk-pin",
  2660. &rt5682->pdata.dmic1_clk_pin);
  2661. device_property_read_u32(dev, "realtek,jd-src",
  2662. &rt5682->pdata.jd_src);
  2663. device_property_read_u32(dev, "realtek,btndet-delay",
  2664. &rt5682->pdata.btndet_delay);
  2665. device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
  2666. &rt5682->pdata.dmic_clk_rate);
  2667. device_property_read_u32(dev, "realtek,dmic-delay-ms",
  2668. &rt5682->pdata.dmic_delay);
  2669. rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
  2670. "realtek,ldo1-en-gpios", 0);
  2671. if (device_property_read_string_array(dev, "clock-output-names",
  2672. rt5682->pdata.dai_clk_names,
  2673. RT5682_DAI_NUM_CLKS) < 0)
  2674. dev_warn(dev, "Using default DAI clk names: %s, %s\n",
  2675. rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
  2676. rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
  2677. return 0;
  2678. }
  2679. EXPORT_SYMBOL_GPL(rt5682_parse_dt);
  2680. void rt5682_calibrate(struct rt5682_priv *rt5682)
  2681. {
  2682. int value, count;
  2683. mutex_lock(&rt5682->calibrate_mutex);
  2684. rt5682_reset(rt5682);
  2685. regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
  2686. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
  2687. usleep_range(15000, 20000);
  2688. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
  2689. regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
  2690. regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
  2691. regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
  2692. regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
  2693. regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
  2694. regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
  2695. regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
  2696. regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
  2697. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
  2698. regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
  2699. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
  2700. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
  2701. regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
  2702. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
  2703. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
  2704. for (count = 0; count < 60; count++) {
  2705. regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
  2706. if (!(value & 0x8000))
  2707. break;
  2708. usleep_range(10000, 10005);
  2709. }
  2710. if (count >= 60)
  2711. dev_err(rt5682->component->dev, "HP Calibration Failure\n");
  2712. /* restore settings */
  2713. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
  2714. regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
  2715. regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
  2716. regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
  2717. regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
  2718. regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
  2719. regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
  2720. regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
  2721. mutex_unlock(&rt5682->calibrate_mutex);
  2722. }
  2723. EXPORT_SYMBOL_GPL(rt5682_calibrate);
  2724. MODULE_DESCRIPTION("ASoC RT5682 driver");
  2725. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  2726. MODULE_LICENSE("GPL v2");