rt5682-sdw.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // rt5682-sdw.c -- RT5682 ALSA SoC audio component driver
  4. //
  5. // Copyright 2019 Realtek Semiconductor Corp.
  6. // Author: Oder Chiou <oder_chiou@realtek.com>
  7. //
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/acpi.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/mutex.h>
  19. #include <linux/soundwire/sdw.h>
  20. #include <linux/soundwire/sdw_type.h>
  21. #include <linux/soundwire/sdw_registers.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/jack.h>
  26. #include <sound/soc.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #include "rt5682.h"
  31. #define RT5682_SDW_ADDR_L 0x3000
  32. #define RT5682_SDW_ADDR_H 0x3001
  33. #define RT5682_SDW_DATA_L 0x3004
  34. #define RT5682_SDW_DATA_H 0x3005
  35. #define RT5682_SDW_CMD 0x3008
  36. static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
  37. {
  38. struct device *dev = context;
  39. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  40. unsigned int data_l, data_h;
  41. regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
  42. regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
  43. regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
  44. regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
  45. regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
  46. *val = (data_h << 8) | data_l;
  47. dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
  48. return 0;
  49. }
  50. static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
  51. {
  52. struct device *dev = context;
  53. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  54. regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
  55. regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
  56. regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
  57. regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
  58. regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
  59. dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
  60. return 0;
  61. }
  62. static const struct regmap_config rt5682_sdw_indirect_regmap = {
  63. .reg_bits = 16,
  64. .val_bits = 16,
  65. .max_register = RT5682_I2C_MODE,
  66. .volatile_reg = rt5682_volatile_register,
  67. .readable_reg = rt5682_readable_register,
  68. .cache_type = REGCACHE_RBTREE,
  69. .reg_defaults = rt5682_reg,
  70. .num_reg_defaults = RT5682_REG_NUM,
  71. .use_single_read = true,
  72. .use_single_write = true,
  73. .reg_read = rt5682_sdw_read,
  74. .reg_write = rt5682_sdw_write,
  75. };
  76. struct sdw_stream_data {
  77. struct sdw_stream_runtime *sdw_stream;
  78. };
  79. static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
  80. int direction)
  81. {
  82. struct sdw_stream_data *stream;
  83. if (!sdw_stream)
  84. return 0;
  85. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  86. if (!stream)
  87. return -ENOMEM;
  88. stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream;
  89. /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
  90. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  91. dai->playback_dma_data = stream;
  92. else
  93. dai->capture_dma_data = stream;
  94. return 0;
  95. }
  96. static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
  97. struct snd_soc_dai *dai)
  98. {
  99. struct sdw_stream_data *stream;
  100. stream = snd_soc_dai_get_dma_data(dai, substream);
  101. snd_soc_dai_set_dma_data(dai, substream, NULL);
  102. kfree(stream);
  103. }
  104. static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
  105. struct snd_pcm_hw_params *params,
  106. struct snd_soc_dai *dai)
  107. {
  108. struct snd_soc_component *component = dai->component;
  109. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  110. struct sdw_stream_config stream_config;
  111. struct sdw_port_config port_config;
  112. enum sdw_data_direction direction;
  113. struct sdw_stream_data *stream;
  114. int retval, port, num_channels;
  115. unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
  116. dev_dbg(dai->dev, "%s %s", __func__, dai->name);
  117. stream = snd_soc_dai_get_dma_data(dai, substream);
  118. if (!stream)
  119. return -ENOMEM;
  120. if (!rt5682->slave)
  121. return -EINVAL;
  122. /* SoundWire specific configuration */
  123. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  124. direction = SDW_DATA_DIR_RX;
  125. port = 1;
  126. } else {
  127. direction = SDW_DATA_DIR_TX;
  128. port = 2;
  129. }
  130. stream_config.frame_rate = params_rate(params);
  131. stream_config.ch_count = params_channels(params);
  132. stream_config.bps = snd_pcm_format_width(params_format(params));
  133. stream_config.direction = direction;
  134. num_channels = params_channels(params);
  135. port_config.ch_mask = (1 << (num_channels)) - 1;
  136. port_config.num = port;
  137. retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
  138. &port_config, 1, stream->sdw_stream);
  139. if (retval) {
  140. dev_err(dai->dev, "Unable to configure port\n");
  141. return retval;
  142. }
  143. switch (params_rate(params)) {
  144. case 48000:
  145. val_p = RT5682_SDW_REF_1_48K;
  146. val_c = RT5682_SDW_REF_2_48K;
  147. break;
  148. case 96000:
  149. val_p = RT5682_SDW_REF_1_96K;
  150. val_c = RT5682_SDW_REF_2_96K;
  151. break;
  152. case 192000:
  153. val_p = RT5682_SDW_REF_1_192K;
  154. val_c = RT5682_SDW_REF_2_192K;
  155. break;
  156. case 32000:
  157. val_p = RT5682_SDW_REF_1_32K;
  158. val_c = RT5682_SDW_REF_2_32K;
  159. break;
  160. case 24000:
  161. val_p = RT5682_SDW_REF_1_24K;
  162. val_c = RT5682_SDW_REF_2_24K;
  163. break;
  164. case 16000:
  165. val_p = RT5682_SDW_REF_1_16K;
  166. val_c = RT5682_SDW_REF_2_16K;
  167. break;
  168. case 12000:
  169. val_p = RT5682_SDW_REF_1_12K;
  170. val_c = RT5682_SDW_REF_2_12K;
  171. break;
  172. case 8000:
  173. val_p = RT5682_SDW_REF_1_8K;
  174. val_c = RT5682_SDW_REF_2_8K;
  175. break;
  176. case 44100:
  177. val_p = RT5682_SDW_REF_1_44K;
  178. val_c = RT5682_SDW_REF_2_44K;
  179. break;
  180. case 88200:
  181. val_p = RT5682_SDW_REF_1_88K;
  182. val_c = RT5682_SDW_REF_2_88K;
  183. break;
  184. case 176400:
  185. val_p = RT5682_SDW_REF_1_176K;
  186. val_c = RT5682_SDW_REF_2_176K;
  187. break;
  188. case 22050:
  189. val_p = RT5682_SDW_REF_1_22K;
  190. val_c = RT5682_SDW_REF_2_22K;
  191. break;
  192. case 11025:
  193. val_p = RT5682_SDW_REF_1_11K;
  194. val_c = RT5682_SDW_REF_2_11K;
  195. break;
  196. default:
  197. return -EINVAL;
  198. }
  199. if (params_rate(params) <= 48000) {
  200. osr_p = RT5682_DAC_OSR_D_8;
  201. osr_c = RT5682_ADC_OSR_D_8;
  202. } else if (params_rate(params) <= 96000) {
  203. osr_p = RT5682_DAC_OSR_D_4;
  204. osr_c = RT5682_ADC_OSR_D_4;
  205. } else {
  206. osr_p = RT5682_DAC_OSR_D_2;
  207. osr_c = RT5682_ADC_OSR_D_2;
  208. }
  209. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  210. regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
  211. RT5682_SDW_REF_1_MASK, val_p);
  212. regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
  213. RT5682_DAC_OSR_MASK, osr_p);
  214. } else {
  215. regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
  216. RT5682_SDW_REF_2_MASK, val_c);
  217. regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
  218. RT5682_ADC_OSR_MASK, osr_c);
  219. }
  220. return retval;
  221. }
  222. static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
  223. struct snd_soc_dai *dai)
  224. {
  225. struct snd_soc_component *component = dai->component;
  226. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  227. struct sdw_stream_data *stream =
  228. snd_soc_dai_get_dma_data(dai, substream);
  229. if (!rt5682->slave)
  230. return -EINVAL;
  231. sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream);
  232. return 0;
  233. }
  234. static struct snd_soc_dai_ops rt5682_sdw_ops = {
  235. .hw_params = rt5682_sdw_hw_params,
  236. .hw_free = rt5682_sdw_hw_free,
  237. .set_sdw_stream = rt5682_set_sdw_stream,
  238. .shutdown = rt5682_sdw_shutdown,
  239. };
  240. static struct snd_soc_dai_driver rt5682_dai[] = {
  241. {
  242. .name = "rt5682-aif1",
  243. .id = RT5682_AIF1,
  244. .playback = {
  245. .stream_name = "AIF1 Playback",
  246. .channels_min = 1,
  247. .channels_max = 2,
  248. .rates = RT5682_STEREO_RATES,
  249. .formats = RT5682_FORMATS,
  250. },
  251. .capture = {
  252. .stream_name = "AIF1 Capture",
  253. .channels_min = 1,
  254. .channels_max = 2,
  255. .rates = RT5682_STEREO_RATES,
  256. .formats = RT5682_FORMATS,
  257. },
  258. .ops = &rt5682_aif1_dai_ops,
  259. },
  260. {
  261. .name = "rt5682-aif2",
  262. .id = RT5682_AIF2,
  263. .capture = {
  264. .stream_name = "AIF2 Capture",
  265. .channels_min = 1,
  266. .channels_max = 2,
  267. .rates = RT5682_STEREO_RATES,
  268. .formats = RT5682_FORMATS,
  269. },
  270. .ops = &rt5682_aif2_dai_ops,
  271. },
  272. {
  273. .name = "rt5682-sdw",
  274. .id = RT5682_SDW,
  275. .playback = {
  276. .stream_name = "SDW Playback",
  277. .channels_min = 1,
  278. .channels_max = 2,
  279. .rates = RT5682_STEREO_RATES,
  280. .formats = RT5682_FORMATS,
  281. },
  282. .capture = {
  283. .stream_name = "SDW Capture",
  284. .channels_min = 1,
  285. .channels_max = 2,
  286. .rates = RT5682_STEREO_RATES,
  287. .formats = RT5682_FORMATS,
  288. },
  289. .ops = &rt5682_sdw_ops,
  290. },
  291. };
  292. static int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
  293. struct sdw_slave *slave)
  294. {
  295. struct rt5682_priv *rt5682;
  296. int ret;
  297. rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
  298. if (!rt5682)
  299. return -ENOMEM;
  300. dev_set_drvdata(dev, rt5682);
  301. rt5682->slave = slave;
  302. rt5682->sdw_regmap = regmap;
  303. rt5682->is_sdw = true;
  304. rt5682->regmap = devm_regmap_init(dev, NULL, dev,
  305. &rt5682_sdw_indirect_regmap);
  306. if (IS_ERR(rt5682->regmap)) {
  307. ret = PTR_ERR(rt5682->regmap);
  308. dev_err(dev, "Failed to allocate register map: %d\n",
  309. ret);
  310. return ret;
  311. }
  312. /*
  313. * Mark hw_init to false
  314. * HW init will be performed when device reports present
  315. */
  316. rt5682->hw_init = false;
  317. rt5682->first_hw_init = false;
  318. mutex_init(&rt5682->calibrate_mutex);
  319. INIT_DELAYED_WORK(&rt5682->jack_detect_work,
  320. rt5682_jack_detect_handler);
  321. ret = devm_snd_soc_register_component(dev,
  322. &rt5682_soc_component_dev,
  323. rt5682_dai, ARRAY_SIZE(rt5682_dai));
  324. dev_dbg(&slave->dev, "%s\n", __func__);
  325. return ret;
  326. }
  327. static int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
  328. {
  329. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  330. int ret = 0, loop = 10;
  331. unsigned int val;
  332. if (rt5682->hw_init)
  333. return 0;
  334. /*
  335. * PM runtime is only enabled when a Slave reports as Attached
  336. */
  337. if (!rt5682->first_hw_init) {
  338. /* set autosuspend parameters */
  339. pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
  340. pm_runtime_use_autosuspend(&slave->dev);
  341. /* update count of parent 'active' children */
  342. pm_runtime_set_active(&slave->dev);
  343. /* make sure the device does not suspend immediately */
  344. pm_runtime_mark_last_busy(&slave->dev);
  345. pm_runtime_enable(&slave->dev);
  346. }
  347. pm_runtime_get_noresume(&slave->dev);
  348. if (rt5682->first_hw_init) {
  349. regcache_cache_only(rt5682->regmap, false);
  350. regcache_cache_bypass(rt5682->regmap, true);
  351. }
  352. while (loop > 0) {
  353. regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
  354. if (val == DEVICE_ID)
  355. break;
  356. dev_warn(dev, "Device with ID register %x is not rt5682\n", val);
  357. usleep_range(30000, 30005);
  358. loop--;
  359. }
  360. if (val != DEVICE_ID) {
  361. dev_err(dev, "Device with ID register %x is not rt5682\n", val);
  362. return -ENODEV;
  363. }
  364. rt5682_calibrate(rt5682);
  365. if (rt5682->first_hw_init) {
  366. regcache_cache_bypass(rt5682->regmap, false);
  367. regcache_mark_dirty(rt5682->regmap);
  368. regcache_sync(rt5682->regmap);
  369. /* volatile registers */
  370. regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
  371. RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
  372. goto reinit;
  373. }
  374. rt5682_apply_patch_list(rt5682, dev);
  375. regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
  376. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
  377. RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
  378. RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
  379. regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
  380. regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
  381. regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
  382. RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
  383. regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
  384. RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
  385. regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
  386. RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
  387. /* Soundwire */
  388. regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
  389. regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
  390. regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
  391. regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
  392. regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
  393. regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
  394. regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
  395. regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
  396. RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
  397. RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
  398. regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
  399. RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
  400. regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd142);
  401. regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
  402. regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
  403. RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
  404. regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
  405. RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
  406. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  407. RT5682_POW_IRQ | RT5682_POW_JDH |
  408. RT5682_POW_ANA, RT5682_POW_IRQ |
  409. RT5682_POW_JDH | RT5682_POW_ANA);
  410. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
  411. RT5682_PWR_JDH, RT5682_PWR_JDH);
  412. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  413. RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
  414. RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
  415. reinit:
  416. mod_delayed_work(system_power_efficient_wq,
  417. &rt5682->jack_detect_work, msecs_to_jiffies(250));
  418. /* Mark Slave initialization complete */
  419. rt5682->hw_init = true;
  420. rt5682->first_hw_init = true;
  421. pm_runtime_mark_last_busy(&slave->dev);
  422. pm_runtime_put_autosuspend(&slave->dev);
  423. dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
  424. return ret;
  425. }
  426. static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
  427. {
  428. switch (reg) {
  429. case 0x00e0:
  430. case 0x00f0:
  431. case 0x3000:
  432. case 0x3001:
  433. case 0x3004:
  434. case 0x3005:
  435. case 0x3008:
  436. return true;
  437. default:
  438. return false;
  439. }
  440. }
  441. static const struct regmap_config rt5682_sdw_regmap = {
  442. .name = "sdw",
  443. .reg_bits = 32,
  444. .val_bits = 8,
  445. .max_register = RT5682_I2C_MODE,
  446. .readable_reg = rt5682_sdw_readable_register,
  447. .cache_type = REGCACHE_NONE,
  448. .use_single_read = true,
  449. .use_single_write = true,
  450. };
  451. static int rt5682_update_status(struct sdw_slave *slave,
  452. enum sdw_slave_status status)
  453. {
  454. struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
  455. /* Update the status */
  456. rt5682->status = status;
  457. if (status == SDW_SLAVE_UNATTACHED)
  458. rt5682->hw_init = false;
  459. /*
  460. * Perform initialization only if slave status is present and
  461. * hw_init flag is false
  462. */
  463. if (rt5682->hw_init || rt5682->status != SDW_SLAVE_ATTACHED)
  464. return 0;
  465. /* perform I/O transfers required for Slave initialization */
  466. return rt5682_io_init(&slave->dev, slave);
  467. }
  468. static int rt5682_read_prop(struct sdw_slave *slave)
  469. {
  470. struct sdw_slave_prop *prop = &slave->prop;
  471. int nval, i;
  472. u32 bit;
  473. unsigned long addr;
  474. struct sdw_dpn_prop *dpn;
  475. prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
  476. SDW_SCP_INT1_PARITY;
  477. prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
  478. prop->paging_support = false;
  479. /* first we need to allocate memory for set bits in port lists */
  480. prop->source_ports = 0x4; /* BITMAP: 00000100 */
  481. prop->sink_ports = 0x2; /* BITMAP: 00000010 */
  482. nval = hweight32(prop->source_ports);
  483. prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
  484. sizeof(*prop->src_dpn_prop),
  485. GFP_KERNEL);
  486. if (!prop->src_dpn_prop)
  487. return -ENOMEM;
  488. i = 0;
  489. dpn = prop->src_dpn_prop;
  490. addr = prop->source_ports;
  491. for_each_set_bit(bit, &addr, 32) {
  492. dpn[i].num = bit;
  493. dpn[i].type = SDW_DPN_FULL;
  494. dpn[i].simple_ch_prep_sm = true;
  495. dpn[i].ch_prep_timeout = 10;
  496. i++;
  497. }
  498. /* do this again for sink now */
  499. nval = hweight32(prop->sink_ports);
  500. prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
  501. sizeof(*prop->sink_dpn_prop),
  502. GFP_KERNEL);
  503. if (!prop->sink_dpn_prop)
  504. return -ENOMEM;
  505. i = 0;
  506. dpn = prop->sink_dpn_prop;
  507. addr = prop->sink_ports;
  508. for_each_set_bit(bit, &addr, 32) {
  509. dpn[i].num = bit;
  510. dpn[i].type = SDW_DPN_FULL;
  511. dpn[i].simple_ch_prep_sm = true;
  512. dpn[i].ch_prep_timeout = 10;
  513. i++;
  514. }
  515. /* set the timeout values */
  516. prop->clk_stop_timeout = 20;
  517. /* wake-up event */
  518. prop->wake_capable = 1;
  519. return 0;
  520. }
  521. /* Bus clock frequency */
  522. #define RT5682_CLK_FREQ_9600000HZ 9600000
  523. #define RT5682_CLK_FREQ_12000000HZ 12000000
  524. #define RT5682_CLK_FREQ_6000000HZ 6000000
  525. #define RT5682_CLK_FREQ_4800000HZ 4800000
  526. #define RT5682_CLK_FREQ_2400000HZ 2400000
  527. #define RT5682_CLK_FREQ_12288000HZ 12288000
  528. static int rt5682_clock_config(struct device *dev)
  529. {
  530. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  531. unsigned int clk_freq, value;
  532. clk_freq = (rt5682->params.curr_dr_freq >> 1);
  533. switch (clk_freq) {
  534. case RT5682_CLK_FREQ_12000000HZ:
  535. value = 0x0;
  536. break;
  537. case RT5682_CLK_FREQ_6000000HZ:
  538. value = 0x1;
  539. break;
  540. case RT5682_CLK_FREQ_9600000HZ:
  541. value = 0x2;
  542. break;
  543. case RT5682_CLK_FREQ_4800000HZ:
  544. value = 0x3;
  545. break;
  546. case RT5682_CLK_FREQ_2400000HZ:
  547. value = 0x4;
  548. break;
  549. case RT5682_CLK_FREQ_12288000HZ:
  550. value = 0x5;
  551. break;
  552. default:
  553. return -EINVAL;
  554. }
  555. regmap_write(rt5682->sdw_regmap, 0xe0, value);
  556. regmap_write(rt5682->sdw_regmap, 0xf0, value);
  557. dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
  558. return 0;
  559. }
  560. static int rt5682_bus_config(struct sdw_slave *slave,
  561. struct sdw_bus_params *params)
  562. {
  563. struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
  564. int ret;
  565. memcpy(&rt5682->params, params, sizeof(*params));
  566. ret = rt5682_clock_config(&slave->dev);
  567. if (ret < 0)
  568. dev_err(&slave->dev, "Invalid clk config");
  569. return ret;
  570. }
  571. static int rt5682_interrupt_callback(struct sdw_slave *slave,
  572. struct sdw_slave_intr_status *status)
  573. {
  574. struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
  575. dev_dbg(&slave->dev,
  576. "%s control_port_stat=%x", __func__, status->control_port);
  577. if (status->control_port & 0x4) {
  578. mod_delayed_work(system_power_efficient_wq,
  579. &rt5682->jack_detect_work, msecs_to_jiffies(250));
  580. }
  581. return 0;
  582. }
  583. static struct sdw_slave_ops rt5682_slave_ops = {
  584. .read_prop = rt5682_read_prop,
  585. .interrupt_callback = rt5682_interrupt_callback,
  586. .update_status = rt5682_update_status,
  587. .bus_config = rt5682_bus_config,
  588. };
  589. static int rt5682_sdw_probe(struct sdw_slave *slave,
  590. const struct sdw_device_id *id)
  591. {
  592. struct regmap *regmap;
  593. /* Regmap Initialization */
  594. regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
  595. if (IS_ERR(regmap))
  596. return -EINVAL;
  597. rt5682_sdw_init(&slave->dev, regmap, slave);
  598. return 0;
  599. }
  600. static int rt5682_sdw_remove(struct sdw_slave *slave)
  601. {
  602. struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
  603. if (rt5682 && rt5682->hw_init)
  604. cancel_delayed_work(&rt5682->jack_detect_work);
  605. return 0;
  606. }
  607. static const struct sdw_device_id rt5682_id[] = {
  608. SDW_SLAVE_ENTRY_EXT(0x025d, 0x5682, 0x2, 0, 0),
  609. {},
  610. };
  611. MODULE_DEVICE_TABLE(sdw, rt5682_id);
  612. static int __maybe_unused rt5682_dev_suspend(struct device *dev)
  613. {
  614. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  615. if (!rt5682->hw_init)
  616. return 0;
  617. regcache_cache_only(rt5682->regmap, true);
  618. regcache_mark_dirty(rt5682->regmap);
  619. return 0;
  620. }
  621. static int __maybe_unused rt5682_dev_resume(struct device *dev)
  622. {
  623. struct sdw_slave *slave = dev_to_sdw_dev(dev);
  624. struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
  625. unsigned long time;
  626. if (!rt5682->first_hw_init)
  627. return 0;
  628. if (!slave->unattach_request)
  629. goto regmap_sync;
  630. time = wait_for_completion_timeout(&slave->initialization_complete,
  631. msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
  632. if (!time) {
  633. dev_err(&slave->dev, "Initialization not complete, timed out\n");
  634. return -ETIMEDOUT;
  635. }
  636. regmap_sync:
  637. slave->unattach_request = 0;
  638. regcache_cache_only(rt5682->regmap, false);
  639. regcache_sync(rt5682->regmap);
  640. return 0;
  641. }
  642. static const struct dev_pm_ops rt5682_pm = {
  643. SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume)
  644. SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
  645. };
  646. static struct sdw_driver rt5682_sdw_driver = {
  647. .driver = {
  648. .name = "rt5682",
  649. .owner = THIS_MODULE,
  650. .pm = &rt5682_pm,
  651. },
  652. .probe = rt5682_sdw_probe,
  653. .remove = rt5682_sdw_remove,
  654. .ops = &rt5682_slave_ops,
  655. .id_table = rt5682_id,
  656. };
  657. module_sdw_driver(rt5682_sdw_driver);
  658. MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
  659. MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
  660. MODULE_LICENSE("GPL v2");