rt5677.h 65 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5677.h -- RT5677 ALSA SoC audio driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Oder Chiou <oder_chiou@realtek.com>
  7. */
  8. #ifndef __RT5677_H__
  9. #define __RT5677_H__
  10. #include <linux/gpio/driver.h>
  11. #include <linux/gpio/consumer.h>
  12. /* Info */
  13. #define RT5677_RESET 0x00
  14. #define RT5677_VENDOR_ID 0xfd
  15. #define RT5677_VENDOR_ID1 0xfe
  16. #define RT5677_VENDOR_ID2 0xff
  17. /* I/O - Output */
  18. #define RT5677_LOUT1 0x01
  19. /* I/O - Input */
  20. #define RT5677_IN1 0x03
  21. #define RT5677_MICBIAS 0x04
  22. /* I/O - SLIMBus */
  23. #define RT5677_SLIMBUS_PARAM 0x07
  24. #define RT5677_SLIMBUS_RX 0x08
  25. #define RT5677_SLIMBUS_CTRL 0x09
  26. /* I/O */
  27. #define RT5677_SIDETONE_CTRL 0x13
  28. /* I/O - ADC/DAC */
  29. #define RT5677_ANA_DAC1_2_3_SRC 0x15
  30. #define RT5677_IF_DSP_DAC3_4_MIXER 0x16
  31. #define RT5677_DAC4_DIG_VOL 0x17
  32. #define RT5677_DAC3_DIG_VOL 0x18
  33. #define RT5677_DAC1_DIG_VOL 0x19
  34. #define RT5677_DAC2_DIG_VOL 0x1a
  35. #define RT5677_IF_DSP_DAC2_MIXER 0x1b
  36. #define RT5677_STO1_ADC_DIG_VOL 0x1c
  37. #define RT5677_MONO_ADC_DIG_VOL 0x1d
  38. #define RT5677_STO1_2_ADC_BST 0x1e
  39. #define RT5677_STO2_ADC_DIG_VOL 0x1f
  40. /* Mixer - D-D */
  41. #define RT5677_ADC_BST_CTRL2 0x20
  42. #define RT5677_STO3_4_ADC_BST 0x21
  43. #define RT5677_STO3_ADC_DIG_VOL 0x22
  44. #define RT5677_STO4_ADC_DIG_VOL 0x23
  45. #define RT5677_STO4_ADC_MIXER 0x24
  46. #define RT5677_STO3_ADC_MIXER 0x25
  47. #define RT5677_STO2_ADC_MIXER 0x26
  48. #define RT5677_STO1_ADC_MIXER 0x27
  49. #define RT5677_MONO_ADC_MIXER 0x28
  50. #define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
  51. #define RT5677_STO1_DAC_MIXER 0x2a
  52. #define RT5677_MONO_DAC_MIXER 0x2b
  53. #define RT5677_DD1_MIXER 0x2c
  54. #define RT5677_DD2_MIXER 0x2d
  55. #define RT5677_IF3_DATA 0x2f
  56. #define RT5677_IF4_DATA 0x30
  57. /* Mixer - PDM */
  58. #define RT5677_PDM_OUT_CTRL 0x31
  59. #define RT5677_PDM_DATA_CTRL1 0x32
  60. #define RT5677_PDM_DATA_CTRL2 0x33
  61. #define RT5677_PDM1_DATA_CTRL2 0x34
  62. #define RT5677_PDM1_DATA_CTRL3 0x35
  63. #define RT5677_PDM1_DATA_CTRL4 0x36
  64. #define RT5677_PDM2_DATA_CTRL2 0x37
  65. #define RT5677_PDM2_DATA_CTRL3 0x38
  66. #define RT5677_PDM2_DATA_CTRL4 0x39
  67. /* TDM */
  68. #define RT5677_TDM1_CTRL1 0x3b
  69. #define RT5677_TDM1_CTRL2 0x3c
  70. #define RT5677_TDM1_CTRL3 0x3d
  71. #define RT5677_TDM1_CTRL4 0x3e
  72. #define RT5677_TDM1_CTRL5 0x3f
  73. #define RT5677_TDM2_CTRL1 0x40
  74. #define RT5677_TDM2_CTRL2 0x41
  75. #define RT5677_TDM2_CTRL3 0x42
  76. #define RT5677_TDM2_CTRL4 0x43
  77. #define RT5677_TDM2_CTRL5 0x44
  78. /* I2C_MASTER_CTRL */
  79. #define RT5677_I2C_MASTER_CTRL1 0x47
  80. #define RT5677_I2C_MASTER_CTRL2 0x48
  81. #define RT5677_I2C_MASTER_CTRL3 0x49
  82. #define RT5677_I2C_MASTER_CTRL4 0x4a
  83. #define RT5677_I2C_MASTER_CTRL5 0x4b
  84. #define RT5677_I2C_MASTER_CTRL6 0x4c
  85. #define RT5677_I2C_MASTER_CTRL7 0x4d
  86. #define RT5677_I2C_MASTER_CTRL8 0x4e
  87. /* DMIC */
  88. #define RT5677_DMIC_CTRL1 0x50
  89. #define RT5677_DMIC_CTRL2 0x51
  90. /* Haptic Generator */
  91. #define RT5677_HAP_GENE_CTRL1 0x56
  92. #define RT5677_HAP_GENE_CTRL2 0x57
  93. #define RT5677_HAP_GENE_CTRL3 0x58
  94. #define RT5677_HAP_GENE_CTRL4 0x59
  95. #define RT5677_HAP_GENE_CTRL5 0x5a
  96. #define RT5677_HAP_GENE_CTRL6 0x5b
  97. #define RT5677_HAP_GENE_CTRL7 0x5c
  98. #define RT5677_HAP_GENE_CTRL8 0x5d
  99. #define RT5677_HAP_GENE_CTRL9 0x5e
  100. #define RT5677_HAP_GENE_CTRL10 0x5f
  101. /* Power */
  102. #define RT5677_PWR_DIG1 0x61
  103. #define RT5677_PWR_DIG2 0x62
  104. #define RT5677_PWR_ANLG1 0x63
  105. #define RT5677_PWR_ANLG2 0x64
  106. #define RT5677_PWR_DSP1 0x65
  107. #define RT5677_PWR_DSP_ST 0x66
  108. #define RT5677_PWR_DSP2 0x67
  109. #define RT5677_ADC_DAC_HPF_CTRL1 0x68
  110. /* Private Register Control */
  111. #define RT5677_PRIV_INDEX 0x6a
  112. #define RT5677_PRIV_DATA 0x6c
  113. /* Format - ADC/DAC */
  114. #define RT5677_I2S4_SDP 0x6f
  115. #define RT5677_I2S1_SDP 0x70
  116. #define RT5677_I2S2_SDP 0x71
  117. #define RT5677_I2S3_SDP 0x72
  118. #define RT5677_CLK_TREE_CTRL1 0x73
  119. #define RT5677_CLK_TREE_CTRL2 0x74
  120. #define RT5677_CLK_TREE_CTRL3 0x75
  121. /* Function - Analog */
  122. #define RT5677_PLL1_CTRL1 0x7a
  123. #define RT5677_PLL1_CTRL2 0x7b
  124. #define RT5677_PLL2_CTRL1 0x7c
  125. #define RT5677_PLL2_CTRL2 0x7d
  126. #define RT5677_GLB_CLK1 0x80
  127. #define RT5677_GLB_CLK2 0x81
  128. #define RT5677_ASRC_1 0x83
  129. #define RT5677_ASRC_2 0x84
  130. #define RT5677_ASRC_3 0x85
  131. #define RT5677_ASRC_4 0x86
  132. #define RT5677_ASRC_5 0x87
  133. #define RT5677_ASRC_6 0x88
  134. #define RT5677_ASRC_7 0x89
  135. #define RT5677_ASRC_8 0x8a
  136. #define RT5677_ASRC_9 0x8b
  137. #define RT5677_ASRC_10 0x8c
  138. #define RT5677_ASRC_11 0x8d
  139. #define RT5677_ASRC_12 0x8e
  140. #define RT5677_ASRC_13 0x8f
  141. #define RT5677_ASRC_14 0x90
  142. #define RT5677_ASRC_15 0x91
  143. #define RT5677_ASRC_16 0x92
  144. #define RT5677_ASRC_17 0x93
  145. #define RT5677_ASRC_18 0x94
  146. #define RT5677_ASRC_19 0x95
  147. #define RT5677_ASRC_20 0x97
  148. #define RT5677_ASRC_21 0x98
  149. #define RT5677_ASRC_22 0x99
  150. #define RT5677_ASRC_23 0x9a
  151. #define RT5677_VAD_CTRL1 0x9c
  152. #define RT5677_VAD_CTRL2 0x9d
  153. #define RT5677_VAD_CTRL3 0x9e
  154. #define RT5677_VAD_CTRL4 0x9f
  155. #define RT5677_VAD_CTRL5 0xa0
  156. /* Function - Digital */
  157. #define RT5677_DSP_INB_CTRL1 0xa3
  158. #define RT5677_DSP_INB_CTRL2 0xa4
  159. #define RT5677_DSP_IN_OUTB_CTRL 0xa5
  160. #define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
  161. #define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
  162. #define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
  163. #define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
  164. #define RT5677_ADC_EQ_CTRL1 0xae
  165. #define RT5677_ADC_EQ_CTRL2 0xaf
  166. #define RT5677_EQ_CTRL1 0xb0
  167. #define RT5677_EQ_CTRL2 0xb1
  168. #define RT5677_EQ_CTRL3 0xb2
  169. #define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
  170. #define RT5677_JD_CTRL1 0xb5
  171. #define RT5677_JD_CTRL2 0xb6
  172. #define RT5677_JD_CTRL3 0xb8
  173. #define RT5677_IRQ_CTRL1 0xbd
  174. #define RT5677_IRQ_CTRL2 0xbe
  175. #define RT5677_GPIO_ST 0xbf
  176. #define RT5677_GPIO_CTRL1 0xc0
  177. #define RT5677_GPIO_CTRL2 0xc1
  178. #define RT5677_GPIO_CTRL3 0xc2
  179. #define RT5677_STO1_ADC_HI_FILTER1 0xc5
  180. #define RT5677_STO1_ADC_HI_FILTER2 0xc6
  181. #define RT5677_MONO_ADC_HI_FILTER1 0xc7
  182. #define RT5677_MONO_ADC_HI_FILTER2 0xc8
  183. #define RT5677_STO2_ADC_HI_FILTER1 0xc9
  184. #define RT5677_STO2_ADC_HI_FILTER2 0xca
  185. #define RT5677_STO3_ADC_HI_FILTER1 0xcb
  186. #define RT5677_STO3_ADC_HI_FILTER2 0xcc
  187. #define RT5677_STO4_ADC_HI_FILTER1 0xcd
  188. #define RT5677_STO4_ADC_HI_FILTER2 0xce
  189. #define RT5677_MB_DRC_CTRL1 0xd0
  190. #define RT5677_DRC1_CTRL1 0xd2
  191. #define RT5677_DRC1_CTRL2 0xd3
  192. #define RT5677_DRC1_CTRL3 0xd4
  193. #define RT5677_DRC1_CTRL4 0xd5
  194. #define RT5677_DRC1_CTRL5 0xd6
  195. #define RT5677_DRC1_CTRL6 0xd7
  196. #define RT5677_DRC2_CTRL1 0xd8
  197. #define RT5677_DRC2_CTRL2 0xd9
  198. #define RT5677_DRC2_CTRL3 0xda
  199. #define RT5677_DRC2_CTRL4 0xdb
  200. #define RT5677_DRC2_CTRL5 0xdc
  201. #define RT5677_DRC2_CTRL6 0xdd
  202. #define RT5677_DRC1_HL_CTRL1 0xde
  203. #define RT5677_DRC1_HL_CTRL2 0xdf
  204. #define RT5677_DRC2_HL_CTRL1 0xe0
  205. #define RT5677_DRC2_HL_CTRL2 0xe1
  206. #define RT5677_DSP_INB1_SRC_CTRL1 0xe3
  207. #define RT5677_DSP_INB1_SRC_CTRL2 0xe4
  208. #define RT5677_DSP_INB1_SRC_CTRL3 0xe5
  209. #define RT5677_DSP_INB1_SRC_CTRL4 0xe6
  210. #define RT5677_DSP_INB2_SRC_CTRL1 0xe7
  211. #define RT5677_DSP_INB2_SRC_CTRL2 0xe8
  212. #define RT5677_DSP_INB2_SRC_CTRL3 0xe9
  213. #define RT5677_DSP_INB2_SRC_CTRL4 0xea
  214. #define RT5677_DSP_INB3_SRC_CTRL1 0xeb
  215. #define RT5677_DSP_INB3_SRC_CTRL2 0xec
  216. #define RT5677_DSP_INB3_SRC_CTRL3 0xed
  217. #define RT5677_DSP_INB3_SRC_CTRL4 0xee
  218. #define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
  219. #define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
  220. #define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
  221. #define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
  222. #define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
  223. #define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
  224. #define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
  225. #define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
  226. /* Virtual DSP Mixer Control */
  227. #define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
  228. #define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
  229. #define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
  230. /* General Control */
  231. #define RT5677_DIG_MISC 0xfa
  232. #define RT5677_GEN_CTRL1 0xfb
  233. #define RT5677_GEN_CTRL2 0xfc
  234. /* DSP Mode I2C Control*/
  235. #define RT5677_DSP_I2C_OP_CODE 0x00
  236. #define RT5677_DSP_I2C_ADDR_LSB 0x01
  237. #define RT5677_DSP_I2C_ADDR_MSB 0x02
  238. #define RT5677_DSP_I2C_DATA_LSB 0x03
  239. #define RT5677_DSP_I2C_DATA_MSB 0x04
  240. /* Index of Codec Private Register definition */
  241. #define RT5677_PR_DRC1_CTRL_1 0x01
  242. #define RT5677_PR_DRC1_CTRL_2 0x02
  243. #define RT5677_PR_DRC1_CTRL_3 0x03
  244. #define RT5677_PR_DRC1_CTRL_4 0x04
  245. #define RT5677_PR_DRC1_CTRL_5 0x05
  246. #define RT5677_PR_DRC1_CTRL_6 0x06
  247. #define RT5677_PR_DRC1_CTRL_7 0x07
  248. #define RT5677_PR_DRC2_CTRL_1 0x08
  249. #define RT5677_PR_DRC2_CTRL_2 0x09
  250. #define RT5677_PR_DRC2_CTRL_3 0x0a
  251. #define RT5677_PR_DRC2_CTRL_4 0x0b
  252. #define RT5677_PR_DRC2_CTRL_5 0x0c
  253. #define RT5677_PR_DRC2_CTRL_6 0x0d
  254. #define RT5677_PR_DRC2_CTRL_7 0x0e
  255. #define RT5677_BIAS_CUR1 0x10
  256. #define RT5677_BIAS_CUR2 0x12
  257. #define RT5677_BIAS_CUR3 0x13
  258. #define RT5677_BIAS_CUR4 0x14
  259. #define RT5677_BIAS_CUR5 0x15
  260. #define RT5677_VREF_LOUT_CTRL 0x17
  261. #define RT5677_DIG_VOL_CTRL1 0x1a
  262. #define RT5677_DIG_VOL_CTRL2 0x1b
  263. #define RT5677_ANA_ADC_GAIN_CTRL 0x1e
  264. #define RT5677_VAD_SRAM_TEST1 0x20
  265. #define RT5677_VAD_SRAM_TEST2 0x21
  266. #define RT5677_VAD_SRAM_TEST3 0x22
  267. #define RT5677_VAD_SRAM_TEST4 0x23
  268. #define RT5677_PAD_DRV_CTRL 0x26
  269. #define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
  270. #define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
  271. #define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
  272. #define RT5677_PLL1_INT 0x38
  273. #define RT5677_PLL2_INT 0x39
  274. #define RT5677_TEST_CTRL1 0x3a
  275. #define RT5677_TEST_CTRL2 0x3b
  276. #define RT5677_TEST_CTRL3 0x3c
  277. #define RT5677_CHOP_DAC_ADC 0x3d
  278. #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
  279. #define RT5677_CROSS_OVER_FILTER1 0x90
  280. #define RT5677_CROSS_OVER_FILTER2 0x91
  281. #define RT5677_CROSS_OVER_FILTER3 0x92
  282. #define RT5677_CROSS_OVER_FILTER4 0x93
  283. #define RT5677_CROSS_OVER_FILTER5 0x94
  284. #define RT5677_CROSS_OVER_FILTER6 0x95
  285. #define RT5677_CROSS_OVER_FILTER7 0x96
  286. #define RT5677_CROSS_OVER_FILTER8 0x97
  287. #define RT5677_CROSS_OVER_FILTER9 0x98
  288. #define RT5677_CROSS_OVER_FILTER10 0x99
  289. /* global definition */
  290. #define RT5677_L_MUTE (0x1 << 15)
  291. #define RT5677_L_MUTE_SFT 15
  292. #define RT5677_VOL_L_MUTE (0x1 << 14)
  293. #define RT5677_VOL_L_SFT 14
  294. #define RT5677_R_MUTE (0x1 << 7)
  295. #define RT5677_R_MUTE_SFT 7
  296. #define RT5677_VOL_R_MUTE (0x1 << 6)
  297. #define RT5677_VOL_R_SFT 6
  298. #define RT5677_L_VOL_MASK (0x7f << 9)
  299. #define RT5677_L_VOL_SFT 9
  300. #define RT5677_R_VOL_MASK (0x7f << 1)
  301. #define RT5677_R_VOL_SFT 1
  302. /* LOUT1 Control (0x01) */
  303. #define RT5677_LOUT1_L_MUTE (0x1 << 15)
  304. #define RT5677_LOUT1_L_MUTE_SFT (15)
  305. #define RT5677_LOUT1_L_DF (0x1 << 14)
  306. #define RT5677_LOUT1_L_DF_SFT (14)
  307. #define RT5677_LOUT2_L_MUTE (0x1 << 13)
  308. #define RT5677_LOUT2_L_MUTE_SFT (13)
  309. #define RT5677_LOUT2_L_DF (0x1 << 12)
  310. #define RT5677_LOUT2_L_DF_SFT (12)
  311. #define RT5677_LOUT3_L_MUTE (0x1 << 11)
  312. #define RT5677_LOUT3_L_MUTE_SFT (11)
  313. #define RT5677_LOUT3_L_DF (0x1 << 10)
  314. #define RT5677_LOUT3_L_DF_SFT (10)
  315. #define RT5677_LOUT1_ENH_DRV (0x1 << 9)
  316. #define RT5677_LOUT1_ENH_DRV_SFT (9)
  317. #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
  318. #define RT5677_LOUT2_ENH_DRV_SFT (8)
  319. #define RT5677_LOUT3_ENH_DRV (0x1 << 7)
  320. #define RT5677_LOUT3_ENH_DRV_SFT (7)
  321. /* IN1 Control (0x03) */
  322. #define RT5677_BST_MASK1 (0xf << 12)
  323. #define RT5677_BST_SFT1 12
  324. #define RT5677_BST_MASK2 (0xf << 8)
  325. #define RT5677_BST_SFT2 8
  326. #define RT5677_IN_DF1 (0x1 << 7)
  327. #define RT5677_IN_DF1_SFT 7
  328. #define RT5677_IN_DF2 (0x1 << 6)
  329. #define RT5677_IN_DF2_SFT 6
  330. /* Micbias Control (0x04) */
  331. #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
  332. #define RT5677_MICBIAS1_OUTVOLT_SFT (15)
  333. #define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
  334. #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
  335. #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
  336. #define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
  337. #define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
  338. #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
  339. #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
  340. #define RT5677_MICBIAS1_OVCD_SHIFT (11)
  341. #define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
  342. #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
  343. #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
  344. #define RT5677_MICBIAS1_OVTH_SFT 9
  345. #define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
  346. #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
  347. #define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
  348. /* SLIMbus Parameter (0x07) */
  349. /* SLIMbus Rx (0x08) */
  350. #define RT5677_SLB_ADC4_MASK (0x3 << 6)
  351. #define RT5677_SLB_ADC4_SFT 6
  352. #define RT5677_SLB_ADC3_MASK (0x3 << 4)
  353. #define RT5677_SLB_ADC3_SFT 4
  354. #define RT5677_SLB_ADC2_MASK (0x3 << 2)
  355. #define RT5677_SLB_ADC2_SFT 2
  356. #define RT5677_SLB_ADC1_MASK (0x3 << 0)
  357. #define RT5677_SLB_ADC1_SFT 0
  358. /* SLIMBus control (0x09) */
  359. /* Sidetone Control (0x13) */
  360. #define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
  361. #define RT5677_ST_HPF_SEL_SFT 13
  362. #define RT5677_ST_HPF_PATH (0x1 << 12)
  363. #define RT5677_ST_HPF_PATH_SFT 12
  364. #define RT5677_ST_SEL_MASK (0x7 << 9)
  365. #define RT5677_ST_SEL_SFT 9
  366. #define RT5677_ST_EN (0x1 << 6)
  367. #define RT5677_ST_EN_SFT 6
  368. #define RT5677_ST_GAIN (0x1 << 5)
  369. #define RT5677_ST_GAIN_SFT 5
  370. #define RT5677_ST_VOL_MASK (0x1f << 0)
  371. #define RT5677_ST_VOL_SFT 0
  372. /* Analog DAC1/2/3 Source Control (0x15) */
  373. #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
  374. #define RT5677_ANA_DAC3_SRC_SEL_SFT 4
  375. #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
  376. #define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
  377. /* IF/DSP to DAC3/4 Mixer Control (0x16) */
  378. #define RT5677_M_DAC4_L_VOL (0x1 << 15)
  379. #define RT5677_M_DAC4_L_VOL_SFT 15
  380. #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
  381. #define RT5677_SEL_DAC4_L_SRC_SFT 12
  382. #define RT5677_M_DAC4_R_VOL (0x1 << 11)
  383. #define RT5677_M_DAC4_R_VOL_SFT 11
  384. #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
  385. #define RT5677_SEL_DAC4_R_SRC_SFT 8
  386. #define RT5677_M_DAC3_L_VOL (0x1 << 7)
  387. #define RT5677_M_DAC3_L_VOL_SFT 7
  388. #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
  389. #define RT5677_SEL_DAC3_L_SRC_SFT 4
  390. #define RT5677_M_DAC3_R_VOL (0x1 << 3)
  391. #define RT5677_M_DAC3_R_VOL_SFT 3
  392. #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
  393. #define RT5677_SEL_DAC3_R_SRC_SFT 0
  394. /* DAC4 Digital Volume (0x17) */
  395. #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
  396. #define RT5677_DAC4_L_VOL_SFT 8
  397. #define RT5677_DAC4_R_VOL_MASK (0xff)
  398. #define RT5677_DAC4_R_VOL_SFT 0
  399. /* DAC3 Digital Volume (0x18) */
  400. #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
  401. #define RT5677_DAC3_L_VOL_SFT 8
  402. #define RT5677_DAC3_R_VOL_MASK (0xff)
  403. #define RT5677_DAC3_R_VOL_SFT 0
  404. /* DAC3 Digital Volume (0x19) */
  405. #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
  406. #define RT5677_DAC1_L_VOL_SFT 8
  407. #define RT5677_DAC1_R_VOL_MASK (0xff)
  408. #define RT5677_DAC1_R_VOL_SFT 0
  409. /* DAC2 Digital Volume (0x1a) */
  410. #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
  411. #define RT5677_DAC2_L_VOL_SFT 8
  412. #define RT5677_DAC2_R_VOL_MASK (0xff)
  413. #define RT5677_DAC2_R_VOL_SFT 0
  414. /* IF/DSP to DAC2 Mixer Control (0x1b) */
  415. #define RT5677_M_DAC2_L_VOL (0x1 << 7)
  416. #define RT5677_M_DAC2_L_VOL_SFT 7
  417. #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
  418. #define RT5677_SEL_DAC2_L_SRC_SFT 4
  419. #define RT5677_M_DAC2_R_VOL (0x1 << 3)
  420. #define RT5677_M_DAC2_R_VOL_SFT 3
  421. #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
  422. #define RT5677_SEL_DAC2_R_SRC_SFT 0
  423. /* Stereo1 ADC Digital Volume Control (0x1c) */
  424. #define RT5677_STO1_ADC_L_VOL_MASK (0x3f << 9)
  425. #define RT5677_STO1_ADC_L_VOL_SFT 9
  426. #define RT5677_STO1_ADC_R_VOL_MASK (0x3f << 1)
  427. #define RT5677_STO1_ADC_R_VOL_SFT 1
  428. /* Mono ADC Digital Volume Control (0x1d) */
  429. #define RT5677_MONO_ADC_L_VOL_MASK (0x3f << 9)
  430. #define RT5677_MONO_ADC_L_VOL_SFT 9
  431. #define RT5677_MONO_ADC_R_VOL_MASK (0x3f << 1)
  432. #define RT5677_MONO_ADC_R_VOL_SFT 1
  433. /* Stereo 1/2 ADC Boost Gain Control (0x1e) */
  434. #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
  435. #define RT5677_STO1_ADC_L_BST_SFT 14
  436. #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
  437. #define RT5677_STO1_ADC_R_BST_SFT 12
  438. #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
  439. #define RT5677_STO1_ADC_COMP_SFT 10
  440. #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
  441. #define RT5677_STO2_ADC_L_BST_SFT 8
  442. #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
  443. #define RT5677_STO2_ADC_R_BST_SFT 6
  444. #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
  445. #define RT5677_STO2_ADC_COMP_SFT 4
  446. /* Stereo2 ADC Digital Volume Control (0x1f) */
  447. #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
  448. #define RT5677_STO2_ADC_L_VOL_SFT 8
  449. #define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
  450. #define RT5677_STO2_ADC_R_VOL_SFT 0
  451. /* ADC Boost Gain Control 2 (0x20) */
  452. #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
  453. #define RT5677_MONO_ADC_L_BST_SFT 14
  454. #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
  455. #define RT5677_MONO_ADC_R_BST_SFT 12
  456. #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
  457. #define RT5677_MONO_ADC_COMP_SFT 10
  458. /* Stereo 3/4 ADC Boost Gain Control (0x21) */
  459. #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
  460. #define RT5677_STO3_ADC_L_BST_SFT 14
  461. #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
  462. #define RT5677_STO3_ADC_R_BST_SFT 12
  463. #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
  464. #define RT5677_STO3_ADC_COMP_SFT 10
  465. #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
  466. #define RT5677_STO4_ADC_L_BST_SFT 8
  467. #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
  468. #define RT5677_STO4_ADC_R_BST_SFT 6
  469. #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
  470. #define RT5677_STO4_ADC_COMP_SFT 4
  471. /* Stereo3 ADC Digital Volume Control (0x22) */
  472. #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
  473. #define RT5677_STO3_ADC_L_VOL_SFT 8
  474. #define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
  475. #define RT5677_STO3_ADC_R_VOL_SFT 0
  476. /* Stereo4 ADC Digital Volume Control (0x23) */
  477. #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
  478. #define RT5677_STO4_ADC_L_VOL_SFT 8
  479. #define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
  480. #define RT5677_STO4_ADC_R_VOL_SFT 0
  481. /* Stereo4 ADC Mixer control (0x24) */
  482. #define RT5677_M_STO4_ADC_L2 (0x1 << 15)
  483. #define RT5677_M_STO4_ADC_L2_SFT 15
  484. #define RT5677_M_STO4_ADC_L1 (0x1 << 14)
  485. #define RT5677_M_STO4_ADC_L1_SFT 14
  486. #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
  487. #define RT5677_SEL_STO4_ADC1_SFT 12
  488. #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
  489. #define RT5677_SEL_STO4_ADC2_SFT 10
  490. #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
  491. #define RT5677_SEL_STO4_DMIC_SFT 8
  492. #define RT5677_M_STO4_ADC_R1 (0x1 << 7)
  493. #define RT5677_M_STO4_ADC_R1_SFT 7
  494. #define RT5677_M_STO4_ADC_R2 (0x1 << 6)
  495. #define RT5677_M_STO4_ADC_R2_SFT 6
  496. /* Stereo3 ADC Mixer control (0x25) */
  497. #define RT5677_M_STO3_ADC_L2 (0x1 << 15)
  498. #define RT5677_M_STO3_ADC_L2_SFT 15
  499. #define RT5677_M_STO3_ADC_L1 (0x1 << 14)
  500. #define RT5677_M_STO3_ADC_L1_SFT 14
  501. #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
  502. #define RT5677_SEL_STO3_ADC1_SFT 12
  503. #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
  504. #define RT5677_SEL_STO3_ADC2_SFT 10
  505. #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
  506. #define RT5677_SEL_STO3_DMIC_SFT 8
  507. #define RT5677_M_STO3_ADC_R1 (0x1 << 7)
  508. #define RT5677_M_STO3_ADC_R1_SFT 7
  509. #define RT5677_M_STO3_ADC_R2 (0x1 << 6)
  510. #define RT5677_M_STO3_ADC_R2_SFT 6
  511. /* Stereo2 ADC Mixer Control (0x26) */
  512. #define RT5677_M_STO2_ADC_L2 (0x1 << 15)
  513. #define RT5677_M_STO2_ADC_L2_SFT 15
  514. #define RT5677_M_STO2_ADC_L1 (0x1 << 14)
  515. #define RT5677_M_STO2_ADC_L1_SFT 14
  516. #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
  517. #define RT5677_SEL_STO2_ADC1_SFT 12
  518. #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
  519. #define RT5677_SEL_STO2_ADC2_SFT 10
  520. #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
  521. #define RT5677_SEL_STO2_DMIC_SFT 8
  522. #define RT5677_M_STO2_ADC_R1 (0x1 << 7)
  523. #define RT5677_M_STO2_ADC_R1_SFT 7
  524. #define RT5677_M_STO2_ADC_R2 (0x1 << 6)
  525. #define RT5677_M_STO2_ADC_R2_SFT 6
  526. #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
  527. #define RT5677_SEL_STO2_LR_MIX_SFT 0
  528. #define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
  529. #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
  530. /* Stereo1 ADC Mixer control (0x27) */
  531. #define RT5677_M_STO1_ADC_L2 (0x1 << 15)
  532. #define RT5677_M_STO1_ADC_L2_SFT 15
  533. #define RT5677_M_STO1_ADC_L1 (0x1 << 14)
  534. #define RT5677_M_STO1_ADC_L1_SFT 14
  535. #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
  536. #define RT5677_SEL_STO1_ADC1_SFT 12
  537. #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
  538. #define RT5677_SEL_STO1_ADC2_SFT 10
  539. #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
  540. #define RT5677_SEL_STO1_DMIC_SFT 8
  541. #define RT5677_M_STO1_ADC_R1 (0x1 << 7)
  542. #define RT5677_M_STO1_ADC_R1_SFT 7
  543. #define RT5677_M_STO1_ADC_R2 (0x1 << 6)
  544. #define RT5677_M_STO1_ADC_R2_SFT 6
  545. /* Mono ADC Mixer control (0x28) */
  546. #define RT5677_M_MONO_ADC_L2 (0x1 << 15)
  547. #define RT5677_M_MONO_ADC_L2_SFT 15
  548. #define RT5677_M_MONO_ADC_L1 (0x1 << 14)
  549. #define RT5677_M_MONO_ADC_L1_SFT 14
  550. #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
  551. #define RT5677_SEL_MONO_ADC_L1_SFT 12
  552. #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
  553. #define RT5677_SEL_MONO_ADC_L2_SFT 10
  554. #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
  555. #define RT5677_SEL_MONO_DMIC_L_SFT 8
  556. #define RT5677_M_MONO_ADC_R1 (0x1 << 7)
  557. #define RT5677_M_MONO_ADC_R1_SFT 7
  558. #define RT5677_M_MONO_ADC_R2 (0x1 << 6)
  559. #define RT5677_M_MONO_ADC_R2_SFT 6
  560. #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
  561. #define RT5677_SEL_MONO_ADC_R1_SFT 4
  562. #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
  563. #define RT5677_SEL_MONO_ADC_R2_SFT 2
  564. #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
  565. #define RT5677_SEL_MONO_DMIC_R_SFT 0
  566. /* ADC/IF/DSP to DAC1 Mixer control (0x29) */
  567. #define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
  568. #define RT5677_M_ADDA_MIXER1_L_SFT 15
  569. #define RT5677_M_DAC1_L (0x1 << 14)
  570. #define RT5677_M_DAC1_L_SFT 14
  571. #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
  572. #define RT5677_DAC1_L_SEL_SFT 8
  573. #define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
  574. #define RT5677_M_ADDA_MIXER1_R_SFT 7
  575. #define RT5677_M_DAC1_R (0x1 << 6)
  576. #define RT5677_M_DAC1_R_SFT 6
  577. #define RT5677_ADDA1_SEL_MASK (0x3 << 0)
  578. #define RT5677_ADDA1_SEL_SFT 0
  579. /* Stereo1 DAC Mixer L/R Control (0x2a) */
  580. #define RT5677_M_ST_DAC1_L (0x1 << 15)
  581. #define RT5677_M_ST_DAC1_L_SFT 15
  582. #define RT5677_M_DAC1_L_STO_L (0x1 << 13)
  583. #define RT5677_M_DAC1_L_STO_L_SFT 13
  584. #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
  585. #define RT5677_DAC1_L_STO_L_VOL_SFT 12
  586. #define RT5677_M_DAC2_L_STO_L (0x1 << 11)
  587. #define RT5677_M_DAC2_L_STO_L_SFT 11
  588. #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
  589. #define RT5677_DAC2_L_STO_L_VOL_SFT 10
  590. #define RT5677_M_DAC1_R_STO_L (0x1 << 9)
  591. #define RT5677_M_DAC1_R_STO_L_SFT 9
  592. #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
  593. #define RT5677_DAC1_R_STO_L_VOL_SFT 8
  594. #define RT5677_M_ST_DAC1_R (0x1 << 7)
  595. #define RT5677_M_ST_DAC1_R_SFT 7
  596. #define RT5677_M_DAC1_R_STO_R (0x1 << 5)
  597. #define RT5677_M_DAC1_R_STO_R_SFT 5
  598. #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
  599. #define RT5677_DAC1_R_STO_R_VOL_SFT 4
  600. #define RT5677_M_DAC2_R_STO_R (0x1 << 3)
  601. #define RT5677_M_DAC2_R_STO_R_SFT 3
  602. #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
  603. #define RT5677_DAC2_R_STO_R_VOL_SFT 2
  604. #define RT5677_M_DAC1_L_STO_R (0x1 << 1)
  605. #define RT5677_M_DAC1_L_STO_R_SFT 1
  606. #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
  607. #define RT5677_DAC1_L_STO_R_VOL_SFT 0
  608. /* Mono DAC Mixer L/R Control (0x2b) */
  609. #define RT5677_M_ST_DAC2_L (0x1 << 15)
  610. #define RT5677_M_ST_DAC2_L_SFT 15
  611. #define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
  612. #define RT5677_M_DAC2_L_MONO_L_SFT 13
  613. #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
  614. #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
  615. #define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
  616. #define RT5677_M_DAC2_R_MONO_L_SFT 11
  617. #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
  618. #define RT5677_DAC2_R_MONO_L_VOL_SFT 10
  619. #define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
  620. #define RT5677_M_DAC1_L_MONO_L_SFT 9
  621. #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
  622. #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
  623. #define RT5677_M_ST_DAC2_R (0x1 << 7)
  624. #define RT5677_M_ST_DAC2_R_SFT 7
  625. #define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
  626. #define RT5677_M_DAC2_R_MONO_R_SFT 5
  627. #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
  628. #define RT5677_DAC2_R_MONO_R_VOL_SFT 4
  629. #define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
  630. #define RT5677_M_DAC1_R_MONO_R_SFT 3
  631. #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
  632. #define RT5677_DAC1_R_MONO_R_VOL_SFT 2
  633. #define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
  634. #define RT5677_M_DAC2_L_MONO_R_SFT 1
  635. #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
  636. #define RT5677_DAC2_L_MONO_R_VOL_SFT 0
  637. /* DD Mixer 1 Control (0x2c) */
  638. #define RT5677_M_STO_L_DD1_L (0x1 << 15)
  639. #define RT5677_M_STO_L_DD1_L_SFT 15
  640. #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
  641. #define RT5677_STO_L_DD1_L_VOL_SFT 14
  642. #define RT5677_M_MONO_L_DD1_L (0x1 << 13)
  643. #define RT5677_M_MONO_L_DD1_L_SFT 13
  644. #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
  645. #define RT5677_MONO_L_DD1_L_VOL_SFT 12
  646. #define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
  647. #define RT5677_M_DAC3_L_DD1_L_SFT 11
  648. #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
  649. #define RT5677_DAC3_L_DD1_L_VOL_SFT 10
  650. #define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
  651. #define RT5677_M_DAC3_R_DD1_L_SFT 9
  652. #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
  653. #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
  654. #define RT5677_M_STO_R_DD1_R (0x1 << 7)
  655. #define RT5677_M_STO_R_DD1_R_SFT 7
  656. #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
  657. #define RT5677_STO_R_DD1_R_VOL_SFT 6
  658. #define RT5677_M_MONO_R_DD1_R (0x1 << 5)
  659. #define RT5677_M_MONO_R_DD1_R_SFT 5
  660. #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
  661. #define RT5677_MONO_R_DD1_R_VOL_SFT 4
  662. #define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
  663. #define RT5677_M_DAC3_R_DD1_R_SFT 3
  664. #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
  665. #define RT5677_DAC3_R_DD1_R_VOL_SFT 2
  666. #define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
  667. #define RT5677_M_DAC3_L_DD1_R_SFT 1
  668. #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
  669. #define RT5677_DAC3_L_DD1_R_VOL_SFT 0
  670. /* DD Mixer 2 Control (0x2d) */
  671. #define RT5677_M_STO_L_DD2_L (0x1 << 15)
  672. #define RT5677_M_STO_L_DD2_L_SFT 15
  673. #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
  674. #define RT5677_STO_L_DD2_L_VOL_SFT 14
  675. #define RT5677_M_MONO_L_DD2_L (0x1 << 13)
  676. #define RT5677_M_MONO_L_DD2_L_SFT 13
  677. #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
  678. #define RT5677_MONO_L_DD2_L_VOL_SFT 12
  679. #define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
  680. #define RT5677_M_DAC4_L_DD2_L_SFT 11
  681. #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
  682. #define RT5677_DAC4_L_DD2_L_VOL_SFT 10
  683. #define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
  684. #define RT5677_M_DAC4_R_DD2_L_SFT 9
  685. #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
  686. #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
  687. #define RT5677_M_STO_R_DD2_R (0x1 << 7)
  688. #define RT5677_M_STO_R_DD2_R_SFT 7
  689. #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
  690. #define RT5677_STO_R_DD2_R_VOL_SFT 6
  691. #define RT5677_M_MONO_R_DD2_R (0x1 << 5)
  692. #define RT5677_M_MONO_R_DD2_R_SFT 5
  693. #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
  694. #define RT5677_MONO_R_DD2_R_VOL_SFT 4
  695. #define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
  696. #define RT5677_M_DAC4_R_DD2_R_SFT 3
  697. #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
  698. #define RT5677_DAC4_R_DD2_R_VOL_SFT 2
  699. #define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
  700. #define RT5677_M_DAC4_L_DD2_R_SFT 1
  701. #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
  702. #define RT5677_DAC4_L_DD2_R_VOL_SFT 0
  703. /* IF3 data control (0x2f) */
  704. #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
  705. #define RT5677_IF3_DAC_SEL_SFT 6
  706. #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
  707. #define RT5677_IF3_ADC_SEL_SFT 4
  708. #define RT5677_IF3_ADC_IN_MASK (0xf << 0)
  709. #define RT5677_IF3_ADC_IN_SFT 0
  710. /* IF4 data control (0x30) */
  711. #define RT5677_IF4_ADC_IN_MASK (0xf << 4)
  712. #define RT5677_IF4_ADC_IN_SFT 4
  713. #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
  714. #define RT5677_IF4_DAC_SEL_SFT 2
  715. #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
  716. #define RT5677_IF4_ADC_SEL_SFT 0
  717. /* PDM Output Control (0x31) */
  718. #define RT5677_M_PDM1_L (0x1 << 15)
  719. #define RT5677_M_PDM1_L_SFT 15
  720. #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
  721. #define RT5677_SEL_PDM1_L_SFT 12
  722. #define RT5677_M_PDM1_R (0x1 << 11)
  723. #define RT5677_M_PDM1_R_SFT 11
  724. #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
  725. #define RT5677_SEL_PDM1_R_SFT 8
  726. #define RT5677_M_PDM2_L (0x1 << 7)
  727. #define RT5677_M_PDM2_L_SFT 7
  728. #define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
  729. #define RT5677_SEL_PDM2_L_SFT 4
  730. #define RT5677_M_PDM2_R (0x1 << 3)
  731. #define RT5677_M_PDM2_R_SFT 3
  732. #define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
  733. #define RT5677_SEL_PDM2_R_SFT 0
  734. /* PDM I2C / Data Control 1 (0x32) */
  735. #define RT5677_PDM2_PW_DOWN (0x1 << 7)
  736. #define RT5677_PDM1_PW_DOWN (0x1 << 6)
  737. #define RT5677_PDM2_BUSY (0x1 << 5)
  738. #define RT5677_PDM1_BUSY (0x1 << 4)
  739. #define RT5677_PDM_PATTERN (0x1 << 3)
  740. #define RT5677_PDM_GAIN (0x1 << 2)
  741. #define RT5677_PDM_DIV_MASK (0x3 << 0)
  742. /* PDM I2C / Data Control 2 (0x33) */
  743. #define RT5677_PDM1_I2C_ID (0xf << 12)
  744. #define RT5677_PDM1_EXE (0x1 << 11)
  745. #define RT5677_PDM1_I2C_CMD (0x1 << 10)
  746. #define RT5677_PDM1_I2C_EXE (0x1 << 9)
  747. #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
  748. #define RT5677_PDM2_I2C_ID (0xf << 4)
  749. #define RT5677_PDM2_EXE (0x1 << 3)
  750. #define RT5677_PDM2_I2C_CMD (0x1 << 2)
  751. #define RT5677_PDM2_I2C_EXE (0x1 << 1)
  752. #define RT5677_PDM2_I2C_BUSY (0x1 << 0)
  753. /* TDM1 control 1 (0x3b) */
  754. #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)
  755. #define RT5677_IF1_ADC_MODE_SFT 12
  756. #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12)
  757. #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)
  758. #define RT5677_IF1_ADC1_SWAP_MASK (0x3 << 6)
  759. #define RT5677_IF1_ADC1_SWAP_SFT 6
  760. #define RT5677_IF1_ADC2_SWAP_MASK (0x3 << 4)
  761. #define RT5677_IF1_ADC2_SWAP_SFT 4
  762. #define RT5677_IF1_ADC3_SWAP_MASK (0x3 << 2)
  763. #define RT5677_IF1_ADC3_SWAP_SFT 2
  764. #define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0)
  765. #define RT5677_IF1_ADC4_SWAP_SFT 0
  766. /* TDM1 control 2 (0x3c) */
  767. #define RT5677_IF1_ADC4_MASK (0x3 << 10)
  768. #define RT5677_IF1_ADC4_SFT 10
  769. #define RT5677_IF1_ADC3_MASK (0x3 << 8)
  770. #define RT5677_IF1_ADC3_SFT 8
  771. #define RT5677_IF1_ADC2_MASK (0x3 << 6)
  772. #define RT5677_IF1_ADC2_SFT 6
  773. #define RT5677_IF1_ADC1_MASK (0x3 << 4)
  774. #define RT5677_IF1_ADC1_SFT 4
  775. #define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0)
  776. #define RT5677_IF1_ADC_CTRL_SFT 0
  777. /* TDM1 control 4 (0x3e) */
  778. #define RT5677_IF1_DAC0_MASK (0x7 << 12)
  779. #define RT5677_IF1_DAC0_SFT 12
  780. #define RT5677_IF1_DAC1_MASK (0x7 << 8)
  781. #define RT5677_IF1_DAC1_SFT 8
  782. #define RT5677_IF1_DAC2_MASK (0x7 << 4)
  783. #define RT5677_IF1_DAC2_SFT 4
  784. #define RT5677_IF1_DAC3_MASK (0x7 << 0)
  785. #define RT5677_IF1_DAC3_SFT 0
  786. /* TDM1 control 5 (0x3f) */
  787. #define RT5677_IF1_DAC4_MASK (0x7 << 12)
  788. #define RT5677_IF1_DAC4_SFT 12
  789. #define RT5677_IF1_DAC5_MASK (0x7 << 8)
  790. #define RT5677_IF1_DAC5_SFT 8
  791. #define RT5677_IF1_DAC6_MASK (0x7 << 4)
  792. #define RT5677_IF1_DAC6_SFT 4
  793. #define RT5677_IF1_DAC7_MASK (0x7 << 0)
  794. #define RT5677_IF1_DAC7_SFT 0
  795. /* TDM2 control 1 (0x40) */
  796. #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)
  797. #define RT5677_IF2_ADC_MODE_SFT 12
  798. #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12)
  799. #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)
  800. #define RT5677_IF2_ADC1_SWAP_MASK (0x3 << 6)
  801. #define RT5677_IF2_ADC1_SWAP_SFT 6
  802. #define RT5677_IF2_ADC2_SWAP_MASK (0x3 << 4)
  803. #define RT5677_IF2_ADC2_SWAP_SFT 4
  804. #define RT5677_IF2_ADC3_SWAP_MASK (0x3 << 2)
  805. #define RT5677_IF2_ADC3_SWAP_SFT 2
  806. #define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0)
  807. #define RT5677_IF2_ADC4_SWAP_SFT 0
  808. /* TDM2 control 2 (0x41) */
  809. #define RT5677_IF2_ADC4_MASK (0x3 << 10)
  810. #define RT5677_IF2_ADC4_SFT 10
  811. #define RT5677_IF2_ADC3_MASK (0x3 << 8)
  812. #define RT5677_IF2_ADC3_SFT 8
  813. #define RT5677_IF2_ADC2_MASK (0x3 << 6)
  814. #define RT5677_IF2_ADC2_SFT 6
  815. #define RT5677_IF2_ADC1_MASK (0x3 << 4)
  816. #define RT5677_IF2_ADC1_SFT 4
  817. #define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0)
  818. #define RT5677_IF2_ADC_CTRL_SFT 0
  819. /* TDM2 control 4 (0x43) */
  820. #define RT5677_IF2_DAC0_MASK (0x7 << 12)
  821. #define RT5677_IF2_DAC0_SFT 12
  822. #define RT5677_IF2_DAC1_MASK (0x7 << 8)
  823. #define RT5677_IF2_DAC1_SFT 8
  824. #define RT5677_IF2_DAC2_MASK (0x7 << 4)
  825. #define RT5677_IF2_DAC2_SFT 4
  826. #define RT5677_IF2_DAC3_MASK (0x7 << 0)
  827. #define RT5677_IF2_DAC3_SFT 0
  828. /* TDM2 control 5 (0x44) */
  829. #define RT5677_IF2_DAC4_MASK (0x7 << 12)
  830. #define RT5677_IF2_DAC4_SFT 12
  831. #define RT5677_IF2_DAC5_MASK (0x7 << 8)
  832. #define RT5677_IF2_DAC5_SFT 8
  833. #define RT5677_IF2_DAC6_MASK (0x7 << 4)
  834. #define RT5677_IF2_DAC6_SFT 4
  835. #define RT5677_IF2_DAC7_MASK (0x7 << 0)
  836. #define RT5677_IF2_DAC7_SFT 0
  837. /* Digital Microphone Control 1 (0x50) */
  838. #define RT5677_DMIC_1_EN_MASK (0x1 << 15)
  839. #define RT5677_DMIC_1_EN_SFT 15
  840. #define RT5677_DMIC_1_DIS (0x0 << 15)
  841. #define RT5677_DMIC_1_EN (0x1 << 15)
  842. #define RT5677_DMIC_2_EN_MASK (0x1 << 14)
  843. #define RT5677_DMIC_2_EN_SFT 14
  844. #define RT5677_DMIC_2_DIS (0x0 << 14)
  845. #define RT5677_DMIC_2_EN (0x1 << 14)
  846. #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
  847. #define RT5677_DMIC_L_STO1_LH_SFT 13
  848. #define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
  849. #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
  850. #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
  851. #define RT5677_DMIC_R_STO1_LH_SFT 12
  852. #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
  853. #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
  854. #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
  855. #define RT5677_DMIC_L_STO3_LH_SFT 11
  856. #define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
  857. #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
  858. #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
  859. #define RT5677_DMIC_R_STO3_LH_SFT 10
  860. #define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
  861. #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
  862. #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
  863. #define RT5677_DMIC_L_STO2_LH_SFT 9
  864. #define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
  865. #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
  866. #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
  867. #define RT5677_DMIC_R_STO2_LH_SFT 8
  868. #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
  869. #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
  870. #define RT5677_DMIC_CLK_MASK (0x7 << 5)
  871. #define RT5677_DMIC_CLK_SFT 5
  872. #define RT5677_DMIC_3_EN_MASK (0x1 << 4)
  873. #define RT5677_DMIC_3_EN_SFT 4
  874. #define RT5677_DMIC_3_DIS (0x0 << 4)
  875. #define RT5677_DMIC_3_EN (0x1 << 4)
  876. #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
  877. #define RT5677_DMIC_R_MONO_LH_SFT 2
  878. #define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
  879. #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
  880. #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
  881. #define RT5677_DMIC_L_STO4_LH_SFT 1
  882. #define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
  883. #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
  884. #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
  885. #define RT5677_DMIC_R_STO4_LH_SFT 0
  886. #define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
  887. #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
  888. /* Digital Microphone Control 2 (0x51) */
  889. #define RT5677_DMIC_4_EN_MASK (0x1 << 15)
  890. #define RT5677_DMIC_4_EN_SFT 15
  891. #define RT5677_DMIC_4_DIS (0x0 << 15)
  892. #define RT5677_DMIC_4_EN (0x1 << 15)
  893. #define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
  894. #define RT5677_DMIC_4L_LH_SFT 7
  895. #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
  896. #define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
  897. #define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
  898. #define RT5677_DMIC_4R_LH_SFT 6
  899. #define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
  900. #define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
  901. #define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
  902. #define RT5677_DMIC_3L_LH_SFT 5
  903. #define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
  904. #define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
  905. #define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
  906. #define RT5677_DMIC_3R_LH_SFT 4
  907. #define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
  908. #define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
  909. #define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
  910. #define RT5677_DMIC_2L_LH_SFT 3
  911. #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
  912. #define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
  913. #define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
  914. #define RT5677_DMIC_2R_LH_SFT 2
  915. #define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
  916. #define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
  917. #define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
  918. #define RT5677_DMIC_1L_LH_SFT 1
  919. #define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
  920. #define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
  921. #define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
  922. #define RT5677_DMIC_1R_LH_SFT 0
  923. #define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
  924. #define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
  925. /* Power Management for Digital 1 (0x61) */
  926. #define RT5677_PWR_I2S1 (0x1 << 15)
  927. #define RT5677_PWR_I2S1_BIT 15
  928. #define RT5677_PWR_I2S2 (0x1 << 14)
  929. #define RT5677_PWR_I2S2_BIT 14
  930. #define RT5677_PWR_I2S3 (0x1 << 13)
  931. #define RT5677_PWR_I2S3_BIT 13
  932. #define RT5677_PWR_DAC1 (0x1 << 12)
  933. #define RT5677_PWR_DAC1_BIT 12
  934. #define RT5677_PWR_DAC2 (0x1 << 11)
  935. #define RT5677_PWR_DAC2_BIT 11
  936. #define RT5677_PWR_I2S4 (0x1 << 10)
  937. #define RT5677_PWR_I2S4_BIT 10
  938. #define RT5677_PWR_SLB (0x1 << 9)
  939. #define RT5677_PWR_SLB_BIT 9
  940. #define RT5677_PWR_DAC3 (0x1 << 7)
  941. #define RT5677_PWR_DAC3_BIT 7
  942. #define RT5677_PWR_ADCFED2 (0x1 << 4)
  943. #define RT5677_PWR_ADCFED2_BIT 4
  944. #define RT5677_PWR_ADCFED1 (0x1 << 3)
  945. #define RT5677_PWR_ADCFED1_BIT 3
  946. #define RT5677_PWR_ADC_L (0x1 << 2)
  947. #define RT5677_PWR_ADC_L_BIT 2
  948. #define RT5677_PWR_ADC_R (0x1 << 1)
  949. #define RT5677_PWR_ADC_R_BIT 1
  950. #define RT5677_PWR_I2C_MASTER (0x1 << 0)
  951. #define RT5677_PWR_I2C_MASTER_BIT 0
  952. /* Power Management for Digital 2 (0x62) */
  953. #define RT5677_PWR_ADC_S1F (0x1 << 15)
  954. #define RT5677_PWR_ADC_S1F_BIT 15
  955. #define RT5677_PWR_ADC_MF_L (0x1 << 14)
  956. #define RT5677_PWR_ADC_MF_L_BIT 14
  957. #define RT5677_PWR_ADC_MF_R (0x1 << 13)
  958. #define RT5677_PWR_ADC_MF_R_BIT 13
  959. #define RT5677_PWR_DAC_S1F (0x1 << 12)
  960. #define RT5677_PWR_DAC_S1F_BIT 12
  961. #define RT5677_PWR_DAC_M2F_L (0x1 << 11)
  962. #define RT5677_PWR_DAC_M2F_L_BIT 11
  963. #define RT5677_PWR_DAC_M2F_R (0x1 << 10)
  964. #define RT5677_PWR_DAC_M2F_R_BIT 10
  965. #define RT5677_PWR_DAC_M3F_L (0x1 << 9)
  966. #define RT5677_PWR_DAC_M3F_L_BIT 9
  967. #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
  968. #define RT5677_PWR_DAC_M3F_R_BIT 8
  969. #define RT5677_PWR_DAC_M4F_L (0x1 << 7)
  970. #define RT5677_PWR_DAC_M4F_L_BIT 7
  971. #define RT5677_PWR_DAC_M4F_R (0x1 << 6)
  972. #define RT5677_PWR_DAC_M4F_R_BIT 6
  973. #define RT5677_PWR_ADC_S2F (0x1 << 5)
  974. #define RT5677_PWR_ADC_S2F_BIT 5
  975. #define RT5677_PWR_ADC_S3F (0x1 << 4)
  976. #define RT5677_PWR_ADC_S3F_BIT 4
  977. #define RT5677_PWR_ADC_S4F (0x1 << 3)
  978. #define RT5677_PWR_ADC_S4F_BIT 3
  979. #define RT5677_PWR_PDM1 (0x1 << 2)
  980. #define RT5677_PWR_PDM1_BIT 2
  981. #define RT5677_PWR_PDM2 (0x1 << 1)
  982. #define RT5677_PWR_PDM2_BIT 1
  983. /* Power Management for Analog 1 (0x63) */
  984. #define RT5677_PWR_VREF1 (0x1 << 15)
  985. #define RT5677_PWR_VREF1_BIT 15
  986. #define RT5677_PWR_FV1 (0x1 << 14)
  987. #define RT5677_PWR_FV1_BIT 14
  988. #define RT5677_PWR_MB (0x1 << 13)
  989. #define RT5677_PWR_MB_BIT 13
  990. #define RT5677_PWR_LO1 (0x1 << 12)
  991. #define RT5677_PWR_LO1_BIT 12
  992. #define RT5677_PWR_BG (0x1 << 11)
  993. #define RT5677_PWR_BG_BIT 11
  994. #define RT5677_PWR_LO2 (0x1 << 10)
  995. #define RT5677_PWR_LO2_BIT 10
  996. #define RT5677_PWR_LO3 (0x1 << 9)
  997. #define RT5677_PWR_LO3_BIT 9
  998. #define RT5677_PWR_VREF2 (0x1 << 8)
  999. #define RT5677_PWR_VREF2_BIT 8
  1000. #define RT5677_PWR_FV2 (0x1 << 7)
  1001. #define RT5677_PWR_FV2_BIT 7
  1002. #define RT5677_LDO2_SEL_MASK (0x7 << 4)
  1003. #define RT5677_LDO2_SEL_SFT 4
  1004. #define RT5677_LDO1_SEL_MASK (0x7 << 0)
  1005. #define RT5677_LDO1_SEL_SFT 0
  1006. /* Power Management for Analog 2 (0x64) */
  1007. #define RT5677_PWR_BST1 (0x1 << 15)
  1008. #define RT5677_PWR_BST1_BIT 15
  1009. #define RT5677_PWR_BST2 (0x1 << 14)
  1010. #define RT5677_PWR_BST2_BIT 14
  1011. #define RT5677_PWR_CLK_MB1 (0x1 << 13)
  1012. #define RT5677_PWR_CLK_MB1_BIT 13
  1013. #define RT5677_PWR_SLIM (0x1 << 12)
  1014. #define RT5677_PWR_SLIM_BIT 12
  1015. #define RT5677_PWR_MB1 (0x1 << 11)
  1016. #define RT5677_PWR_MB1_BIT 11
  1017. #define RT5677_PWR_PP_MB1 (0x1 << 10)
  1018. #define RT5677_PWR_PP_MB1_BIT 10
  1019. #define RT5677_PWR_PLL1 (0x1 << 9)
  1020. #define RT5677_PWR_PLL1_BIT 9
  1021. #define RT5677_PWR_PLL2 (0x1 << 8)
  1022. #define RT5677_PWR_PLL2_BIT 8
  1023. #define RT5677_PWR_CORE (0x1 << 7)
  1024. #define RT5677_PWR_CORE_BIT 7
  1025. #define RT5677_PWR_CLK_MB (0x1 << 6)
  1026. #define RT5677_PWR_CLK_MB_BIT 6
  1027. #define RT5677_PWR_BST1_P (0x1 << 5)
  1028. #define RT5677_PWR_BST1_P_BIT 5
  1029. #define RT5677_PWR_BST2_P (0x1 << 4)
  1030. #define RT5677_PWR_BST2_P_BIT 4
  1031. #define RT5677_PWR_IPTV (0x1 << 3)
  1032. #define RT5677_PWR_IPTV_BIT 3
  1033. #define RT5677_PWR_25M_CLK (0x1 << 1)
  1034. #define RT5677_PWR_25M_CLK_BIT 1
  1035. #define RT5677_PWR_LDO1 (0x1 << 0)
  1036. #define RT5677_PWR_LDO1_BIT 0
  1037. /* Power Management for DSP (0x65) */
  1038. #define RT5677_PWR_SR7 (0x1 << 10)
  1039. #define RT5677_PWR_SR7_BIT 10
  1040. #define RT5677_PWR_SR6 (0x1 << 9)
  1041. #define RT5677_PWR_SR6_BIT 9
  1042. #define RT5677_PWR_SR5 (0x1 << 8)
  1043. #define RT5677_PWR_SR5_BIT 8
  1044. #define RT5677_PWR_SR4 (0x1 << 7)
  1045. #define RT5677_PWR_SR4_BIT 7
  1046. #define RT5677_PWR_SR3 (0x1 << 6)
  1047. #define RT5677_PWR_SR3_BIT 6
  1048. #define RT5677_PWR_SR2 (0x1 << 5)
  1049. #define RT5677_PWR_SR2_BIT 5
  1050. #define RT5677_PWR_SR1 (0x1 << 4)
  1051. #define RT5677_PWR_SR1_BIT 4
  1052. #define RT5677_PWR_SR0 (0x1 << 3)
  1053. #define RT5677_PWR_SR0_BIT 3
  1054. #define RT5677_PWR_MLT (0x1 << 2)
  1055. #define RT5677_PWR_MLT_BIT 2
  1056. #define RT5677_PWR_DSP (0x1 << 1)
  1057. #define RT5677_PWR_DSP_BIT 1
  1058. #define RT5677_PWR_DSP_CPU (0x1 << 0)
  1059. #define RT5677_PWR_DSP_CPU_BIT 0
  1060. /* Power Status for DSP (0x66) */
  1061. #define RT5677_PWR_SR7_RDY (0x1 << 9)
  1062. #define RT5677_PWR_SR7_RDY_BIT 9
  1063. #define RT5677_PWR_SR6_RDY (0x1 << 8)
  1064. #define RT5677_PWR_SR6_RDY_BIT 8
  1065. #define RT5677_PWR_SR5_RDY (0x1 << 7)
  1066. #define RT5677_PWR_SR5_RDY_BIT 7
  1067. #define RT5677_PWR_SR4_RDY (0x1 << 6)
  1068. #define RT5677_PWR_SR4_RDY_BIT 6
  1069. #define RT5677_PWR_SR3_RDY (0x1 << 5)
  1070. #define RT5677_PWR_SR3_RDY_BIT 5
  1071. #define RT5677_PWR_SR2_RDY (0x1 << 4)
  1072. #define RT5677_PWR_SR2_RDY_BIT 4
  1073. #define RT5677_PWR_SR1_RDY (0x1 << 3)
  1074. #define RT5677_PWR_SR1_RDY_BIT 3
  1075. #define RT5677_PWR_SR0_RDY (0x1 << 2)
  1076. #define RT5677_PWR_SR0_RDY_BIT 2
  1077. #define RT5677_PWR_MLT_RDY (0x1 << 1)
  1078. #define RT5677_PWR_MLT_RDY_BIT 1
  1079. #define RT5677_PWR_DSP_RDY (0x1 << 0)
  1080. #define RT5677_PWR_DSP_RDY_BIT 0
  1081. /* Power Management for DSP (0x67) */
  1082. #define RT5677_PWR_SLIM_ISO (0x1 << 11)
  1083. #define RT5677_PWR_SLIM_ISO_BIT 11
  1084. #define RT5677_PWR_CORE_ISO (0x1 << 10)
  1085. #define RT5677_PWR_CORE_ISO_BIT 10
  1086. #define RT5677_PWR_DSP_ISO (0x1 << 9)
  1087. #define RT5677_PWR_DSP_ISO_BIT 9
  1088. #define RT5677_PWR_SR7_ISO (0x1 << 8)
  1089. #define RT5677_PWR_SR7_ISO_BIT 8
  1090. #define RT5677_PWR_SR6_ISO (0x1 << 7)
  1091. #define RT5677_PWR_SR6_ISO_BIT 7
  1092. #define RT5677_PWR_SR5_ISO (0x1 << 6)
  1093. #define RT5677_PWR_SR5_ISO_BIT 6
  1094. #define RT5677_PWR_SR4_ISO (0x1 << 5)
  1095. #define RT5677_PWR_SR4_ISO_BIT 5
  1096. #define RT5677_PWR_SR3_ISO (0x1 << 4)
  1097. #define RT5677_PWR_SR3_ISO_BIT 4
  1098. #define RT5677_PWR_SR2_ISO (0x1 << 3)
  1099. #define RT5677_PWR_SR2_ISO_BIT 3
  1100. #define RT5677_PWR_SR1_ISO (0x1 << 2)
  1101. #define RT5677_PWR_SR1_ISO_BIT 2
  1102. #define RT5677_PWR_SR0_ISO (0x1 << 1)
  1103. #define RT5677_PWR_SR0_ISO_BIT 1
  1104. #define RT5677_PWR_MLT_ISO (0x1 << 0)
  1105. #define RT5677_PWR_MLT_ISO_BIT 0
  1106. /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
  1107. #define RT5677_I2S_MS_MASK (0x1 << 15)
  1108. #define RT5677_I2S_MS_SFT 15
  1109. #define RT5677_I2S_MS_M (0x0 << 15)
  1110. #define RT5677_I2S_MS_S (0x1 << 15)
  1111. #define RT5677_I2S_O_CP_MASK (0x3 << 10)
  1112. #define RT5677_I2S_O_CP_SFT 10
  1113. #define RT5677_I2S_O_CP_OFF (0x0 << 10)
  1114. #define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
  1115. #define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
  1116. #define RT5677_I2S_I_CP_MASK (0x3 << 8)
  1117. #define RT5677_I2S_I_CP_SFT 8
  1118. #define RT5677_I2S_I_CP_OFF (0x0 << 8)
  1119. #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
  1120. #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
  1121. #define RT5677_I2S_BP_MASK (0x1 << 7)
  1122. #define RT5677_I2S_BP_SFT 7
  1123. #define RT5677_I2S_BP_NOR (0x0 << 7)
  1124. #define RT5677_I2S_BP_INV (0x1 << 7)
  1125. #define RT5677_I2S_DL_MASK (0x3 << 2)
  1126. #define RT5677_I2S_DL_SFT 2
  1127. #define RT5677_I2S_DL_16 (0x0 << 2)
  1128. #define RT5677_I2S_DL_20 (0x1 << 2)
  1129. #define RT5677_I2S_DL_24 (0x2 << 2)
  1130. #define RT5677_I2S_DL_8 (0x3 << 2)
  1131. #define RT5677_I2S_DF_MASK (0x3 << 0)
  1132. #define RT5677_I2S_DF_SFT 0
  1133. #define RT5677_I2S_DF_I2S (0x0 << 0)
  1134. #define RT5677_I2S_DF_LEFT (0x1 << 0)
  1135. #define RT5677_I2S_DF_PCM_A (0x2 << 0)
  1136. #define RT5677_I2S_DF_PCM_B (0x3 << 0)
  1137. /* Clock Tree Control 1 (0x73) */
  1138. #define RT5677_I2S_PD1_MASK (0x7 << 12)
  1139. #define RT5677_I2S_PD1_SFT 12
  1140. #define RT5677_I2S_PD1_1 (0x0 << 12)
  1141. #define RT5677_I2S_PD1_2 (0x1 << 12)
  1142. #define RT5677_I2S_PD1_3 (0x2 << 12)
  1143. #define RT5677_I2S_PD1_4 (0x3 << 12)
  1144. #define RT5677_I2S_PD1_6 (0x4 << 12)
  1145. #define RT5677_I2S_PD1_8 (0x5 << 12)
  1146. #define RT5677_I2S_PD1_12 (0x6 << 12)
  1147. #define RT5677_I2S_PD1_16 (0x7 << 12)
  1148. #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
  1149. #define RT5677_I2S_BCLK_MS2_SFT 11
  1150. #define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
  1151. #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
  1152. #define RT5677_I2S_PD2_MASK (0x7 << 8)
  1153. #define RT5677_I2S_PD2_SFT 8
  1154. #define RT5677_I2S_PD2_1 (0x0 << 8)
  1155. #define RT5677_I2S_PD2_2 (0x1 << 8)
  1156. #define RT5677_I2S_PD2_3 (0x2 << 8)
  1157. #define RT5677_I2S_PD2_4 (0x3 << 8)
  1158. #define RT5677_I2S_PD2_6 (0x4 << 8)
  1159. #define RT5677_I2S_PD2_8 (0x5 << 8)
  1160. #define RT5677_I2S_PD2_12 (0x6 << 8)
  1161. #define RT5677_I2S_PD2_16 (0x7 << 8)
  1162. #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
  1163. #define RT5677_I2S_BCLK_MS3_SFT 7
  1164. #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
  1165. #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
  1166. #define RT5677_I2S_PD3_MASK (0x7 << 4)
  1167. #define RT5677_I2S_PD3_SFT 4
  1168. #define RT5677_I2S_PD3_1 (0x0 << 4)
  1169. #define RT5677_I2S_PD3_2 (0x1 << 4)
  1170. #define RT5677_I2S_PD3_3 (0x2 << 4)
  1171. #define RT5677_I2S_PD3_4 (0x3 << 4)
  1172. #define RT5677_I2S_PD3_6 (0x4 << 4)
  1173. #define RT5677_I2S_PD3_8 (0x5 << 4)
  1174. #define RT5677_I2S_PD3_12 (0x6 << 4)
  1175. #define RT5677_I2S_PD3_16 (0x7 << 4)
  1176. #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
  1177. #define RT5677_I2S_BCLK_MS4_SFT 3
  1178. #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
  1179. #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
  1180. #define RT5677_I2S_PD4_MASK (0x7 << 0)
  1181. #define RT5677_I2S_PD4_SFT 0
  1182. #define RT5677_I2S_PD4_1 (0x0 << 0)
  1183. #define RT5677_I2S_PD4_2 (0x1 << 0)
  1184. #define RT5677_I2S_PD4_3 (0x2 << 0)
  1185. #define RT5677_I2S_PD4_4 (0x3 << 0)
  1186. #define RT5677_I2S_PD4_6 (0x4 << 0)
  1187. #define RT5677_I2S_PD4_8 (0x5 << 0)
  1188. #define RT5677_I2S_PD4_12 (0x6 << 0)
  1189. #define RT5677_I2S_PD4_16 (0x7 << 0)
  1190. /* Clock Tree Control 2 (0x74) */
  1191. #define RT5677_I2S_PD5_MASK (0x7 << 12)
  1192. #define RT5677_I2S_PD5_SFT 12
  1193. #define RT5677_I2S_PD5_1 (0x0 << 12)
  1194. #define RT5677_I2S_PD5_2 (0x1 << 12)
  1195. #define RT5677_I2S_PD5_3 (0x2 << 12)
  1196. #define RT5677_I2S_PD5_4 (0x3 << 12)
  1197. #define RT5677_I2S_PD5_6 (0x4 << 12)
  1198. #define RT5677_I2S_PD5_8 (0x5 << 12)
  1199. #define RT5677_I2S_PD5_12 (0x6 << 12)
  1200. #define RT5677_I2S_PD5_16 (0x7 << 12)
  1201. #define RT5677_I2S_PD6_MASK (0x7 << 8)
  1202. #define RT5677_I2S_PD6_SFT 8
  1203. #define RT5677_I2S_PD6_1 (0x0 << 8)
  1204. #define RT5677_I2S_PD6_2 (0x1 << 8)
  1205. #define RT5677_I2S_PD6_3 (0x2 << 8)
  1206. #define RT5677_I2S_PD6_4 (0x3 << 8)
  1207. #define RT5677_I2S_PD6_6 (0x4 << 8)
  1208. #define RT5677_I2S_PD6_8 (0x5 << 8)
  1209. #define RT5677_I2S_PD6_12 (0x6 << 8)
  1210. #define RT5677_I2S_PD6_16 (0x7 << 8)
  1211. #define RT5677_I2S_PD7_MASK (0x7 << 4)
  1212. #define RT5677_I2S_PD7_SFT 4
  1213. #define RT5677_I2S_PD7_1 (0x0 << 4)
  1214. #define RT5677_I2S_PD7_2 (0x1 << 4)
  1215. #define RT5677_I2S_PD7_3 (0x2 << 4)
  1216. #define RT5677_I2S_PD7_4 (0x3 << 4)
  1217. #define RT5677_I2S_PD7_6 (0x4 << 4)
  1218. #define RT5677_I2S_PD7_8 (0x5 << 4)
  1219. #define RT5677_I2S_PD7_12 (0x6 << 4)
  1220. #define RT5677_I2S_PD7_16 (0x7 << 4)
  1221. #define RT5677_I2S_PD8_MASK (0x7 << 0)
  1222. #define RT5677_I2S_PD8_SFT 0
  1223. #define RT5677_I2S_PD8_1 (0x0 << 0)
  1224. #define RT5677_I2S_PD8_2 (0x1 << 0)
  1225. #define RT5677_I2S_PD8_3 (0x2 << 0)
  1226. #define RT5677_I2S_PD8_4 (0x3 << 0)
  1227. #define RT5677_I2S_PD8_6 (0x4 << 0)
  1228. #define RT5677_I2S_PD8_8 (0x5 << 0)
  1229. #define RT5677_I2S_PD8_12 (0x6 << 0)
  1230. #define RT5677_I2S_PD8_16 (0x7 << 0)
  1231. /* Clock Tree Control 3 (0x75) */
  1232. #define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
  1233. #define RT5677_DSP_ASRC_O_SFT 6
  1234. #define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
  1235. #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
  1236. #define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
  1237. #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
  1238. #define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
  1239. #define RT5677_DSP_ASRC_I_SFT 4
  1240. #define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
  1241. #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
  1242. #define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
  1243. #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
  1244. #define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
  1245. #define RT5677_DSP_BUS_PD_SFT 0
  1246. #define RT5677_DSP_BUS_PD_1 (0x0 << 0)
  1247. #define RT5677_DSP_BUS_PD_2 (0x1 << 0)
  1248. #define RT5677_DSP_BUS_PD_3 (0x2 << 0)
  1249. #define RT5677_DSP_BUS_PD_4 (0x3 << 0)
  1250. #define RT5677_DSP_BUS_PD_6 (0x4 << 0)
  1251. #define RT5677_DSP_BUS_PD_8 (0x5 << 0)
  1252. #define RT5677_DSP_BUS_PD_12 (0x6 << 0)
  1253. #define RT5677_DSP_BUS_PD_16 (0x7 << 0)
  1254. #define RT5677_PLL_INP_MAX 40000000
  1255. #define RT5677_PLL_INP_MIN 2048000
  1256. /* PLL M/N/K Code Control 1 (0x7a 0x7c) */
  1257. #define RT5677_PLL_N_MAX 0x1ff
  1258. #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
  1259. #define RT5677_PLL_N_SFT 7
  1260. #define RT5677_PLL_K_BP (0x1 << 5)
  1261. #define RT5677_PLL_K_BP_SFT 5
  1262. #define RT5677_PLL_K_MAX 0x1f
  1263. #define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
  1264. #define RT5677_PLL_K_SFT 0
  1265. /* PLL M/N/K Code Control 2 (0x7b 0x7d) */
  1266. #define RT5677_PLL_M_MAX 0xf
  1267. #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
  1268. #define RT5677_PLL_M_SFT 12
  1269. #define RT5677_PLL_M_BP (0x1 << 11)
  1270. #define RT5677_PLL_M_BP_SFT 11
  1271. #define RT5677_PLL_UPDATE_PLL1 (0x1 << 1)
  1272. #define RT5677_PLL_UPDATE_PLL1_SFT 1
  1273. /* Global Clock Control 1 (0x80) */
  1274. #define RT5677_SCLK_SRC_MASK (0x3 << 14)
  1275. #define RT5677_SCLK_SRC_SFT 14
  1276. #define RT5677_SCLK_SRC_MCLK (0x0 << 14)
  1277. #define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
  1278. #define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
  1279. #define RT5677_SCLK_SRC_SLIM (0x3 << 14)
  1280. #define RT5677_PLL1_SRC_MASK (0x7 << 11)
  1281. #define RT5677_PLL1_SRC_SFT 11
  1282. #define RT5677_PLL1_SRC_MCLK (0x0 << 11)
  1283. #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
  1284. #define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
  1285. #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
  1286. #define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
  1287. #define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
  1288. #define RT5677_PLL1_SRC_SLIM (0x6 << 11)
  1289. #define RT5677_MCLK_SRC_MASK (0x1 << 10)
  1290. #define RT5677_MCLK_SRC_SFT 10
  1291. #define RT5677_MCLK1_SRC (0x0 << 10)
  1292. #define RT5677_MCLK2_SRC (0x1 << 10)
  1293. #define RT5677_PLL1_PD_MASK (0x1 << 8)
  1294. #define RT5677_PLL1_PD_SFT 8
  1295. #define RT5677_PLL1_PD_1 (0x0 << 8)
  1296. #define RT5677_PLL1_PD_2 (0x1 << 8)
  1297. #define RT5677_DAC_OSR_MASK (0x3 << 6)
  1298. #define RT5677_DAC_OSR_SFT 6
  1299. #define RT5677_DAC_OSR_128 (0x0 << 6)
  1300. #define RT5677_DAC_OSR_64 (0x1 << 6)
  1301. #define RT5677_DAC_OSR_32 (0x2 << 6)
  1302. #define RT5677_ADC_OSR_MASK (0x3 << 4)
  1303. #define RT5677_ADC_OSR_SFT 4
  1304. #define RT5677_ADC_OSR_128 (0x0 << 4)
  1305. #define RT5677_ADC_OSR_64 (0x1 << 4)
  1306. #define RT5677_ADC_OSR_32 (0x2 << 4)
  1307. /* Global Clock Control 2 (0x81) */
  1308. #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
  1309. #define RT5677_PLL2_PR_SRC_SFT 15
  1310. #define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
  1311. #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
  1312. #define RT5677_PLL2_SRC_MASK (0x7 << 12)
  1313. #define RT5677_PLL2_SRC_SFT 12
  1314. #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
  1315. #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
  1316. #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
  1317. #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
  1318. #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
  1319. #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
  1320. #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
  1321. #define RT5677_DSP_ASRC_O_SRC (0x3 << 10)
  1322. #define RT5677_DSP_ASRC_O_SRC_SFT 10
  1323. #define RT5677_DSP_ASRC_O_MCLK (0x0 << 10)
  1324. #define RT5677_DSP_ASRC_O_PLL1 (0x1 << 10)
  1325. #define RT5677_DSP_ASRC_O_SLIM (0x2 << 10)
  1326. #define RT5677_DSP_ASRC_O_RCCLK (0x3 << 10)
  1327. #define RT5677_DSP_ASRC_I_SRC (0x3 << 8)
  1328. #define RT5677_DSP_ASRC_I_SRC_SFT 8
  1329. #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8)
  1330. #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)
  1331. #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8)
  1332. #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)
  1333. #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
  1334. #define RT5677_DSP_CLK_SRC_SFT 7
  1335. #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
  1336. #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
  1337. /* ASRC Control 3 (0x85) */
  1338. #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)
  1339. #define RT5677_DA_STO_CLK_SEL_SFT 12
  1340. #define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4)
  1341. #define RT5677_DA_MONO2L_CLK_SEL_SFT 4
  1342. #define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0)
  1343. #define RT5677_DA_MONO2R_CLK_SEL_SFT 0
  1344. /* ASRC Control 4 (0x86) */
  1345. #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)
  1346. #define RT5677_DA_MONO3L_CLK_SEL_SFT 12
  1347. #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)
  1348. #define RT5677_DA_MONO3R_CLK_SEL_SFT 8
  1349. #define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4)
  1350. #define RT5677_DA_MONO4L_CLK_SEL_SFT 4
  1351. #define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0)
  1352. #define RT5677_DA_MONO4R_CLK_SEL_SFT 0
  1353. /* ASRC Control 5 (0x87) */
  1354. #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)
  1355. #define RT5677_AD_STO1_CLK_SEL_SFT 12
  1356. #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)
  1357. #define RT5677_AD_STO2_CLK_SEL_SFT 8
  1358. #define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4)
  1359. #define RT5677_AD_STO3_CLK_SEL_SFT 4
  1360. #define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0)
  1361. #define RT5677_AD_STO4_CLK_SEL_SFT 0
  1362. /* ASRC Control 6 (0x88) */
  1363. #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)
  1364. #define RT5677_AD_MONOL_CLK_SEL_SFT 12
  1365. #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)
  1366. #define RT5677_AD_MONOR_CLK_SEL_SFT 8
  1367. /* ASRC Control 7 (0x89) */
  1368. #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)
  1369. #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12
  1370. #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
  1371. #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
  1372. /* ASRC Control 8 (0x8a) */
  1373. #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)
  1374. #define RT5677_I2S1_CLK_SEL_SFT 12
  1375. #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)
  1376. #define RT5677_I2S2_CLK_SEL_SFT 8
  1377. #define RT5677_I2S3_CLK_SEL_MASK (0xf << 4)
  1378. #define RT5677_I2S3_CLK_SEL_SFT 4
  1379. #define RT5677_I2S4_CLK_SEL_MASK (0xf)
  1380. #define RT5677_I2S4_CLK_SEL_SFT 0
  1381. /* VAD Function Control 1 (0x9c) */
  1382. #define RT5677_VAD_MIN_DUR_MASK (0x3 << 13)
  1383. #define RT5677_VAD_MIN_DUR_SFT 13
  1384. #define RT5677_VAD_ADPCM_BYPASS (1 << 10)
  1385. #define RT5677_VAD_ADPCM_BYPASS_BIT 10
  1386. #define RT5677_VAD_FG2ENC (1 << 9)
  1387. #define RT5677_VAD_FG2ENC_BIT 9
  1388. #define RT5677_VAD_BUF_OW (1 << 8)
  1389. #define RT5677_VAD_BUF_OW_BIT 8
  1390. #define RT5677_VAD_CLR_FLAG (1 << 7)
  1391. #define RT5677_VAD_CLR_FLAG_BIT 7
  1392. #define RT5677_VAD_BUF_POP (1 << 6)
  1393. #define RT5677_VAD_BUF_POP_BIT 6
  1394. #define RT5677_VAD_BUF_PUSH (1 << 5)
  1395. #define RT5677_VAD_BUF_PUSH_BIT 5
  1396. #define RT5677_VAD_DET_ENABLE (1 << 4)
  1397. #define RT5677_VAD_DET_ENABLE_BIT 4
  1398. #define RT5677_VAD_FUNC_ENABLE (1 << 3)
  1399. #define RT5677_VAD_FUNC_ENABLE_BIT 3
  1400. #define RT5677_VAD_FUNC_RESET (1 << 2)
  1401. #define RT5677_VAD_FUNC_RESET_BIT 2
  1402. /* VAD Function Control 4 (0x9f) */
  1403. #define RT5677_VAD_OUT_SRC_RATE_MASK (0x1 << 11)
  1404. #define RT5677_VAD_OUT_SRC_RATE_SFT 11
  1405. #define RT5677_VAD_OUT_SRC_MASK (0x1 << 10)
  1406. #define RT5677_VAD_OUT_SRC_SFT 10
  1407. #define RT5677_VAD_SRC_MASK (0x3 << 8)
  1408. #define RT5677_VAD_SRC_SFT 8
  1409. #define RT5677_VAD_LV_DIFF_MASK (0xff << 0)
  1410. #define RT5677_VAD_LV_DIFF_SFT 0
  1411. /* DSP InBound Control (0xa3) */
  1412. #define RT5677_IB01_SRC_MASK (0x7 << 12)
  1413. #define RT5677_IB01_SRC_SFT 12
  1414. #define RT5677_IB23_SRC_MASK (0x7 << 8)
  1415. #define RT5677_IB23_SRC_SFT 8
  1416. #define RT5677_IB45_SRC_MASK (0x7 << 4)
  1417. #define RT5677_IB45_SRC_SFT 4
  1418. #define RT5677_IB6_SRC_MASK (0x7 << 0)
  1419. #define RT5677_IB6_SRC_SFT 0
  1420. /* DSP InBound Control (0xa4) */
  1421. #define RT5677_IB7_SRC_MASK (0x7 << 12)
  1422. #define RT5677_IB7_SRC_SFT 12
  1423. #define RT5677_IB8_SRC_MASK (0x7 << 8)
  1424. #define RT5677_IB8_SRC_SFT 8
  1425. #define RT5677_IB9_SRC_MASK (0x7 << 4)
  1426. #define RT5677_IB9_SRC_SFT 4
  1427. /* DSP In/OutBound Control (0xa5) */
  1428. #define RT5677_SEL_SRC_OB23 (0x1 << 4)
  1429. #define RT5677_SEL_SRC_OB23_SFT 4
  1430. #define RT5677_SEL_SRC_OB01 (0x1 << 3)
  1431. #define RT5677_SEL_SRC_OB01_SFT 3
  1432. #define RT5677_SEL_SRC_IB45 (0x1 << 2)
  1433. #define RT5677_SEL_SRC_IB45_SFT 2
  1434. #define RT5677_SEL_SRC_IB23 (0x1 << 1)
  1435. #define RT5677_SEL_SRC_IB23_SFT 1
  1436. #define RT5677_SEL_SRC_IB01 (0x1 << 0)
  1437. #define RT5677_SEL_SRC_IB01_SFT 0
  1438. /* Jack Detect Control 1 (0xb5) */
  1439. #define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14)
  1440. #define RT5677_SEL_GPIO_JD1_SFT 14
  1441. #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
  1442. #define RT5677_SEL_GPIO_JD2_SFT 12
  1443. #define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10)
  1444. #define RT5677_SEL_GPIO_JD3_SFT 10
  1445. /* IRQ Control 1 (0xbd) */
  1446. #define RT5677_STA_GPIO_JD1 (0x1 << 15)
  1447. #define RT5677_STA_GPIO_JD1_SFT 15
  1448. #define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14)
  1449. #define RT5677_EN_IRQ_GPIO_JD1_SFT 14
  1450. #define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13)
  1451. #define RT5677_EN_GPIO_JD1_STICKY_SFT 13
  1452. #define RT5677_INV_GPIO_JD1 (0x1 << 12)
  1453. #define RT5677_INV_GPIO_JD1_SFT 12
  1454. #define RT5677_STA_GPIO_JD2 (0x1 << 11)
  1455. #define RT5677_STA_GPIO_JD2_SFT 11
  1456. #define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10)
  1457. #define RT5677_EN_IRQ_GPIO_JD2_SFT 10
  1458. #define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9)
  1459. #define RT5677_EN_GPIO_JD2_STICKY_SFT 9
  1460. #define RT5677_INV_GPIO_JD2 (0x1 << 8)
  1461. #define RT5677_INV_GPIO_JD2_SFT 8
  1462. #define RT5677_STA_MICBIAS1_OVCD (0x1 << 7)
  1463. #define RT5677_STA_MICBIAS1_OVCD_SFT 7
  1464. #define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6)
  1465. #define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT 6
  1466. #define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5)
  1467. #define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT 5
  1468. #define RT5677_INV_MICBIAS1_OVCD (0x1 << 4)
  1469. #define RT5677_INV_MICBIAS1_OVCD_SFT 4
  1470. #define RT5677_STA_GPIO_JD3 (0x1 << 3)
  1471. #define RT5677_STA_GPIO_JD3_SFT 3
  1472. #define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2)
  1473. #define RT5677_EN_IRQ_GPIO_JD3_SFT 2
  1474. #define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1)
  1475. #define RT5677_EN_GPIO_JD3_STICKY_SFT 1
  1476. #define RT5677_INV_GPIO_JD3 (0x1 << 0)
  1477. #define RT5677_INV_GPIO_JD3_SFT 0
  1478. /* GPIO status (0xbf) */
  1479. #define RT5677_GPIO6_STATUS_MASK (0x1 << 5)
  1480. #define RT5677_GPIO6_STATUS_SFT 5
  1481. #define RT5677_GPIO5_STATUS_MASK (0x1 << 4)
  1482. #define RT5677_GPIO5_STATUS_SFT 4
  1483. #define RT5677_GPIO4_STATUS_MASK (0x1 << 3)
  1484. #define RT5677_GPIO4_STATUS_SFT 3
  1485. #define RT5677_GPIO3_STATUS_MASK (0x1 << 2)
  1486. #define RT5677_GPIO3_STATUS_SFT 2
  1487. #define RT5677_GPIO2_STATUS_MASK (0x1 << 1)
  1488. #define RT5677_GPIO2_STATUS_SFT 1
  1489. #define RT5677_GPIO1_STATUS_MASK (0x1 << 0)
  1490. #define RT5677_GPIO1_STATUS_SFT 0
  1491. /* GPIO Control 1 (0xc0) */
  1492. #define RT5677_GPIO1_PIN_MASK (0x1 << 15)
  1493. #define RT5677_GPIO1_PIN_SFT 15
  1494. #define RT5677_GPIO1_PIN_GPIO1 (0x0 << 15)
  1495. #define RT5677_GPIO1_PIN_IRQ (0x1 << 15)
  1496. #define RT5677_IPTV_MODE_MASK (0x1 << 14)
  1497. #define RT5677_IPTV_MODE_SFT 14
  1498. #define RT5677_IPTV_MODE_GPIO (0x0 << 14)
  1499. #define RT5677_IPTV_MODE_IPTV (0x1 << 14)
  1500. #define RT5677_FUNC_MODE_MASK (0x1 << 13)
  1501. #define RT5677_FUNC_MODE_SFT 13
  1502. #define RT5677_FUNC_MODE_DMIC_GPIO (0x0 << 13)
  1503. #define RT5677_FUNC_MODE_JTAG (0x1 << 13)
  1504. /* GPIO Control 2 (0xc1) */
  1505. #define RT5677_GPIO5_DIR_MASK (0x1 << 14)
  1506. #define RT5677_GPIO5_DIR_SFT 14
  1507. #define RT5677_GPIO5_DIR_IN (0x0 << 14)
  1508. #define RT5677_GPIO5_DIR_OUT (0x1 << 14)
  1509. #define RT5677_GPIO5_OUT_MASK (0x1 << 13)
  1510. #define RT5677_GPIO5_OUT_SFT 13
  1511. #define RT5677_GPIO5_OUT_LO (0x0 << 13)
  1512. #define RT5677_GPIO5_OUT_HI (0x1 << 13)
  1513. #define RT5677_GPIO5_P_MASK (0x1 << 12)
  1514. #define RT5677_GPIO5_P_SFT 12
  1515. #define RT5677_GPIO5_P_NOR (0x0 << 12)
  1516. #define RT5677_GPIO5_P_INV (0x1 << 12)
  1517. #define RT5677_GPIO4_DIR_MASK (0x1 << 11)
  1518. #define RT5677_GPIO4_DIR_SFT 11
  1519. #define RT5677_GPIO4_DIR_IN (0x0 << 11)
  1520. #define RT5677_GPIO4_DIR_OUT (0x1 << 11)
  1521. #define RT5677_GPIO4_OUT_MASK (0x1 << 10)
  1522. #define RT5677_GPIO4_OUT_SFT 10
  1523. #define RT5677_GPIO4_OUT_LO (0x0 << 10)
  1524. #define RT5677_GPIO4_OUT_HI (0x1 << 10)
  1525. #define RT5677_GPIO4_P_MASK (0x1 << 9)
  1526. #define RT5677_GPIO4_P_SFT 9
  1527. #define RT5677_GPIO4_P_NOR (0x0 << 9)
  1528. #define RT5677_GPIO4_P_INV (0x1 << 9)
  1529. #define RT5677_GPIO3_DIR_MASK (0x1 << 8)
  1530. #define RT5677_GPIO3_DIR_SFT 8
  1531. #define RT5677_GPIO3_DIR_IN (0x0 << 8)
  1532. #define RT5677_GPIO3_DIR_OUT (0x1 << 8)
  1533. #define RT5677_GPIO3_OUT_MASK (0x1 << 7)
  1534. #define RT5677_GPIO3_OUT_SFT 7
  1535. #define RT5677_GPIO3_OUT_LO (0x0 << 7)
  1536. #define RT5677_GPIO3_OUT_HI (0x1 << 7)
  1537. #define RT5677_GPIO3_P_MASK (0x1 << 6)
  1538. #define RT5677_GPIO3_P_SFT 6
  1539. #define RT5677_GPIO3_P_NOR (0x0 << 6)
  1540. #define RT5677_GPIO3_P_INV (0x1 << 6)
  1541. #define RT5677_GPIO2_DIR_MASK (0x1 << 5)
  1542. #define RT5677_GPIO2_DIR_SFT 5
  1543. #define RT5677_GPIO2_DIR_IN (0x0 << 5)
  1544. #define RT5677_GPIO2_DIR_OUT (0x1 << 5)
  1545. #define RT5677_GPIO2_OUT_MASK (0x1 << 4)
  1546. #define RT5677_GPIO2_OUT_SFT 4
  1547. #define RT5677_GPIO2_OUT_LO (0x0 << 4)
  1548. #define RT5677_GPIO2_OUT_HI (0x1 << 4)
  1549. #define RT5677_GPIO2_P_MASK (0x1 << 3)
  1550. #define RT5677_GPIO2_P_SFT 3
  1551. #define RT5677_GPIO2_P_NOR (0x0 << 3)
  1552. #define RT5677_GPIO2_P_INV (0x1 << 3)
  1553. #define RT5677_GPIO1_DIR_MASK (0x1 << 2)
  1554. #define RT5677_GPIO1_DIR_SFT 2
  1555. #define RT5677_GPIO1_DIR_IN (0x0 << 2)
  1556. #define RT5677_GPIO1_DIR_OUT (0x1 << 2)
  1557. #define RT5677_GPIO1_OUT_MASK (0x1 << 1)
  1558. #define RT5677_GPIO1_OUT_SFT 1
  1559. #define RT5677_GPIO1_OUT_LO (0x0 << 1)
  1560. #define RT5677_GPIO1_OUT_HI (0x1 << 1)
  1561. #define RT5677_GPIO1_P_MASK (0x1 << 0)
  1562. #define RT5677_GPIO1_P_SFT 0
  1563. #define RT5677_GPIO1_P_NOR (0x0 << 0)
  1564. #define RT5677_GPIO1_P_INV (0x1 << 0)
  1565. /* GPIO Control 3 (0xc2) */
  1566. #define RT5677_GPIO6_DIR_MASK (0x1 << 2)
  1567. #define RT5677_GPIO6_DIR_SFT 2
  1568. #define RT5677_GPIO6_DIR_IN (0x0 << 2)
  1569. #define RT5677_GPIO6_DIR_OUT (0x1 << 2)
  1570. #define RT5677_GPIO6_OUT_MASK (0x1 << 1)
  1571. #define RT5677_GPIO6_OUT_SFT 1
  1572. #define RT5677_GPIO6_OUT_LO (0x0 << 1)
  1573. #define RT5677_GPIO6_OUT_HI (0x1 << 1)
  1574. #define RT5677_GPIO6_P_MASK (0x1 << 0)
  1575. #define RT5677_GPIO6_P_SFT 0
  1576. #define RT5677_GPIO6_P_NOR (0x0 << 0)
  1577. #define RT5677_GPIO6_P_INV (0x1 << 0)
  1578. /* General Control (0xfa) */
  1579. #define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3)
  1580. #define RT5677_IRQ_DEBOUNCE_SEL_MCLK (0x0 << 3)
  1581. #define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3)
  1582. #define RT5677_IRQ_DEBOUNCE_SEL_SLIM (0x2 << 3)
  1583. /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
  1584. #define RT5677_DSP_IB_01_H (0x1 << 15)
  1585. #define RT5677_DSP_IB_01_H_SFT 15
  1586. #define RT5677_DSP_IB_23_H (0x1 << 14)
  1587. #define RT5677_DSP_IB_23_H_SFT 14
  1588. #define RT5677_DSP_IB_45_H (0x1 << 13)
  1589. #define RT5677_DSP_IB_45_H_SFT 13
  1590. #define RT5677_DSP_IB_6_H (0x1 << 12)
  1591. #define RT5677_DSP_IB_6_H_SFT 12
  1592. #define RT5677_DSP_IB_7_H (0x1 << 11)
  1593. #define RT5677_DSP_IB_7_H_SFT 11
  1594. #define RT5677_DSP_IB_8_H (0x1 << 10)
  1595. #define RT5677_DSP_IB_8_H_SFT 10
  1596. #define RT5677_DSP_IB_9_H (0x1 << 9)
  1597. #define RT5677_DSP_IB_9_H_SFT 9
  1598. #define RT5677_DSP_IB_01_L (0x1 << 7)
  1599. #define RT5677_DSP_IB_01_L_SFT 7
  1600. #define RT5677_DSP_IB_23_L (0x1 << 6)
  1601. #define RT5677_DSP_IB_23_L_SFT 6
  1602. #define RT5677_DSP_IB_45_L (0x1 << 5)
  1603. #define RT5677_DSP_IB_45_L_SFT 5
  1604. #define RT5677_DSP_IB_6_L (0x1 << 4)
  1605. #define RT5677_DSP_IB_6_L_SFT 4
  1606. #define RT5677_DSP_IB_7_L (0x1 << 3)
  1607. #define RT5677_DSP_IB_7_L_SFT 3
  1608. #define RT5677_DSP_IB_8_L (0x1 << 2)
  1609. #define RT5677_DSP_IB_8_L_SFT 2
  1610. #define RT5677_DSP_IB_9_L (0x1 << 1)
  1611. #define RT5677_DSP_IB_9_L_SFT 1
  1612. /* General Control2 (0xfc)*/
  1613. #define RT5677_GPIO5_FUNC_MASK (0x1 << 9)
  1614. #define RT5677_GPIO5_FUNC_GPIO (0x0 << 9)
  1615. #define RT5677_GPIO5_FUNC_DMIC (0x1 << 9)
  1616. #define RT5677_FIRMWARE1 "rt5677_dsp_fw1.bin"
  1617. #define RT5677_FIRMWARE2 "rt5677_dsp_fw2.bin"
  1618. #define RT5677_DRV_NAME "rt5677"
  1619. /* System Clock Source */
  1620. enum {
  1621. RT5677_SCLK_S_MCLK,
  1622. RT5677_SCLK_S_PLL1,
  1623. RT5677_SCLK_S_RCCLK,
  1624. };
  1625. /* PLL1 Source */
  1626. enum {
  1627. RT5677_PLL1_S_MCLK,
  1628. RT5677_PLL1_S_BCLK1,
  1629. RT5677_PLL1_S_BCLK2,
  1630. RT5677_PLL1_S_BCLK3,
  1631. RT5677_PLL1_S_BCLK4,
  1632. };
  1633. enum {
  1634. RT5677_AIF1,
  1635. RT5677_AIF2,
  1636. RT5677_AIF3,
  1637. RT5677_AIF4,
  1638. RT5677_AIF5,
  1639. RT5677_AIFS,
  1640. RT5677_DSPBUFF,
  1641. };
  1642. enum {
  1643. RT5677_GPIO1,
  1644. RT5677_GPIO2,
  1645. RT5677_GPIO3,
  1646. RT5677_GPIO4,
  1647. RT5677_GPIO5,
  1648. RT5677_GPIO6,
  1649. RT5677_GPIO_NUM,
  1650. };
  1651. enum {
  1652. RT5677_IRQ_JD1,
  1653. RT5677_IRQ_JD2,
  1654. RT5677_IRQ_JD3,
  1655. RT5677_IRQ_NUM,
  1656. };
  1657. enum rt5677_type {
  1658. RT5677,
  1659. RT5676,
  1660. };
  1661. /* ASRC clock source selection */
  1662. enum {
  1663. RT5677_CLK_SEL_SYS,
  1664. RT5677_CLK_SEL_I2S1_ASRC,
  1665. RT5677_CLK_SEL_I2S2_ASRC,
  1666. RT5677_CLK_SEL_I2S3_ASRC,
  1667. RT5677_CLK_SEL_I2S4_ASRC,
  1668. RT5677_CLK_SEL_I2S5_ASRC,
  1669. RT5677_CLK_SEL_I2S6_ASRC,
  1670. RT5677_CLK_SEL_SYS2,
  1671. RT5677_CLK_SEL_SYS3,
  1672. RT5677_CLK_SEL_SYS4,
  1673. RT5677_CLK_SEL_SYS5,
  1674. RT5677_CLK_SEL_SYS6,
  1675. RT5677_CLK_SEL_SYS7,
  1676. };
  1677. /* filter mask */
  1678. enum {
  1679. RT5677_DA_STEREO_FILTER = 0x1,
  1680. RT5677_DA_MONO2_L_FILTER = (0x1 << 1),
  1681. RT5677_DA_MONO2_R_FILTER = (0x1 << 2),
  1682. RT5677_DA_MONO3_L_FILTER = (0x1 << 3),
  1683. RT5677_DA_MONO3_R_FILTER = (0x1 << 4),
  1684. RT5677_DA_MONO4_L_FILTER = (0x1 << 5),
  1685. RT5677_DA_MONO4_R_FILTER = (0x1 << 6),
  1686. RT5677_AD_STEREO1_FILTER = (0x1 << 7),
  1687. RT5677_AD_STEREO2_FILTER = (0x1 << 8),
  1688. RT5677_AD_STEREO3_FILTER = (0x1 << 9),
  1689. RT5677_AD_STEREO4_FILTER = (0x1 << 10),
  1690. RT5677_AD_MONO_L_FILTER = (0x1 << 11),
  1691. RT5677_AD_MONO_R_FILTER = (0x1 << 12),
  1692. RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
  1693. RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
  1694. RT5677_I2S1_SOURCE = (0x1 << 15),
  1695. RT5677_I2S2_SOURCE = (0x1 << 16),
  1696. RT5677_I2S3_SOURCE = (0x1 << 17),
  1697. RT5677_I2S4_SOURCE = (0x1 << 18),
  1698. };
  1699. enum rt5677_dmic2_clk {
  1700. RT5677_DMIC_CLK1 = 0,
  1701. RT5677_DMIC_CLK2 = 1,
  1702. };
  1703. struct rt5677_platform_data {
  1704. /* IN1/IN2/LOUT1/LOUT2/LOUT3 can optionally be differential */
  1705. bool in1_diff;
  1706. bool in2_diff;
  1707. bool lout1_diff;
  1708. bool lout2_diff;
  1709. bool lout3_diff;
  1710. /* DMIC2 clock source selection */
  1711. enum rt5677_dmic2_clk dmic2_clk_pin;
  1712. /* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */
  1713. u8 gpio_config[6];
  1714. /* jd1 can select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively */
  1715. unsigned int jd1_gpio;
  1716. /* jd2 and jd3 can select 0 ~ 3 as
  1717. OFF, GPIO4, GPIO5 and GPIO6 respectively */
  1718. unsigned int jd2_gpio;
  1719. unsigned int jd3_gpio;
  1720. /* Set MICBIAS1 VDD 1v8 or 3v3 */
  1721. bool micbias1_vdd_3v3;
  1722. };
  1723. struct rt5677_priv {
  1724. struct snd_soc_component *component;
  1725. struct device *dev;
  1726. struct rt5677_platform_data pdata;
  1727. struct regmap *regmap, *regmap_physical;
  1728. const struct firmware *fw1, *fw2;
  1729. struct mutex dsp_cmd_lock, dsp_pri_lock;
  1730. int sysclk;
  1731. int sysclk_src;
  1732. int lrck[RT5677_AIFS];
  1733. int bclk[RT5677_AIFS];
  1734. int master[RT5677_AIFS];
  1735. int pll_src;
  1736. int pll_in;
  1737. int pll_out;
  1738. struct gpio_desc *pow_ldo2; /* POW_LDO2 pin */
  1739. struct gpio_desc *reset_pin; /* RESET pin */
  1740. enum rt5677_type type;
  1741. #ifdef CONFIG_GPIOLIB
  1742. struct gpio_chip gpio_chip;
  1743. #endif
  1744. bool dsp_vad_en_request; /* DSP VAD enable/disable request */
  1745. bool dsp_vad_en; /* dsp_work parameter */
  1746. bool is_dsp_mode;
  1747. bool is_vref_slow;
  1748. struct delayed_work dsp_work;
  1749. /* Interrupt handling */
  1750. struct irq_domain *domain;
  1751. struct mutex irq_lock;
  1752. unsigned int irq_en;
  1753. struct delayed_work resume_irq_check;
  1754. int irq;
  1755. int (*set_dsp_vad)(struct snd_soc_component *component, bool on);
  1756. };
  1757. int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
  1758. unsigned int filter_mask, unsigned int clk_src);
  1759. #endif /* __RT5677_H__ */