rt5677.c 183 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5677.c -- RT5677 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Oder Chiou <oder_chiou@realtek.com>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/fs.h>
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/regmap.h>
  16. #include <linux/i2c.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/firmware.h>
  20. #include <linux/of_device.h>
  21. #include <linux/property.h>
  22. #include <linux/irq.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irqdomain.h>
  25. #include <linux/workqueue.h>
  26. #include <sound/core.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/soc.h>
  30. #include <sound/soc-dapm.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include "rl6231.h"
  34. #include "rt5677.h"
  35. #include "rt5677-spi.h"
  36. #define RT5677_DEVICE_ID 0x6327
  37. /* Register controlling boot vector */
  38. #define RT5677_DSP_BOOT_VECTOR 0x1801f090
  39. #define RT5677_MODEL_ADDR 0x5FFC9800
  40. #define RT5677_PR_RANGE_BASE (0xff + 1)
  41. #define RT5677_PR_SPACING 0x100
  42. #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
  43. static const struct regmap_range_cfg rt5677_ranges[] = {
  44. {
  45. .name = "PR",
  46. .range_min = RT5677_PR_BASE,
  47. .range_max = RT5677_PR_BASE + 0xfd,
  48. .selector_reg = RT5677_PRIV_INDEX,
  49. .selector_mask = 0xff,
  50. .selector_shift = 0x0,
  51. .window_start = RT5677_PRIV_DATA,
  52. .window_len = 0x1,
  53. },
  54. };
  55. static const struct reg_sequence init_list[] = {
  56. {RT5677_ASRC_12, 0x0018},
  57. {RT5677_PR_BASE + 0x3d, 0x364d},
  58. {RT5677_PR_BASE + 0x17, 0x4fc0},
  59. {RT5677_PR_BASE + 0x13, 0x0312},
  60. {RT5677_PR_BASE + 0x1e, 0x0000},
  61. {RT5677_PR_BASE + 0x12, 0x0eaa},
  62. {RT5677_PR_BASE + 0x14, 0x018a},
  63. {RT5677_PR_BASE + 0x15, 0x0490},
  64. {RT5677_PR_BASE + 0x38, 0x0f71},
  65. {RT5677_PR_BASE + 0x39, 0x0f71},
  66. };
  67. #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
  68. static const struct reg_default rt5677_reg[] = {
  69. {RT5677_RESET , 0x0000},
  70. {RT5677_LOUT1 , 0xa800},
  71. {RT5677_IN1 , 0x0000},
  72. {RT5677_MICBIAS , 0x0000},
  73. {RT5677_SLIMBUS_PARAM , 0x0000},
  74. {RT5677_SLIMBUS_RX , 0x0000},
  75. {RT5677_SLIMBUS_CTRL , 0x0000},
  76. {RT5677_SIDETONE_CTRL , 0x000b},
  77. {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
  78. {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
  79. {RT5677_DAC4_DIG_VOL , 0xafaf},
  80. {RT5677_DAC3_DIG_VOL , 0xafaf},
  81. {RT5677_DAC1_DIG_VOL , 0xafaf},
  82. {RT5677_DAC2_DIG_VOL , 0xafaf},
  83. {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
  84. {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
  85. {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
  86. {RT5677_STO1_2_ADC_BST , 0x0000},
  87. {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
  88. {RT5677_ADC_BST_CTRL2 , 0x0000},
  89. {RT5677_STO3_4_ADC_BST , 0x0000},
  90. {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
  91. {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
  92. {RT5677_STO4_ADC_MIXER , 0xd4c0},
  93. {RT5677_STO3_ADC_MIXER , 0xd4c0},
  94. {RT5677_STO2_ADC_MIXER , 0xd4c0},
  95. {RT5677_STO1_ADC_MIXER , 0xd4c0},
  96. {RT5677_MONO_ADC_MIXER , 0xd4d1},
  97. {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
  98. {RT5677_STO1_DAC_MIXER , 0xaaaa},
  99. {RT5677_MONO_DAC_MIXER , 0xaaaa},
  100. {RT5677_DD1_MIXER , 0xaaaa},
  101. {RT5677_DD2_MIXER , 0xaaaa},
  102. {RT5677_IF3_DATA , 0x0000},
  103. {RT5677_IF4_DATA , 0x0000},
  104. {RT5677_PDM_OUT_CTRL , 0x8888},
  105. {RT5677_PDM_DATA_CTRL1 , 0x0000},
  106. {RT5677_PDM_DATA_CTRL2 , 0x0000},
  107. {RT5677_PDM1_DATA_CTRL2 , 0x0000},
  108. {RT5677_PDM1_DATA_CTRL3 , 0x0000},
  109. {RT5677_PDM1_DATA_CTRL4 , 0x0000},
  110. {RT5677_PDM2_DATA_CTRL2 , 0x0000},
  111. {RT5677_PDM2_DATA_CTRL3 , 0x0000},
  112. {RT5677_PDM2_DATA_CTRL4 , 0x0000},
  113. {RT5677_TDM1_CTRL1 , 0x0300},
  114. {RT5677_TDM1_CTRL2 , 0x0000},
  115. {RT5677_TDM1_CTRL3 , 0x4000},
  116. {RT5677_TDM1_CTRL4 , 0x0123},
  117. {RT5677_TDM1_CTRL5 , 0x4567},
  118. {RT5677_TDM2_CTRL1 , 0x0300},
  119. {RT5677_TDM2_CTRL2 , 0x0000},
  120. {RT5677_TDM2_CTRL3 , 0x4000},
  121. {RT5677_TDM2_CTRL4 , 0x0123},
  122. {RT5677_TDM2_CTRL5 , 0x4567},
  123. {RT5677_I2C_MASTER_CTRL1 , 0x0001},
  124. {RT5677_I2C_MASTER_CTRL2 , 0x0000},
  125. {RT5677_I2C_MASTER_CTRL3 , 0x0000},
  126. {RT5677_I2C_MASTER_CTRL4 , 0x0000},
  127. {RT5677_I2C_MASTER_CTRL5 , 0x0000},
  128. {RT5677_I2C_MASTER_CTRL6 , 0x0000},
  129. {RT5677_I2C_MASTER_CTRL7 , 0x0000},
  130. {RT5677_I2C_MASTER_CTRL8 , 0x0000},
  131. {RT5677_DMIC_CTRL1 , 0x1505},
  132. {RT5677_DMIC_CTRL2 , 0x0055},
  133. {RT5677_HAP_GENE_CTRL1 , 0x0111},
  134. {RT5677_HAP_GENE_CTRL2 , 0x0064},
  135. {RT5677_HAP_GENE_CTRL3 , 0xef0e},
  136. {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
  137. {RT5677_HAP_GENE_CTRL5 , 0xef0e},
  138. {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
  139. {RT5677_HAP_GENE_CTRL7 , 0xef0e},
  140. {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
  141. {RT5677_HAP_GENE_CTRL9 , 0xf000},
  142. {RT5677_HAP_GENE_CTRL10 , 0x0000},
  143. {RT5677_PWR_DIG1 , 0x0000},
  144. {RT5677_PWR_DIG2 , 0x0000},
  145. {RT5677_PWR_ANLG1 , 0x0055},
  146. {RT5677_PWR_ANLG2 , 0x0000},
  147. {RT5677_PWR_DSP1 , 0x0001},
  148. {RT5677_PWR_DSP_ST , 0x0000},
  149. {RT5677_PWR_DSP2 , 0x0000},
  150. {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
  151. {RT5677_PRIV_INDEX , 0x0000},
  152. {RT5677_PRIV_DATA , 0x0000},
  153. {RT5677_I2S4_SDP , 0x8000},
  154. {RT5677_I2S1_SDP , 0x8000},
  155. {RT5677_I2S2_SDP , 0x8000},
  156. {RT5677_I2S3_SDP , 0x8000},
  157. {RT5677_CLK_TREE_CTRL1 , 0x1111},
  158. {RT5677_CLK_TREE_CTRL2 , 0x1111},
  159. {RT5677_CLK_TREE_CTRL3 , 0x0000},
  160. {RT5677_PLL1_CTRL1 , 0x0000},
  161. {RT5677_PLL1_CTRL2 , 0x0000},
  162. {RT5677_PLL2_CTRL1 , 0x0c60},
  163. {RT5677_PLL2_CTRL2 , 0x2000},
  164. {RT5677_GLB_CLK1 , 0x0000},
  165. {RT5677_GLB_CLK2 , 0x0000},
  166. {RT5677_ASRC_1 , 0x0000},
  167. {RT5677_ASRC_2 , 0x0000},
  168. {RT5677_ASRC_3 , 0x0000},
  169. {RT5677_ASRC_4 , 0x0000},
  170. {RT5677_ASRC_5 , 0x0000},
  171. {RT5677_ASRC_6 , 0x0000},
  172. {RT5677_ASRC_7 , 0x0000},
  173. {RT5677_ASRC_8 , 0x0000},
  174. {RT5677_ASRC_9 , 0x0000},
  175. {RT5677_ASRC_10 , 0x0000},
  176. {RT5677_ASRC_11 , 0x0000},
  177. {RT5677_ASRC_12 , 0x0018},
  178. {RT5677_ASRC_13 , 0x0000},
  179. {RT5677_ASRC_14 , 0x0000},
  180. {RT5677_ASRC_15 , 0x0000},
  181. {RT5677_ASRC_16 , 0x0000},
  182. {RT5677_ASRC_17 , 0x0000},
  183. {RT5677_ASRC_18 , 0x0000},
  184. {RT5677_ASRC_19 , 0x0000},
  185. {RT5677_ASRC_20 , 0x0000},
  186. {RT5677_ASRC_21 , 0x000c},
  187. {RT5677_ASRC_22 , 0x0000},
  188. {RT5677_ASRC_23 , 0x0000},
  189. {RT5677_VAD_CTRL1 , 0x2184},
  190. {RT5677_VAD_CTRL2 , 0x010a},
  191. {RT5677_VAD_CTRL3 , 0x0aea},
  192. {RT5677_VAD_CTRL4 , 0x000c},
  193. {RT5677_VAD_CTRL5 , 0x0000},
  194. {RT5677_DSP_INB_CTRL1 , 0x0000},
  195. {RT5677_DSP_INB_CTRL2 , 0x0000},
  196. {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
  197. {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
  198. {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
  199. {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
  200. {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
  201. {RT5677_ADC_EQ_CTRL1 , 0x6000},
  202. {RT5677_ADC_EQ_CTRL2 , 0x0000},
  203. {RT5677_EQ_CTRL1 , 0xc000},
  204. {RT5677_EQ_CTRL2 , 0x0000},
  205. {RT5677_EQ_CTRL3 , 0x0000},
  206. {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
  207. {RT5677_JD_CTRL1 , 0x0000},
  208. {RT5677_JD_CTRL2 , 0x0000},
  209. {RT5677_JD_CTRL3 , 0x0000},
  210. {RT5677_IRQ_CTRL1 , 0x0000},
  211. {RT5677_IRQ_CTRL2 , 0x0000},
  212. {RT5677_GPIO_ST , 0x0000},
  213. {RT5677_GPIO_CTRL1 , 0x0000},
  214. {RT5677_GPIO_CTRL2 , 0x0000},
  215. {RT5677_GPIO_CTRL3 , 0x0000},
  216. {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
  217. {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
  218. {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
  219. {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
  220. {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
  221. {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
  222. {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
  223. {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
  224. {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
  225. {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
  226. {RT5677_MB_DRC_CTRL1 , 0x0f20},
  227. {RT5677_DRC1_CTRL1 , 0x001f},
  228. {RT5677_DRC1_CTRL2 , 0x020c},
  229. {RT5677_DRC1_CTRL3 , 0x1f00},
  230. {RT5677_DRC1_CTRL4 , 0x0000},
  231. {RT5677_DRC1_CTRL5 , 0x0000},
  232. {RT5677_DRC1_CTRL6 , 0x0029},
  233. {RT5677_DRC2_CTRL1 , 0x001f},
  234. {RT5677_DRC2_CTRL2 , 0x020c},
  235. {RT5677_DRC2_CTRL3 , 0x1f00},
  236. {RT5677_DRC2_CTRL4 , 0x0000},
  237. {RT5677_DRC2_CTRL5 , 0x0000},
  238. {RT5677_DRC2_CTRL6 , 0x0029},
  239. {RT5677_DRC1_HL_CTRL1 , 0x8000},
  240. {RT5677_DRC1_HL_CTRL2 , 0x0200},
  241. {RT5677_DRC2_HL_CTRL1 , 0x8000},
  242. {RT5677_DRC2_HL_CTRL2 , 0x0200},
  243. {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
  244. {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
  245. {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
  246. {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
  247. {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
  248. {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
  249. {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
  250. {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
  251. {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
  252. {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
  253. {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
  254. {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
  255. {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
  256. {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
  257. {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
  258. {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
  259. {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
  260. {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
  261. {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
  262. {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
  263. {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
  264. {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
  265. {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
  266. {RT5677_DIG_MISC , 0x0000},
  267. {RT5677_GEN_CTRL1 , 0x0000},
  268. {RT5677_GEN_CTRL2 , 0x0000},
  269. {RT5677_VENDOR_ID , 0x0000},
  270. {RT5677_VENDOR_ID1 , 0x10ec},
  271. {RT5677_VENDOR_ID2 , 0x6327},
  272. };
  273. static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
  274. {
  275. int i;
  276. for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
  277. if (reg >= rt5677_ranges[i].range_min &&
  278. reg <= rt5677_ranges[i].range_max) {
  279. return true;
  280. }
  281. }
  282. switch (reg) {
  283. case RT5677_RESET:
  284. case RT5677_SLIMBUS_PARAM:
  285. case RT5677_PDM_DATA_CTRL1:
  286. case RT5677_PDM_DATA_CTRL2:
  287. case RT5677_PDM1_DATA_CTRL4:
  288. case RT5677_PDM2_DATA_CTRL4:
  289. case RT5677_I2C_MASTER_CTRL1:
  290. case RT5677_I2C_MASTER_CTRL7:
  291. case RT5677_I2C_MASTER_CTRL8:
  292. case RT5677_HAP_GENE_CTRL2:
  293. case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
  294. case RT5677_PWR_DSP_ST:
  295. case RT5677_PRIV_DATA:
  296. case RT5677_ASRC_22:
  297. case RT5677_ASRC_23:
  298. case RT5677_VAD_CTRL5:
  299. case RT5677_ADC_EQ_CTRL1:
  300. case RT5677_EQ_CTRL1:
  301. case RT5677_IRQ_CTRL1:
  302. case RT5677_IRQ_CTRL2:
  303. case RT5677_GPIO_ST:
  304. case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */
  305. case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */
  306. case RT5677_DSP_INB1_SRC_CTRL4:
  307. case RT5677_DSP_INB2_SRC_CTRL4:
  308. case RT5677_DSP_INB3_SRC_CTRL4:
  309. case RT5677_DSP_OUTB1_SRC_CTRL4:
  310. case RT5677_DSP_OUTB2_SRC_CTRL4:
  311. case RT5677_VENDOR_ID:
  312. case RT5677_VENDOR_ID1:
  313. case RT5677_VENDOR_ID2:
  314. return true;
  315. default:
  316. return false;
  317. }
  318. }
  319. static bool rt5677_readable_register(struct device *dev, unsigned int reg)
  320. {
  321. int i;
  322. for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
  323. if (reg >= rt5677_ranges[i].range_min &&
  324. reg <= rt5677_ranges[i].range_max) {
  325. return true;
  326. }
  327. }
  328. switch (reg) {
  329. case RT5677_RESET:
  330. case RT5677_LOUT1:
  331. case RT5677_IN1:
  332. case RT5677_MICBIAS:
  333. case RT5677_SLIMBUS_PARAM:
  334. case RT5677_SLIMBUS_RX:
  335. case RT5677_SLIMBUS_CTRL:
  336. case RT5677_SIDETONE_CTRL:
  337. case RT5677_ANA_DAC1_2_3_SRC:
  338. case RT5677_IF_DSP_DAC3_4_MIXER:
  339. case RT5677_DAC4_DIG_VOL:
  340. case RT5677_DAC3_DIG_VOL:
  341. case RT5677_DAC1_DIG_VOL:
  342. case RT5677_DAC2_DIG_VOL:
  343. case RT5677_IF_DSP_DAC2_MIXER:
  344. case RT5677_STO1_ADC_DIG_VOL:
  345. case RT5677_MONO_ADC_DIG_VOL:
  346. case RT5677_STO1_2_ADC_BST:
  347. case RT5677_STO2_ADC_DIG_VOL:
  348. case RT5677_ADC_BST_CTRL2:
  349. case RT5677_STO3_4_ADC_BST:
  350. case RT5677_STO3_ADC_DIG_VOL:
  351. case RT5677_STO4_ADC_DIG_VOL:
  352. case RT5677_STO4_ADC_MIXER:
  353. case RT5677_STO3_ADC_MIXER:
  354. case RT5677_STO2_ADC_MIXER:
  355. case RT5677_STO1_ADC_MIXER:
  356. case RT5677_MONO_ADC_MIXER:
  357. case RT5677_ADC_IF_DSP_DAC1_MIXER:
  358. case RT5677_STO1_DAC_MIXER:
  359. case RT5677_MONO_DAC_MIXER:
  360. case RT5677_DD1_MIXER:
  361. case RT5677_DD2_MIXER:
  362. case RT5677_IF3_DATA:
  363. case RT5677_IF4_DATA:
  364. case RT5677_PDM_OUT_CTRL:
  365. case RT5677_PDM_DATA_CTRL1:
  366. case RT5677_PDM_DATA_CTRL2:
  367. case RT5677_PDM1_DATA_CTRL2:
  368. case RT5677_PDM1_DATA_CTRL3:
  369. case RT5677_PDM1_DATA_CTRL4:
  370. case RT5677_PDM2_DATA_CTRL2:
  371. case RT5677_PDM2_DATA_CTRL3:
  372. case RT5677_PDM2_DATA_CTRL4:
  373. case RT5677_TDM1_CTRL1:
  374. case RT5677_TDM1_CTRL2:
  375. case RT5677_TDM1_CTRL3:
  376. case RT5677_TDM1_CTRL4:
  377. case RT5677_TDM1_CTRL5:
  378. case RT5677_TDM2_CTRL1:
  379. case RT5677_TDM2_CTRL2:
  380. case RT5677_TDM2_CTRL3:
  381. case RT5677_TDM2_CTRL4:
  382. case RT5677_TDM2_CTRL5:
  383. case RT5677_I2C_MASTER_CTRL1:
  384. case RT5677_I2C_MASTER_CTRL2:
  385. case RT5677_I2C_MASTER_CTRL3:
  386. case RT5677_I2C_MASTER_CTRL4:
  387. case RT5677_I2C_MASTER_CTRL5:
  388. case RT5677_I2C_MASTER_CTRL6:
  389. case RT5677_I2C_MASTER_CTRL7:
  390. case RT5677_I2C_MASTER_CTRL8:
  391. case RT5677_DMIC_CTRL1:
  392. case RT5677_DMIC_CTRL2:
  393. case RT5677_HAP_GENE_CTRL1:
  394. case RT5677_HAP_GENE_CTRL2:
  395. case RT5677_HAP_GENE_CTRL3:
  396. case RT5677_HAP_GENE_CTRL4:
  397. case RT5677_HAP_GENE_CTRL5:
  398. case RT5677_HAP_GENE_CTRL6:
  399. case RT5677_HAP_GENE_CTRL7:
  400. case RT5677_HAP_GENE_CTRL8:
  401. case RT5677_HAP_GENE_CTRL9:
  402. case RT5677_HAP_GENE_CTRL10:
  403. case RT5677_PWR_DIG1:
  404. case RT5677_PWR_DIG2:
  405. case RT5677_PWR_ANLG1:
  406. case RT5677_PWR_ANLG2:
  407. case RT5677_PWR_DSP1:
  408. case RT5677_PWR_DSP_ST:
  409. case RT5677_PWR_DSP2:
  410. case RT5677_ADC_DAC_HPF_CTRL1:
  411. case RT5677_PRIV_INDEX:
  412. case RT5677_PRIV_DATA:
  413. case RT5677_I2S4_SDP:
  414. case RT5677_I2S1_SDP:
  415. case RT5677_I2S2_SDP:
  416. case RT5677_I2S3_SDP:
  417. case RT5677_CLK_TREE_CTRL1:
  418. case RT5677_CLK_TREE_CTRL2:
  419. case RT5677_CLK_TREE_CTRL3:
  420. case RT5677_PLL1_CTRL1:
  421. case RT5677_PLL1_CTRL2:
  422. case RT5677_PLL2_CTRL1:
  423. case RT5677_PLL2_CTRL2:
  424. case RT5677_GLB_CLK1:
  425. case RT5677_GLB_CLK2:
  426. case RT5677_ASRC_1:
  427. case RT5677_ASRC_2:
  428. case RT5677_ASRC_3:
  429. case RT5677_ASRC_4:
  430. case RT5677_ASRC_5:
  431. case RT5677_ASRC_6:
  432. case RT5677_ASRC_7:
  433. case RT5677_ASRC_8:
  434. case RT5677_ASRC_9:
  435. case RT5677_ASRC_10:
  436. case RT5677_ASRC_11:
  437. case RT5677_ASRC_12:
  438. case RT5677_ASRC_13:
  439. case RT5677_ASRC_14:
  440. case RT5677_ASRC_15:
  441. case RT5677_ASRC_16:
  442. case RT5677_ASRC_17:
  443. case RT5677_ASRC_18:
  444. case RT5677_ASRC_19:
  445. case RT5677_ASRC_20:
  446. case RT5677_ASRC_21:
  447. case RT5677_ASRC_22:
  448. case RT5677_ASRC_23:
  449. case RT5677_VAD_CTRL1:
  450. case RT5677_VAD_CTRL2:
  451. case RT5677_VAD_CTRL3:
  452. case RT5677_VAD_CTRL4:
  453. case RT5677_VAD_CTRL5:
  454. case RT5677_DSP_INB_CTRL1:
  455. case RT5677_DSP_INB_CTRL2:
  456. case RT5677_DSP_IN_OUTB_CTRL:
  457. case RT5677_DSP_OUTB0_1_DIG_VOL:
  458. case RT5677_DSP_OUTB2_3_DIG_VOL:
  459. case RT5677_DSP_OUTB4_5_DIG_VOL:
  460. case RT5677_DSP_OUTB6_7_DIG_VOL:
  461. case RT5677_ADC_EQ_CTRL1:
  462. case RT5677_ADC_EQ_CTRL2:
  463. case RT5677_EQ_CTRL1:
  464. case RT5677_EQ_CTRL2:
  465. case RT5677_EQ_CTRL3:
  466. case RT5677_SOFT_VOL_ZERO_CROSS1:
  467. case RT5677_JD_CTRL1:
  468. case RT5677_JD_CTRL2:
  469. case RT5677_JD_CTRL3:
  470. case RT5677_IRQ_CTRL1:
  471. case RT5677_IRQ_CTRL2:
  472. case RT5677_GPIO_ST:
  473. case RT5677_GPIO_CTRL1:
  474. case RT5677_GPIO_CTRL2:
  475. case RT5677_GPIO_CTRL3:
  476. case RT5677_STO1_ADC_HI_FILTER1:
  477. case RT5677_STO1_ADC_HI_FILTER2:
  478. case RT5677_MONO_ADC_HI_FILTER1:
  479. case RT5677_MONO_ADC_HI_FILTER2:
  480. case RT5677_STO2_ADC_HI_FILTER1:
  481. case RT5677_STO2_ADC_HI_FILTER2:
  482. case RT5677_STO3_ADC_HI_FILTER1:
  483. case RT5677_STO3_ADC_HI_FILTER2:
  484. case RT5677_STO4_ADC_HI_FILTER1:
  485. case RT5677_STO4_ADC_HI_FILTER2:
  486. case RT5677_MB_DRC_CTRL1:
  487. case RT5677_DRC1_CTRL1:
  488. case RT5677_DRC1_CTRL2:
  489. case RT5677_DRC1_CTRL3:
  490. case RT5677_DRC1_CTRL4:
  491. case RT5677_DRC1_CTRL5:
  492. case RT5677_DRC1_CTRL6:
  493. case RT5677_DRC2_CTRL1:
  494. case RT5677_DRC2_CTRL2:
  495. case RT5677_DRC2_CTRL3:
  496. case RT5677_DRC2_CTRL4:
  497. case RT5677_DRC2_CTRL5:
  498. case RT5677_DRC2_CTRL6:
  499. case RT5677_DRC1_HL_CTRL1:
  500. case RT5677_DRC1_HL_CTRL2:
  501. case RT5677_DRC2_HL_CTRL1:
  502. case RT5677_DRC2_HL_CTRL2:
  503. case RT5677_DSP_INB1_SRC_CTRL1:
  504. case RT5677_DSP_INB1_SRC_CTRL2:
  505. case RT5677_DSP_INB1_SRC_CTRL3:
  506. case RT5677_DSP_INB1_SRC_CTRL4:
  507. case RT5677_DSP_INB2_SRC_CTRL1:
  508. case RT5677_DSP_INB2_SRC_CTRL2:
  509. case RT5677_DSP_INB2_SRC_CTRL3:
  510. case RT5677_DSP_INB2_SRC_CTRL4:
  511. case RT5677_DSP_INB3_SRC_CTRL1:
  512. case RT5677_DSP_INB3_SRC_CTRL2:
  513. case RT5677_DSP_INB3_SRC_CTRL3:
  514. case RT5677_DSP_INB3_SRC_CTRL4:
  515. case RT5677_DSP_OUTB1_SRC_CTRL1:
  516. case RT5677_DSP_OUTB1_SRC_CTRL2:
  517. case RT5677_DSP_OUTB1_SRC_CTRL3:
  518. case RT5677_DSP_OUTB1_SRC_CTRL4:
  519. case RT5677_DSP_OUTB2_SRC_CTRL1:
  520. case RT5677_DSP_OUTB2_SRC_CTRL2:
  521. case RT5677_DSP_OUTB2_SRC_CTRL3:
  522. case RT5677_DSP_OUTB2_SRC_CTRL4:
  523. case RT5677_DSP_OUTB_0123_MIXER_CTRL:
  524. case RT5677_DSP_OUTB_45_MIXER_CTRL:
  525. case RT5677_DSP_OUTB_67_MIXER_CTRL:
  526. case RT5677_DIG_MISC:
  527. case RT5677_GEN_CTRL1:
  528. case RT5677_GEN_CTRL2:
  529. case RT5677_VENDOR_ID:
  530. case RT5677_VENDOR_ID1:
  531. case RT5677_VENDOR_ID2:
  532. return true;
  533. default:
  534. return false;
  535. }
  536. }
  537. /**
  538. * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
  539. * @rt5677: Private Data.
  540. * @addr: Address index.
  541. * @value: Address data.
  542. * @opcode: opcode value
  543. *
  544. * Returns 0 for success or negative error code.
  545. */
  546. static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
  547. unsigned int addr, unsigned int value, unsigned int opcode)
  548. {
  549. struct snd_soc_component *component = rt5677->component;
  550. int ret;
  551. mutex_lock(&rt5677->dsp_cmd_lock);
  552. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
  553. addr >> 16);
  554. if (ret < 0) {
  555. dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
  556. goto err;
  557. }
  558. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
  559. addr & 0xffff);
  560. if (ret < 0) {
  561. dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
  562. goto err;
  563. }
  564. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
  565. value >> 16);
  566. if (ret < 0) {
  567. dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
  568. goto err;
  569. }
  570. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
  571. value & 0xffff);
  572. if (ret < 0) {
  573. dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
  574. goto err;
  575. }
  576. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
  577. opcode);
  578. if (ret < 0) {
  579. dev_err(component->dev, "Failed to set op code value: %d\n", ret);
  580. goto err;
  581. }
  582. err:
  583. mutex_unlock(&rt5677->dsp_cmd_lock);
  584. return ret;
  585. }
  586. /**
  587. * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
  588. * @rt5677: Private Data.
  589. * @addr: Address index.
  590. * @value: Address data.
  591. *
  592. *
  593. * Returns 0 for success or negative error code.
  594. */
  595. static int rt5677_dsp_mode_i2c_read_addr(
  596. struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
  597. {
  598. struct snd_soc_component *component = rt5677->component;
  599. int ret;
  600. unsigned int msb, lsb;
  601. mutex_lock(&rt5677->dsp_cmd_lock);
  602. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
  603. addr >> 16);
  604. if (ret < 0) {
  605. dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
  606. goto err;
  607. }
  608. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
  609. addr & 0xffff);
  610. if (ret < 0) {
  611. dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
  612. goto err;
  613. }
  614. ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
  615. 0x0002);
  616. if (ret < 0) {
  617. dev_err(component->dev, "Failed to set op code value: %d\n", ret);
  618. goto err;
  619. }
  620. regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
  621. regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
  622. *value = (msb << 16) | lsb;
  623. err:
  624. mutex_unlock(&rt5677->dsp_cmd_lock);
  625. return ret;
  626. }
  627. /**
  628. * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
  629. * @rt5677: Private Data.
  630. * @reg: Register index.
  631. * @value: Register data.
  632. *
  633. *
  634. * Returns 0 for success or negative error code.
  635. */
  636. static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
  637. unsigned int reg, unsigned int value)
  638. {
  639. return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
  640. value, 0x0001);
  641. }
  642. /**
  643. * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
  644. * @rt5677: Private Data
  645. * @reg: Register index.
  646. * @value: Register data.
  647. *
  648. *
  649. * Returns 0 for success or negative error code.
  650. */
  651. static int rt5677_dsp_mode_i2c_read(
  652. struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
  653. {
  654. int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
  655. value);
  656. *value &= 0xffff;
  657. return ret;
  658. }
  659. static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
  660. {
  661. if (on) {
  662. regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
  663. RT5677_PWR_DSP, RT5677_PWR_DSP);
  664. rt5677->is_dsp_mode = true;
  665. } else {
  666. regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
  667. RT5677_PWR_DSP, 0x0);
  668. rt5677->is_dsp_mode = false;
  669. }
  670. }
  671. static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
  672. {
  673. struct snd_soc_dapm_context *dapm =
  674. snd_soc_component_get_dapm(rt5677->component);
  675. /* Force dapm to sync before we enable the
  676. * DSP to prevent write corruption
  677. */
  678. snd_soc_dapm_sync(dapm);
  679. /* DMIC1 power = enabled
  680. * DMIC CLK = 256 * fs / 12
  681. */
  682. regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
  683. RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT);
  684. /* I2S pre divide 2 = /6 (clk_sys2) */
  685. regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
  686. RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6);
  687. /* DSP Clock = MCLK1 (bypassed PLL2) */
  688. regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
  689. RT5677_DSP_CLK_SRC_BYPASS);
  690. /* SAD Threshold1 */
  691. regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
  692. /* SAD Threshold2 */
  693. regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
  694. /* SAD Sample Rate Converter = Up 6 (8K to 48K)
  695. * SAD Output Sample Rate = Same as I2S
  696. * SAD Threshold3
  697. */
  698. regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
  699. RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK |
  700. RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT);
  701. /* Minimum frame level within a pre-determined duration = 32 frames
  702. * Bypass ADPCM Encoder/Decoder = Bypass ADPCM
  703. * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable
  704. * SAD Buffer Over-Writing = enable
  705. * SAD Buffer Pop Mode Control = disable
  706. * SAD Buffer Push Mode Control = enable
  707. * SAD Detector Control = enable
  708. * SAD Function Control = enable
  709. * SAD Function Reset = normal
  710. */
  711. regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
  712. RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE |
  713. RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH |
  714. RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC |
  715. RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT);
  716. /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
  717. * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save
  718. * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack
  719. * Detection" for more info.
  720. */
  721. /* Private register, no doc */
  722. regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
  723. 0x0f00, 0x0100);
  724. /* LDO2 output = 1.2V
  725. * LDO1 output = 1.2V (LDO_IN = 1.8V)
  726. */
  727. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
  728. RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
  729. 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT);
  730. /* Codec core power = power on
  731. * LDO1 power = power on
  732. */
  733. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  734. RT5677_PWR_CORE | RT5677_PWR_LDO1,
  735. RT5677_PWR_CORE | RT5677_PWR_LDO1);
  736. /* Isolation for DCVDD4 = normal (set during probe)
  737. * Isolation for DCVDD2 = normal (set during probe)
  738. * Isolation for DSP = normal
  739. * Isolation for Band 0~7 = disable
  740. * Isolation for InBound 4~10 and OutBound 4~10 = disable
  741. */
  742. regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
  743. RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO |
  744. RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO |
  745. RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO |
  746. RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO |
  747. RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO |
  748. RT5677_PWR_MLT_ISO);
  749. /* System Band 0~7 = power on
  750. * InBound 4~10 and OutBound 4~10 = power on
  751. * DSP = power on
  752. * DSP CPU = stop (will be set to "run" after firmware loaded)
  753. */
  754. regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
  755. RT5677_PWR_SR7 | RT5677_PWR_SR6 |
  756. RT5677_PWR_SR5 | RT5677_PWR_SR4 |
  757. RT5677_PWR_SR3 | RT5677_PWR_SR2 |
  758. RT5677_PWR_SR1 | RT5677_PWR_SR0 |
  759. RT5677_PWR_MLT | RT5677_PWR_DSP |
  760. RT5677_PWR_DSP_CPU);
  761. return 0;
  762. }
  763. static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
  764. unsigned int len)
  765. {
  766. struct snd_soc_component *component = rt5677->component;
  767. Elf32_Ehdr *elf_hdr;
  768. Elf32_Phdr *pr_hdr;
  769. Elf32_Half i;
  770. int ret = 0;
  771. if (!buf || (len < sizeof(Elf32_Ehdr)))
  772. return -ENOMEM;
  773. elf_hdr = (Elf32_Ehdr *)buf;
  774. #ifndef EM_XTENSA
  775. #define EM_XTENSA 94
  776. #endif
  777. if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
  778. dev_err(component->dev, "Wrong ELF header prefix\n");
  779. if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
  780. dev_err(component->dev, "Wrong Elf header size\n");
  781. if (elf_hdr->e_machine != EM_XTENSA)
  782. dev_err(component->dev, "Wrong DSP code file\n");
  783. if (len < elf_hdr->e_phoff)
  784. return -ENOMEM;
  785. pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
  786. for (i = 0; i < elf_hdr->e_phnum; i++) {
  787. /* TODO: handle p_memsz != p_filesz */
  788. if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
  789. dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
  790. pr_hdr->p_filesz, pr_hdr->p_paddr);
  791. ret = rt5677_spi_write(pr_hdr->p_paddr,
  792. buf + pr_hdr->p_offset,
  793. pr_hdr->p_filesz);
  794. if (ret)
  795. dev_err(component->dev, "Load firmware failed %d\n",
  796. ret);
  797. }
  798. pr_hdr++;
  799. }
  800. return ret;
  801. }
  802. static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
  803. {
  804. const struct firmware *fwp;
  805. struct device *dev = rt5677->component->dev;
  806. int ret = 0;
  807. /* Load dsp firmware from rt5677_elf_vad file */
  808. ret = request_firmware(&fwp, "rt5677_elf_vad", dev);
  809. if (ret) {
  810. dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret);
  811. return ret;
  812. }
  813. dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);
  814. ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
  815. release_firmware(fwp);
  816. return ret;
  817. }
  818. static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
  819. {
  820. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  821. rt5677->dsp_vad_en_request = on;
  822. rt5677->dsp_vad_en = on;
  823. if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
  824. return -ENXIO;
  825. schedule_delayed_work(&rt5677->dsp_work, 0);
  826. return 0;
  827. }
  828. static void rt5677_dsp_work(struct work_struct *work)
  829. {
  830. struct rt5677_priv *rt5677 =
  831. container_of(work, struct rt5677_priv, dsp_work.work);
  832. static bool activity;
  833. bool enable = rt5677->dsp_vad_en;
  834. int i, val;
  835. dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
  836. enable, activity);
  837. if (enable && !activity) {
  838. activity = true;
  839. /* Before a hotword is detected, GPIO1 pin is configured as IRQ
  840. * output so that jack detect works. When a hotword is detected,
  841. * the DSP firmware configures the GPIO1 pin as GPIO1 and
  842. * drives a 1. rt5677_irq() is called after a rising edge on
  843. * the GPIO1 pin, due to either jack detect event or hotword
  844. * event, or both. All possible events are checked and handled
  845. * in rt5677_irq() where GPIO1 pin is configured back to IRQ
  846. * output if a hotword is detected.
  847. */
  848. rt5677_set_vad_source(rt5677);
  849. rt5677_set_dsp_mode(rt5677, true);
  850. #define RT5677_BOOT_RETRY 20
  851. for (i = 0; i < RT5677_BOOT_RETRY; i++) {
  852. regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
  853. if (val == 0x3ff)
  854. break;
  855. udelay(500);
  856. }
  857. if (i == RT5677_BOOT_RETRY && val != 0x3ff) {
  858. dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
  859. return;
  860. }
  861. /* Boot the firmware from IRAM instead of SRAM0. */
  862. rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
  863. 0x0009, 0x0003);
  864. rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
  865. 0x0019, 0x0003);
  866. rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
  867. 0x0009, 0x0003);
  868. rt5677_load_dsp_from_file(rt5677);
  869. /* Set DSP CPU to Run */
  870. regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
  871. RT5677_PWR_DSP_CPU, 0x0);
  872. } else if (!enable && activity) {
  873. activity = false;
  874. /* Don't turn off the DSP while handling irqs */
  875. mutex_lock(&rt5677->irq_lock);
  876. /* Set DSP CPU to Stop */
  877. regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
  878. RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU);
  879. rt5677_set_dsp_mode(rt5677, false);
  880. /* Disable and clear VAD interrupt */
  881. regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
  882. /* Set GPIO1 pin back to be IRQ output for jack detect */
  883. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
  884. RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
  885. mutex_unlock(&rt5677->irq_lock);
  886. }
  887. }
  888. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
  889. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
  890. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  891. static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
  892. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  893. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  894. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  895. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  896. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  897. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  898. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  899. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  900. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  901. );
  902. static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  906. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  907. ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
  908. return 0;
  909. }
  910. static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  914. rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
  915. return 0;
  916. }
  917. static const struct snd_kcontrol_new rt5677_snd_controls[] = {
  918. /* OUTPUT Control */
  919. SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
  920. RT5677_LOUT1_L_MUTE_SFT, 1, 1),
  921. SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
  922. RT5677_LOUT2_L_MUTE_SFT, 1, 1),
  923. SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
  924. RT5677_LOUT3_L_MUTE_SFT, 1, 1),
  925. /* DAC Digital Volume */
  926. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
  927. RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
  928. SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
  929. RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
  930. SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
  931. RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
  932. SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
  933. RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
  934. /* IN1/IN2 Control */
  935. SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
  936. SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
  937. /* ADC Digital Volume Control */
  938. SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
  939. RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
  940. SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
  941. RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
  942. SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
  943. RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
  944. SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
  945. RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
  946. SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
  947. RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
  948. SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
  949. RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
  950. adc_vol_tlv),
  951. SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
  952. RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
  953. adc_vol_tlv),
  954. SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
  955. RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
  956. adc_vol_tlv),
  957. SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
  958. RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
  959. adc_vol_tlv),
  960. SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
  961. RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
  962. adc_vol_tlv),
  963. /* Sidetone Control */
  964. SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
  965. RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
  966. /* ADC Boost Volume Control */
  967. SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
  968. RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
  969. adc_bst_tlv),
  970. SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
  971. RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
  972. adc_bst_tlv),
  973. SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
  974. RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
  975. adc_bst_tlv),
  976. SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
  977. RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
  978. adc_bst_tlv),
  979. SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
  980. RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
  981. adc_bst_tlv),
  982. SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
  983. rt5677_dsp_vad_get, rt5677_dsp_vad_put),
  984. };
  985. /**
  986. * set_dmic_clk - Set parameter of dmic.
  987. *
  988. * @w: DAPM widget.
  989. * @kcontrol: The kcontrol of this widget.
  990. * @event: Event id.
  991. *
  992. * Choose dmic clock between 1MHz and 3MHz.
  993. * It is better for clock to approximate 3MHz.
  994. */
  995. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  996. struct snd_kcontrol *kcontrol, int event)
  997. {
  998. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  999. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1000. int idx, rate;
  1001. rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
  1002. RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
  1003. idx = rl6231_calc_dmic_clk(rate);
  1004. if (idx < 0)
  1005. dev_err(component->dev, "Failed to set DMIC clock\n");
  1006. else
  1007. regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
  1008. RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
  1009. return idx;
  1010. }
  1011. static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  1012. struct snd_soc_dapm_widget *sink)
  1013. {
  1014. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  1015. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1016. unsigned int val;
  1017. regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
  1018. val &= RT5677_SCLK_SRC_MASK;
  1019. if (val == RT5677_SCLK_SRC_PLL1)
  1020. return 1;
  1021. else
  1022. return 0;
  1023. }
  1024. static int is_using_asrc(struct snd_soc_dapm_widget *source,
  1025. struct snd_soc_dapm_widget *sink)
  1026. {
  1027. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  1028. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1029. unsigned int reg, shift, val;
  1030. if (source->reg == RT5677_ASRC_1) {
  1031. switch (source->shift) {
  1032. case 12:
  1033. reg = RT5677_ASRC_4;
  1034. shift = 0;
  1035. break;
  1036. case 13:
  1037. reg = RT5677_ASRC_4;
  1038. shift = 4;
  1039. break;
  1040. case 14:
  1041. reg = RT5677_ASRC_4;
  1042. shift = 8;
  1043. break;
  1044. case 15:
  1045. reg = RT5677_ASRC_4;
  1046. shift = 12;
  1047. break;
  1048. default:
  1049. return 0;
  1050. }
  1051. } else {
  1052. switch (source->shift) {
  1053. case 0:
  1054. reg = RT5677_ASRC_6;
  1055. shift = 8;
  1056. break;
  1057. case 1:
  1058. reg = RT5677_ASRC_6;
  1059. shift = 12;
  1060. break;
  1061. case 2:
  1062. reg = RT5677_ASRC_5;
  1063. shift = 0;
  1064. break;
  1065. case 3:
  1066. reg = RT5677_ASRC_5;
  1067. shift = 4;
  1068. break;
  1069. case 4:
  1070. reg = RT5677_ASRC_5;
  1071. shift = 8;
  1072. break;
  1073. case 5:
  1074. reg = RT5677_ASRC_5;
  1075. shift = 12;
  1076. break;
  1077. case 12:
  1078. reg = RT5677_ASRC_3;
  1079. shift = 0;
  1080. break;
  1081. case 13:
  1082. reg = RT5677_ASRC_3;
  1083. shift = 4;
  1084. break;
  1085. case 14:
  1086. reg = RT5677_ASRC_3;
  1087. shift = 12;
  1088. break;
  1089. default:
  1090. return 0;
  1091. }
  1092. }
  1093. regmap_read(rt5677->regmap, reg, &val);
  1094. val = (val >> shift) & 0xf;
  1095. switch (val) {
  1096. case 1 ... 6:
  1097. return 1;
  1098. default:
  1099. return 0;
  1100. }
  1101. }
  1102. static int can_use_asrc(struct snd_soc_dapm_widget *source,
  1103. struct snd_soc_dapm_widget *sink)
  1104. {
  1105. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  1106. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1107. if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
  1108. return 1;
  1109. return 0;
  1110. }
  1111. /**
  1112. * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
  1113. * @component: SoC audio component device.
  1114. * @filter_mask: mask of filters.
  1115. * @clk_src: clock source
  1116. *
  1117. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
  1118. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  1119. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  1120. * ASRC function will track i2s clock and generate a corresponding system clock
  1121. * for codec. This function provides an API to select the clock source for a
  1122. * set of filters specified by the mask. And the codec driver will turn on ASRC
  1123. * for these filters if ASRC is selected as their clock source.
  1124. */
  1125. int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
  1126. unsigned int filter_mask, unsigned int clk_src)
  1127. {
  1128. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1129. unsigned int asrc3_mask = 0, asrc3_value = 0;
  1130. unsigned int asrc4_mask = 0, asrc4_value = 0;
  1131. unsigned int asrc5_mask = 0, asrc5_value = 0;
  1132. unsigned int asrc6_mask = 0, asrc6_value = 0;
  1133. unsigned int asrc7_mask = 0, asrc7_value = 0;
  1134. unsigned int asrc8_mask = 0, asrc8_value = 0;
  1135. switch (clk_src) {
  1136. case RT5677_CLK_SEL_SYS:
  1137. case RT5677_CLK_SEL_I2S1_ASRC:
  1138. case RT5677_CLK_SEL_I2S2_ASRC:
  1139. case RT5677_CLK_SEL_I2S3_ASRC:
  1140. case RT5677_CLK_SEL_I2S4_ASRC:
  1141. case RT5677_CLK_SEL_I2S5_ASRC:
  1142. case RT5677_CLK_SEL_I2S6_ASRC:
  1143. case RT5677_CLK_SEL_SYS2:
  1144. case RT5677_CLK_SEL_SYS3:
  1145. case RT5677_CLK_SEL_SYS4:
  1146. case RT5677_CLK_SEL_SYS5:
  1147. case RT5677_CLK_SEL_SYS6:
  1148. case RT5677_CLK_SEL_SYS7:
  1149. break;
  1150. default:
  1151. return -EINVAL;
  1152. }
  1153. /* ASRC 3 */
  1154. if (filter_mask & RT5677_DA_STEREO_FILTER) {
  1155. asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
  1156. asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
  1157. | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
  1158. }
  1159. if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
  1160. asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
  1161. asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
  1162. | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
  1163. }
  1164. if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
  1165. asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
  1166. asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
  1167. | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
  1168. }
  1169. if (asrc3_mask)
  1170. regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
  1171. asrc3_value);
  1172. /* ASRC 4 */
  1173. if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
  1174. asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
  1175. asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
  1176. | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
  1177. }
  1178. if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
  1179. asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
  1180. asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
  1181. | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
  1182. }
  1183. if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
  1184. asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
  1185. asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
  1186. | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
  1187. }
  1188. if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
  1189. asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
  1190. asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
  1191. | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
  1192. }
  1193. if (asrc4_mask)
  1194. regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
  1195. asrc4_value);
  1196. /* ASRC 5 */
  1197. if (filter_mask & RT5677_AD_STEREO1_FILTER) {
  1198. asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
  1199. asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
  1200. | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
  1201. }
  1202. if (filter_mask & RT5677_AD_STEREO2_FILTER) {
  1203. asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
  1204. asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
  1205. | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
  1206. }
  1207. if (filter_mask & RT5677_AD_STEREO3_FILTER) {
  1208. asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
  1209. asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
  1210. | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
  1211. }
  1212. if (filter_mask & RT5677_AD_STEREO4_FILTER) {
  1213. asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
  1214. asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
  1215. | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
  1216. }
  1217. if (asrc5_mask)
  1218. regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
  1219. asrc5_value);
  1220. /* ASRC 6 */
  1221. if (filter_mask & RT5677_AD_MONO_L_FILTER) {
  1222. asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
  1223. asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
  1224. | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
  1225. }
  1226. if (filter_mask & RT5677_AD_MONO_R_FILTER) {
  1227. asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
  1228. asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
  1229. | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
  1230. }
  1231. if (asrc6_mask)
  1232. regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
  1233. asrc6_value);
  1234. /* ASRC 7 */
  1235. if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
  1236. asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
  1237. asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
  1238. | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
  1239. }
  1240. if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
  1241. asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
  1242. asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
  1243. | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
  1244. }
  1245. if (asrc7_mask)
  1246. regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
  1247. asrc7_value);
  1248. /* ASRC 8 */
  1249. if (filter_mask & RT5677_I2S1_SOURCE) {
  1250. asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
  1251. asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
  1252. | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
  1253. }
  1254. if (filter_mask & RT5677_I2S2_SOURCE) {
  1255. asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
  1256. asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
  1257. | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
  1258. }
  1259. if (filter_mask & RT5677_I2S3_SOURCE) {
  1260. asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
  1261. asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
  1262. | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
  1263. }
  1264. if (filter_mask & RT5677_I2S4_SOURCE) {
  1265. asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
  1266. asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
  1267. | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
  1268. }
  1269. if (asrc8_mask)
  1270. regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
  1271. asrc8_value);
  1272. return 0;
  1273. }
  1274. EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
  1275. static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
  1276. struct snd_soc_dapm_widget *sink)
  1277. {
  1278. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  1279. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  1280. unsigned int asrc_setting;
  1281. switch (source->shift) {
  1282. case 11:
  1283. regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
  1284. asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
  1285. RT5677_AD_STO1_CLK_SEL_SFT;
  1286. break;
  1287. case 10:
  1288. regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
  1289. asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
  1290. RT5677_AD_STO2_CLK_SEL_SFT;
  1291. break;
  1292. case 9:
  1293. regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
  1294. asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
  1295. RT5677_AD_STO3_CLK_SEL_SFT;
  1296. break;
  1297. case 8:
  1298. regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
  1299. asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
  1300. RT5677_AD_STO4_CLK_SEL_SFT;
  1301. break;
  1302. case 7:
  1303. regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
  1304. asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
  1305. RT5677_AD_MONOL_CLK_SEL_SFT;
  1306. break;
  1307. case 6:
  1308. regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
  1309. asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
  1310. RT5677_AD_MONOR_CLK_SEL_SFT;
  1311. break;
  1312. default:
  1313. return 0;
  1314. }
  1315. if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
  1316. asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
  1317. return 1;
  1318. return 0;
  1319. }
  1320. /* Digital Mixer */
  1321. static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
  1322. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
  1323. RT5677_M_STO1_ADC_L1_SFT, 1, 1),
  1324. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
  1325. RT5677_M_STO1_ADC_L2_SFT, 1, 1),
  1326. };
  1327. static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
  1328. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
  1329. RT5677_M_STO1_ADC_R1_SFT, 1, 1),
  1330. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
  1331. RT5677_M_STO1_ADC_R2_SFT, 1, 1),
  1332. };
  1333. static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
  1334. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
  1335. RT5677_M_STO2_ADC_L1_SFT, 1, 1),
  1336. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
  1337. RT5677_M_STO2_ADC_L2_SFT, 1, 1),
  1338. };
  1339. static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
  1340. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
  1341. RT5677_M_STO2_ADC_R1_SFT, 1, 1),
  1342. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
  1343. RT5677_M_STO2_ADC_R2_SFT, 1, 1),
  1344. };
  1345. static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
  1346. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
  1347. RT5677_M_STO3_ADC_L1_SFT, 1, 1),
  1348. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
  1349. RT5677_M_STO3_ADC_L2_SFT, 1, 1),
  1350. };
  1351. static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
  1352. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
  1353. RT5677_M_STO3_ADC_R1_SFT, 1, 1),
  1354. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
  1355. RT5677_M_STO3_ADC_R2_SFT, 1, 1),
  1356. };
  1357. static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
  1358. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
  1359. RT5677_M_STO4_ADC_L1_SFT, 1, 1),
  1360. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
  1361. RT5677_M_STO4_ADC_L2_SFT, 1, 1),
  1362. };
  1363. static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
  1364. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
  1365. RT5677_M_STO4_ADC_R1_SFT, 1, 1),
  1366. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
  1367. RT5677_M_STO4_ADC_R2_SFT, 1, 1),
  1368. };
  1369. static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
  1370. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
  1371. RT5677_M_MONO_ADC_L1_SFT, 1, 1),
  1372. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
  1373. RT5677_M_MONO_ADC_L2_SFT, 1, 1),
  1374. };
  1375. static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
  1376. SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
  1377. RT5677_M_MONO_ADC_R1_SFT, 1, 1),
  1378. SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
  1379. RT5677_M_MONO_ADC_R2_SFT, 1, 1),
  1380. };
  1381. static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
  1382. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
  1383. RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
  1384. SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
  1385. RT5677_M_DAC1_L_SFT, 1, 1),
  1386. };
  1387. static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
  1388. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
  1389. RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
  1390. SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
  1391. RT5677_M_DAC1_R_SFT, 1, 1),
  1392. };
  1393. static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
  1394. SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
  1395. RT5677_M_ST_DAC1_L_SFT, 1, 1),
  1396. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
  1397. RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
  1398. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
  1399. RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
  1400. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
  1401. RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
  1402. };
  1403. static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
  1404. SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
  1405. RT5677_M_ST_DAC1_R_SFT, 1, 1),
  1406. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
  1407. RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
  1408. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
  1409. RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
  1410. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
  1411. RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
  1412. };
  1413. static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
  1414. SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
  1415. RT5677_M_ST_DAC2_L_SFT, 1, 1),
  1416. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
  1417. RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
  1418. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
  1419. RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
  1420. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
  1421. RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
  1422. };
  1423. static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
  1424. SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
  1425. RT5677_M_ST_DAC2_R_SFT, 1, 1),
  1426. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
  1427. RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
  1428. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
  1429. RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
  1430. SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
  1431. RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
  1432. };
  1433. static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
  1434. SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
  1435. RT5677_M_STO_L_DD1_L_SFT, 1, 1),
  1436. SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
  1437. RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
  1438. SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
  1439. RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
  1440. SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
  1441. RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
  1442. };
  1443. static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
  1444. SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
  1445. RT5677_M_STO_R_DD1_R_SFT, 1, 1),
  1446. SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
  1447. RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
  1448. SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
  1449. RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
  1450. SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
  1451. RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
  1452. };
  1453. static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
  1454. SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
  1455. RT5677_M_STO_L_DD2_L_SFT, 1, 1),
  1456. SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
  1457. RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
  1458. SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
  1459. RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
  1460. SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
  1461. RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
  1462. };
  1463. static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
  1464. SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
  1465. RT5677_M_STO_R_DD2_R_SFT, 1, 1),
  1466. SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
  1467. RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
  1468. SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
  1469. RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
  1470. SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
  1471. RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
  1472. };
  1473. static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
  1474. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1475. RT5677_DSP_IB_01_H_SFT, 1, 1),
  1476. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1477. RT5677_DSP_IB_23_H_SFT, 1, 1),
  1478. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1479. RT5677_DSP_IB_45_H_SFT, 1, 1),
  1480. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1481. RT5677_DSP_IB_6_H_SFT, 1, 1),
  1482. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1483. RT5677_DSP_IB_7_H_SFT, 1, 1),
  1484. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1485. RT5677_DSP_IB_8_H_SFT, 1, 1),
  1486. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1487. RT5677_DSP_IB_9_H_SFT, 1, 1),
  1488. };
  1489. static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
  1490. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1491. RT5677_DSP_IB_01_L_SFT, 1, 1),
  1492. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1493. RT5677_DSP_IB_23_L_SFT, 1, 1),
  1494. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1495. RT5677_DSP_IB_45_L_SFT, 1, 1),
  1496. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1497. RT5677_DSP_IB_6_L_SFT, 1, 1),
  1498. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1499. RT5677_DSP_IB_7_L_SFT, 1, 1),
  1500. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1501. RT5677_DSP_IB_8_L_SFT, 1, 1),
  1502. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
  1503. RT5677_DSP_IB_9_L_SFT, 1, 1),
  1504. };
  1505. static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
  1506. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1507. RT5677_DSP_IB_01_H_SFT, 1, 1),
  1508. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1509. RT5677_DSP_IB_23_H_SFT, 1, 1),
  1510. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1511. RT5677_DSP_IB_45_H_SFT, 1, 1),
  1512. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1513. RT5677_DSP_IB_6_H_SFT, 1, 1),
  1514. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1515. RT5677_DSP_IB_7_H_SFT, 1, 1),
  1516. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1517. RT5677_DSP_IB_8_H_SFT, 1, 1),
  1518. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1519. RT5677_DSP_IB_9_H_SFT, 1, 1),
  1520. };
  1521. static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
  1522. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1523. RT5677_DSP_IB_01_L_SFT, 1, 1),
  1524. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1525. RT5677_DSP_IB_23_L_SFT, 1, 1),
  1526. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1527. RT5677_DSP_IB_45_L_SFT, 1, 1),
  1528. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1529. RT5677_DSP_IB_6_L_SFT, 1, 1),
  1530. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1531. RT5677_DSP_IB_7_L_SFT, 1, 1),
  1532. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1533. RT5677_DSP_IB_8_L_SFT, 1, 1),
  1534. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
  1535. RT5677_DSP_IB_9_L_SFT, 1, 1),
  1536. };
  1537. static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
  1538. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1539. RT5677_DSP_IB_01_H_SFT, 1, 1),
  1540. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1541. RT5677_DSP_IB_23_H_SFT, 1, 1),
  1542. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1543. RT5677_DSP_IB_45_H_SFT, 1, 1),
  1544. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1545. RT5677_DSP_IB_6_H_SFT, 1, 1),
  1546. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1547. RT5677_DSP_IB_7_H_SFT, 1, 1),
  1548. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1549. RT5677_DSP_IB_8_H_SFT, 1, 1),
  1550. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1551. RT5677_DSP_IB_9_H_SFT, 1, 1),
  1552. };
  1553. static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
  1554. SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1555. RT5677_DSP_IB_01_L_SFT, 1, 1),
  1556. SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1557. RT5677_DSP_IB_23_L_SFT, 1, 1),
  1558. SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1559. RT5677_DSP_IB_45_L_SFT, 1, 1),
  1560. SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1561. RT5677_DSP_IB_6_L_SFT, 1, 1),
  1562. SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1563. RT5677_DSP_IB_7_L_SFT, 1, 1),
  1564. SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1565. RT5677_DSP_IB_8_L_SFT, 1, 1),
  1566. SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
  1567. RT5677_DSP_IB_9_L_SFT, 1, 1),
  1568. };
  1569. /* Mux */
  1570. /* DAC1 L/R Source */ /* MX-29 [10:8] */
  1571. static const char * const rt5677_dac1_src[] = {
  1572. "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
  1573. "OB 01"
  1574. };
  1575. static SOC_ENUM_SINGLE_DECL(
  1576. rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
  1577. RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
  1578. static const struct snd_kcontrol_new rt5677_dac1_mux =
  1579. SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
  1580. /* ADDA1 L/R Source */ /* MX-29 [1:0] */
  1581. static const char * const rt5677_adda1_src[] = {
  1582. "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
  1583. };
  1584. static SOC_ENUM_SINGLE_DECL(
  1585. rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
  1586. RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
  1587. static const struct snd_kcontrol_new rt5677_adda1_mux =
  1588. SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
  1589. /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
  1590. static const char * const rt5677_dac2l_src[] = {
  1591. "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
  1592. "OB 2",
  1593. };
  1594. static SOC_ENUM_SINGLE_DECL(
  1595. rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
  1596. RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
  1597. static const struct snd_kcontrol_new rt5677_dac2_l_mux =
  1598. SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
  1599. static const char * const rt5677_dac2r_src[] = {
  1600. "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
  1601. "OB 3", "Haptic Generator", "VAD ADC"
  1602. };
  1603. static SOC_ENUM_SINGLE_DECL(
  1604. rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
  1605. RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
  1606. static const struct snd_kcontrol_new rt5677_dac2_r_mux =
  1607. SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
  1608. /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
  1609. static const char * const rt5677_dac3l_src[] = {
  1610. "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
  1611. "SLB DAC 4", "OB 4"
  1612. };
  1613. static SOC_ENUM_SINGLE_DECL(
  1614. rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
  1615. RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
  1616. static const struct snd_kcontrol_new rt5677_dac3_l_mux =
  1617. SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
  1618. static const char * const rt5677_dac3r_src[] = {
  1619. "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
  1620. "SLB DAC 5", "OB 5"
  1621. };
  1622. static SOC_ENUM_SINGLE_DECL(
  1623. rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
  1624. RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
  1625. static const struct snd_kcontrol_new rt5677_dac3_r_mux =
  1626. SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
  1627. /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
  1628. static const char * const rt5677_dac4l_src[] = {
  1629. "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
  1630. "SLB DAC 6", "OB 6"
  1631. };
  1632. static SOC_ENUM_SINGLE_DECL(
  1633. rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
  1634. RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
  1635. static const struct snd_kcontrol_new rt5677_dac4_l_mux =
  1636. SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
  1637. static const char * const rt5677_dac4r_src[] = {
  1638. "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
  1639. "SLB DAC 7", "OB 7"
  1640. };
  1641. static SOC_ENUM_SINGLE_DECL(
  1642. rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
  1643. RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
  1644. static const struct snd_kcontrol_new rt5677_dac4_r_mux =
  1645. SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
  1646. /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
  1647. static const char * const rt5677_iob_bypass_src[] = {
  1648. "Bypass", "Pass SRC"
  1649. };
  1650. static SOC_ENUM_SINGLE_DECL(
  1651. rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
  1652. RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
  1653. static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
  1654. SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
  1655. static SOC_ENUM_SINGLE_DECL(
  1656. rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
  1657. RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
  1658. static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
  1659. SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
  1660. static SOC_ENUM_SINGLE_DECL(
  1661. rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
  1662. RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
  1663. static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
  1664. SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
  1665. static SOC_ENUM_SINGLE_DECL(
  1666. rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
  1667. RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
  1668. static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
  1669. SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
  1670. static SOC_ENUM_SINGLE_DECL(
  1671. rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
  1672. RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
  1673. static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
  1674. SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
  1675. /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
  1676. static const char * const rt5677_stereo_adc2_src[] = {
  1677. "DD MIX1", "DMIC", "Stereo DAC MIX"
  1678. };
  1679. static SOC_ENUM_SINGLE_DECL(
  1680. rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
  1681. RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
  1682. static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
  1683. SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
  1684. static SOC_ENUM_SINGLE_DECL(
  1685. rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
  1686. RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
  1687. static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
  1688. SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
  1689. static SOC_ENUM_SINGLE_DECL(
  1690. rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
  1691. RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
  1692. static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
  1693. SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
  1694. /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
  1695. static const char * const rt5677_dmic_src[] = {
  1696. "DMIC1", "DMIC2", "DMIC3", "DMIC4"
  1697. };
  1698. static SOC_ENUM_SINGLE_DECL(
  1699. rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
  1700. RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
  1701. static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
  1702. SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
  1703. static SOC_ENUM_SINGLE_DECL(
  1704. rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
  1705. RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
  1706. static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
  1707. SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
  1708. static SOC_ENUM_SINGLE_DECL(
  1709. rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
  1710. RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
  1711. static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
  1712. SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
  1713. static SOC_ENUM_SINGLE_DECL(
  1714. rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
  1715. RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
  1716. static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
  1717. SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
  1718. static SOC_ENUM_SINGLE_DECL(
  1719. rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
  1720. RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
  1721. static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
  1722. SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
  1723. static SOC_ENUM_SINGLE_DECL(
  1724. rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
  1725. RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
  1726. static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
  1727. SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
  1728. /* Stereo2 ADC Source */ /* MX-26 [0] */
  1729. static const char * const rt5677_stereo2_adc_lr_src[] = {
  1730. "L", "LR"
  1731. };
  1732. static SOC_ENUM_SINGLE_DECL(
  1733. rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
  1734. RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
  1735. static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
  1736. SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
  1737. /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
  1738. static const char * const rt5677_stereo_adc1_src[] = {
  1739. "DD MIX1", "ADC1/2", "Stereo DAC MIX"
  1740. };
  1741. static SOC_ENUM_SINGLE_DECL(
  1742. rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
  1743. RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
  1744. static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
  1745. SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
  1746. static SOC_ENUM_SINGLE_DECL(
  1747. rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
  1748. RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
  1749. static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
  1750. SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
  1751. static SOC_ENUM_SINGLE_DECL(
  1752. rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
  1753. RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
  1754. static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
  1755. SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
  1756. /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
  1757. static const char * const rt5677_mono_adc2_l_src[] = {
  1758. "DD MIX1L", "DMIC", "MONO DAC MIXL"
  1759. };
  1760. static SOC_ENUM_SINGLE_DECL(
  1761. rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
  1762. RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
  1763. static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
  1764. SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
  1765. /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
  1766. static const char * const rt5677_mono_adc1_l_src[] = {
  1767. "DD MIX1L", "ADC1", "MONO DAC MIXL"
  1768. };
  1769. static SOC_ENUM_SINGLE_DECL(
  1770. rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
  1771. RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
  1772. static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
  1773. SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
  1774. /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
  1775. static const char * const rt5677_mono_adc2_r_src[] = {
  1776. "DD MIX1R", "DMIC", "MONO DAC MIXR"
  1777. };
  1778. static SOC_ENUM_SINGLE_DECL(
  1779. rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
  1780. RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
  1781. static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
  1782. SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
  1783. /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
  1784. static const char * const rt5677_mono_adc1_r_src[] = {
  1785. "DD MIX1R", "ADC2", "MONO DAC MIXR"
  1786. };
  1787. static SOC_ENUM_SINGLE_DECL(
  1788. rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
  1789. RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
  1790. static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
  1791. SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
  1792. /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
  1793. static const char * const rt5677_stereo4_adc2_src[] = {
  1794. "DD MIX1", "DMIC", "DD MIX2"
  1795. };
  1796. static SOC_ENUM_SINGLE_DECL(
  1797. rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
  1798. RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
  1799. static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
  1800. SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
  1801. /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
  1802. static const char * const rt5677_stereo4_adc1_src[] = {
  1803. "DD MIX1", "ADC1/2", "DD MIX2"
  1804. };
  1805. static SOC_ENUM_SINGLE_DECL(
  1806. rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
  1807. RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
  1808. static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
  1809. SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
  1810. /* InBound0/1 Source */ /* MX-A3 [14:12] */
  1811. static const char * const rt5677_inbound01_src[] = {
  1812. "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
  1813. "VAD ADC/DAC1 FS"
  1814. };
  1815. static SOC_ENUM_SINGLE_DECL(
  1816. rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
  1817. RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
  1818. static const struct snd_kcontrol_new rt5677_ib01_src_mux =
  1819. SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
  1820. /* InBound2/3 Source */ /* MX-A3 [10:8] */
  1821. static const char * const rt5677_inbound23_src[] = {
  1822. "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
  1823. "DAC1 FS", "IF4 DAC"
  1824. };
  1825. static SOC_ENUM_SINGLE_DECL(
  1826. rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
  1827. RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
  1828. static const struct snd_kcontrol_new rt5677_ib23_src_mux =
  1829. SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
  1830. /* InBound4/5 Source */ /* MX-A3 [6:4] */
  1831. static const char * const rt5677_inbound45_src[] = {
  1832. "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
  1833. "IF3 DAC"
  1834. };
  1835. static SOC_ENUM_SINGLE_DECL(
  1836. rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
  1837. RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
  1838. static const struct snd_kcontrol_new rt5677_ib45_src_mux =
  1839. SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
  1840. /* InBound6 Source */ /* MX-A3 [2:0] */
  1841. static const char * const rt5677_inbound6_src[] = {
  1842. "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
  1843. "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
  1844. };
  1845. static SOC_ENUM_SINGLE_DECL(
  1846. rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
  1847. RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
  1848. static const struct snd_kcontrol_new rt5677_ib6_src_mux =
  1849. SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
  1850. /* InBound7 Source */ /* MX-A4 [14:12] */
  1851. static const char * const rt5677_inbound7_src[] = {
  1852. "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
  1853. "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
  1854. };
  1855. static SOC_ENUM_SINGLE_DECL(
  1856. rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
  1857. RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
  1858. static const struct snd_kcontrol_new rt5677_ib7_src_mux =
  1859. SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
  1860. /* InBound8 Source */ /* MX-A4 [10:8] */
  1861. static const char * const rt5677_inbound8_src[] = {
  1862. "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
  1863. "MONO ADC MIX L", "DACL1 FS"
  1864. };
  1865. static SOC_ENUM_SINGLE_DECL(
  1866. rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
  1867. RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
  1868. static const struct snd_kcontrol_new rt5677_ib8_src_mux =
  1869. SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
  1870. /* InBound9 Source */ /* MX-A4 [6:4] */
  1871. static const char * const rt5677_inbound9_src[] = {
  1872. "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
  1873. "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
  1874. };
  1875. static SOC_ENUM_SINGLE_DECL(
  1876. rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
  1877. RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
  1878. static const struct snd_kcontrol_new rt5677_ib9_src_mux =
  1879. SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
  1880. /* VAD Source */ /* MX-9F [6:4] */
  1881. static const char * const rt5677_vad_src[] = {
  1882. "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
  1883. "STO3 ADC MIX L"
  1884. };
  1885. static SOC_ENUM_SINGLE_DECL(
  1886. rt5677_vad_enum, RT5677_VAD_CTRL4,
  1887. RT5677_VAD_SRC_SFT, rt5677_vad_src);
  1888. static const struct snd_kcontrol_new rt5677_vad_src_mux =
  1889. SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
  1890. /* Sidetone Source */ /* MX-13 [11:9] */
  1891. static const char * const rt5677_sidetone_src[] = {
  1892. "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
  1893. };
  1894. static SOC_ENUM_SINGLE_DECL(
  1895. rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
  1896. RT5677_ST_SEL_SFT, rt5677_sidetone_src);
  1897. static const struct snd_kcontrol_new rt5677_sidetone_mux =
  1898. SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
  1899. /* DAC1/2 Source */ /* MX-15 [1:0] */
  1900. static const char * const rt5677_dac12_src[] = {
  1901. "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
  1902. };
  1903. static SOC_ENUM_SINGLE_DECL(
  1904. rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
  1905. RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
  1906. static const struct snd_kcontrol_new rt5677_dac12_mux =
  1907. SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
  1908. /* DAC3 Source */ /* MX-15 [5:4] */
  1909. static const char * const rt5677_dac3_src[] = {
  1910. "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
  1911. };
  1912. static SOC_ENUM_SINGLE_DECL(
  1913. rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
  1914. RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
  1915. static const struct snd_kcontrol_new rt5677_dac3_mux =
  1916. SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
  1917. /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
  1918. static const char * const rt5677_pdm_src[] = {
  1919. "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
  1920. };
  1921. static SOC_ENUM_SINGLE_DECL(
  1922. rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
  1923. RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
  1924. static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
  1925. SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
  1926. static SOC_ENUM_SINGLE_DECL(
  1927. rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
  1928. RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
  1929. static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
  1930. SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
  1931. static SOC_ENUM_SINGLE_DECL(
  1932. rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
  1933. RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
  1934. static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
  1935. SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
  1936. static SOC_ENUM_SINGLE_DECL(
  1937. rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
  1938. RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
  1939. static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
  1940. SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
  1941. /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
  1942. static const char * const rt5677_if12_adc1_src[] = {
  1943. "STO1 ADC MIX", "OB01", "VAD ADC"
  1944. };
  1945. static SOC_ENUM_SINGLE_DECL(
  1946. rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
  1947. RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
  1948. static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
  1949. SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
  1950. static SOC_ENUM_SINGLE_DECL(
  1951. rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
  1952. RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
  1953. static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
  1954. SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
  1955. static SOC_ENUM_SINGLE_DECL(
  1956. rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
  1957. RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
  1958. static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
  1959. SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
  1960. /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
  1961. static const char * const rt5677_if12_adc2_src[] = {
  1962. "STO2 ADC MIX", "OB23"
  1963. };
  1964. static SOC_ENUM_SINGLE_DECL(
  1965. rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
  1966. RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
  1967. static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
  1968. SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
  1969. static SOC_ENUM_SINGLE_DECL(
  1970. rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
  1971. RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
  1972. static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
  1973. SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
  1974. static SOC_ENUM_SINGLE_DECL(
  1975. rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
  1976. RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
  1977. static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
  1978. SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
  1979. /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
  1980. static const char * const rt5677_if12_adc3_src[] = {
  1981. "STO3 ADC MIX", "MONO ADC MIX", "OB45"
  1982. };
  1983. static SOC_ENUM_SINGLE_DECL(
  1984. rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
  1985. RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
  1986. static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
  1987. SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
  1988. static SOC_ENUM_SINGLE_DECL(
  1989. rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
  1990. RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
  1991. static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
  1992. SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
  1993. static SOC_ENUM_SINGLE_DECL(
  1994. rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
  1995. RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
  1996. static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
  1997. SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
  1998. /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
  1999. static const char * const rt5677_if12_adc4_src[] = {
  2000. "STO4 ADC MIX", "OB67", "OB01"
  2001. };
  2002. static SOC_ENUM_SINGLE_DECL(
  2003. rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
  2004. RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
  2005. static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
  2006. SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
  2007. static SOC_ENUM_SINGLE_DECL(
  2008. rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
  2009. RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
  2010. static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
  2011. SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
  2012. static SOC_ENUM_SINGLE_DECL(
  2013. rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
  2014. RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
  2015. static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
  2016. SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
  2017. /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
  2018. static const char * const rt5677_if34_adc_src[] = {
  2019. "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
  2020. "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
  2021. };
  2022. static SOC_ENUM_SINGLE_DECL(
  2023. rt5677_if3_adc_enum, RT5677_IF3_DATA,
  2024. RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
  2025. static const struct snd_kcontrol_new rt5677_if3_adc_mux =
  2026. SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
  2027. static SOC_ENUM_SINGLE_DECL(
  2028. rt5677_if4_adc_enum, RT5677_IF4_DATA,
  2029. RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
  2030. static const struct snd_kcontrol_new rt5677_if4_adc_mux =
  2031. SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
  2032. /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
  2033. static const char * const rt5677_if12_adc_swap_src[] = {
  2034. "L/R", "R/L", "L/L", "R/R"
  2035. };
  2036. static SOC_ENUM_SINGLE_DECL(
  2037. rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
  2038. RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
  2039. static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
  2040. SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
  2041. static SOC_ENUM_SINGLE_DECL(
  2042. rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
  2043. RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
  2044. static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
  2045. SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
  2046. static SOC_ENUM_SINGLE_DECL(
  2047. rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
  2048. RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
  2049. static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
  2050. SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
  2051. static SOC_ENUM_SINGLE_DECL(
  2052. rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
  2053. RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
  2054. static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
  2055. SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
  2056. static SOC_ENUM_SINGLE_DECL(
  2057. rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
  2058. RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
  2059. static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
  2060. SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
  2061. static SOC_ENUM_SINGLE_DECL(
  2062. rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
  2063. RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
  2064. static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
  2065. SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
  2066. static SOC_ENUM_SINGLE_DECL(
  2067. rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
  2068. RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
  2069. static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
  2070. SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
  2071. static SOC_ENUM_SINGLE_DECL(
  2072. rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
  2073. RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
  2074. static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
  2075. SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
  2076. /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
  2077. static const char * const rt5677_if1_adc_tdm_swap_src[] = {
  2078. "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
  2079. "3/1/2/4", "3/4/1/2"
  2080. };
  2081. static SOC_ENUM_SINGLE_DECL(
  2082. rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
  2083. RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
  2084. static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
  2085. SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
  2086. /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
  2087. static const char * const rt5677_if2_adc_tdm_swap_src[] = {
  2088. "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
  2089. "2/3/1/4", "3/4/1/2"
  2090. };
  2091. static SOC_ENUM_SINGLE_DECL(
  2092. rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
  2093. RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
  2094. static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
  2095. SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
  2096. /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
  2097. MX-3F[14:12][10:8][6:4][2:0]
  2098. MX-43[14:12][10:8][6:4][2:0]
  2099. MX-44[14:12][10:8][6:4][2:0] */
  2100. static const char * const rt5677_if12_dac_tdm_sel_src[] = {
  2101. "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
  2102. };
  2103. static SOC_ENUM_SINGLE_DECL(
  2104. rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
  2105. RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
  2106. static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
  2107. SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
  2108. static SOC_ENUM_SINGLE_DECL(
  2109. rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
  2110. RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
  2111. static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
  2112. SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
  2113. static SOC_ENUM_SINGLE_DECL(
  2114. rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
  2115. RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
  2116. static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
  2117. SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
  2118. static SOC_ENUM_SINGLE_DECL(
  2119. rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
  2120. RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
  2121. static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
  2122. SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
  2123. static SOC_ENUM_SINGLE_DECL(
  2124. rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
  2125. RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
  2126. static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
  2127. SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
  2128. static SOC_ENUM_SINGLE_DECL(
  2129. rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
  2130. RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
  2131. static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
  2132. SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
  2133. static SOC_ENUM_SINGLE_DECL(
  2134. rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
  2135. RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
  2136. static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
  2137. SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
  2138. static SOC_ENUM_SINGLE_DECL(
  2139. rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
  2140. RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
  2141. static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
  2142. SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
  2143. static SOC_ENUM_SINGLE_DECL(
  2144. rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
  2145. RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
  2146. static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
  2147. SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
  2148. static SOC_ENUM_SINGLE_DECL(
  2149. rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
  2150. RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
  2151. static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
  2152. SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
  2153. static SOC_ENUM_SINGLE_DECL(
  2154. rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
  2155. RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
  2156. static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
  2157. SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
  2158. static SOC_ENUM_SINGLE_DECL(
  2159. rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
  2160. RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
  2161. static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
  2162. SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
  2163. static SOC_ENUM_SINGLE_DECL(
  2164. rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
  2165. RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
  2166. static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
  2167. SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
  2168. static SOC_ENUM_SINGLE_DECL(
  2169. rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
  2170. RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
  2171. static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
  2172. SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
  2173. static SOC_ENUM_SINGLE_DECL(
  2174. rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
  2175. RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
  2176. static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
  2177. SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
  2178. static SOC_ENUM_SINGLE_DECL(
  2179. rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
  2180. RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
  2181. static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
  2182. SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
  2183. static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
  2184. struct snd_kcontrol *kcontrol, int event)
  2185. {
  2186. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2187. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2188. switch (event) {
  2189. case SND_SOC_DAPM_POST_PMU:
  2190. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2191. RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
  2192. break;
  2193. case SND_SOC_DAPM_PRE_PMD:
  2194. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2195. RT5677_PWR_BST1_P, 0);
  2196. break;
  2197. default:
  2198. return 0;
  2199. }
  2200. return 0;
  2201. }
  2202. static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
  2203. struct snd_kcontrol *kcontrol, int event)
  2204. {
  2205. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2206. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2207. switch (event) {
  2208. case SND_SOC_DAPM_POST_PMU:
  2209. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2210. RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
  2211. break;
  2212. case SND_SOC_DAPM_PRE_PMD:
  2213. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2214. RT5677_PWR_BST2_P, 0);
  2215. break;
  2216. default:
  2217. return 0;
  2218. }
  2219. return 0;
  2220. }
  2221. static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
  2222. struct snd_kcontrol *kcontrol, int event)
  2223. {
  2224. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2225. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2226. switch (event) {
  2227. case SND_SOC_DAPM_PRE_PMU:
  2228. regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
  2229. break;
  2230. case SND_SOC_DAPM_POST_PMU:
  2231. regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
  2232. break;
  2233. default:
  2234. return 0;
  2235. }
  2236. return 0;
  2237. }
  2238. static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
  2239. struct snd_kcontrol *kcontrol, int event)
  2240. {
  2241. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2242. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2243. switch (event) {
  2244. case SND_SOC_DAPM_PRE_PMU:
  2245. regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
  2246. break;
  2247. case SND_SOC_DAPM_POST_PMU:
  2248. regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
  2249. break;
  2250. default:
  2251. return 0;
  2252. }
  2253. return 0;
  2254. }
  2255. static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
  2256. struct snd_kcontrol *kcontrol, int event)
  2257. {
  2258. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2259. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2260. switch (event) {
  2261. case SND_SOC_DAPM_POST_PMU:
  2262. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2263. RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
  2264. RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
  2265. RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
  2266. break;
  2267. case SND_SOC_DAPM_PRE_PMD:
  2268. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  2269. RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
  2270. RT5677_PWR_CLK_MB, 0);
  2271. break;
  2272. default:
  2273. return 0;
  2274. }
  2275. return 0;
  2276. }
  2277. static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
  2278. struct snd_kcontrol *kcontrol, int event)
  2279. {
  2280. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2281. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2282. unsigned int value;
  2283. switch (event) {
  2284. case SND_SOC_DAPM_PRE_PMU:
  2285. regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
  2286. if (value & RT5677_IF1_ADC_CTRL_MASK)
  2287. regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
  2288. RT5677_IF1_ADC_MODE_MASK,
  2289. RT5677_IF1_ADC_MODE_TDM);
  2290. break;
  2291. default:
  2292. return 0;
  2293. }
  2294. return 0;
  2295. }
  2296. static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
  2297. struct snd_kcontrol *kcontrol, int event)
  2298. {
  2299. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2300. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2301. unsigned int value;
  2302. switch (event) {
  2303. case SND_SOC_DAPM_PRE_PMU:
  2304. regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
  2305. if (value & RT5677_IF2_ADC_CTRL_MASK)
  2306. regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
  2307. RT5677_IF2_ADC_MODE_MASK,
  2308. RT5677_IF2_ADC_MODE_TDM);
  2309. break;
  2310. default:
  2311. return 0;
  2312. }
  2313. return 0;
  2314. }
  2315. static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
  2316. struct snd_kcontrol *kcontrol, int event)
  2317. {
  2318. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2319. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  2320. switch (event) {
  2321. case SND_SOC_DAPM_POST_PMU:
  2322. if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
  2323. !rt5677->is_vref_slow) {
  2324. mdelay(20);
  2325. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
  2326. RT5677_PWR_FV1 | RT5677_PWR_FV2,
  2327. RT5677_PWR_FV1 | RT5677_PWR_FV2);
  2328. rt5677->is_vref_slow = true;
  2329. }
  2330. break;
  2331. default:
  2332. return 0;
  2333. }
  2334. return 0;
  2335. }
  2336. static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
  2337. struct snd_kcontrol *kcontrol, int event)
  2338. {
  2339. switch (event) {
  2340. case SND_SOC_DAPM_POST_PMU:
  2341. msleep(50);
  2342. break;
  2343. default:
  2344. return 0;
  2345. }
  2346. return 0;
  2347. }
  2348. static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
  2349. SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
  2350. 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
  2351. SND_SOC_DAPM_POST_PMU),
  2352. SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
  2353. 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
  2354. SND_SOC_DAPM_POST_PMU),
  2355. /* ASRC */
  2356. SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
  2357. SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
  2358. SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
  2359. SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
  2360. SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0,
  2361. rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU),
  2362. SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
  2363. 0),
  2364. SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
  2365. 0),
  2366. SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
  2367. 0),
  2368. SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
  2369. 0),
  2370. SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
  2371. 0),
  2372. SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
  2373. 0),
  2374. SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
  2375. 0),
  2376. SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
  2377. 0),
  2378. SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
  2379. 0),
  2380. SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
  2381. 0),
  2382. SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
  2383. 0),
  2384. SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
  2385. 0),
  2386. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
  2387. SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
  2388. SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
  2389. SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
  2390. SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
  2391. 0),
  2392. SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
  2393. 0),
  2394. /* Input Side */
  2395. /* micbias */
  2396. SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
  2397. 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
  2398. SND_SOC_DAPM_POST_PMU),
  2399. /* Input Lines */
  2400. SND_SOC_DAPM_INPUT("DMIC L1"),
  2401. SND_SOC_DAPM_INPUT("DMIC R1"),
  2402. SND_SOC_DAPM_INPUT("DMIC L2"),
  2403. SND_SOC_DAPM_INPUT("DMIC R2"),
  2404. SND_SOC_DAPM_INPUT("DMIC L3"),
  2405. SND_SOC_DAPM_INPUT("DMIC R3"),
  2406. SND_SOC_DAPM_INPUT("DMIC L4"),
  2407. SND_SOC_DAPM_INPUT("DMIC R4"),
  2408. SND_SOC_DAPM_INPUT("IN1P"),
  2409. SND_SOC_DAPM_INPUT("IN1N"),
  2410. SND_SOC_DAPM_INPUT("IN2P"),
  2411. SND_SOC_DAPM_INPUT("IN2N"),
  2412. SND_SOC_DAPM_INPUT("Haptic Generator"),
  2413. SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2414. SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2415. SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2416. SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2417. SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
  2418. RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
  2419. SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
  2420. RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
  2421. SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
  2422. RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
  2423. SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
  2424. RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
  2425. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  2426. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  2427. /* Boost */
  2428. SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
  2429. RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
  2430. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  2431. SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
  2432. RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
  2433. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  2434. /* ADCs */
  2435. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
  2436. 0, 0),
  2437. SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
  2438. 0, 0),
  2439. SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2440. SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
  2441. RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
  2442. SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
  2443. RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
  2444. SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
  2445. RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
  2446. SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
  2447. RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
  2448. /* ADC Mux */
  2449. SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
  2450. &rt5677_sto1_dmic_mux),
  2451. SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2452. &rt5677_sto1_adc1_mux),
  2453. SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2454. &rt5677_sto1_adc2_mux),
  2455. SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
  2456. &rt5677_sto2_dmic_mux),
  2457. SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2458. &rt5677_sto2_adc1_mux),
  2459. SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2460. &rt5677_sto2_adc2_mux),
  2461. SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
  2462. &rt5677_sto2_adc_lr_mux),
  2463. SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
  2464. &rt5677_sto3_dmic_mux),
  2465. SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2466. &rt5677_sto3_adc1_mux),
  2467. SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2468. &rt5677_sto3_adc2_mux),
  2469. SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
  2470. &rt5677_sto4_dmic_mux),
  2471. SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2472. &rt5677_sto4_adc1_mux),
  2473. SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2474. &rt5677_sto4_adc2_mux),
  2475. SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
  2476. &rt5677_mono_dmic_l_mux),
  2477. SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
  2478. &rt5677_mono_dmic_r_mux),
  2479. SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
  2480. &rt5677_mono_adc2_l_mux),
  2481. SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
  2482. &rt5677_mono_adc1_l_mux),
  2483. SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
  2484. &rt5677_mono_adc1_r_mux),
  2485. SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
  2486. &rt5677_mono_adc2_r_mux),
  2487. /* ADC Mixer */
  2488. SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
  2489. RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
  2490. SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
  2491. RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
  2492. SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
  2493. RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
  2494. SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
  2495. RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
  2496. SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  2497. rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
  2498. SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  2499. rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
  2500. SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
  2501. rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
  2502. SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
  2503. rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
  2504. SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
  2505. rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
  2506. SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
  2507. rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
  2508. SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
  2509. rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
  2510. SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
  2511. rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
  2512. SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
  2513. RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
  2514. SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
  2515. rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
  2516. SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
  2517. RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
  2518. SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
  2519. rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
  2520. /* ADC PGA */
  2521. SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  2522. SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  2523. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2524. SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  2525. SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  2526. SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2527. SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  2528. SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  2529. SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2530. SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  2531. SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  2532. SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2533. SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2534. SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2535. SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2536. SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2537. /* DSP */
  2538. SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
  2539. &rt5677_ib9_src_mux),
  2540. SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
  2541. &rt5677_ib8_src_mux),
  2542. SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
  2543. &rt5677_ib7_src_mux),
  2544. SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
  2545. &rt5677_ib6_src_mux),
  2546. SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
  2547. &rt5677_ib45_src_mux),
  2548. SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
  2549. &rt5677_ib23_src_mux),
  2550. SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
  2551. &rt5677_ib01_src_mux),
  2552. SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
  2553. &rt5677_ib45_bypass_src_mux),
  2554. SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
  2555. &rt5677_ib23_bypass_src_mux),
  2556. SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
  2557. &rt5677_ib01_bypass_src_mux),
  2558. SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
  2559. &rt5677_ob23_bypass_src_mux),
  2560. SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
  2561. &rt5677_ob01_bypass_src_mux),
  2562. SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
  2563. SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
  2564. SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2565. SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2566. SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2567. SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
  2568. SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
  2569. SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
  2570. /* Digital Interface */
  2571. SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
  2572. RT5677_PWR_I2S1_BIT, 0, NULL, 0),
  2573. SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
  2574. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2575. SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2576. SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2577. SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2578. SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
  2579. SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
  2580. SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
  2581. SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
  2582. SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
  2583. SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
  2584. SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
  2585. SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2586. SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2587. SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2588. SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2589. SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
  2590. RT5677_PWR_I2S2_BIT, 0, NULL, 0),
  2591. SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
  2592. SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2593. SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2594. SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2595. SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2596. SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
  2597. SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
  2598. SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
  2599. SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
  2600. SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
  2601. SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
  2602. SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
  2603. SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2604. SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2605. SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2606. SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2607. SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
  2608. RT5677_PWR_I2S3_BIT, 0, NULL, 0),
  2609. SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2610. SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2611. SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2612. SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2613. SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2614. SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2615. SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
  2616. RT5677_PWR_I2S4_BIT, 0, NULL, 0),
  2617. SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2618. SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2619. SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2620. SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2621. SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2622. SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2623. SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
  2624. RT5677_PWR_SLB_BIT, 0, NULL, 0),
  2625. SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
  2626. SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2627. SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2628. SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2629. SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2630. SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
  2631. SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
  2632. SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
  2633. SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
  2634. SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
  2635. SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
  2636. SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
  2637. SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2638. SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2639. SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2640. SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2641. /* Digital Interface Select */
  2642. SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2643. &rt5677_if1_adc1_mux),
  2644. SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2645. &rt5677_if1_adc2_mux),
  2646. SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
  2647. &rt5677_if1_adc3_mux),
  2648. SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
  2649. &rt5677_if1_adc4_mux),
  2650. SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
  2651. &rt5677_if1_adc1_swap_mux),
  2652. SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
  2653. &rt5677_if1_adc2_swap_mux),
  2654. SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
  2655. &rt5677_if1_adc3_swap_mux),
  2656. SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
  2657. &rt5677_if1_adc4_swap_mux),
  2658. SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
  2659. &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
  2660. SND_SOC_DAPM_PRE_PMU),
  2661. SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2662. &rt5677_if2_adc1_mux),
  2663. SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2664. &rt5677_if2_adc2_mux),
  2665. SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
  2666. &rt5677_if2_adc3_mux),
  2667. SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
  2668. &rt5677_if2_adc4_mux),
  2669. SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
  2670. &rt5677_if2_adc1_swap_mux),
  2671. SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
  2672. &rt5677_if2_adc2_swap_mux),
  2673. SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
  2674. &rt5677_if2_adc3_swap_mux),
  2675. SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
  2676. &rt5677_if2_adc4_swap_mux),
  2677. SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
  2678. &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
  2679. SND_SOC_DAPM_PRE_PMU),
  2680. SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
  2681. &rt5677_if3_adc_mux),
  2682. SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
  2683. &rt5677_if4_adc_mux),
  2684. SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2685. &rt5677_slb_adc1_mux),
  2686. SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2687. &rt5677_slb_adc2_mux),
  2688. SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
  2689. &rt5677_slb_adc3_mux),
  2690. SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
  2691. &rt5677_slb_adc4_mux),
  2692. SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
  2693. &rt5677_if1_dac0_tdm_sel_mux),
  2694. SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
  2695. &rt5677_if1_dac1_tdm_sel_mux),
  2696. SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
  2697. &rt5677_if1_dac2_tdm_sel_mux),
  2698. SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
  2699. &rt5677_if1_dac3_tdm_sel_mux),
  2700. SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
  2701. &rt5677_if1_dac4_tdm_sel_mux),
  2702. SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
  2703. &rt5677_if1_dac5_tdm_sel_mux),
  2704. SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
  2705. &rt5677_if1_dac6_tdm_sel_mux),
  2706. SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
  2707. &rt5677_if1_dac7_tdm_sel_mux),
  2708. SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
  2709. &rt5677_if2_dac0_tdm_sel_mux),
  2710. SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
  2711. &rt5677_if2_dac1_tdm_sel_mux),
  2712. SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
  2713. &rt5677_if2_dac2_tdm_sel_mux),
  2714. SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
  2715. &rt5677_if2_dac3_tdm_sel_mux),
  2716. SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
  2717. &rt5677_if2_dac4_tdm_sel_mux),
  2718. SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
  2719. &rt5677_if2_dac5_tdm_sel_mux),
  2720. SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
  2721. &rt5677_if2_dac6_tdm_sel_mux),
  2722. SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
  2723. &rt5677_if2_dac7_tdm_sel_mux),
  2724. /* Audio Interface */
  2725. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  2726. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  2727. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  2728. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  2729. SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
  2730. SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
  2731. SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
  2732. SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
  2733. SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
  2734. SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
  2735. SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0),
  2736. /* Sidetone Mux */
  2737. SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
  2738. &rt5677_sidetone_mux),
  2739. SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
  2740. RT5677_ST_EN_SFT, 0, NULL, 0),
  2741. /* VAD Mux*/
  2742. SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
  2743. &rt5677_vad_src_mux),
  2744. /* Tensilica DSP */
  2745. SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
  2746. SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
  2747. rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
  2748. SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
  2749. rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
  2750. SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
  2751. rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
  2752. SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
  2753. rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
  2754. SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
  2755. rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
  2756. SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
  2757. rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
  2758. /* Output Side */
  2759. /* DAC mixer before sound effect */
  2760. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  2761. rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
  2762. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  2763. rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
  2764. SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
  2765. /* DAC Mux */
  2766. SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
  2767. &rt5677_dac1_mux),
  2768. SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
  2769. &rt5677_adda1_mux),
  2770. SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
  2771. &rt5677_dac12_mux),
  2772. SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
  2773. &rt5677_dac3_mux),
  2774. /* DAC2 channel Mux */
  2775. SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
  2776. &rt5677_dac2_l_mux),
  2777. SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
  2778. &rt5677_dac2_r_mux),
  2779. /* DAC3 channel Mux */
  2780. SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
  2781. &rt5677_dac3_l_mux),
  2782. SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
  2783. &rt5677_dac3_r_mux),
  2784. /* DAC4 channel Mux */
  2785. SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
  2786. &rt5677_dac4_l_mux),
  2787. SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
  2788. &rt5677_dac4_r_mux),
  2789. /* DAC Mixer */
  2790. SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
  2791. RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
  2792. SND_SOC_DAPM_POST_PMU),
  2793. SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
  2794. RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
  2795. SND_SOC_DAPM_POST_PMU),
  2796. SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
  2797. RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
  2798. SND_SOC_DAPM_POST_PMU),
  2799. SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
  2800. RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
  2801. SND_SOC_DAPM_POST_PMU),
  2802. SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
  2803. RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
  2804. SND_SOC_DAPM_POST_PMU),
  2805. SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
  2806. RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
  2807. SND_SOC_DAPM_POST_PMU),
  2808. SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
  2809. RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
  2810. SND_SOC_DAPM_POST_PMU),
  2811. SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
  2812. rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
  2813. SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
  2814. rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
  2815. SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
  2816. rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
  2817. SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
  2818. rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
  2819. SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
  2820. rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
  2821. SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
  2822. rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
  2823. SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
  2824. rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
  2825. SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
  2826. rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
  2827. SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2828. SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2829. SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2830. SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2831. /* DACs */
  2832. SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
  2833. RT5677_PWR_DAC1_BIT, 0),
  2834. SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
  2835. RT5677_PWR_DAC2_BIT, 0),
  2836. SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
  2837. RT5677_PWR_DAC3_BIT, 0),
  2838. /* PDM */
  2839. SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
  2840. RT5677_PWR_PDM1_BIT, 0, NULL, 0),
  2841. SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
  2842. RT5677_PWR_PDM2_BIT, 0, NULL, 0),
  2843. SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
  2844. 1, &rt5677_pdm1_l_mux),
  2845. SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
  2846. 1, &rt5677_pdm1_r_mux),
  2847. SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
  2848. 1, &rt5677_pdm2_l_mux),
  2849. SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
  2850. 1, &rt5677_pdm2_r_mux),
  2851. SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
  2852. 0, NULL, 0),
  2853. SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
  2854. 0, NULL, 0),
  2855. SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
  2856. 0, NULL, 0),
  2857. SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
  2858. rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
  2859. SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
  2860. rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
  2861. SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
  2862. rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
  2863. /* Output Lines */
  2864. SND_SOC_DAPM_OUTPUT("LOUT1"),
  2865. SND_SOC_DAPM_OUTPUT("LOUT2"),
  2866. SND_SOC_DAPM_OUTPUT("LOUT3"),
  2867. SND_SOC_DAPM_OUTPUT("PDM1L"),
  2868. SND_SOC_DAPM_OUTPUT("PDM1R"),
  2869. SND_SOC_DAPM_OUTPUT("PDM2L"),
  2870. SND_SOC_DAPM_OUTPUT("PDM2R"),
  2871. SND_SOC_DAPM_POST("vref", rt5677_vref_event),
  2872. };
  2873. static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
  2874. { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
  2875. { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
  2876. { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
  2877. { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
  2878. { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
  2879. { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
  2880. { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
  2881. { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
  2882. { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
  2883. { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
  2884. { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
  2885. { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
  2886. { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
  2887. { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
  2888. { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
  2889. { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
  2890. { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
  2891. { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
  2892. { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
  2893. { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
  2894. { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
  2895. { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
  2896. { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
  2897. { "DMIC1", NULL, "DMIC L1" },
  2898. { "DMIC1", NULL, "DMIC R1" },
  2899. { "DMIC2", NULL, "DMIC L2" },
  2900. { "DMIC2", NULL, "DMIC R2" },
  2901. { "DMIC3", NULL, "DMIC L3" },
  2902. { "DMIC3", NULL, "DMIC R3" },
  2903. { "DMIC4", NULL, "DMIC L4" },
  2904. { "DMIC4", NULL, "DMIC R4" },
  2905. { "DMIC L1", NULL, "DMIC CLK" },
  2906. { "DMIC R1", NULL, "DMIC CLK" },
  2907. { "DMIC L2", NULL, "DMIC CLK" },
  2908. { "DMIC R2", NULL, "DMIC CLK" },
  2909. { "DMIC L3", NULL, "DMIC CLK" },
  2910. { "DMIC R3", NULL, "DMIC CLK" },
  2911. { "DMIC L4", NULL, "DMIC CLK" },
  2912. { "DMIC R4", NULL, "DMIC CLK" },
  2913. { "DMIC L1", NULL, "DMIC1 power" },
  2914. { "DMIC R1", NULL, "DMIC1 power" },
  2915. { "DMIC L3", NULL, "DMIC3 power" },
  2916. { "DMIC R3", NULL, "DMIC3 power" },
  2917. { "DMIC L4", NULL, "DMIC4 power" },
  2918. { "DMIC R4", NULL, "DMIC4 power" },
  2919. { "BST1", NULL, "IN1P" },
  2920. { "BST1", NULL, "IN1N" },
  2921. { "BST2", NULL, "IN2P" },
  2922. { "BST2", NULL, "IN2N" },
  2923. { "IN1P", NULL, "MICBIAS1" },
  2924. { "IN1N", NULL, "MICBIAS1" },
  2925. { "IN2P", NULL, "MICBIAS1" },
  2926. { "IN2N", NULL, "MICBIAS1" },
  2927. { "ADC 1", NULL, "BST1" },
  2928. { "ADC 1", NULL, "ADC 1 power" },
  2929. { "ADC 1", NULL, "ADC1 clock" },
  2930. { "ADC 2", NULL, "BST2" },
  2931. { "ADC 2", NULL, "ADC 2 power" },
  2932. { "ADC 2", NULL, "ADC2 clock" },
  2933. { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
  2934. { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
  2935. { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
  2936. { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
  2937. { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
  2938. { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
  2939. { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
  2940. { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
  2941. { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
  2942. { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
  2943. { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
  2944. { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
  2945. { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
  2946. { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
  2947. { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
  2948. { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
  2949. { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
  2950. { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
  2951. { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
  2952. { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
  2953. { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
  2954. { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
  2955. { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
  2956. { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
  2957. { "ADC 1_2", NULL, "ADC 1" },
  2958. { "ADC 1_2", NULL, "ADC 2" },
  2959. { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
  2960. { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
  2961. { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2962. { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
  2963. { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
  2964. { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2965. { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
  2966. { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
  2967. { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2968. { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
  2969. { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
  2970. { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2971. { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
  2972. { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
  2973. { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2974. { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
  2975. { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
  2976. { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
  2977. { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
  2978. { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
  2979. { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
  2980. { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
  2981. { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
  2982. { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
  2983. { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
  2984. { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
  2985. { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
  2986. { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
  2987. { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
  2988. { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
  2989. { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
  2990. { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
  2991. { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
  2992. { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
  2993. { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
  2994. { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
  2995. { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
  2996. { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
  2997. { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
  2998. { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
  2999. { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
  3000. { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
  3001. { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
  3002. { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
  3003. { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
  3004. { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
  3005. { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
  3006. { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
  3007. { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
  3008. { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
  3009. { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
  3010. { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
  3011. { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
  3012. { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
  3013. { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
  3014. { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
  3015. { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
  3016. { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
  3017. { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
  3018. { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
  3019. { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
  3020. { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
  3021. { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
  3022. { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
  3023. { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
  3024. { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
  3025. { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
  3026. { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
  3027. { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
  3028. { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
  3029. { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
  3030. { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
  3031. { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
  3032. { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
  3033. { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
  3034. { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
  3035. { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
  3036. { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
  3037. { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
  3038. { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
  3039. { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
  3040. { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
  3041. { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
  3042. { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
  3043. { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
  3044. { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
  3045. { "Mono ADC MIXL", NULL, "adc mono left filter" },
  3046. { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
  3047. { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
  3048. { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
  3049. { "Mono ADC MIXR", NULL, "adc mono right filter" },
  3050. { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
  3051. { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
  3052. { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
  3053. { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
  3054. { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
  3055. { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
  3056. { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
  3057. { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
  3058. { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3059. { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
  3060. { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
  3061. { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3062. { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
  3063. { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3064. { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
  3065. { "IF1 ADC3 Mux", "OB45", "OB45" },
  3066. { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
  3067. { "IF1 ADC4 Mux", "OB67", "OB67" },
  3068. { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
  3069. { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
  3070. { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
  3071. { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
  3072. { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
  3073. { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
  3074. { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
  3075. { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
  3076. { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
  3077. { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
  3078. { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
  3079. { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
  3080. { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
  3081. { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
  3082. { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
  3083. { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
  3084. { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
  3085. { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
  3086. { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
  3087. { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
  3088. { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
  3089. { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
  3090. { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
  3091. { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
  3092. { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
  3093. { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
  3094. { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
  3095. { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
  3096. { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
  3097. { "AIF1TX", NULL, "I2S1" },
  3098. { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
  3099. { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3100. { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
  3101. { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
  3102. { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3103. { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
  3104. { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3105. { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
  3106. { "IF2 ADC3 Mux", "OB45", "OB45" },
  3107. { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
  3108. { "IF2 ADC4 Mux", "OB67", "OB67" },
  3109. { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
  3110. { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
  3111. { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
  3112. { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
  3113. { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
  3114. { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
  3115. { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
  3116. { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
  3117. { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
  3118. { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
  3119. { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
  3120. { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
  3121. { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
  3122. { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
  3123. { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
  3124. { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
  3125. { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
  3126. { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
  3127. { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
  3128. { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
  3129. { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
  3130. { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
  3131. { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
  3132. { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
  3133. { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
  3134. { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
  3135. { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
  3136. { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
  3137. { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
  3138. { "AIF2TX", NULL, "I2S2" },
  3139. { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
  3140. { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3141. { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3142. { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3143. { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
  3144. { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
  3145. { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
  3146. { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
  3147. { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
  3148. { "AIF3TX", NULL, "I2S3" },
  3149. { "AIF3TX", NULL, "IF3 ADC Mux" },
  3150. { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3151. { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3152. { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3153. { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
  3154. { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
  3155. { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
  3156. { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
  3157. { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
  3158. { "AIF4TX", NULL, "I2S4" },
  3159. { "AIF4TX", NULL, "IF4 ADC Mux" },
  3160. { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3161. { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
  3162. { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
  3163. { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3164. { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
  3165. { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3166. { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
  3167. { "SLB ADC3 Mux", "OB45", "OB45" },
  3168. { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
  3169. { "SLB ADC4 Mux", "OB67", "OB67" },
  3170. { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
  3171. { "SLBTX", NULL, "SLB" },
  3172. { "SLBTX", NULL, "SLB ADC1 Mux" },
  3173. { "SLBTX", NULL, "SLB ADC2 Mux" },
  3174. { "SLBTX", NULL, "SLB ADC3 Mux" },
  3175. { "SLBTX", NULL, "SLB ADC4 Mux" },
  3176. { "DSPTX", NULL, "IB01 Bypass Mux" },
  3177. { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
  3178. { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
  3179. { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
  3180. { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3181. /* The IB01 Mux controls the source for InBound0 and InBound1.
  3182. * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to
  3183. * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for
  3184. * hotwording. "DAC1 FS" is not used currently.
  3185. *
  3186. * Creating a common widget node for "VAD ADC" + "DAC1 FS" and
  3187. * connecting the common widget to IB01 Mux causes the issue where
  3188. * there is an active path going from system playback -> "DAC1 FS" ->
  3189. * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
  3190. * DAPM. Therefore "DAC1 FS" is ignored for now.
  3191. */
  3192. { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" },
  3193. { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
  3194. { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
  3195. { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
  3196. { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
  3197. { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
  3198. { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3199. { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
  3200. { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
  3201. { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
  3202. { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
  3203. { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
  3204. { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
  3205. { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
  3206. { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
  3207. { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
  3208. { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
  3209. { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
  3210. { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
  3211. { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
  3212. { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
  3213. { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
  3214. { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
  3215. { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
  3216. { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
  3217. { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
  3218. { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
  3219. { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
  3220. { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
  3221. { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
  3222. { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
  3223. { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
  3224. { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
  3225. { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
  3226. { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
  3227. { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
  3228. { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
  3229. { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
  3230. { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
  3231. { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
  3232. { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
  3233. { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
  3234. { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
  3235. { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
  3236. { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
  3237. { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
  3238. { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
  3239. { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3240. { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3241. { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3242. { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
  3243. { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
  3244. { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
  3245. { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
  3246. { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3247. { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3248. { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3249. { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
  3250. { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
  3251. { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
  3252. { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
  3253. { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3254. { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3255. { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3256. { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
  3257. { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
  3258. { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
  3259. { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
  3260. { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3261. { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3262. { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3263. { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
  3264. { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
  3265. { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
  3266. { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
  3267. { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3268. { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3269. { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3270. { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
  3271. { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
  3272. { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
  3273. { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
  3274. { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
  3275. { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
  3276. { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
  3277. { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
  3278. { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
  3279. { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
  3280. { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
  3281. { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
  3282. { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
  3283. { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
  3284. { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
  3285. { "OutBound2", NULL, "OB23 Bypass Mux" },
  3286. { "OutBound3", NULL, "OB23 Bypass Mux" },
  3287. { "OutBound4", NULL, "OB4 MIX" },
  3288. { "OutBound5", NULL, "OB5 MIX" },
  3289. { "OutBound6", NULL, "OB6 MIX" },
  3290. { "OutBound7", NULL, "OB7 MIX" },
  3291. { "OB45", NULL, "OutBound4" },
  3292. { "OB45", NULL, "OutBound5" },
  3293. { "OB67", NULL, "OutBound6" },
  3294. { "OB67", NULL, "OutBound7" },
  3295. { "IF1 DAC0", NULL, "AIF1RX" },
  3296. { "IF1 DAC1", NULL, "AIF1RX" },
  3297. { "IF1 DAC2", NULL, "AIF1RX" },
  3298. { "IF1 DAC3", NULL, "AIF1RX" },
  3299. { "IF1 DAC4", NULL, "AIF1RX" },
  3300. { "IF1 DAC5", NULL, "AIF1RX" },
  3301. { "IF1 DAC6", NULL, "AIF1RX" },
  3302. { "IF1 DAC7", NULL, "AIF1RX" },
  3303. { "IF1 DAC0", NULL, "I2S1" },
  3304. { "IF1 DAC1", NULL, "I2S1" },
  3305. { "IF1 DAC2", NULL, "I2S1" },
  3306. { "IF1 DAC3", NULL, "I2S1" },
  3307. { "IF1 DAC4", NULL, "I2S1" },
  3308. { "IF1 DAC5", NULL, "I2S1" },
  3309. { "IF1 DAC6", NULL, "I2S1" },
  3310. { "IF1 DAC7", NULL, "I2S1" },
  3311. { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
  3312. { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
  3313. { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
  3314. { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
  3315. { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
  3316. { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
  3317. { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
  3318. { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
  3319. { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
  3320. { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
  3321. { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
  3322. { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
  3323. { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
  3324. { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
  3325. { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
  3326. { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
  3327. { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
  3328. { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
  3329. { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
  3330. { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
  3331. { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
  3332. { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
  3333. { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
  3334. { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
  3335. { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
  3336. { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
  3337. { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
  3338. { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
  3339. { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
  3340. { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
  3341. { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
  3342. { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
  3343. { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
  3344. { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
  3345. { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
  3346. { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
  3347. { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
  3348. { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
  3349. { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
  3350. { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
  3351. { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
  3352. { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
  3353. { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
  3354. { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
  3355. { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
  3356. { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
  3357. { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
  3358. { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
  3359. { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
  3360. { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
  3361. { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
  3362. { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
  3363. { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
  3364. { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
  3365. { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
  3366. { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
  3367. { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
  3368. { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
  3369. { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
  3370. { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
  3371. { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
  3372. { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
  3373. { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
  3374. { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
  3375. { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
  3376. { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
  3377. { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
  3378. { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
  3379. { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
  3380. { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
  3381. { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
  3382. { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
  3383. { "IF2 DAC0", NULL, "AIF2RX" },
  3384. { "IF2 DAC1", NULL, "AIF2RX" },
  3385. { "IF2 DAC2", NULL, "AIF2RX" },
  3386. { "IF2 DAC3", NULL, "AIF2RX" },
  3387. { "IF2 DAC4", NULL, "AIF2RX" },
  3388. { "IF2 DAC5", NULL, "AIF2RX" },
  3389. { "IF2 DAC6", NULL, "AIF2RX" },
  3390. { "IF2 DAC7", NULL, "AIF2RX" },
  3391. { "IF2 DAC0", NULL, "I2S2" },
  3392. { "IF2 DAC1", NULL, "I2S2" },
  3393. { "IF2 DAC2", NULL, "I2S2" },
  3394. { "IF2 DAC3", NULL, "I2S2" },
  3395. { "IF2 DAC4", NULL, "I2S2" },
  3396. { "IF2 DAC5", NULL, "I2S2" },
  3397. { "IF2 DAC6", NULL, "I2S2" },
  3398. { "IF2 DAC7", NULL, "I2S2" },
  3399. { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
  3400. { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
  3401. { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
  3402. { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
  3403. { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
  3404. { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
  3405. { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
  3406. { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
  3407. { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
  3408. { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
  3409. { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
  3410. { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
  3411. { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
  3412. { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
  3413. { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
  3414. { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
  3415. { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
  3416. { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
  3417. { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
  3418. { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
  3419. { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
  3420. { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
  3421. { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
  3422. { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
  3423. { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
  3424. { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
  3425. { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
  3426. { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
  3427. { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
  3428. { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
  3429. { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
  3430. { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
  3431. { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
  3432. { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
  3433. { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
  3434. { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
  3435. { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
  3436. { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
  3437. { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
  3438. { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
  3439. { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
  3440. { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
  3441. { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
  3442. { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
  3443. { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
  3444. { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
  3445. { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
  3446. { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
  3447. { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
  3448. { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
  3449. { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
  3450. { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
  3451. { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
  3452. { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
  3453. { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
  3454. { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
  3455. { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
  3456. { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
  3457. { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
  3458. { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
  3459. { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
  3460. { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
  3461. { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
  3462. { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
  3463. { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
  3464. { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
  3465. { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
  3466. { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
  3467. { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
  3468. { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
  3469. { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
  3470. { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
  3471. { "IF3 DAC", NULL, "AIF3RX" },
  3472. { "IF3 DAC", NULL, "I2S3" },
  3473. { "IF4 DAC", NULL, "AIF4RX" },
  3474. { "IF4 DAC", NULL, "I2S4" },
  3475. { "IF3 DAC L", NULL, "IF3 DAC" },
  3476. { "IF3 DAC R", NULL, "IF3 DAC" },
  3477. { "IF4 DAC L", NULL, "IF4 DAC" },
  3478. { "IF4 DAC R", NULL, "IF4 DAC" },
  3479. { "SLB DAC0", NULL, "SLBRX" },
  3480. { "SLB DAC1", NULL, "SLBRX" },
  3481. { "SLB DAC2", NULL, "SLBRX" },
  3482. { "SLB DAC3", NULL, "SLBRX" },
  3483. { "SLB DAC4", NULL, "SLBRX" },
  3484. { "SLB DAC5", NULL, "SLBRX" },
  3485. { "SLB DAC6", NULL, "SLBRX" },
  3486. { "SLB DAC7", NULL, "SLBRX" },
  3487. { "SLB DAC0", NULL, "SLB" },
  3488. { "SLB DAC1", NULL, "SLB" },
  3489. { "SLB DAC2", NULL, "SLB" },
  3490. { "SLB DAC3", NULL, "SLB" },
  3491. { "SLB DAC4", NULL, "SLB" },
  3492. { "SLB DAC5", NULL, "SLB" },
  3493. { "SLB DAC6", NULL, "SLB" },
  3494. { "SLB DAC7", NULL, "SLB" },
  3495. { "SLB DAC01", NULL, "SLB DAC0" },
  3496. { "SLB DAC01", NULL, "SLB DAC1" },
  3497. { "SLB DAC23", NULL, "SLB DAC2" },
  3498. { "SLB DAC23", NULL, "SLB DAC3" },
  3499. { "SLB DAC45", NULL, "SLB DAC4" },
  3500. { "SLB DAC45", NULL, "SLB DAC5" },
  3501. { "SLB DAC67", NULL, "SLB DAC6" },
  3502. { "SLB DAC67", NULL, "SLB DAC7" },
  3503. { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
  3504. { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
  3505. { "ADDA1 Mux", "OB 67", "OB67" },
  3506. { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
  3507. { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
  3508. { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
  3509. { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
  3510. { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
  3511. { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
  3512. { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
  3513. { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
  3514. { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
  3515. { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
  3516. { "DAC1 FS", NULL, "DAC1 MIXL" },
  3517. { "DAC1 FS", NULL, "DAC1 MIXR" },
  3518. { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
  3519. { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
  3520. { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
  3521. { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
  3522. { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
  3523. { "DAC2 L Mux", "OB 2", "OutBound2" },
  3524. { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
  3525. { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
  3526. { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
  3527. { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
  3528. { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
  3529. { "DAC2 R Mux", "OB 3", "OutBound3" },
  3530. { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
  3531. { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
  3532. { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
  3533. { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
  3534. { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
  3535. { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
  3536. { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
  3537. { "DAC3 L Mux", "OB 4", "OutBound4" },
  3538. { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
  3539. { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
  3540. { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
  3541. { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
  3542. { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
  3543. { "DAC3 R Mux", "OB 5", "OutBound5" },
  3544. { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
  3545. { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
  3546. { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
  3547. { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
  3548. { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
  3549. { "DAC4 L Mux", "OB 6", "OutBound6" },
  3550. { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
  3551. { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
  3552. { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
  3553. { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
  3554. { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
  3555. { "DAC4 R Mux", "OB 7", "OutBound7" },
  3556. { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
  3557. { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
  3558. { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
  3559. { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
  3560. { "Sidetone Mux", "ADC1", "ADC 1" },
  3561. { "Sidetone Mux", "ADC2", "ADC 2" },
  3562. { "Sidetone Mux", NULL, "Sidetone Power" },
  3563. { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
  3564. { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
  3565. { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
  3566. { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
  3567. { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
  3568. { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
  3569. { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
  3570. { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
  3571. { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
  3572. { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
  3573. { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
  3574. { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
  3575. { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
  3576. { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
  3577. { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
  3578. { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
  3579. { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
  3580. { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
  3581. { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
  3582. { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
  3583. { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
  3584. { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
  3585. { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
  3586. { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
  3587. { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
  3588. { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
  3589. { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
  3590. { "DD1 MIXL", NULL, "dac mono3 left filter" },
  3591. { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
  3592. { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
  3593. { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
  3594. { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
  3595. { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
  3596. { "DD1 MIXR", NULL, "dac mono3 right filter" },
  3597. { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
  3598. { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
  3599. { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
  3600. { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
  3601. { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
  3602. { "DD2 MIXL", NULL, "dac mono4 left filter" },
  3603. { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
  3604. { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
  3605. { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
  3606. { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
  3607. { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
  3608. { "DD2 MIXR", NULL, "dac mono4 right filter" },
  3609. { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
  3610. { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
  3611. { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
  3612. { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
  3613. { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
  3614. { "DD1 MIX", NULL, "DD1 MIXL" },
  3615. { "DD1 MIX", NULL, "DD1 MIXR" },
  3616. { "DD2 MIX", NULL, "DD2 MIXL" },
  3617. { "DD2 MIX", NULL, "DD2 MIXR" },
  3618. { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
  3619. { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
  3620. { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
  3621. { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
  3622. { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
  3623. { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
  3624. { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
  3625. { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
  3626. { "DAC 1", NULL, "DAC12 SRC Mux" },
  3627. { "DAC 2", NULL, "DAC12 SRC Mux" },
  3628. { "DAC 3", NULL, "DAC3 SRC Mux" },
  3629. { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
  3630. { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
  3631. { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
  3632. { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
  3633. { "PDM1 L Mux", NULL, "PDM1 Power" },
  3634. { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
  3635. { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
  3636. { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
  3637. { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
  3638. { "PDM1 R Mux", NULL, "PDM1 Power" },
  3639. { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
  3640. { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
  3641. { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
  3642. { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
  3643. { "PDM2 L Mux", NULL, "PDM2 Power" },
  3644. { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
  3645. { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
  3646. { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
  3647. { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
  3648. { "PDM2 R Mux", NULL, "PDM2 Power" },
  3649. { "LOUT1 amp", NULL, "DAC 1" },
  3650. { "LOUT2 amp", NULL, "DAC 2" },
  3651. { "LOUT3 amp", NULL, "DAC 3" },
  3652. { "LOUT1 vref", NULL, "LOUT1 amp" },
  3653. { "LOUT2 vref", NULL, "LOUT2 amp" },
  3654. { "LOUT3 vref", NULL, "LOUT3 amp" },
  3655. { "LOUT1", NULL, "LOUT1 vref" },
  3656. { "LOUT2", NULL, "LOUT2 vref" },
  3657. { "LOUT3", NULL, "LOUT3 vref" },
  3658. { "PDM1L", NULL, "PDM1 L Mux" },
  3659. { "PDM1R", NULL, "PDM1 R Mux" },
  3660. { "PDM2L", NULL, "PDM2 L Mux" },
  3661. { "PDM2R", NULL, "PDM2 R Mux" },
  3662. };
  3663. static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
  3664. { "DMIC L2", NULL, "DMIC1 power" },
  3665. { "DMIC R2", NULL, "DMIC1 power" },
  3666. };
  3667. static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
  3668. { "DMIC L2", NULL, "DMIC2 power" },
  3669. { "DMIC R2", NULL, "DMIC2 power" },
  3670. };
  3671. static int rt5677_hw_params(struct snd_pcm_substream *substream,
  3672. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  3673. {
  3674. struct snd_soc_component *component = dai->component;
  3675. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3676. unsigned int val_len = 0, val_clk, mask_clk;
  3677. int pre_div, bclk_ms, frame_size;
  3678. rt5677->lrck[dai->id] = params_rate(params);
  3679. pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
  3680. if (pre_div < 0) {
  3681. dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
  3682. rt5677->sysclk, rt5677->lrck[dai->id]);
  3683. return -EINVAL;
  3684. }
  3685. frame_size = snd_soc_params_to_frame_size(params);
  3686. if (frame_size < 0) {
  3687. dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
  3688. return -EINVAL;
  3689. }
  3690. bclk_ms = frame_size > 32;
  3691. rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
  3692. dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  3693. rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
  3694. dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  3695. bclk_ms, pre_div, dai->id);
  3696. switch (params_width(params)) {
  3697. case 16:
  3698. break;
  3699. case 20:
  3700. val_len |= RT5677_I2S_DL_20;
  3701. break;
  3702. case 24:
  3703. val_len |= RT5677_I2S_DL_24;
  3704. break;
  3705. case 8:
  3706. val_len |= RT5677_I2S_DL_8;
  3707. break;
  3708. default:
  3709. return -EINVAL;
  3710. }
  3711. switch (dai->id) {
  3712. case RT5677_AIF1:
  3713. mask_clk = RT5677_I2S_PD1_MASK;
  3714. val_clk = pre_div << RT5677_I2S_PD1_SFT;
  3715. regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
  3716. RT5677_I2S_DL_MASK, val_len);
  3717. regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
  3718. mask_clk, val_clk);
  3719. break;
  3720. case RT5677_AIF2:
  3721. mask_clk = RT5677_I2S_PD2_MASK;
  3722. val_clk = pre_div << RT5677_I2S_PD2_SFT;
  3723. regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
  3724. RT5677_I2S_DL_MASK, val_len);
  3725. regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
  3726. mask_clk, val_clk);
  3727. break;
  3728. case RT5677_AIF3:
  3729. mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
  3730. val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
  3731. pre_div << RT5677_I2S_PD3_SFT;
  3732. regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
  3733. RT5677_I2S_DL_MASK, val_len);
  3734. regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
  3735. mask_clk, val_clk);
  3736. break;
  3737. case RT5677_AIF4:
  3738. mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
  3739. val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
  3740. pre_div << RT5677_I2S_PD4_SFT;
  3741. regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
  3742. RT5677_I2S_DL_MASK, val_len);
  3743. regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
  3744. mask_clk, val_clk);
  3745. break;
  3746. default:
  3747. break;
  3748. }
  3749. return 0;
  3750. }
  3751. static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  3752. {
  3753. struct snd_soc_component *component = dai->component;
  3754. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3755. unsigned int reg_val = 0;
  3756. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  3757. case SND_SOC_DAIFMT_CBM_CFM:
  3758. rt5677->master[dai->id] = 1;
  3759. break;
  3760. case SND_SOC_DAIFMT_CBS_CFS:
  3761. reg_val |= RT5677_I2S_MS_S;
  3762. rt5677->master[dai->id] = 0;
  3763. break;
  3764. default:
  3765. return -EINVAL;
  3766. }
  3767. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  3768. case SND_SOC_DAIFMT_NB_NF:
  3769. break;
  3770. case SND_SOC_DAIFMT_IB_NF:
  3771. reg_val |= RT5677_I2S_BP_INV;
  3772. break;
  3773. default:
  3774. return -EINVAL;
  3775. }
  3776. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  3777. case SND_SOC_DAIFMT_I2S:
  3778. break;
  3779. case SND_SOC_DAIFMT_LEFT_J:
  3780. reg_val |= RT5677_I2S_DF_LEFT;
  3781. break;
  3782. case SND_SOC_DAIFMT_DSP_A:
  3783. reg_val |= RT5677_I2S_DF_PCM_A;
  3784. break;
  3785. case SND_SOC_DAIFMT_DSP_B:
  3786. reg_val |= RT5677_I2S_DF_PCM_B;
  3787. break;
  3788. default:
  3789. return -EINVAL;
  3790. }
  3791. switch (dai->id) {
  3792. case RT5677_AIF1:
  3793. regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
  3794. RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
  3795. RT5677_I2S_DF_MASK, reg_val);
  3796. break;
  3797. case RT5677_AIF2:
  3798. regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
  3799. RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
  3800. RT5677_I2S_DF_MASK, reg_val);
  3801. break;
  3802. case RT5677_AIF3:
  3803. regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
  3804. RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
  3805. RT5677_I2S_DF_MASK, reg_val);
  3806. break;
  3807. case RT5677_AIF4:
  3808. regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
  3809. RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
  3810. RT5677_I2S_DF_MASK, reg_val);
  3811. break;
  3812. default:
  3813. break;
  3814. }
  3815. return 0;
  3816. }
  3817. static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
  3818. int clk_id, unsigned int freq, int dir)
  3819. {
  3820. struct snd_soc_component *component = dai->component;
  3821. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3822. unsigned int reg_val = 0;
  3823. if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
  3824. return 0;
  3825. switch (clk_id) {
  3826. case RT5677_SCLK_S_MCLK:
  3827. reg_val |= RT5677_SCLK_SRC_MCLK;
  3828. break;
  3829. case RT5677_SCLK_S_PLL1:
  3830. reg_val |= RT5677_SCLK_SRC_PLL1;
  3831. break;
  3832. case RT5677_SCLK_S_RCCLK:
  3833. reg_val |= RT5677_SCLK_SRC_RCCLK;
  3834. break;
  3835. default:
  3836. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  3837. return -EINVAL;
  3838. }
  3839. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3840. RT5677_SCLK_SRC_MASK, reg_val);
  3841. rt5677->sysclk = freq;
  3842. rt5677->sysclk_src = clk_id;
  3843. dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  3844. return 0;
  3845. }
  3846. /**
  3847. * rt5677_pll_calc - Calcualte PLL M/N/K code.
  3848. * @freq_in: external clock provided to codec.
  3849. * @freq_out: target clock which codec works on.
  3850. * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
  3851. *
  3852. * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
  3853. *
  3854. * Returns 0 for success or negative error code.
  3855. */
  3856. static int rt5677_pll_calc(const unsigned int freq_in,
  3857. const unsigned int freq_out, struct rl6231_pll_code *pll_code)
  3858. {
  3859. if (RT5677_PLL_INP_MIN > freq_in)
  3860. return -EINVAL;
  3861. return rl6231_pll_calc(freq_in, freq_out, pll_code);
  3862. }
  3863. static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  3864. unsigned int freq_in, unsigned int freq_out)
  3865. {
  3866. struct snd_soc_component *component = dai->component;
  3867. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3868. struct rl6231_pll_code pll_code;
  3869. int ret;
  3870. if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
  3871. freq_out == rt5677->pll_out)
  3872. return 0;
  3873. if (!freq_in || !freq_out) {
  3874. dev_dbg(component->dev, "PLL disabled\n");
  3875. rt5677->pll_in = 0;
  3876. rt5677->pll_out = 0;
  3877. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3878. RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
  3879. return 0;
  3880. }
  3881. switch (source) {
  3882. case RT5677_PLL1_S_MCLK:
  3883. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3884. RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
  3885. break;
  3886. case RT5677_PLL1_S_BCLK1:
  3887. case RT5677_PLL1_S_BCLK2:
  3888. case RT5677_PLL1_S_BCLK3:
  3889. case RT5677_PLL1_S_BCLK4:
  3890. switch (dai->id) {
  3891. case RT5677_AIF1:
  3892. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3893. RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
  3894. break;
  3895. case RT5677_AIF2:
  3896. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3897. RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
  3898. break;
  3899. case RT5677_AIF3:
  3900. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3901. RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
  3902. break;
  3903. case RT5677_AIF4:
  3904. regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
  3905. RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
  3906. break;
  3907. default:
  3908. break;
  3909. }
  3910. break;
  3911. default:
  3912. dev_err(component->dev, "Unknown PLL source %d\n", source);
  3913. return -EINVAL;
  3914. }
  3915. ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
  3916. if (ret < 0) {
  3917. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  3918. return ret;
  3919. }
  3920. dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
  3921. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  3922. pll_code.n_code, pll_code.k_code);
  3923. regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
  3924. pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
  3925. regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
  3926. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
  3927. pll_code.m_bp << RT5677_PLL_M_BP_SFT);
  3928. rt5677->pll_in = freq_in;
  3929. rt5677->pll_out = freq_out;
  3930. rt5677->pll_src = source;
  3931. return 0;
  3932. }
  3933. static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  3934. unsigned int rx_mask, int slots, int slot_width)
  3935. {
  3936. struct snd_soc_component *component = dai->component;
  3937. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3938. unsigned int val = 0, slot_width_25 = 0;
  3939. if (rx_mask || tx_mask)
  3940. val |= (1 << 12);
  3941. switch (slots) {
  3942. case 4:
  3943. val |= (1 << 10);
  3944. break;
  3945. case 6:
  3946. val |= (2 << 10);
  3947. break;
  3948. case 8:
  3949. val |= (3 << 10);
  3950. break;
  3951. case 2:
  3952. default:
  3953. break;
  3954. }
  3955. switch (slot_width) {
  3956. case 20:
  3957. val |= (1 << 8);
  3958. break;
  3959. case 25:
  3960. slot_width_25 = 0x8080;
  3961. fallthrough;
  3962. case 24:
  3963. val |= (2 << 8);
  3964. break;
  3965. case 32:
  3966. val |= (3 << 8);
  3967. break;
  3968. case 16:
  3969. default:
  3970. break;
  3971. }
  3972. switch (dai->id) {
  3973. case RT5677_AIF1:
  3974. regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
  3975. val);
  3976. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
  3977. slot_width_25);
  3978. break;
  3979. case RT5677_AIF2:
  3980. regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
  3981. val);
  3982. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
  3983. slot_width_25);
  3984. break;
  3985. default:
  3986. break;
  3987. }
  3988. return 0;
  3989. }
  3990. static int rt5677_set_bias_level(struct snd_soc_component *component,
  3991. enum snd_soc_bias_level level)
  3992. {
  3993. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  3994. enum snd_soc_bias_level prev_bias =
  3995. snd_soc_component_get_bias_level(component);
  3996. switch (level) {
  3997. case SND_SOC_BIAS_ON:
  3998. break;
  3999. case SND_SOC_BIAS_PREPARE:
  4000. if (prev_bias == SND_SOC_BIAS_STANDBY) {
  4001. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
  4002. RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
  4003. 5 << RT5677_LDO1_SEL_SFT |
  4004. 5 << RT5677_LDO2_SEL_SFT);
  4005. regmap_update_bits(rt5677->regmap,
  4006. RT5677_PR_BASE + RT5677_BIAS_CUR4,
  4007. 0x0f00, 0x0f00);
  4008. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
  4009. RT5677_PWR_FV1 | RT5677_PWR_FV2 |
  4010. RT5677_PWR_VREF1 | RT5677_PWR_MB |
  4011. RT5677_PWR_BG | RT5677_PWR_VREF2,
  4012. RT5677_PWR_VREF1 | RT5677_PWR_MB |
  4013. RT5677_PWR_BG | RT5677_PWR_VREF2);
  4014. rt5677->is_vref_slow = false;
  4015. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  4016. RT5677_PWR_CORE, RT5677_PWR_CORE);
  4017. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
  4018. 0x1, 0x1);
  4019. }
  4020. break;
  4021. case SND_SOC_BIAS_STANDBY:
  4022. if (prev_bias == SND_SOC_BIAS_OFF &&
  4023. rt5677->dsp_vad_en_request) {
  4024. /* Re-enable the DSP if it was turned off at suspend */
  4025. rt5677->dsp_vad_en = true;
  4026. /* The delay is to wait for MCLK */
  4027. schedule_delayed_work(&rt5677->dsp_work,
  4028. msecs_to_jiffies(1000));
  4029. }
  4030. break;
  4031. case SND_SOC_BIAS_OFF:
  4032. flush_delayed_work(&rt5677->dsp_work);
  4033. if (rt5677->is_dsp_mode) {
  4034. /* Turn off the DSP before suspend */
  4035. rt5677->dsp_vad_en = false;
  4036. schedule_delayed_work(&rt5677->dsp_work, 0);
  4037. flush_delayed_work(&rt5677->dsp_work);
  4038. }
  4039. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
  4040. regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
  4041. regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
  4042. 2 << RT5677_LDO1_SEL_SFT |
  4043. 2 << RT5677_LDO2_SEL_SFT);
  4044. regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
  4045. RT5677_PWR_CORE, 0);
  4046. regmap_update_bits(rt5677->regmap,
  4047. RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
  4048. if (rt5677->dsp_vad_en)
  4049. rt5677_set_dsp_vad(component, true);
  4050. break;
  4051. default:
  4052. break;
  4053. }
  4054. return 0;
  4055. }
  4056. #ifdef CONFIG_GPIOLIB
  4057. static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  4058. {
  4059. struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
  4060. switch (offset) {
  4061. case RT5677_GPIO1 ... RT5677_GPIO5:
  4062. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
  4063. 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
  4064. break;
  4065. case RT5677_GPIO6:
  4066. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
  4067. RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
  4068. break;
  4069. default:
  4070. break;
  4071. }
  4072. }
  4073. static int rt5677_gpio_direction_out(struct gpio_chip *chip,
  4074. unsigned offset, int value)
  4075. {
  4076. struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
  4077. switch (offset) {
  4078. case RT5677_GPIO1 ... RT5677_GPIO5:
  4079. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
  4080. 0x3 << (offset * 3 + 1),
  4081. (0x2 | !!value) << (offset * 3 + 1));
  4082. break;
  4083. case RT5677_GPIO6:
  4084. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
  4085. RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
  4086. RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
  4087. break;
  4088. default:
  4089. break;
  4090. }
  4091. return 0;
  4092. }
  4093. static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
  4094. {
  4095. struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
  4096. int value, ret;
  4097. ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
  4098. if (ret < 0)
  4099. return ret;
  4100. return (value & (0x1 << offset)) >> offset;
  4101. }
  4102. static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  4103. {
  4104. struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
  4105. switch (offset) {
  4106. case RT5677_GPIO1 ... RT5677_GPIO5:
  4107. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
  4108. 0x1 << (offset * 3 + 2), 0x0);
  4109. break;
  4110. case RT5677_GPIO6:
  4111. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
  4112. RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
  4113. break;
  4114. default:
  4115. break;
  4116. }
  4117. return 0;
  4118. }
  4119. /** Configures the gpio as
  4120. * 0 - floating
  4121. * 1 - pull down
  4122. * 2 - pull up
  4123. */
  4124. static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
  4125. int value)
  4126. {
  4127. int shift;
  4128. switch (offset) {
  4129. case RT5677_GPIO1 ... RT5677_GPIO2:
  4130. shift = 2 * (1 - offset);
  4131. regmap_update_bits(rt5677->regmap,
  4132. RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
  4133. 0x3 << shift,
  4134. (value & 0x3) << shift);
  4135. break;
  4136. case RT5677_GPIO3 ... RT5677_GPIO6:
  4137. shift = 2 * (9 - offset);
  4138. regmap_update_bits(rt5677->regmap,
  4139. RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
  4140. 0x3 << shift,
  4141. (value & 0x3) << shift);
  4142. break;
  4143. default:
  4144. break;
  4145. }
  4146. }
  4147. static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
  4148. {
  4149. struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
  4150. int irq;
  4151. if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
  4152. (rt5677->pdata.jd1_gpio == 2 &&
  4153. offset == RT5677_GPIO2) ||
  4154. (rt5677->pdata.jd1_gpio == 3 &&
  4155. offset == RT5677_GPIO3)) {
  4156. irq = RT5677_IRQ_JD1;
  4157. } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
  4158. (rt5677->pdata.jd2_gpio == 2 &&
  4159. offset == RT5677_GPIO5) ||
  4160. (rt5677->pdata.jd2_gpio == 3 &&
  4161. offset == RT5677_GPIO6)) {
  4162. irq = RT5677_IRQ_JD2;
  4163. } else if ((rt5677->pdata.jd3_gpio == 1 &&
  4164. offset == RT5677_GPIO4) ||
  4165. (rt5677->pdata.jd3_gpio == 2 &&
  4166. offset == RT5677_GPIO5) ||
  4167. (rt5677->pdata.jd3_gpio == 3 &&
  4168. offset == RT5677_GPIO6)) {
  4169. irq = RT5677_IRQ_JD3;
  4170. } else {
  4171. return -ENXIO;
  4172. }
  4173. return irq_create_mapping(rt5677->domain, irq);
  4174. }
  4175. static const struct gpio_chip rt5677_template_chip = {
  4176. .label = RT5677_DRV_NAME,
  4177. .owner = THIS_MODULE,
  4178. .direction_output = rt5677_gpio_direction_out,
  4179. .set = rt5677_gpio_set,
  4180. .direction_input = rt5677_gpio_direction_in,
  4181. .get = rt5677_gpio_get,
  4182. .to_irq = rt5677_to_irq,
  4183. .can_sleep = 1,
  4184. };
  4185. static void rt5677_init_gpio(struct i2c_client *i2c)
  4186. {
  4187. struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
  4188. int ret;
  4189. rt5677->gpio_chip = rt5677_template_chip;
  4190. rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
  4191. rt5677->gpio_chip.parent = &i2c->dev;
  4192. rt5677->gpio_chip.base = -1;
  4193. ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
  4194. if (ret != 0)
  4195. dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
  4196. }
  4197. static void rt5677_free_gpio(struct i2c_client *i2c)
  4198. {
  4199. struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
  4200. gpiochip_remove(&rt5677->gpio_chip);
  4201. }
  4202. #else
  4203. static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
  4204. int value)
  4205. {
  4206. }
  4207. static void rt5677_init_gpio(struct i2c_client *i2c)
  4208. {
  4209. }
  4210. static void rt5677_free_gpio(struct i2c_client *i2c)
  4211. {
  4212. }
  4213. #endif
  4214. static int rt5677_probe(struct snd_soc_component *component)
  4215. {
  4216. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  4217. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  4218. int i;
  4219. rt5677->component = component;
  4220. if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
  4221. snd_soc_dapm_add_routes(dapm,
  4222. rt5677_dmic2_clk_2,
  4223. ARRAY_SIZE(rt5677_dmic2_clk_2));
  4224. } else { /*use dmic1 clock by default*/
  4225. snd_soc_dapm_add_routes(dapm,
  4226. rt5677_dmic2_clk_1,
  4227. ARRAY_SIZE(rt5677_dmic2_clk_1));
  4228. }
  4229. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  4230. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
  4231. ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020);
  4232. regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
  4233. RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO);
  4234. for (i = 0; i < RT5677_GPIO_NUM; i++)
  4235. rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
  4236. mutex_init(&rt5677->dsp_cmd_lock);
  4237. mutex_init(&rt5677->dsp_pri_lock);
  4238. return 0;
  4239. }
  4240. static void rt5677_remove(struct snd_soc_component *component)
  4241. {
  4242. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  4243. cancel_delayed_work_sync(&rt5677->dsp_work);
  4244. regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
  4245. gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
  4246. gpiod_set_value_cansleep(rt5677->reset_pin, 1);
  4247. }
  4248. #ifdef CONFIG_PM
  4249. static int rt5677_suspend(struct snd_soc_component *component)
  4250. {
  4251. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  4252. if (rt5677->irq) {
  4253. cancel_delayed_work_sync(&rt5677->resume_irq_check);
  4254. disable_irq(rt5677->irq);
  4255. }
  4256. if (!rt5677->dsp_vad_en) {
  4257. regcache_cache_only(rt5677->regmap, true);
  4258. regcache_mark_dirty(rt5677->regmap);
  4259. gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
  4260. gpiod_set_value_cansleep(rt5677->reset_pin, 1);
  4261. }
  4262. return 0;
  4263. }
  4264. static int rt5677_resume(struct snd_soc_component *component)
  4265. {
  4266. struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  4267. if (!rt5677->dsp_vad_en) {
  4268. rt5677->pll_src = 0;
  4269. rt5677->pll_in = 0;
  4270. rt5677->pll_out = 0;
  4271. gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
  4272. gpiod_set_value_cansleep(rt5677->reset_pin, 0);
  4273. if (rt5677->pow_ldo2 || rt5677->reset_pin)
  4274. msleep(10);
  4275. regcache_cache_only(rt5677->regmap, false);
  4276. regcache_sync(rt5677->regmap);
  4277. }
  4278. if (rt5677->irq) {
  4279. enable_irq(rt5677->irq);
  4280. schedule_delayed_work(&rt5677->resume_irq_check, 0);
  4281. }
  4282. return 0;
  4283. }
  4284. #else
  4285. #define rt5677_suspend NULL
  4286. #define rt5677_resume NULL
  4287. #endif
  4288. static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
  4289. {
  4290. struct i2c_client *client = context;
  4291. struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
  4292. if (rt5677->is_dsp_mode) {
  4293. if (reg > 0xff) {
  4294. mutex_lock(&rt5677->dsp_pri_lock);
  4295. rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
  4296. reg & 0xff);
  4297. rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
  4298. mutex_unlock(&rt5677->dsp_pri_lock);
  4299. } else {
  4300. rt5677_dsp_mode_i2c_read(rt5677, reg, val);
  4301. }
  4302. } else {
  4303. regmap_read(rt5677->regmap_physical, reg, val);
  4304. }
  4305. return 0;
  4306. }
  4307. static int rt5677_write(void *context, unsigned int reg, unsigned int val)
  4308. {
  4309. struct i2c_client *client = context;
  4310. struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
  4311. if (rt5677->is_dsp_mode) {
  4312. if (reg > 0xff) {
  4313. mutex_lock(&rt5677->dsp_pri_lock);
  4314. rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
  4315. reg & 0xff);
  4316. rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
  4317. val);
  4318. mutex_unlock(&rt5677->dsp_pri_lock);
  4319. } else {
  4320. rt5677_dsp_mode_i2c_write(rt5677, reg, val);
  4321. }
  4322. } else {
  4323. regmap_write(rt5677->regmap_physical, reg, val);
  4324. }
  4325. return 0;
  4326. }
  4327. #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
  4328. #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  4329. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  4330. static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
  4331. .hw_params = rt5677_hw_params,
  4332. .set_fmt = rt5677_set_dai_fmt,
  4333. .set_sysclk = rt5677_set_dai_sysclk,
  4334. .set_pll = rt5677_set_dai_pll,
  4335. .set_tdm_slot = rt5677_set_tdm_slot,
  4336. };
  4337. static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = {
  4338. .set_sysclk = rt5677_set_dai_sysclk,
  4339. .set_pll = rt5677_set_dai_pll,
  4340. };
  4341. static struct snd_soc_dai_driver rt5677_dai[] = {
  4342. {
  4343. .name = "rt5677-aif1",
  4344. .id = RT5677_AIF1,
  4345. .playback = {
  4346. .stream_name = "AIF1 Playback",
  4347. .channels_min = 1,
  4348. .channels_max = 2,
  4349. .rates = RT5677_STEREO_RATES,
  4350. .formats = RT5677_FORMATS,
  4351. },
  4352. .capture = {
  4353. .stream_name = "AIF1 Capture",
  4354. .channels_min = 1,
  4355. .channels_max = 2,
  4356. .rates = RT5677_STEREO_RATES,
  4357. .formats = RT5677_FORMATS,
  4358. },
  4359. .ops = &rt5677_aif_dai_ops,
  4360. },
  4361. {
  4362. .name = "rt5677-aif2",
  4363. .id = RT5677_AIF2,
  4364. .playback = {
  4365. .stream_name = "AIF2 Playback",
  4366. .channels_min = 1,
  4367. .channels_max = 2,
  4368. .rates = RT5677_STEREO_RATES,
  4369. .formats = RT5677_FORMATS,
  4370. },
  4371. .capture = {
  4372. .stream_name = "AIF2 Capture",
  4373. .channels_min = 1,
  4374. .channels_max = 2,
  4375. .rates = RT5677_STEREO_RATES,
  4376. .formats = RT5677_FORMATS,
  4377. },
  4378. .ops = &rt5677_aif_dai_ops,
  4379. },
  4380. {
  4381. .name = "rt5677-aif3",
  4382. .id = RT5677_AIF3,
  4383. .playback = {
  4384. .stream_name = "AIF3 Playback",
  4385. .channels_min = 1,
  4386. .channels_max = 2,
  4387. .rates = RT5677_STEREO_RATES,
  4388. .formats = RT5677_FORMATS,
  4389. },
  4390. .capture = {
  4391. .stream_name = "AIF3 Capture",
  4392. .channels_min = 1,
  4393. .channels_max = 2,
  4394. .rates = RT5677_STEREO_RATES,
  4395. .formats = RT5677_FORMATS,
  4396. },
  4397. .ops = &rt5677_aif_dai_ops,
  4398. },
  4399. {
  4400. .name = "rt5677-aif4",
  4401. .id = RT5677_AIF4,
  4402. .playback = {
  4403. .stream_name = "AIF4 Playback",
  4404. .channels_min = 1,
  4405. .channels_max = 2,
  4406. .rates = RT5677_STEREO_RATES,
  4407. .formats = RT5677_FORMATS,
  4408. },
  4409. .capture = {
  4410. .stream_name = "AIF4 Capture",
  4411. .channels_min = 1,
  4412. .channels_max = 2,
  4413. .rates = RT5677_STEREO_RATES,
  4414. .formats = RT5677_FORMATS,
  4415. },
  4416. .ops = &rt5677_aif_dai_ops,
  4417. },
  4418. {
  4419. .name = "rt5677-slimbus",
  4420. .id = RT5677_AIF5,
  4421. .playback = {
  4422. .stream_name = "SLIMBus Playback",
  4423. .channels_min = 1,
  4424. .channels_max = 2,
  4425. .rates = RT5677_STEREO_RATES,
  4426. .formats = RT5677_FORMATS,
  4427. },
  4428. .capture = {
  4429. .stream_name = "SLIMBus Capture",
  4430. .channels_min = 1,
  4431. .channels_max = 2,
  4432. .rates = RT5677_STEREO_RATES,
  4433. .formats = RT5677_FORMATS,
  4434. },
  4435. .ops = &rt5677_aif_dai_ops,
  4436. },
  4437. {
  4438. .name = "rt5677-dspbuffer",
  4439. .id = RT5677_DSPBUFF,
  4440. .capture = {
  4441. .stream_name = "DSP Buffer",
  4442. .channels_min = 1,
  4443. .channels_max = 1,
  4444. .rates = SNDRV_PCM_RATE_16000,
  4445. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  4446. },
  4447. .ops = &rt5677_dsp_dai_ops,
  4448. },
  4449. };
  4450. static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
  4451. .name = RT5677_DRV_NAME,
  4452. .probe = rt5677_probe,
  4453. .remove = rt5677_remove,
  4454. .suspend = rt5677_suspend,
  4455. .resume = rt5677_resume,
  4456. .set_bias_level = rt5677_set_bias_level,
  4457. .controls = rt5677_snd_controls,
  4458. .num_controls = ARRAY_SIZE(rt5677_snd_controls),
  4459. .dapm_widgets = rt5677_dapm_widgets,
  4460. .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
  4461. .dapm_routes = rt5677_dapm_routes,
  4462. .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
  4463. .use_pmdown_time = 1,
  4464. .endianness = 1,
  4465. .non_legacy_dai_naming = 1,
  4466. };
  4467. static const struct regmap_config rt5677_regmap_physical = {
  4468. .name = "physical",
  4469. .reg_bits = 8,
  4470. .val_bits = 16,
  4471. .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
  4472. RT5677_PR_SPACING),
  4473. .readable_reg = rt5677_readable_register,
  4474. .cache_type = REGCACHE_NONE,
  4475. .ranges = rt5677_ranges,
  4476. .num_ranges = ARRAY_SIZE(rt5677_ranges),
  4477. };
  4478. static const struct regmap_config rt5677_regmap = {
  4479. .reg_bits = 8,
  4480. .val_bits = 16,
  4481. .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
  4482. RT5677_PR_SPACING),
  4483. .volatile_reg = rt5677_volatile_register,
  4484. .readable_reg = rt5677_readable_register,
  4485. .reg_read = rt5677_read,
  4486. .reg_write = rt5677_write,
  4487. .cache_type = REGCACHE_RBTREE,
  4488. .reg_defaults = rt5677_reg,
  4489. .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
  4490. .ranges = rt5677_ranges,
  4491. .num_ranges = ARRAY_SIZE(rt5677_ranges),
  4492. };
  4493. static const struct of_device_id rt5677_of_match[] = {
  4494. { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
  4495. { }
  4496. };
  4497. MODULE_DEVICE_TABLE(of, rt5677_of_match);
  4498. static const struct acpi_device_id rt5677_acpi_match[] = {
  4499. { "RT5677CE", RT5677 },
  4500. { }
  4501. };
  4502. MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
  4503. static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
  4504. struct device *dev)
  4505. {
  4506. u32 val;
  4507. rt5677->pdata.in1_diff =
  4508. device_property_read_bool(dev, "IN1") ||
  4509. device_property_read_bool(dev, "realtek,in1-differential");
  4510. rt5677->pdata.in2_diff =
  4511. device_property_read_bool(dev, "IN2") ||
  4512. device_property_read_bool(dev, "realtek,in2-differential");
  4513. rt5677->pdata.lout1_diff =
  4514. device_property_read_bool(dev, "OUT1") ||
  4515. device_property_read_bool(dev, "realtek,lout1-differential");
  4516. rt5677->pdata.lout2_diff =
  4517. device_property_read_bool(dev, "OUT2") ||
  4518. device_property_read_bool(dev, "realtek,lout2-differential");
  4519. rt5677->pdata.lout3_diff =
  4520. device_property_read_bool(dev, "OUT3") ||
  4521. device_property_read_bool(dev, "realtek,lout3-differential");
  4522. device_property_read_u8_array(dev, "realtek,gpio-config",
  4523. rt5677->pdata.gpio_config,
  4524. RT5677_GPIO_NUM);
  4525. if (!device_property_read_u32(dev, "DCLK", &val) ||
  4526. !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val))
  4527. rt5677->pdata.dmic2_clk_pin = val;
  4528. if (!device_property_read_u32(dev, "JD1", &val) ||
  4529. !device_property_read_u32(dev, "realtek,jd1-gpio", &val))
  4530. rt5677->pdata.jd1_gpio = val;
  4531. if (!device_property_read_u32(dev, "JD2", &val) ||
  4532. !device_property_read_u32(dev, "realtek,jd2-gpio", &val))
  4533. rt5677->pdata.jd2_gpio = val;
  4534. if (!device_property_read_u32(dev, "JD3", &val) ||
  4535. !device_property_read_u32(dev, "realtek,jd3-gpio", &val))
  4536. rt5677->pdata.jd3_gpio = val;
  4537. }
  4538. struct rt5677_irq_desc {
  4539. unsigned int enable_mask;
  4540. unsigned int status_mask;
  4541. unsigned int polarity_mask;
  4542. };
  4543. static const struct rt5677_irq_desc rt5677_irq_descs[] = {
  4544. [RT5677_IRQ_JD1] = {
  4545. .enable_mask = RT5677_EN_IRQ_GPIO_JD1,
  4546. .status_mask = RT5677_STA_GPIO_JD1,
  4547. .polarity_mask = RT5677_INV_GPIO_JD1,
  4548. },
  4549. [RT5677_IRQ_JD2] = {
  4550. .enable_mask = RT5677_EN_IRQ_GPIO_JD2,
  4551. .status_mask = RT5677_STA_GPIO_JD2,
  4552. .polarity_mask = RT5677_INV_GPIO_JD2,
  4553. },
  4554. [RT5677_IRQ_JD3] = {
  4555. .enable_mask = RT5677_EN_IRQ_GPIO_JD3,
  4556. .status_mask = RT5677_STA_GPIO_JD3,
  4557. .polarity_mask = RT5677_INV_GPIO_JD3,
  4558. },
  4559. };
  4560. static bool rt5677_check_hotword(struct rt5677_priv *rt5677)
  4561. {
  4562. int reg_gpio;
  4563. if (!rt5677->is_dsp_mode)
  4564. return false;
  4565. if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, &reg_gpio))
  4566. return false;
  4567. /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */
  4568. if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ)
  4569. return false;
  4570. /* Set GPIO1 pin back to be IRQ output for jack detect */
  4571. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
  4572. RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
  4573. rt5677_spi_hotword_detected();
  4574. return true;
  4575. }
  4576. static irqreturn_t rt5677_irq(int unused, void *data)
  4577. {
  4578. struct rt5677_priv *rt5677 = data;
  4579. int ret = 0, loop, i, reg_irq, virq;
  4580. bool irq_fired = false;
  4581. mutex_lock(&rt5677->irq_lock);
  4582. /*
  4583. * Loop to handle interrupts until the last i2c read shows no pending
  4584. * irqs. The interrupt line is shared by multiple interrupt sources.
  4585. * After the regmap_read() below, a new interrupt source line may
  4586. * become high before the regmap_write() finishes, so there isn't a
  4587. * rising edge on the shared interrupt line for the new interrupt. Thus,
  4588. * the loop is needed to avoid missing irqs.
  4589. *
  4590. * A safeguard of 20 loops is used to avoid hanging in the irq handler
  4591. * if there is something wrong with the interrupt status update. The
  4592. * interrupt sources here are audio jack plug/unplug events which
  4593. * shouldn't happen at a high frequency for a long period of time.
  4594. * Empirically, more than 3 loops have never been seen.
  4595. */
  4596. for (loop = 0; loop < 20; loop++) {
  4597. /* Read interrupt status */
  4598. ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, &reg_irq);
  4599. if (ret) {
  4600. dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
  4601. ret);
  4602. goto exit;
  4603. }
  4604. irq_fired = false;
  4605. for (i = 0; i < RT5677_IRQ_NUM; i++) {
  4606. if (reg_irq & rt5677_irq_descs[i].status_mask) {
  4607. irq_fired = true;
  4608. virq = irq_find_mapping(rt5677->domain, i);
  4609. if (virq)
  4610. handle_nested_irq(virq);
  4611. /* Clear the interrupt by flipping the polarity
  4612. * of the interrupt source line that fired
  4613. */
  4614. reg_irq ^= rt5677_irq_descs[i].polarity_mask;
  4615. }
  4616. }
  4617. /* Exit the loop only when we know for sure that GPIO1 pin
  4618. * was low at some point since irq_lock was acquired. Any event
  4619. * after that point creates a rising edge that triggers another
  4620. * call to rt5677_irq().
  4621. */
  4622. if (!irq_fired && !rt5677_check_hotword(rt5677))
  4623. goto exit;
  4624. ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
  4625. if (ret) {
  4626. dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
  4627. ret);
  4628. goto exit;
  4629. }
  4630. }
  4631. exit:
  4632. WARN_ON_ONCE(loop == 20);
  4633. mutex_unlock(&rt5677->irq_lock);
  4634. if (irq_fired)
  4635. return IRQ_HANDLED;
  4636. else
  4637. return IRQ_NONE;
  4638. }
  4639. static void rt5677_resume_irq_check(struct work_struct *work)
  4640. {
  4641. int i, virq;
  4642. struct rt5677_priv *rt5677 =
  4643. container_of(work, struct rt5677_priv, resume_irq_check.work);
  4644. /* This is needed to check and clear the interrupt status register
  4645. * at resume. If the headset is plugged/unplugged when the device is
  4646. * fully suspended, there won't be a rising edge at resume to trigger
  4647. * the interrupt. Without this, we miss the next unplug/plug event.
  4648. */
  4649. rt5677_irq(0, rt5677);
  4650. /* Call all enabled jack detect irq handlers again. This is needed in
  4651. * addition to the above check for a corner case caused by jack gpio
  4652. * debounce. After codec irq is disabled at suspend, the delayed work
  4653. * scheduled by soc-jack may run and read wrong jack gpio values, since
  4654. * the regmap is in cache only mode. At resume, there is no irq because
  4655. * rt5677_irq has already ran and cleared the irq status at suspend.
  4656. * Without this explicit check, unplug the headset right after suspend
  4657. * starts, then after resume the headset is still shown as plugged in.
  4658. */
  4659. mutex_lock(&rt5677->irq_lock);
  4660. for (i = 0; i < RT5677_IRQ_NUM; i++) {
  4661. if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
  4662. virq = irq_find_mapping(rt5677->domain, i);
  4663. if (virq)
  4664. handle_nested_irq(virq);
  4665. }
  4666. }
  4667. mutex_unlock(&rt5677->irq_lock);
  4668. }
  4669. static void rt5677_irq_bus_lock(struct irq_data *data)
  4670. {
  4671. struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
  4672. mutex_lock(&rt5677->irq_lock);
  4673. }
  4674. static void rt5677_irq_bus_sync_unlock(struct irq_data *data)
  4675. {
  4676. struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
  4677. // Set the enable/disable bits for the jack detect IRQs.
  4678. regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
  4679. RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 |
  4680. RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
  4681. mutex_unlock(&rt5677->irq_lock);
  4682. }
  4683. static void rt5677_irq_enable(struct irq_data *data)
  4684. {
  4685. struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
  4686. rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
  4687. }
  4688. static void rt5677_irq_disable(struct irq_data *data)
  4689. {
  4690. struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
  4691. rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
  4692. }
  4693. static struct irq_chip rt5677_irq_chip = {
  4694. .name = "rt5677_irq_chip",
  4695. .irq_bus_lock = rt5677_irq_bus_lock,
  4696. .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock,
  4697. .irq_disable = rt5677_irq_disable,
  4698. .irq_enable = rt5677_irq_enable,
  4699. };
  4700. static int rt5677_irq_map(struct irq_domain *h, unsigned int virq,
  4701. irq_hw_number_t hw)
  4702. {
  4703. struct rt5677_priv *rt5677 = h->host_data;
  4704. irq_set_chip_data(virq, rt5677);
  4705. irq_set_chip(virq, &rt5677_irq_chip);
  4706. irq_set_nested_thread(virq, 1);
  4707. irq_set_noprobe(virq);
  4708. return 0;
  4709. }
  4710. static const struct irq_domain_ops rt5677_domain_ops = {
  4711. .map = rt5677_irq_map,
  4712. .xlate = irq_domain_xlate_twocell,
  4713. };
  4714. static int rt5677_init_irq(struct i2c_client *i2c)
  4715. {
  4716. int ret;
  4717. struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
  4718. unsigned int jd_mask = 0, jd_val = 0;
  4719. if (!rt5677->pdata.jd1_gpio &&
  4720. !rt5677->pdata.jd2_gpio &&
  4721. !rt5677->pdata.jd3_gpio)
  4722. return 0;
  4723. if (!i2c->irq) {
  4724. dev_err(&i2c->dev, "No interrupt specified\n");
  4725. return -EINVAL;
  4726. }
  4727. mutex_init(&rt5677->irq_lock);
  4728. INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
  4729. /*
  4730. * Select RC as the debounce clock so that GPIO works even when
  4731. * MCLK is gated which happens when there is no audio stream
  4732. * (SND_SOC_BIAS_OFF).
  4733. */
  4734. regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
  4735. RT5677_IRQ_DEBOUNCE_SEL_MASK,
  4736. RT5677_IRQ_DEBOUNCE_SEL_RC);
  4737. /* Enable auto power on RC when GPIO states are changed */
  4738. regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
  4739. /* Select and enable jack detection sources per platform data */
  4740. if (rt5677->pdata.jd1_gpio) {
  4741. jd_mask |= RT5677_SEL_GPIO_JD1_MASK;
  4742. jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
  4743. }
  4744. if (rt5677->pdata.jd2_gpio) {
  4745. jd_mask |= RT5677_SEL_GPIO_JD2_MASK;
  4746. jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
  4747. }
  4748. if (rt5677->pdata.jd3_gpio) {
  4749. jd_mask |= RT5677_SEL_GPIO_JD3_MASK;
  4750. jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
  4751. }
  4752. regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
  4753. /* Set GPIO1 pin to be IRQ output */
  4754. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
  4755. RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
  4756. /* Ready to listen for interrupts */
  4757. rt5677->domain = irq_domain_add_linear(i2c->dev.of_node,
  4758. RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
  4759. if (!rt5677->domain) {
  4760. dev_err(&i2c->dev, "Failed to create IRQ domain\n");
  4761. return -ENOMEM;
  4762. }
  4763. ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
  4764. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  4765. "rt5677", rt5677);
  4766. if (ret)
  4767. dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
  4768. rt5677->irq = i2c->irq;
  4769. return ret;
  4770. }
  4771. static int rt5677_i2c_probe(struct i2c_client *i2c)
  4772. {
  4773. struct rt5677_priv *rt5677;
  4774. int ret;
  4775. unsigned int val;
  4776. rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
  4777. GFP_KERNEL);
  4778. if (rt5677 == NULL)
  4779. return -ENOMEM;
  4780. rt5677->dev = &i2c->dev;
  4781. rt5677->set_dsp_vad = rt5677_set_dsp_vad;
  4782. INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
  4783. i2c_set_clientdata(i2c, rt5677);
  4784. if (i2c->dev.of_node) {
  4785. const struct of_device_id *match_id;
  4786. match_id = of_match_device(rt5677_of_match, &i2c->dev);
  4787. if (match_id)
  4788. rt5677->type = (enum rt5677_type)match_id->data;
  4789. } else if (ACPI_HANDLE(&i2c->dev)) {
  4790. const struct acpi_device_id *acpi_id;
  4791. acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
  4792. if (acpi_id)
  4793. rt5677->type = (enum rt5677_type)acpi_id->driver_data;
  4794. } else {
  4795. return -EINVAL;
  4796. }
  4797. rt5677_read_device_properties(rt5677, &i2c->dev);
  4798. /* pow-ldo2 and reset are optional. The codec pins may be statically
  4799. * connected on the board without gpios. If the gpio device property
  4800. * isn't specified, devm_gpiod_get_optional returns NULL.
  4801. */
  4802. rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
  4803. "realtek,pow-ldo2", GPIOD_OUT_HIGH);
  4804. if (IS_ERR(rt5677->pow_ldo2)) {
  4805. ret = PTR_ERR(rt5677->pow_ldo2);
  4806. dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
  4807. return ret;
  4808. }
  4809. rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
  4810. "realtek,reset", GPIOD_OUT_LOW);
  4811. if (IS_ERR(rt5677->reset_pin)) {
  4812. ret = PTR_ERR(rt5677->reset_pin);
  4813. dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
  4814. return ret;
  4815. }
  4816. if (rt5677->pow_ldo2 || rt5677->reset_pin) {
  4817. /* Wait a while until I2C bus becomes available. The datasheet
  4818. * does not specify the exact we should wait but startup
  4819. * sequence mentiones at least a few milliseconds.
  4820. */
  4821. msleep(10);
  4822. }
  4823. rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
  4824. &rt5677_regmap_physical);
  4825. if (IS_ERR(rt5677->regmap_physical)) {
  4826. ret = PTR_ERR(rt5677->regmap_physical);
  4827. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  4828. ret);
  4829. return ret;
  4830. }
  4831. rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
  4832. if (IS_ERR(rt5677->regmap)) {
  4833. ret = PTR_ERR(rt5677->regmap);
  4834. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  4835. ret);
  4836. return ret;
  4837. }
  4838. regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
  4839. if (val != RT5677_DEVICE_ID) {
  4840. dev_err(&i2c->dev,
  4841. "Device with ID register %#x is not rt5677\n", val);
  4842. return -ENODEV;
  4843. }
  4844. regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
  4845. ret = regmap_register_patch(rt5677->regmap, init_list,
  4846. ARRAY_SIZE(init_list));
  4847. if (ret != 0)
  4848. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  4849. if (rt5677->pdata.in1_diff)
  4850. regmap_update_bits(rt5677->regmap, RT5677_IN1,
  4851. RT5677_IN_DF1, RT5677_IN_DF1);
  4852. if (rt5677->pdata.in2_diff)
  4853. regmap_update_bits(rt5677->regmap, RT5677_IN1,
  4854. RT5677_IN_DF2, RT5677_IN_DF2);
  4855. if (rt5677->pdata.lout1_diff)
  4856. regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
  4857. RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
  4858. if (rt5677->pdata.lout2_diff)
  4859. regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
  4860. RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
  4861. if (rt5677->pdata.lout3_diff)
  4862. regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
  4863. RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
  4864. if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
  4865. regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
  4866. RT5677_GPIO5_FUNC_MASK,
  4867. RT5677_GPIO5_FUNC_DMIC);
  4868. regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
  4869. RT5677_GPIO5_DIR_MASK,
  4870. RT5677_GPIO5_DIR_OUT);
  4871. }
  4872. if (rt5677->pdata.micbias1_vdd_3v3)
  4873. regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
  4874. RT5677_MICBIAS1_CTRL_VDD_MASK,
  4875. RT5677_MICBIAS1_CTRL_VDD_3_3V);
  4876. rt5677_init_gpio(i2c);
  4877. ret = rt5677_init_irq(i2c);
  4878. if (ret)
  4879. dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
  4880. return devm_snd_soc_register_component(&i2c->dev,
  4881. &soc_component_dev_rt5677,
  4882. rt5677_dai, ARRAY_SIZE(rt5677_dai));
  4883. }
  4884. static int rt5677_i2c_remove(struct i2c_client *i2c)
  4885. {
  4886. rt5677_free_gpio(i2c);
  4887. return 0;
  4888. }
  4889. static struct i2c_driver rt5677_i2c_driver = {
  4890. .driver = {
  4891. .name = RT5677_DRV_NAME,
  4892. .of_match_table = rt5677_of_match,
  4893. .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
  4894. },
  4895. .probe_new = rt5677_i2c_probe,
  4896. .remove = rt5677_i2c_remove,
  4897. };
  4898. module_i2c_driver(rt5677_i2c_driver);
  4899. MODULE_DESCRIPTION("ASoC RT5677 driver");
  4900. MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
  4901. MODULE_LICENSE("GPL v2");