rt5677-spi.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Oder Chiou <oder_chiou@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/input.h>
  10. #include <linux/spi/spi.h>
  11. #include <linux/device.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/slab.h>
  17. #include <linux/sched.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/pm_qos.h>
  21. #include <linux/sysfs.h>
  22. #include <linux/clk.h>
  23. #include <linux/firmware.h>
  24. #include <linux/acpi.h>
  25. #include <sound/soc.h>
  26. #include "rt5677.h"
  27. #include "rt5677-spi.h"
  28. #define DRV_NAME "rt5677spi"
  29. #define RT5677_SPI_BURST_LEN 240
  30. #define RT5677_SPI_HEADER 5
  31. #define RT5677_SPI_FREQ 6000000
  32. /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
  33. * DataPhase word size of 16-bit commands is 2 bytes.
  34. * DataPhase word size of 32-bit commands is 4 bytes.
  35. * DataPhase word size of burst commands is 8 bytes.
  36. * The DSP CPU is little-endian.
  37. */
  38. #define RT5677_SPI_WRITE_BURST 0x5
  39. #define RT5677_SPI_READ_BURST 0x4
  40. #define RT5677_SPI_WRITE_32 0x3
  41. #define RT5677_SPI_READ_32 0x2
  42. #define RT5677_SPI_WRITE_16 0x1
  43. #define RT5677_SPI_READ_16 0x0
  44. #define RT5677_BUF_BYTES_TOTAL 0x20000
  45. #define RT5677_MIC_BUF_ADDR 0x60030000
  46. #define RT5677_MODEL_ADDR 0x5FFC9800
  47. #define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \
  48. sizeof(u32)))
  49. #define RT5677_MIC_BUF_FIRST_READ_SIZE 0x10000
  50. static struct spi_device *g_spi;
  51. static DEFINE_MUTEX(spi_mutex);
  52. struct rt5677_dsp {
  53. struct device *dev;
  54. struct delayed_work copy_work;
  55. struct mutex dma_lock;
  56. struct snd_pcm_substream *substream;
  57. size_t dma_offset; /* zero-based offset into runtime->dma_area */
  58. size_t avail_bytes; /* number of new bytes since last period */
  59. u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */
  60. bool new_hotword; /* a new hotword is fired */
  61. };
  62. static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = {
  63. .info = SNDRV_PCM_INFO_MMAP |
  64. SNDRV_PCM_INFO_MMAP_VALID |
  65. SNDRV_PCM_INFO_INTERLEAVED,
  66. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  67. .period_bytes_min = PAGE_SIZE,
  68. .period_bytes_max = RT5677_BUF_BYTES_TOTAL / 8,
  69. .periods_min = 8,
  70. .periods_max = 8,
  71. .channels_min = 1,
  72. .channels_max = 1,
  73. .buffer_bytes_max = RT5677_BUF_BYTES_TOTAL,
  74. };
  75. static struct snd_soc_dai_driver rt5677_spi_dai = {
  76. /* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name
  77. * registered with ASoC is the name of the device "spi-RT5677AA:00",
  78. * because we only have one DAI. See snd_soc_register_dais().
  79. */
  80. .name = "rt5677-dsp-cpu-dai",
  81. .id = 0,
  82. .capture = {
  83. .stream_name = "DSP Capture",
  84. .channels_min = 1,
  85. .channels_max = 1,
  86. .rates = SNDRV_PCM_RATE_16000,
  87. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  88. },
  89. };
  90. /* PCM for streaming audio from the DSP buffer */
  91. static int rt5677_spi_pcm_open(
  92. struct snd_soc_component *component,
  93. struct snd_pcm_substream *substream)
  94. {
  95. snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware);
  96. return 0;
  97. }
  98. static int rt5677_spi_pcm_close(
  99. struct snd_soc_component *component,
  100. struct snd_pcm_substream *substream)
  101. {
  102. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  103. struct snd_soc_component *codec_component =
  104. snd_soc_rtdcom_lookup(rtd, "rt5677");
  105. struct rt5677_priv *rt5677 =
  106. snd_soc_component_get_drvdata(codec_component);
  107. struct rt5677_dsp *rt5677_dsp =
  108. snd_soc_component_get_drvdata(component);
  109. cancel_delayed_work_sync(&rt5677_dsp->copy_work);
  110. rt5677->set_dsp_vad(codec_component, false);
  111. return 0;
  112. }
  113. static int rt5677_spi_hw_params(
  114. struct snd_soc_component *component,
  115. struct snd_pcm_substream *substream,
  116. struct snd_pcm_hw_params *hw_params)
  117. {
  118. struct rt5677_dsp *rt5677_dsp =
  119. snd_soc_component_get_drvdata(component);
  120. mutex_lock(&rt5677_dsp->dma_lock);
  121. rt5677_dsp->substream = substream;
  122. mutex_unlock(&rt5677_dsp->dma_lock);
  123. return 0;
  124. }
  125. static int rt5677_spi_hw_free(
  126. struct snd_soc_component *component,
  127. struct snd_pcm_substream *substream)
  128. {
  129. struct rt5677_dsp *rt5677_dsp =
  130. snd_soc_component_get_drvdata(component);
  131. mutex_lock(&rt5677_dsp->dma_lock);
  132. rt5677_dsp->substream = NULL;
  133. mutex_unlock(&rt5677_dsp->dma_lock);
  134. return 0;
  135. }
  136. static int rt5677_spi_prepare(
  137. struct snd_soc_component *component,
  138. struct snd_pcm_substream *substream)
  139. {
  140. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  141. struct snd_soc_component *rt5677_component =
  142. snd_soc_rtdcom_lookup(rtd, "rt5677");
  143. struct rt5677_priv *rt5677 =
  144. snd_soc_component_get_drvdata(rt5677_component);
  145. struct rt5677_dsp *rt5677_dsp =
  146. snd_soc_component_get_drvdata(component);
  147. rt5677->set_dsp_vad(rt5677_component, true);
  148. rt5677_dsp->dma_offset = 0;
  149. rt5677_dsp->avail_bytes = 0;
  150. return 0;
  151. }
  152. static snd_pcm_uframes_t rt5677_spi_pcm_pointer(
  153. struct snd_soc_component *component,
  154. struct snd_pcm_substream *substream)
  155. {
  156. struct snd_pcm_runtime *runtime = substream->runtime;
  157. struct rt5677_dsp *rt5677_dsp =
  158. snd_soc_component_get_drvdata(component);
  159. return bytes_to_frames(runtime, rt5677_dsp->dma_offset);
  160. }
  161. static int rt5677_spi_mic_write_offset(u32 *mic_write_offset)
  162. {
  163. int ret;
  164. /* Grab the first 4 bytes that hold the write pointer on the
  165. * dsp, and check to make sure that it points somewhere inside the
  166. * buffer.
  167. */
  168. ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset,
  169. sizeof(u32));
  170. if (ret)
  171. return ret;
  172. /* Adjust the offset so that it's zero-based */
  173. *mic_write_offset = *mic_write_offset - sizeof(u32);
  174. return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT;
  175. }
  176. /*
  177. * Copy one contiguous block of audio samples from the DSP mic buffer to the
  178. * dma_area of the pcm runtime. The receiving buffer may wrap around.
  179. * @begin: start offset of the block to copy, in bytes.
  180. * @end: offset of the first byte after the block to copy, must be greater
  181. * than or equal to begin.
  182. *
  183. * Return: Zero if successful, or a negative error code on failure.
  184. */
  185. static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp,
  186. u32 begin, u32 end)
  187. {
  188. struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime;
  189. size_t bytes_per_frame = frames_to_bytes(runtime, 1);
  190. size_t first_chunk_len, second_chunk_len;
  191. int ret;
  192. if (begin > end || runtime->dma_bytes < 2 * bytes_per_frame) {
  193. dev_err(rt5677_dsp->dev,
  194. "Invalid copy from (%u, %u), dma_area size %zu\n",
  195. begin, end, runtime->dma_bytes);
  196. return -EINVAL;
  197. }
  198. /* The block to copy is empty */
  199. if (begin == end)
  200. return 0;
  201. /* If the incoming chunk is too big for the receiving buffer, only the
  202. * last "receiving buffer size - one frame" bytes are copied.
  203. */
  204. if (end - begin > runtime->dma_bytes - bytes_per_frame)
  205. begin = end - (runtime->dma_bytes - bytes_per_frame);
  206. /* May need to split to two chunks, calculate the size of each */
  207. first_chunk_len = end - begin;
  208. second_chunk_len = 0;
  209. if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) {
  210. /* Receiving buffer wrapped around */
  211. second_chunk_len = first_chunk_len;
  212. first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset;
  213. second_chunk_len -= first_chunk_len;
  214. }
  215. /* Copy first chunk */
  216. ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin,
  217. runtime->dma_area + rt5677_dsp->dma_offset,
  218. first_chunk_len);
  219. if (ret)
  220. return ret;
  221. rt5677_dsp->dma_offset += first_chunk_len;
  222. if (rt5677_dsp->dma_offset == runtime->dma_bytes)
  223. rt5677_dsp->dma_offset = 0;
  224. /* Copy second chunk */
  225. if (second_chunk_len) {
  226. ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) +
  227. begin + first_chunk_len, runtime->dma_area,
  228. second_chunk_len);
  229. if (!ret)
  230. rt5677_dsp->dma_offset = second_chunk_len;
  231. }
  232. return ret;
  233. }
  234. /*
  235. * Copy a given amount of audio samples from the DSP mic buffer starting at
  236. * mic_read_offset, to the dma_area of the pcm runtime. The source buffer may
  237. * wrap around. mic_read_offset is updated after successful copy.
  238. * @amount: amount of samples to copy, in bytes.
  239. *
  240. * Return: Zero if successful, or a negative error code on failure.
  241. */
  242. static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount)
  243. {
  244. int ret = 0;
  245. u32 target;
  246. if (amount == 0)
  247. return ret;
  248. target = rt5677_dsp->mic_read_offset + amount;
  249. /* Copy the first chunk in DSP's mic buffer */
  250. ret |= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset,
  251. min(target, RT5677_MIC_BUF_BYTES));
  252. if (target >= RT5677_MIC_BUF_BYTES) {
  253. /* Wrap around, copy the second chunk */
  254. target -= RT5677_MIC_BUF_BYTES;
  255. ret |= rt5677_spi_copy_block(rt5677_dsp, 0, target);
  256. }
  257. if (!ret)
  258. rt5677_dsp->mic_read_offset = target;
  259. return ret;
  260. }
  261. /*
  262. * A delayed work that streams audio samples from the DSP mic buffer to the
  263. * dma_area of the pcm runtime via SPI.
  264. */
  265. static void rt5677_spi_copy_work(struct work_struct *work)
  266. {
  267. struct rt5677_dsp *rt5677_dsp =
  268. container_of(work, struct rt5677_dsp, copy_work.work);
  269. struct snd_pcm_runtime *runtime;
  270. u32 mic_write_offset;
  271. size_t new_bytes, copy_bytes, period_bytes;
  272. unsigned int delay;
  273. int ret = 0;
  274. /* Ensure runtime->dma_area buffer does not go away while copying. */
  275. mutex_lock(&rt5677_dsp->dma_lock);
  276. if (!rt5677_dsp->substream) {
  277. dev_err(rt5677_dsp->dev, "No pcm substream\n");
  278. goto done;
  279. }
  280. runtime = rt5677_dsp->substream->runtime;
  281. if (rt5677_spi_mic_write_offset(&mic_write_offset)) {
  282. dev_err(rt5677_dsp->dev, "No mic_write_offset\n");
  283. goto done;
  284. }
  285. /* If this is the first time that we've asked for streaming data after
  286. * a hotword is fired, we should start reading from the previous 2
  287. * seconds of audio from wherever the mic_write_offset is currently.
  288. */
  289. if (rt5677_dsp->new_hotword) {
  290. rt5677_dsp->new_hotword = false;
  291. /* See if buffer wraparound happens */
  292. if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE)
  293. rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES -
  294. (RT5677_MIC_BUF_FIRST_READ_SIZE -
  295. mic_write_offset);
  296. else
  297. rt5677_dsp->mic_read_offset = mic_write_offset -
  298. RT5677_MIC_BUF_FIRST_READ_SIZE;
  299. }
  300. /* Calculate the amount of new samples in bytes */
  301. if (rt5677_dsp->mic_read_offset <= mic_write_offset)
  302. new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset;
  303. else
  304. new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset
  305. - rt5677_dsp->mic_read_offset;
  306. /* Copy all new samples from DSP mic buffer, one period at a time */
  307. period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream);
  308. while (new_bytes) {
  309. copy_bytes = min(new_bytes, period_bytes
  310. - rt5677_dsp->avail_bytes);
  311. ret = rt5677_spi_copy(rt5677_dsp, copy_bytes);
  312. if (ret) {
  313. dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret);
  314. goto done;
  315. }
  316. rt5677_dsp->avail_bytes += copy_bytes;
  317. if (rt5677_dsp->avail_bytes >= period_bytes) {
  318. snd_pcm_period_elapsed(rt5677_dsp->substream);
  319. rt5677_dsp->avail_bytes = 0;
  320. }
  321. new_bytes -= copy_bytes;
  322. }
  323. delay = bytes_to_frames(runtime, period_bytes) / (runtime->rate / 1000);
  324. schedule_delayed_work(&rt5677_dsp->copy_work, msecs_to_jiffies(delay));
  325. done:
  326. mutex_unlock(&rt5677_dsp->dma_lock);
  327. }
  328. static int rt5677_spi_pcm_new(struct snd_soc_component *component,
  329. struct snd_soc_pcm_runtime *rtd)
  330. {
  331. snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
  332. NULL, 0, 0);
  333. return 0;
  334. }
  335. static int rt5677_spi_pcm_probe(struct snd_soc_component *component)
  336. {
  337. struct rt5677_dsp *rt5677_dsp;
  338. rt5677_dsp = devm_kzalloc(component->dev, sizeof(*rt5677_dsp),
  339. GFP_KERNEL);
  340. if (!rt5677_dsp)
  341. return -ENOMEM;
  342. rt5677_dsp->dev = &g_spi->dev;
  343. mutex_init(&rt5677_dsp->dma_lock);
  344. INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work);
  345. snd_soc_component_set_drvdata(component, rt5677_dsp);
  346. return 0;
  347. }
  348. static const struct snd_soc_component_driver rt5677_spi_dai_component = {
  349. .name = DRV_NAME,
  350. .probe = rt5677_spi_pcm_probe,
  351. .open = rt5677_spi_pcm_open,
  352. .close = rt5677_spi_pcm_close,
  353. .hw_params = rt5677_spi_hw_params,
  354. .hw_free = rt5677_spi_hw_free,
  355. .prepare = rt5677_spi_prepare,
  356. .pointer = rt5677_spi_pcm_pointer,
  357. .pcm_construct = rt5677_spi_pcm_new,
  358. };
  359. /* Select a suitable transfer command for the next transfer to ensure
  360. * the transfer address is always naturally aligned while minimizing
  361. * the total number of transfers required.
  362. *
  363. * 3 transfer commands are available:
  364. * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes
  365. * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes
  366. * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
  367. *
  368. * Note:
  369. * 16 Bit writes and reads are restricted to the address range
  370. * 0x18020000 ~ 0x18021000
  371. *
  372. * For example, reading 256 bytes at 0x60030004 uses the following commands:
  373. * 0x60030004 RT5677_SPI_READ_32 4 bytes
  374. * 0x60030008 RT5677_SPI_READ_BURST 240 bytes
  375. * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes
  376. * 0x60030100 RT5677_SPI_READ_32 4 bytes
  377. *
  378. * Input:
  379. * @read: true for read commands; false for write commands
  380. * @align: alignment of the next transfer address
  381. * @remain: number of bytes remaining to transfer
  382. *
  383. * Output:
  384. * @len: number of bytes to transfer with the selected command
  385. * Returns the selected command
  386. */
  387. static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
  388. {
  389. u8 cmd;
  390. if (align == 4 || remain <= 4) {
  391. cmd = RT5677_SPI_READ_32;
  392. *len = 4;
  393. } else {
  394. cmd = RT5677_SPI_READ_BURST;
  395. *len = (((remain - 1) >> 3) + 1) << 3;
  396. *len = min_t(u32, *len, RT5677_SPI_BURST_LEN);
  397. }
  398. return read ? cmd : cmd + 1;
  399. }
  400. /* Copy dstlen bytes from src to dst, while reversing byte order for each word.
  401. * If srclen < dstlen, zeros are padded.
  402. */
  403. static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
  404. {
  405. u32 w, i, si;
  406. u32 word_size = min_t(u32, dstlen, 8);
  407. for (w = 0; w < dstlen; w += word_size) {
  408. for (i = 0; i < word_size && i + w < dstlen; i++) {
  409. si = w + word_size - i - 1;
  410. dst[w + i] = si < srclen ? src[si] : 0;
  411. }
  412. }
  413. }
  414. /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
  415. int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
  416. {
  417. u32 offset;
  418. int status = 0;
  419. struct spi_transfer t[2];
  420. struct spi_message m;
  421. /* +4 bytes is for the DummyPhase following the AddressPhase */
  422. u8 header[RT5677_SPI_HEADER + 4];
  423. u8 body[RT5677_SPI_BURST_LEN];
  424. u8 spi_cmd;
  425. u8 *cb = rxbuf;
  426. if (!g_spi)
  427. return -ENODEV;
  428. if ((addr & 3) || (len & 3)) {
  429. dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
  430. return -EACCES;
  431. }
  432. memset(t, 0, sizeof(t));
  433. t[0].tx_buf = header;
  434. t[0].len = sizeof(header);
  435. t[0].speed_hz = RT5677_SPI_FREQ;
  436. t[1].rx_buf = body;
  437. t[1].speed_hz = RT5677_SPI_FREQ;
  438. spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
  439. for (offset = 0; offset < len; offset += t[1].len) {
  440. spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
  441. len - offset, &t[1].len);
  442. /* Construct SPI message header */
  443. header[0] = spi_cmd;
  444. header[1] = ((addr + offset) & 0xff000000) >> 24;
  445. header[2] = ((addr + offset) & 0x00ff0000) >> 16;
  446. header[3] = ((addr + offset) & 0x0000ff00) >> 8;
  447. header[4] = ((addr + offset) & 0x000000ff) >> 0;
  448. mutex_lock(&spi_mutex);
  449. status |= spi_sync(g_spi, &m);
  450. mutex_unlock(&spi_mutex);
  451. /* Copy data back to caller buffer */
  452. rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
  453. }
  454. return status;
  455. }
  456. EXPORT_SYMBOL_GPL(rt5677_spi_read);
  457. /* Write DSP address space using SPI. addr has to be 4-byte aligned.
  458. * If len is not 4-byte aligned, then extra zeros are written at the end
  459. * as padding.
  460. */
  461. int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
  462. {
  463. u32 offset;
  464. int status = 0;
  465. struct spi_transfer t;
  466. struct spi_message m;
  467. /* +1 byte is for the DummyPhase following the DataPhase */
  468. u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
  469. u8 *body = buf + RT5677_SPI_HEADER;
  470. u8 spi_cmd;
  471. const u8 *cb = txbuf;
  472. if (!g_spi)
  473. return -ENODEV;
  474. if (addr & 3) {
  475. dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
  476. return -EACCES;
  477. }
  478. memset(&t, 0, sizeof(t));
  479. t.tx_buf = buf;
  480. t.speed_hz = RT5677_SPI_FREQ;
  481. spi_message_init_with_transfers(&m, &t, 1);
  482. for (offset = 0; offset < len;) {
  483. spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
  484. len - offset, &t.len);
  485. /* Construct SPI message header */
  486. buf[0] = spi_cmd;
  487. buf[1] = ((addr + offset) & 0xff000000) >> 24;
  488. buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
  489. buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
  490. buf[4] = ((addr + offset) & 0x000000ff) >> 0;
  491. /* Fetch data from caller buffer */
  492. rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
  493. offset += t.len;
  494. t.len += RT5677_SPI_HEADER + 1;
  495. mutex_lock(&spi_mutex);
  496. status |= spi_sync(g_spi, &m);
  497. mutex_unlock(&spi_mutex);
  498. }
  499. return status;
  500. }
  501. EXPORT_SYMBOL_GPL(rt5677_spi_write);
  502. int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
  503. {
  504. return rt5677_spi_write(addr, fw->data, fw->size);
  505. }
  506. EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
  507. void rt5677_spi_hotword_detected(void)
  508. {
  509. struct rt5677_dsp *rt5677_dsp;
  510. if (!g_spi)
  511. return;
  512. rt5677_dsp = dev_get_drvdata(&g_spi->dev);
  513. if (!rt5677_dsp) {
  514. dev_err(&g_spi->dev, "Can't get rt5677_dsp\n");
  515. return;
  516. }
  517. mutex_lock(&rt5677_dsp->dma_lock);
  518. dev_info(rt5677_dsp->dev, "Hotword detected\n");
  519. rt5677_dsp->new_hotword = true;
  520. mutex_unlock(&rt5677_dsp->dma_lock);
  521. schedule_delayed_work(&rt5677_dsp->copy_work, 0);
  522. }
  523. EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected);
  524. static int rt5677_spi_probe(struct spi_device *spi)
  525. {
  526. int ret;
  527. g_spi = spi;
  528. ret = devm_snd_soc_register_component(&spi->dev,
  529. &rt5677_spi_dai_component,
  530. &rt5677_spi_dai, 1);
  531. if (ret < 0)
  532. dev_err(&spi->dev, "Failed to register component.\n");
  533. return ret;
  534. }
  535. #ifdef CONFIG_ACPI
  536. static const struct acpi_device_id rt5677_spi_acpi_id[] = {
  537. { "RT5677AA", 0 },
  538. { }
  539. };
  540. MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);
  541. #endif
  542. static struct spi_driver rt5677_spi_driver = {
  543. .driver = {
  544. .name = DRV_NAME,
  545. .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
  546. },
  547. .probe = rt5677_spi_probe,
  548. };
  549. module_spi_driver(rt5677_spi_driver);
  550. MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
  551. MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
  552. MODULE_LICENSE("GPL v2");