rt5670.h 69 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5670.h -- RT5670 ALSA SoC audio driver
  4. *
  5. * Copyright 2014 Realtek Microelectronics
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #ifndef __RT5670_H__
  9. #define __RT5670_H__
  10. /* Info */
  11. #define RT5670_RESET 0x00
  12. #define RT5670_VENDOR_ID 0xfd
  13. #define RT5670_VENDOR_ID1 0xfe
  14. #define RT5670_VENDOR_ID2 0xff
  15. /* I/O - Output */
  16. #define RT5670_HP_VOL 0x02
  17. #define RT5670_LOUT1 0x03
  18. /* I/O - Input */
  19. #define RT5670_CJ_CTRL1 0x0a
  20. #define RT5670_CJ_CTRL2 0x0b
  21. #define RT5670_CJ_CTRL3 0x0c
  22. #define RT5670_IN2 0x0e
  23. #define RT5670_INL1_INR1_VOL 0x0f
  24. /* I/O - ADC/DAC/DMIC */
  25. #define RT5670_DAC1_DIG_VOL 0x19
  26. #define RT5670_DAC2_DIG_VOL 0x1a
  27. #define RT5670_DAC_CTRL 0x1b
  28. #define RT5670_STO1_ADC_DIG_VOL 0x1c
  29. #define RT5670_MONO_ADC_DIG_VOL 0x1d
  30. #define RT5670_ADC_BST_VOL1 0x1e
  31. #define RT5670_STO2_ADC_DIG_VOL 0x1f
  32. /* Mixer - D-D */
  33. #define RT5670_ADC_BST_VOL2 0x20
  34. #define RT5670_STO2_ADC_MIXER 0x26
  35. #define RT5670_STO1_ADC_MIXER 0x27
  36. #define RT5670_MONO_ADC_MIXER 0x28
  37. #define RT5670_AD_DA_MIXER 0x29
  38. #define RT5670_STO_DAC_MIXER 0x2a
  39. #define RT5670_DD_MIXER 0x2b
  40. #define RT5670_DIG_MIXER 0x2c
  41. #define RT5670_DSP_PATH1 0x2d
  42. #define RT5670_DSP_PATH2 0x2e
  43. #define RT5670_DIG_INF1_DATA 0x2f
  44. #define RT5670_DIG_INF2_DATA 0x30
  45. /* Mixer - PDM */
  46. #define RT5670_PDM_OUT_CTRL 0x31
  47. #define RT5670_PDM_DATA_CTRL1 0x32
  48. #define RT5670_PDM1_DATA_CTRL2 0x33
  49. #define RT5670_PDM1_DATA_CTRL3 0x34
  50. #define RT5670_PDM1_DATA_CTRL4 0x35
  51. #define RT5670_PDM2_DATA_CTRL2 0x36
  52. #define RT5670_PDM2_DATA_CTRL3 0x37
  53. #define RT5670_PDM2_DATA_CTRL4 0x38
  54. /* Mixer - ADC */
  55. #define RT5670_REC_L1_MIXER 0x3b
  56. #define RT5670_REC_L2_MIXER 0x3c
  57. #define RT5670_REC_R1_MIXER 0x3d
  58. #define RT5670_REC_R2_MIXER 0x3e
  59. /* Mixer - DAC */
  60. #define RT5670_HPO_MIXER 0x45
  61. #define RT5670_MONO_MIXER 0x4c
  62. #define RT5670_OUT_L1_MIXER 0x4f
  63. #define RT5670_OUT_R1_MIXER 0x52
  64. #define RT5670_LOUT_MIXER 0x53
  65. /* Power */
  66. #define RT5670_PWR_DIG1 0x61
  67. #define RT5670_PWR_DIG2 0x62
  68. #define RT5670_PWR_ANLG1 0x63
  69. #define RT5670_PWR_ANLG2 0x64
  70. #define RT5670_PWR_MIXER 0x65
  71. #define RT5670_PWR_VOL 0x66
  72. /* Private Register Control */
  73. #define RT5670_PRIV_INDEX 0x6a
  74. #define RT5670_PRIV_DATA 0x6c
  75. /* Format - ADC/DAC */
  76. #define RT5670_I2S4_SDP 0x6f
  77. #define RT5670_I2S1_SDP 0x70
  78. #define RT5670_I2S2_SDP 0x71
  79. #define RT5670_I2S3_SDP 0x72
  80. #define RT5670_ADDA_CLK1 0x73
  81. #define RT5670_ADDA_CLK2 0x74
  82. #define RT5670_DMIC_CTRL1 0x75
  83. #define RT5670_DMIC_CTRL2 0x76
  84. /* Format - TDM Control */
  85. #define RT5670_TDM_CTRL_1 0x77
  86. #define RT5670_TDM_CTRL_2 0x78
  87. #define RT5670_TDM_CTRL_3 0x79
  88. /* Function - Analog */
  89. #define RT5670_DSP_CLK 0x7f
  90. #define RT5670_GLB_CLK 0x80
  91. #define RT5670_PLL_CTRL1 0x81
  92. #define RT5670_PLL_CTRL2 0x82
  93. #define RT5670_ASRC_1 0x83
  94. #define RT5670_ASRC_2 0x84
  95. #define RT5670_ASRC_3 0x85
  96. #define RT5670_ASRC_4 0x86
  97. #define RT5670_ASRC_5 0x87
  98. #define RT5670_ASRC_7 0x89
  99. #define RT5670_ASRC_8 0x8a
  100. #define RT5670_ASRC_9 0x8b
  101. #define RT5670_ASRC_10 0x8c
  102. #define RT5670_ASRC_11 0x8d
  103. #define RT5670_DEPOP_M1 0x8e
  104. #define RT5670_DEPOP_M2 0x8f
  105. #define RT5670_DEPOP_M3 0x90
  106. #define RT5670_CHARGE_PUMP 0x91
  107. #define RT5670_MICBIAS 0x93
  108. #define RT5670_A_JD_CTRL1 0x94
  109. #define RT5670_A_JD_CTRL2 0x95
  110. #define RT5670_ASRC_12 0x97
  111. #define RT5670_ASRC_13 0x98
  112. #define RT5670_ASRC_14 0x99
  113. #define RT5670_VAD_CTRL1 0x9a
  114. #define RT5670_VAD_CTRL2 0x9b
  115. #define RT5670_VAD_CTRL3 0x9c
  116. #define RT5670_VAD_CTRL4 0x9d
  117. #define RT5670_VAD_CTRL5 0x9e
  118. /* Function - Digital */
  119. #define RT5670_ADC_EQ_CTRL1 0xae
  120. #define RT5670_ADC_EQ_CTRL2 0xaf
  121. #define RT5670_EQ_CTRL1 0xb0
  122. #define RT5670_EQ_CTRL2 0xb1
  123. #define RT5670_ALC_DRC_CTRL1 0xb2
  124. #define RT5670_ALC_DRC_CTRL2 0xb3
  125. #define RT5670_ALC_CTRL_1 0xb4
  126. #define RT5670_ALC_CTRL_2 0xb5
  127. #define RT5670_ALC_CTRL_3 0xb6
  128. #define RT5670_ALC_CTRL_4 0xb7
  129. #define RT5670_JD_CTRL 0xbb
  130. #define RT5670_IRQ_CTRL1 0xbd
  131. #define RT5670_IRQ_CTRL2 0xbe
  132. #define RT5670_INT_IRQ_ST 0xbf
  133. #define RT5670_GPIO_CTRL1 0xc0
  134. #define RT5670_GPIO_CTRL2 0xc1
  135. #define RT5670_GPIO_CTRL3 0xc2
  136. #define RT5670_SCRABBLE_FUN 0xcd
  137. #define RT5670_SCRABBLE_CTRL 0xce
  138. #define RT5670_BASE_BACK 0xcf
  139. #define RT5670_MP3_PLUS1 0xd0
  140. #define RT5670_MP3_PLUS2 0xd1
  141. #define RT5670_ADJ_HPF1 0xd3
  142. #define RT5670_ADJ_HPF2 0xd4
  143. #define RT5670_HP_CALIB_AMP_DET 0xd6
  144. #define RT5670_SV_ZCD1 0xd9
  145. #define RT5670_SV_ZCD2 0xda
  146. #define RT5670_IL_CMD 0xdb
  147. #define RT5670_IL_CMD2 0xdc
  148. #define RT5670_IL_CMD3 0xdd
  149. #define RT5670_DRC_HL_CTRL1 0xe6
  150. #define RT5670_DRC_HL_CTRL2 0xe7
  151. #define RT5670_ADC_MONO_HP_CTRL1 0xec
  152. #define RT5670_ADC_MONO_HP_CTRL2 0xed
  153. #define RT5670_ADC_STO2_HP_CTRL1 0xee
  154. #define RT5670_ADC_STO2_HP_CTRL2 0xef
  155. #define RT5670_JD_CTRL3 0xf8
  156. #define RT5670_JD_CTRL4 0xf9
  157. /* General Control */
  158. #define RT5670_DIG_MISC 0xfa
  159. #define RT5670_GEN_CTRL2 0xfb
  160. #define RT5670_GEN_CTRL3 0xfc
  161. /* Index of Codec Private Register definition */
  162. #define RT5670_DIG_VOL 0x00
  163. #define RT5670_PR_ALC_CTRL_1 0x01
  164. #define RT5670_PR_ALC_CTRL_2 0x02
  165. #define RT5670_PR_ALC_CTRL_3 0x03
  166. #define RT5670_PR_ALC_CTRL_4 0x04
  167. #define RT5670_PR_ALC_CTRL_5 0x05
  168. #define RT5670_PR_ALC_CTRL_6 0x06
  169. #define RT5670_BIAS_CUR1 0x12
  170. #define RT5670_BIAS_CUR3 0x14
  171. #define RT5670_CLSD_INT_REG1 0x1c
  172. #define RT5670_MAMP_INT_REG2 0x37
  173. #define RT5670_CHOP_DAC_ADC 0x3d
  174. #define RT5670_MIXER_INT_REG 0x3f
  175. #define RT5670_3D_SPK 0x63
  176. #define RT5670_WND_1 0x6c
  177. #define RT5670_WND_2 0x6d
  178. #define RT5670_WND_3 0x6e
  179. #define RT5670_WND_4 0x6f
  180. #define RT5670_WND_5 0x70
  181. #define RT5670_WND_8 0x73
  182. #define RT5670_DIP_SPK_INF 0x75
  183. #define RT5670_HP_DCC_INT1 0x77
  184. #define RT5670_EQ_BW_LOP 0xa0
  185. #define RT5670_EQ_GN_LOP 0xa1
  186. #define RT5670_EQ_FC_BP1 0xa2
  187. #define RT5670_EQ_BW_BP1 0xa3
  188. #define RT5670_EQ_GN_BP1 0xa4
  189. #define RT5670_EQ_FC_BP2 0xa5
  190. #define RT5670_EQ_BW_BP2 0xa6
  191. #define RT5670_EQ_GN_BP2 0xa7
  192. #define RT5670_EQ_FC_BP3 0xa8
  193. #define RT5670_EQ_BW_BP3 0xa9
  194. #define RT5670_EQ_GN_BP3 0xaa
  195. #define RT5670_EQ_FC_BP4 0xab
  196. #define RT5670_EQ_BW_BP4 0xac
  197. #define RT5670_EQ_GN_BP4 0xad
  198. #define RT5670_EQ_FC_HIP1 0xae
  199. #define RT5670_EQ_GN_HIP1 0xaf
  200. #define RT5670_EQ_FC_HIP2 0xb0
  201. #define RT5670_EQ_BW_HIP2 0xb1
  202. #define RT5670_EQ_GN_HIP2 0xb2
  203. #define RT5670_EQ_PRE_VOL 0xb3
  204. #define RT5670_EQ_PST_VOL 0xb4
  205. /* global definition */
  206. #define RT5670_L_MUTE (0x1 << 15)
  207. #define RT5670_L_MUTE_SFT 15
  208. #define RT5670_VOL_L_MUTE (0x1 << 14)
  209. #define RT5670_VOL_L_SFT 14
  210. #define RT5670_R_MUTE (0x1 << 7)
  211. #define RT5670_R_MUTE_SFT 7
  212. #define RT5670_VOL_R_MUTE (0x1 << 6)
  213. #define RT5670_VOL_R_SFT 6
  214. #define RT5670_L_VOL_MASK (0x3f << 8)
  215. #define RT5670_L_VOL_SFT 8
  216. #define RT5670_R_VOL_MASK (0x3f)
  217. #define RT5670_R_VOL_SFT 0
  218. /* SW Reset & Device ID (0x00) */
  219. #define RT5670_ID_MASK (0x3 << 1)
  220. #define RT5670_ID_5670 (0x0 << 1)
  221. #define RT5670_ID_5672 (0x1 << 1)
  222. #define RT5670_ID_5671 (0x2 << 1)
  223. /* Combo Jack Control 1 (0x0a) */
  224. #define RT5670_CBJ_BST1_MASK (0xf << 12)
  225. #define RT5670_CBJ_BST1_SFT (12)
  226. #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
  227. #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
  228. #define RT5670_CBJ_BST1_EN (0x1 << 2)
  229. /* Combo Jack Control 1 (0x0b) */
  230. #define RT5670_CBJ_MN_JD (0x1 << 12)
  231. #define RT5670_CAPLESS_EN (0x1 << 11)
  232. #define RT5670_CBJ_DET_MODE (0x1 << 7)
  233. /* IN2 Control (0x0e) */
  234. #define RT5670_BST_MASK1 (0xf<<12)
  235. #define RT5670_BST_SFT1 12
  236. #define RT5670_BST_MASK2 (0xf<<8)
  237. #define RT5670_BST_SFT2 8
  238. #define RT5670_IN_DF1 (0x1 << 7)
  239. #define RT5670_IN_SFT1 7
  240. #define RT5670_IN_DF2 (0x1 << 6)
  241. #define RT5670_IN_SFT2 6
  242. /* INL and INR Volume Control (0x0f) */
  243. #define RT5670_INL_SEL_MASK (0x1 << 15)
  244. #define RT5670_INL_SEL_SFT 15
  245. #define RT5670_INL_SEL_IN4P (0x0 << 15)
  246. #define RT5670_INL_SEL_MONOP (0x1 << 15)
  247. #define RT5670_INL_VOL_MASK (0x1f << 8)
  248. #define RT5670_INL_VOL_SFT 8
  249. #define RT5670_INR_SEL_MASK (0x1 << 7)
  250. #define RT5670_INR_SEL_SFT 7
  251. #define RT5670_INR_SEL_IN4N (0x0 << 7)
  252. #define RT5670_INR_SEL_MONON (0x1 << 7)
  253. #define RT5670_INR_VOL_MASK (0x1f)
  254. #define RT5670_INR_VOL_SFT 0
  255. /* Sidetone Control (0x18) */
  256. #define RT5670_ST_SEL_MASK (0x7 << 9)
  257. #define RT5670_ST_SEL_SFT 9
  258. #define RT5670_M_ST_DACR2 (0x1 << 8)
  259. #define RT5670_M_ST_DACR2_SFT 8
  260. #define RT5670_M_ST_DACL2 (0x1 << 7)
  261. #define RT5670_M_ST_DACL2_SFT 7
  262. #define RT5670_ST_EN (0x1 << 6)
  263. #define RT5670_ST_EN_SFT 6
  264. /* DAC1 Digital Volume (0x19) */
  265. #define RT5670_DAC_L1_VOL_MASK (0xff << 8)
  266. #define RT5670_DAC_L1_VOL_SFT 8
  267. #define RT5670_DAC_R1_VOL_MASK (0xff)
  268. #define RT5670_DAC_R1_VOL_SFT 0
  269. /* DAC2 Digital Volume (0x1a) */
  270. #define RT5670_DAC_L2_VOL_MASK (0xff << 8)
  271. #define RT5670_DAC_L2_VOL_SFT 8
  272. #define RT5670_DAC_R2_VOL_MASK (0xff)
  273. #define RT5670_DAC_R2_VOL_SFT 0
  274. /* DAC2 Control (0x1b) */
  275. #define RT5670_M_DAC_L2_VOL (0x1 << 13)
  276. #define RT5670_M_DAC_L2_VOL_SFT 13
  277. #define RT5670_M_DAC_R2_VOL (0x1 << 12)
  278. #define RT5670_M_DAC_R2_VOL_SFT 12
  279. #define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
  280. #define RT5670_DAC2_L_SEL_SFT 4
  281. #define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
  282. #define RT5670_DAC2_R_SEL_SFT 0
  283. /* ADC Digital Volume Control (0x1c) */
  284. #define RT5670_ADC_L_VOL_MASK (0x7f << 8)
  285. #define RT5670_ADC_L_VOL_SFT 8
  286. #define RT5670_ADC_R_VOL_MASK (0x7f)
  287. #define RT5670_ADC_R_VOL_SFT 0
  288. /* Mono ADC Digital Volume Control (0x1d) */
  289. #define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
  290. #define RT5670_MONO_ADC_L_VOL_SFT 8
  291. #define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
  292. #define RT5670_MONO_ADC_R_VOL_SFT 0
  293. /* ADC Boost Volume Control (0x1e) */
  294. #define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
  295. #define RT5670_STO1_ADC_L_BST_SFT 14
  296. #define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
  297. #define RT5670_STO1_ADC_R_BST_SFT 12
  298. #define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
  299. #define RT5670_STO1_ADC_COMP_SFT 10
  300. #define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
  301. #define RT5670_STO2_ADC_L_BST_SFT 8
  302. #define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
  303. #define RT5670_STO2_ADC_R_BST_SFT 6
  304. #define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
  305. #define RT5670_STO2_ADC_COMP_SFT 4
  306. /* Stereo2 ADC Mixer Control (0x26) */
  307. #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
  308. #define RT5670_STO2_ADC_SRC_SFT 15
  309. /* Stereo ADC Mixer Control (0x26 0x27) */
  310. #define RT5670_M_ADC_L1 (0x1 << 14)
  311. #define RT5670_M_ADC_L1_SFT 14
  312. #define RT5670_M_ADC_L2 (0x1 << 13)
  313. #define RT5670_M_ADC_L2_SFT 13
  314. #define RT5670_ADC_1_SRC_MASK (0x1 << 12)
  315. #define RT5670_ADC_1_SRC_SFT 12
  316. #define RT5670_ADC_1_SRC_ADC (0x1 << 12)
  317. #define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
  318. #define RT5670_ADC_2_SRC_MASK (0x1 << 11)
  319. #define RT5670_ADC_2_SRC_SFT 11
  320. #define RT5670_ADC_SRC_MASK (0x1 << 10)
  321. #define RT5670_ADC_SRC_SFT 10
  322. #define RT5670_DMIC_SRC_MASK (0x3 << 8)
  323. #define RT5670_DMIC_SRC_SFT 8
  324. #define RT5670_M_ADC_R1 (0x1 << 6)
  325. #define RT5670_M_ADC_R1_SFT 6
  326. #define RT5670_M_ADC_R2 (0x1 << 5)
  327. #define RT5670_M_ADC_R2_SFT 5
  328. #define RT5670_DMIC3_SRC_MASK (0x1 << 1)
  329. #define RT5670_DMIC3_SRC_SFT 0
  330. /* Mono ADC Mixer Control (0x28) */
  331. #define RT5670_M_MONO_ADC_L1 (0x1 << 14)
  332. #define RT5670_M_MONO_ADC_L1_SFT 14
  333. #define RT5670_M_MONO_ADC_L2 (0x1 << 13)
  334. #define RT5670_M_MONO_ADC_L2_SFT 13
  335. #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
  336. #define RT5670_MONO_ADC_L1_SRC_SFT 12
  337. #define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
  338. #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
  339. #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
  340. #define RT5670_MONO_ADC_L2_SRC_SFT 11
  341. #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
  342. #define RT5670_MONO_ADC_L_SRC_SFT 10
  343. #define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
  344. #define RT5670_MONO_DMIC_L_SRC_SFT 8
  345. #define RT5670_M_MONO_ADC_R1 (0x1 << 6)
  346. #define RT5670_M_MONO_ADC_R1_SFT 6
  347. #define RT5670_M_MONO_ADC_R2 (0x1 << 5)
  348. #define RT5670_M_MONO_ADC_R2_SFT 5
  349. #define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
  350. #define RT5670_MONO_ADC_R1_SRC_SFT 4
  351. #define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
  352. #define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
  353. #define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
  354. #define RT5670_MONO_ADC_R2_SRC_SFT 3
  355. #define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
  356. #define RT5670_MONO_DMIC_R_SRC_SFT 0
  357. /* ADC Mixer to DAC Mixer Control (0x29) */
  358. #define RT5670_M_ADCMIX_L (0x1 << 15)
  359. #define RT5670_M_ADCMIX_L_SFT 15
  360. #define RT5670_M_DAC1_L (0x1 << 14)
  361. #define RT5670_M_DAC1_L_SFT 14
  362. #define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
  363. #define RT5670_DAC1_R_SEL_SFT 10
  364. #define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
  365. #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
  366. #define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
  367. #define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
  368. #define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
  369. #define RT5670_DAC1_L_SEL_SFT 8
  370. #define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
  371. #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
  372. #define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
  373. #define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
  374. #define RT5670_M_ADCMIX_R (0x1 << 7)
  375. #define RT5670_M_ADCMIX_R_SFT 7
  376. #define RT5670_M_DAC1_R (0x1 << 6)
  377. #define RT5670_M_DAC1_R_SFT 6
  378. /* Stereo DAC Mixer Control (0x2a) */
  379. #define RT5670_M_DAC_L1 (0x1 << 14)
  380. #define RT5670_M_DAC_L1_SFT 14
  381. #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
  382. #define RT5670_DAC_L1_STO_L_VOL_SFT 13
  383. #define RT5670_M_DAC_L2 (0x1 << 12)
  384. #define RT5670_M_DAC_L2_SFT 12
  385. #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
  386. #define RT5670_DAC_L2_STO_L_VOL_SFT 11
  387. #define RT5670_M_DAC_R1_STO_L (0x1 << 9)
  388. #define RT5670_M_DAC_R1_STO_L_SFT 9
  389. #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
  390. #define RT5670_DAC_R1_STO_L_VOL_SFT 8
  391. #define RT5670_M_DAC_R1 (0x1 << 6)
  392. #define RT5670_M_DAC_R1_SFT 6
  393. #define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
  394. #define RT5670_DAC_R1_STO_R_VOL_SFT 5
  395. #define RT5670_M_DAC_R2 (0x1 << 4)
  396. #define RT5670_M_DAC_R2_SFT 4
  397. #define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
  398. #define RT5670_DAC_R2_STO_R_VOL_SFT 3
  399. #define RT5670_M_DAC_L1_STO_R (0x1 << 1)
  400. #define RT5670_M_DAC_L1_STO_R_SFT 1
  401. #define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
  402. #define RT5670_DAC_L1_STO_R_VOL_SFT 0
  403. /* Mono DAC Mixer Control (0x2b) */
  404. #define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
  405. #define RT5670_M_DAC_L1_MONO_L_SFT 14
  406. #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
  407. #define RT5670_DAC_L1_MONO_L_VOL_SFT 13
  408. #define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
  409. #define RT5670_M_DAC_L2_MONO_L_SFT 12
  410. #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
  411. #define RT5670_DAC_L2_MONO_L_VOL_SFT 11
  412. #define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
  413. #define RT5670_M_DAC_R2_MONO_L_SFT 10
  414. #define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
  415. #define RT5670_DAC_R2_MONO_L_VOL_SFT 9
  416. #define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
  417. #define RT5670_M_DAC_R1_MONO_R_SFT 6
  418. #define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
  419. #define RT5670_DAC_R1_MONO_R_VOL_SFT 5
  420. #define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
  421. #define RT5670_M_DAC_R2_MONO_R_SFT 4
  422. #define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
  423. #define RT5670_DAC_R2_MONO_R_VOL_SFT 3
  424. #define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
  425. #define RT5670_M_DAC_L2_MONO_R_SFT 2
  426. #define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
  427. #define RT5670_DAC_L2_MONO_R_VOL_SFT 1
  428. /* Digital Mixer Control (0x2c) */
  429. #define RT5670_M_STO_L_DAC_L (0x1 << 15)
  430. #define RT5670_M_STO_L_DAC_L_SFT 15
  431. #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
  432. #define RT5670_STO_L_DAC_L_VOL_SFT 14
  433. #define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
  434. #define RT5670_M_DAC_L2_DAC_L_SFT 13
  435. #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
  436. #define RT5670_DAC_L2_DAC_L_VOL_SFT 12
  437. #define RT5670_M_STO_R_DAC_R (0x1 << 11)
  438. #define RT5670_M_STO_R_DAC_R_SFT 11
  439. #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
  440. #define RT5670_STO_R_DAC_R_VOL_SFT 10
  441. #define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
  442. #define RT5670_M_DAC_R2_DAC_R_SFT 9
  443. #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
  444. #define RT5670_DAC_R2_DAC_R_VOL_SFT 8
  445. #define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
  446. #define RT5670_M_DAC_R2_DAC_L_SFT 7
  447. #define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
  448. #define RT5670_DAC_R2_DAC_L_VOL_SFT 6
  449. #define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
  450. #define RT5670_M_DAC_L2_DAC_R_SFT 5
  451. #define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
  452. #define RT5670_DAC_L2_DAC_R_VOL_SFT 4
  453. /* DSP Path Control 1 (0x2d) */
  454. #define RT5670_RXDP_SEL_MASK (0x7 << 13)
  455. #define RT5670_RXDP_SEL_SFT 13
  456. #define RT5670_RXDP_SRC_MASK (0x3 << 11)
  457. #define RT5670_RXDP_SRC_SFT 11
  458. #define RT5670_RXDP_SRC_NOR (0x0 << 11)
  459. #define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
  460. #define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
  461. #define RT5670_TXDP_SRC_MASK (0x3 << 4)
  462. #define RT5670_TXDP_SRC_SFT 4
  463. #define RT5670_TXDP_SRC_NOR (0x0 << 4)
  464. #define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
  465. #define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
  466. #define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
  467. #define RT5670_TXDP_SLOT_SEL_SFT 2
  468. #define RT5670_DSP_UL_SEL (0x1 << 1)
  469. #define RT5670_DSP_UL_SFT 1
  470. #define RT5670_DSP_DL_SEL 0x1
  471. #define RT5670_DSP_DL_SFT 0
  472. /* DSP Path Control 2 (0x2e) */
  473. #define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
  474. #define RT5670_TXDP_L_VOL_SFT 8
  475. #define RT5670_TXDP_R_VOL_MASK (0x7f)
  476. #define RT5670_TXDP_R_VOL_SFT 0
  477. /* Digital Interface Data Control (0x2f) */
  478. #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
  479. #define RT5670_IF1_ADC2_IN_SFT 15
  480. #define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
  481. #define RT5670_IF2_ADC_IN_SFT 12
  482. #define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
  483. #define RT5670_IF2_DAC_SEL_SFT 10
  484. #define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
  485. #define RT5670_IF2_ADC_SEL_SFT 8
  486. /* Digital Interface Data Control (0x30) */
  487. #define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
  488. #define RT5670_IF4_ADC_IN_SFT 4
  489. /* PDM Output Control (0x31) */
  490. #define RT5670_PDM1_L_MASK (0x1 << 15)
  491. #define RT5670_PDM1_L_SFT 15
  492. #define RT5670_M_PDM1_L (0x1 << 14)
  493. #define RT5670_M_PDM1_L_SFT 14
  494. #define RT5670_PDM1_R_MASK (0x1 << 13)
  495. #define RT5670_PDM1_R_SFT 13
  496. #define RT5670_M_PDM1_R (0x1 << 12)
  497. #define RT5670_M_PDM1_R_SFT 12
  498. #define RT5670_PDM2_L_MASK (0x1 << 11)
  499. #define RT5670_PDM2_L_SFT 11
  500. #define RT5670_M_PDM2_L (0x1 << 10)
  501. #define RT5670_M_PDM2_L_SFT 10
  502. #define RT5670_PDM2_R_MASK (0x1 << 9)
  503. #define RT5670_PDM2_R_SFT 9
  504. #define RT5670_M_PDM2_R (0x1 << 8)
  505. #define RT5670_M_PDM2_R_SFT 8
  506. #define RT5670_PDM2_BUSY (0x1 << 7)
  507. #define RT5670_PDM1_BUSY (0x1 << 6)
  508. #define RT5670_PDM_PATTERN (0x1 << 5)
  509. #define RT5670_PDM_GAIN (0x1 << 4)
  510. #define RT5670_PDM_DIV_MASK (0x3)
  511. /* REC Left Mixer Control 1 (0x3b) */
  512. #define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
  513. #define RT5670_G_HP_L_RM_L_SFT 13
  514. #define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
  515. #define RT5670_G_IN_L_RM_L_SFT 10
  516. #define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
  517. #define RT5670_G_BST4_RM_L_SFT 7
  518. #define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
  519. #define RT5670_G_BST3_RM_L_SFT 4
  520. #define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
  521. #define RT5670_G_BST2_RM_L_SFT 1
  522. /* REC Left Mixer Control 2 (0x3c) */
  523. #define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
  524. #define RT5670_G_BST1_RM_L_SFT 13
  525. #define RT5670_M_IN_L_RM_L (0x1 << 5)
  526. #define RT5670_M_IN_L_RM_L_SFT 5
  527. #define RT5670_M_BST2_RM_L (0x1 << 3)
  528. #define RT5670_M_BST2_RM_L_SFT 3
  529. #define RT5670_M_BST1_RM_L (0x1 << 1)
  530. #define RT5670_M_BST1_RM_L_SFT 1
  531. /* REC Right Mixer Control 1 (0x3d) */
  532. #define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
  533. #define RT5670_G_HP_R_RM_R_SFT 13
  534. #define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
  535. #define RT5670_G_IN_R_RM_R_SFT 10
  536. #define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
  537. #define RT5670_G_BST4_RM_R_SFT 7
  538. #define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
  539. #define RT5670_G_BST3_RM_R_SFT 4
  540. #define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
  541. #define RT5670_G_BST2_RM_R_SFT 1
  542. /* REC Right Mixer Control 2 (0x3e) */
  543. #define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
  544. #define RT5670_G_BST1_RM_R_SFT 13
  545. #define RT5670_M_IN_R_RM_R (0x1 << 5)
  546. #define RT5670_M_IN_R_RM_R_SFT 5
  547. #define RT5670_M_BST2_RM_R (0x1 << 3)
  548. #define RT5670_M_BST2_RM_R_SFT 3
  549. #define RT5670_M_BST1_RM_R (0x1 << 1)
  550. #define RT5670_M_BST1_RM_R_SFT 1
  551. /* HPMIX Control (0x45) */
  552. #define RT5670_M_DAC2_HM (0x1 << 15)
  553. #define RT5670_M_DAC2_HM_SFT 15
  554. #define RT5670_M_HPVOL_HM (0x1 << 14)
  555. #define RT5670_M_HPVOL_HM_SFT 14
  556. #define RT5670_M_DAC1_HM (0x1 << 13)
  557. #define RT5670_M_DAC1_HM_SFT 13
  558. #define RT5670_G_HPOMIX_MASK (0x1 << 12)
  559. #define RT5670_G_HPOMIX_SFT 12
  560. #define RT5670_M_INR1_HMR (0x1 << 3)
  561. #define RT5670_M_INR1_HMR_SFT 3
  562. #define RT5670_M_DACR1_HMR (0x1 << 2)
  563. #define RT5670_M_DACR1_HMR_SFT 2
  564. #define RT5670_M_INL1_HML (0x1 << 1)
  565. #define RT5670_M_INL1_HML_SFT 1
  566. #define RT5670_M_DACL1_HML (0x1)
  567. #define RT5670_M_DACL1_HML_SFT 0
  568. /* Mono Output Mixer Control (0x4c) */
  569. #define RT5670_M_DAC_R2_MA (0x1 << 15)
  570. #define RT5670_M_DAC_R2_MA_SFT 15
  571. #define RT5670_M_DAC_L2_MA (0x1 << 14)
  572. #define RT5670_M_DAC_L2_MA_SFT 14
  573. #define RT5670_M_OV_R_MM (0x1 << 13)
  574. #define RT5670_M_OV_R_MM_SFT 13
  575. #define RT5670_M_OV_L_MM (0x1 << 12)
  576. #define RT5670_M_OV_L_MM_SFT 12
  577. #define RT5670_G_MONOMIX_MASK (0x1 << 10)
  578. #define RT5670_G_MONOMIX_SFT 10
  579. #define RT5670_M_DAC_R2_MM (0x1 << 9)
  580. #define RT5670_M_DAC_R2_MM_SFT 9
  581. #define RT5670_M_DAC_L2_MM (0x1 << 8)
  582. #define RT5670_M_DAC_L2_MM_SFT 8
  583. #define RT5670_M_BST4_MM (0x1 << 7)
  584. #define RT5670_M_BST4_MM_SFT 7
  585. /* Output Left Mixer Control 1 (0x4d) */
  586. #define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
  587. #define RT5670_G_BST3_OM_L_SFT 13
  588. #define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
  589. #define RT5670_G_BST2_OM_L_SFT 10
  590. #define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
  591. #define RT5670_G_BST1_OM_L_SFT 7
  592. #define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
  593. #define RT5670_G_IN_L_OM_L_SFT 4
  594. #define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
  595. #define RT5670_G_RM_L_OM_L_SFT 1
  596. /* Output Left Mixer Control 2 (0x4e) */
  597. #define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
  598. #define RT5670_G_DAC_R2_OM_L_SFT 13
  599. #define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
  600. #define RT5670_G_DAC_L2_OM_L_SFT 10
  601. #define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
  602. #define RT5670_G_DAC_L1_OM_L_SFT 7
  603. /* Output Left Mixer Control 3 (0x4f) */
  604. #define RT5670_M_BST1_OM_L (0x1 << 5)
  605. #define RT5670_M_BST1_OM_L_SFT 5
  606. #define RT5670_M_IN_L_OM_L (0x1 << 4)
  607. #define RT5670_M_IN_L_OM_L_SFT 4
  608. #define RT5670_M_DAC_L2_OM_L (0x1 << 1)
  609. #define RT5670_M_DAC_L2_OM_L_SFT 1
  610. #define RT5670_M_DAC_L1_OM_L (0x1)
  611. #define RT5670_M_DAC_L1_OM_L_SFT 0
  612. /* Output Right Mixer Control 1 (0x50) */
  613. #define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
  614. #define RT5670_G_BST4_OM_R_SFT 13
  615. #define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
  616. #define RT5670_G_BST2_OM_R_SFT 10
  617. #define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
  618. #define RT5670_G_BST1_OM_R_SFT 7
  619. #define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
  620. #define RT5670_G_IN_R_OM_R_SFT 4
  621. #define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
  622. #define RT5670_G_RM_R_OM_R_SFT 1
  623. /* Output Right Mixer Control 2 (0x51) */
  624. #define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
  625. #define RT5670_G_DAC_L2_OM_R_SFT 13
  626. #define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
  627. #define RT5670_G_DAC_R2_OM_R_SFT 10
  628. #define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
  629. #define RT5670_G_DAC_R1_OM_R_SFT 7
  630. /* Output Right Mixer Control 3 (0x52) */
  631. #define RT5670_M_BST2_OM_R (0x1 << 6)
  632. #define RT5670_M_BST2_OM_R_SFT 6
  633. #define RT5670_M_IN_R_OM_R (0x1 << 4)
  634. #define RT5670_M_IN_R_OM_R_SFT 4
  635. #define RT5670_M_DAC_R2_OM_R (0x1 << 1)
  636. #define RT5670_M_DAC_R2_OM_R_SFT 1
  637. #define RT5670_M_DAC_R1_OM_R (0x1)
  638. #define RT5670_M_DAC_R1_OM_R_SFT 0
  639. /* LOUT Mixer Control (0x53) */
  640. #define RT5670_M_DAC_L1_LM (0x1 << 15)
  641. #define RT5670_M_DAC_L1_LM_SFT 15
  642. #define RT5670_M_DAC_R1_LM (0x1 << 14)
  643. #define RT5670_M_DAC_R1_LM_SFT 14
  644. #define RT5670_M_OV_L_LM (0x1 << 13)
  645. #define RT5670_M_OV_L_LM_SFT 13
  646. #define RT5670_M_OV_R_LM (0x1 << 12)
  647. #define RT5670_M_OV_R_LM_SFT 12
  648. #define RT5670_G_LOUTMIX_MASK (0x1 << 11)
  649. #define RT5670_G_LOUTMIX_SFT 11
  650. /* Power Management for Digital 1 (0x61) */
  651. #define RT5670_PWR_I2S1 (0x1 << 15)
  652. #define RT5670_PWR_I2S1_BIT 15
  653. #define RT5670_PWR_I2S2 (0x1 << 14)
  654. #define RT5670_PWR_I2S2_BIT 14
  655. #define RT5670_PWR_DAC_L1 (0x1 << 12)
  656. #define RT5670_PWR_DAC_L1_BIT 12
  657. #define RT5670_PWR_DAC_R1 (0x1 << 11)
  658. #define RT5670_PWR_DAC_R1_BIT 11
  659. #define RT5670_PWR_DAC_L2 (0x1 << 7)
  660. #define RT5670_PWR_DAC_L2_BIT 7
  661. #define RT5670_PWR_DAC_R2 (0x1 << 6)
  662. #define RT5670_PWR_DAC_R2_BIT 6
  663. #define RT5670_PWR_ADC_L (0x1 << 2)
  664. #define RT5670_PWR_ADC_L_BIT 2
  665. #define RT5670_PWR_ADC_R (0x1 << 1)
  666. #define RT5670_PWR_ADC_R_BIT 1
  667. #define RT5670_PWR_CLS_D (0x1)
  668. #define RT5670_PWR_CLS_D_BIT 0
  669. /* Power Management for Digital 2 (0x62) */
  670. #define RT5670_PWR_ADC_S1F (0x1 << 15)
  671. #define RT5670_PWR_ADC_S1F_BIT 15
  672. #define RT5670_PWR_ADC_MF_L (0x1 << 14)
  673. #define RT5670_PWR_ADC_MF_L_BIT 14
  674. #define RT5670_PWR_ADC_MF_R (0x1 << 13)
  675. #define RT5670_PWR_ADC_MF_R_BIT 13
  676. #define RT5670_PWR_I2S_DSP (0x1 << 12)
  677. #define RT5670_PWR_I2S_DSP_BIT 12
  678. #define RT5670_PWR_DAC_S1F (0x1 << 11)
  679. #define RT5670_PWR_DAC_S1F_BIT 11
  680. #define RT5670_PWR_DAC_MF_L (0x1 << 10)
  681. #define RT5670_PWR_DAC_MF_L_BIT 10
  682. #define RT5670_PWR_DAC_MF_R (0x1 << 9)
  683. #define RT5670_PWR_DAC_MF_R_BIT 9
  684. #define RT5670_PWR_ADC_S2F (0x1 << 8)
  685. #define RT5670_PWR_ADC_S2F_BIT 8
  686. #define RT5670_PWR_PDM1 (0x1 << 7)
  687. #define RT5670_PWR_PDM1_BIT 7
  688. #define RT5670_PWR_PDM2 (0x1 << 6)
  689. #define RT5670_PWR_PDM2_BIT 6
  690. /* Power Management for Analog 1 (0x63) */
  691. #define RT5670_PWR_VREF1 (0x1 << 15)
  692. #define RT5670_PWR_VREF1_BIT 15
  693. #define RT5670_PWR_FV1 (0x1 << 14)
  694. #define RT5670_PWR_FV1_BIT 14
  695. #define RT5670_PWR_MB (0x1 << 13)
  696. #define RT5670_PWR_MB_BIT 13
  697. #define RT5670_PWR_LM (0x1 << 12)
  698. #define RT5670_PWR_LM_BIT 12
  699. #define RT5670_PWR_BG (0x1 << 11)
  700. #define RT5670_PWR_BG_BIT 11
  701. #define RT5670_PWR_HP_L (0x1 << 7)
  702. #define RT5670_PWR_HP_L_BIT 7
  703. #define RT5670_PWR_HP_R (0x1 << 6)
  704. #define RT5670_PWR_HP_R_BIT 6
  705. #define RT5670_PWR_HA (0x1 << 5)
  706. #define RT5670_PWR_HA_BIT 5
  707. #define RT5670_PWR_VREF2 (0x1 << 4)
  708. #define RT5670_PWR_VREF2_BIT 4
  709. #define RT5670_PWR_FV2 (0x1 << 3)
  710. #define RT5670_PWR_FV2_BIT 3
  711. #define RT5670_LDO_SEL_MASK (0x7)
  712. #define RT5670_LDO_SEL_SFT 0
  713. /* Power Management for Analog 2 (0x64) */
  714. #define RT5670_PWR_BST1 (0x1 << 15)
  715. #define RT5670_PWR_BST1_BIT 15
  716. #define RT5670_PWR_BST2 (0x1 << 13)
  717. #define RT5670_PWR_BST2_BIT 13
  718. #define RT5670_PWR_MB1 (0x1 << 11)
  719. #define RT5670_PWR_MB1_BIT 11
  720. #define RT5670_PWR_MB2 (0x1 << 10)
  721. #define RT5670_PWR_MB2_BIT 10
  722. #define RT5670_PWR_PLL (0x1 << 9)
  723. #define RT5670_PWR_PLL_BIT 9
  724. #define RT5670_PWR_BST1_P (0x1 << 6)
  725. #define RT5670_PWR_BST1_P_BIT 6
  726. #define RT5670_PWR_BST2_P (0x1 << 4)
  727. #define RT5670_PWR_BST2_P_BIT 4
  728. #define RT5670_PWR_JD1 (0x1 << 2)
  729. #define RT5670_PWR_JD1_BIT 2
  730. #define RT5670_PWR_JD (0x1 << 1)
  731. #define RT5670_PWR_JD_BIT 1
  732. /* Power Management for Mixer (0x65) */
  733. #define RT5670_PWR_OM_L (0x1 << 15)
  734. #define RT5670_PWR_OM_L_BIT 15
  735. #define RT5670_PWR_OM_R (0x1 << 14)
  736. #define RT5670_PWR_OM_R_BIT 14
  737. #define RT5670_PWR_RM_L (0x1 << 11)
  738. #define RT5670_PWR_RM_L_BIT 11
  739. #define RT5670_PWR_RM_R (0x1 << 10)
  740. #define RT5670_PWR_RM_R_BIT 10
  741. /* Power Management for Volume (0x66) */
  742. #define RT5670_PWR_HV_L (0x1 << 11)
  743. #define RT5670_PWR_HV_L_BIT 11
  744. #define RT5670_PWR_HV_R (0x1 << 10)
  745. #define RT5670_PWR_HV_R_BIT 10
  746. #define RT5670_PWR_IN_L (0x1 << 9)
  747. #define RT5670_PWR_IN_L_BIT 9
  748. #define RT5670_PWR_IN_R (0x1 << 8)
  749. #define RT5670_PWR_IN_R_BIT 8
  750. #define RT5670_PWR_MIC_DET (0x1 << 5)
  751. #define RT5670_PWR_MIC_DET_BIT 5
  752. /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
  753. #define RT5670_I2S_MS_MASK (0x1 << 15)
  754. #define RT5670_I2S_MS_SFT 15
  755. #define RT5670_I2S_MS_M (0x0 << 15)
  756. #define RT5670_I2S_MS_S (0x1 << 15)
  757. #define RT5670_I2S_IF_MASK (0x7 << 12)
  758. #define RT5670_I2S_IF_SFT 12
  759. #define RT5670_I2S_O_CP_MASK (0x3 << 10)
  760. #define RT5670_I2S_O_CP_SFT 10
  761. #define RT5670_I2S_O_CP_OFF (0x0 << 10)
  762. #define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
  763. #define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
  764. #define RT5670_I2S_I_CP_MASK (0x3 << 8)
  765. #define RT5670_I2S_I_CP_SFT 8
  766. #define RT5670_I2S_I_CP_OFF (0x0 << 8)
  767. #define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
  768. #define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
  769. #define RT5670_I2S_BP_MASK (0x1 << 7)
  770. #define RT5670_I2S_BP_SFT 7
  771. #define RT5670_I2S_BP_NOR (0x0 << 7)
  772. #define RT5670_I2S_BP_INV (0x1 << 7)
  773. #define RT5670_I2S_DL_MASK (0x3 << 2)
  774. #define RT5670_I2S_DL_SFT 2
  775. #define RT5670_I2S_DL_16 (0x0 << 2)
  776. #define RT5670_I2S_DL_20 (0x1 << 2)
  777. #define RT5670_I2S_DL_24 (0x2 << 2)
  778. #define RT5670_I2S_DL_8 (0x3 << 2)
  779. #define RT5670_I2S_DF_MASK (0x3)
  780. #define RT5670_I2S_DF_SFT 0
  781. #define RT5670_I2S_DF_I2S (0x0)
  782. #define RT5670_I2S_DF_LEFT (0x1)
  783. #define RT5670_I2S_DF_PCM_A (0x2)
  784. #define RT5670_I2S_DF_PCM_B (0x3)
  785. /* I2S2 Audio Serial Data Port Control (0x71) */
  786. #define RT5670_I2S2_SDI_MASK (0x1 << 6)
  787. #define RT5670_I2S2_SDI_SFT 6
  788. #define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
  789. #define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
  790. /* ADC/DAC Clock Control 1 (0x73) */
  791. #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
  792. #define RT5670_I2S_BCLK_MS1_SFT 15
  793. #define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
  794. #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
  795. #define RT5670_I2S_PD1_MASK (0x7 << 12)
  796. #define RT5670_I2S_PD1_SFT 12
  797. #define RT5670_I2S_PD1_1 (0x0 << 12)
  798. #define RT5670_I2S_PD1_2 (0x1 << 12)
  799. #define RT5670_I2S_PD1_3 (0x2 << 12)
  800. #define RT5670_I2S_PD1_4 (0x3 << 12)
  801. #define RT5670_I2S_PD1_6 (0x4 << 12)
  802. #define RT5670_I2S_PD1_8 (0x5 << 12)
  803. #define RT5670_I2S_PD1_12 (0x6 << 12)
  804. #define RT5670_I2S_PD1_16 (0x7 << 12)
  805. #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
  806. #define RT5670_I2S_BCLK_MS2_SFT 11
  807. #define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
  808. #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
  809. #define RT5670_I2S_PD2_MASK (0x7 << 8)
  810. #define RT5670_I2S_PD2_SFT 8
  811. #define RT5670_I2S_PD2_1 (0x0 << 8)
  812. #define RT5670_I2S_PD2_2 (0x1 << 8)
  813. #define RT5670_I2S_PD2_3 (0x2 << 8)
  814. #define RT5670_I2S_PD2_4 (0x3 << 8)
  815. #define RT5670_I2S_PD2_6 (0x4 << 8)
  816. #define RT5670_I2S_PD2_8 (0x5 << 8)
  817. #define RT5670_I2S_PD2_12 (0x6 << 8)
  818. #define RT5670_I2S_PD2_16 (0x7 << 8)
  819. #define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
  820. #define RT5670_I2S_BCLK_MS3_SFT 7
  821. #define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
  822. #define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
  823. #define RT5670_I2S_PD3_MASK (0x7 << 4)
  824. #define RT5670_I2S_PD3_SFT 4
  825. #define RT5670_I2S_PD3_1 (0x0 << 4)
  826. #define RT5670_I2S_PD3_2 (0x1 << 4)
  827. #define RT5670_I2S_PD3_3 (0x2 << 4)
  828. #define RT5670_I2S_PD3_4 (0x3 << 4)
  829. #define RT5670_I2S_PD3_6 (0x4 << 4)
  830. #define RT5670_I2S_PD3_8 (0x5 << 4)
  831. #define RT5670_I2S_PD3_12 (0x6 << 4)
  832. #define RT5670_I2S_PD3_16 (0x7 << 4)
  833. #define RT5670_DAC_OSR_MASK (0x3 << 2)
  834. #define RT5670_DAC_OSR_SFT 2
  835. #define RT5670_DAC_OSR_128 (0x0 << 2)
  836. #define RT5670_DAC_OSR_64 (0x1 << 2)
  837. #define RT5670_DAC_OSR_32 (0x2 << 2)
  838. #define RT5670_DAC_OSR_16 (0x3 << 2)
  839. #define RT5670_ADC_OSR_MASK (0x3)
  840. #define RT5670_ADC_OSR_SFT 0
  841. #define RT5670_ADC_OSR_128 (0x0)
  842. #define RT5670_ADC_OSR_64 (0x1)
  843. #define RT5670_ADC_OSR_32 (0x2)
  844. #define RT5670_ADC_OSR_16 (0x3)
  845. /* ADC/DAC Clock Control 2 (0x74) */
  846. #define RT5670_DAC_L_OSR_MASK (0x3 << 14)
  847. #define RT5670_DAC_L_OSR_SFT 14
  848. #define RT5670_DAC_L_OSR_128 (0x0 << 14)
  849. #define RT5670_DAC_L_OSR_64 (0x1 << 14)
  850. #define RT5670_DAC_L_OSR_32 (0x2 << 14)
  851. #define RT5670_DAC_L_OSR_16 (0x3 << 14)
  852. #define RT5670_ADC_R_OSR_MASK (0x3 << 12)
  853. #define RT5670_ADC_R_OSR_SFT 12
  854. #define RT5670_ADC_R_OSR_128 (0x0 << 12)
  855. #define RT5670_ADC_R_OSR_64 (0x1 << 12)
  856. #define RT5670_ADC_R_OSR_32 (0x2 << 12)
  857. #define RT5670_ADC_R_OSR_16 (0x3 << 12)
  858. #define RT5670_DAHPF_EN (0x1 << 11)
  859. #define RT5670_DAHPF_EN_SFT 11
  860. #define RT5670_ADHPF_EN (0x1 << 10)
  861. #define RT5670_ADHPF_EN_SFT 10
  862. /* Digital Microphone Control (0x75) */
  863. #define RT5670_DMIC_1_EN_MASK (0x1 << 15)
  864. #define RT5670_DMIC_1_EN_SFT 15
  865. #define RT5670_DMIC_1_DIS (0x0 << 15)
  866. #define RT5670_DMIC_1_EN (0x1 << 15)
  867. #define RT5670_DMIC_2_EN_MASK (0x1 << 14)
  868. #define RT5670_DMIC_2_EN_SFT 14
  869. #define RT5670_DMIC_2_DIS (0x0 << 14)
  870. #define RT5670_DMIC_2_EN (0x1 << 14)
  871. #define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
  872. #define RT5670_DMIC_1L_LH_SFT 13
  873. #define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
  874. #define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
  875. #define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
  876. #define RT5670_DMIC_1R_LH_SFT 12
  877. #define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
  878. #define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
  879. #define RT5670_DMIC_2_DP_MASK (0x1 << 10)
  880. #define RT5670_DMIC_2_DP_SFT 10
  881. #define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
  882. #define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
  883. #define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
  884. #define RT5670_DMIC_2L_LH_SFT 9
  885. #define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
  886. #define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
  887. #define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
  888. #define RT5670_DMIC_2R_LH_SFT 8
  889. #define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
  890. #define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
  891. #define RT5670_DMIC_CLK_MASK (0x7 << 5)
  892. #define RT5670_DMIC_CLK_SFT 5
  893. #define RT5670_DMIC_3_EN_MASK (0x1 << 4)
  894. #define RT5670_DMIC_3_EN_SFT 4
  895. #define RT5670_DMIC_3_DIS (0x0 << 4)
  896. #define RT5670_DMIC_3_EN (0x1 << 4)
  897. #define RT5670_DMIC_1_DP_MASK (0x3 << 0)
  898. #define RT5670_DMIC_1_DP_SFT 0
  899. #define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
  900. #define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
  901. #define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
  902. /* Digital Microphone Control2 (0x76) */
  903. #define RT5670_DMIC_3_DP_MASK (0x3 << 6)
  904. #define RT5670_DMIC_3_DP_SFT 6
  905. #define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
  906. #define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
  907. #define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
  908. /* Global Clock Control (0x80) */
  909. #define RT5670_SCLK_SRC_MASK (0x3 << 14)
  910. #define RT5670_SCLK_SRC_SFT 14
  911. #define RT5670_SCLK_SRC_MCLK (0x0 << 14)
  912. #define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
  913. #define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
  914. #define RT5670_PLL1_SRC_MASK (0x7 << 11)
  915. #define RT5670_PLL1_SRC_SFT 11
  916. #define RT5670_PLL1_SRC_MCLK (0x0 << 11)
  917. #define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
  918. #define RT5670_PLL1_SRC_BCLK2 (0x2 << 11)
  919. #define RT5670_PLL1_SRC_BCLK3 (0x3 << 11)
  920. #define RT5670_PLL1_PD_MASK (0x1 << 3)
  921. #define RT5670_PLL1_PD_SFT 3
  922. #define RT5670_PLL1_PD_1 (0x0 << 3)
  923. #define RT5670_PLL1_PD_2 (0x1 << 3)
  924. #define RT5670_PLL_INP_MAX 40000000
  925. #define RT5670_PLL_INP_MIN 256000
  926. /* PLL M/N/K Code Control 1 (0x81) */
  927. #define RT5670_PLL_N_MAX 0x1ff
  928. #define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7)
  929. #define RT5670_PLL_N_SFT 7
  930. #define RT5670_PLL_K_MAX 0x1f
  931. #define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX)
  932. #define RT5670_PLL_K_SFT 0
  933. /* PLL M/N/K Code Control 2 (0x82) */
  934. #define RT5670_PLL_M_MAX 0xf
  935. #define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
  936. #define RT5670_PLL_M_SFT 12
  937. #define RT5670_PLL_M_BP (0x1 << 11)
  938. #define RT5670_PLL_M_BP_SFT 11
  939. /* ASRC Control 1 (0x83) */
  940. #define RT5670_STO_T_MASK (0x1 << 15)
  941. #define RT5670_STO_T_SFT 15
  942. #define RT5670_STO_T_SCLK (0x0 << 15)
  943. #define RT5670_STO_T_LRCK1 (0x1 << 15)
  944. #define RT5670_M1_T_MASK (0x1 << 14)
  945. #define RT5670_M1_T_SFT 14
  946. #define RT5670_M1_T_I2S2 (0x0 << 14)
  947. #define RT5670_M1_T_I2S2_D3 (0x1 << 14)
  948. #define RT5670_I2S2_F_MASK (0x1 << 12)
  949. #define RT5670_I2S2_F_SFT 12
  950. #define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
  951. #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
  952. #define RT5670_DMIC_1_M_MASK (0x1 << 9)
  953. #define RT5670_DMIC_1_M_SFT 9
  954. #define RT5670_DMIC_1_M_NOR (0x0 << 9)
  955. #define RT5670_DMIC_1_M_ASYN (0x1 << 9)
  956. #define RT5670_DMIC_2_M_MASK (0x1 << 8)
  957. #define RT5670_DMIC_2_M_SFT 8
  958. #define RT5670_DMIC_2_M_NOR (0x0 << 8)
  959. #define RT5670_DMIC_2_M_ASYN (0x1 << 8)
  960. /* ASRC clock source selection (0x84, 0x85) */
  961. #define RT5670_CLK_SEL_SYS (0x0)
  962. #define RT5670_CLK_SEL_I2S1_ASRC (0x1)
  963. #define RT5670_CLK_SEL_I2S2_ASRC (0x2)
  964. #define RT5670_CLK_SEL_I2S3_ASRC (0x3)
  965. #define RT5670_CLK_SEL_SYS2 (0x5)
  966. #define RT5670_CLK_SEL_SYS3 (0x6)
  967. /* ASRC Control 2 (0x84) */
  968. #define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
  969. #define RT5670_DA_STO_CLK_SEL_SFT 12
  970. #define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
  971. #define RT5670_DA_MONOL_CLK_SEL_SFT 8
  972. #define RT5670_DA_MONOR_CLK_SEL_MASK (0xf << 4)
  973. #define RT5670_DA_MONOR_CLK_SEL_SFT 4
  974. #define RT5670_AD_STO1_CLK_SEL_MASK (0xf << 0)
  975. #define RT5670_AD_STO1_CLK_SEL_SFT 0
  976. /* ASRC Control 3 (0x85) */
  977. #define RT5670_UP_CLK_SEL_MASK (0xf << 12)
  978. #define RT5670_UP_CLK_SEL_SFT 12
  979. #define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
  980. #define RT5670_DOWN_CLK_SEL_SFT 8
  981. #define RT5670_AD_MONOL_CLK_SEL_MASK (0xf << 4)
  982. #define RT5670_AD_MONOL_CLK_SEL_SFT 4
  983. #define RT5670_AD_MONOR_CLK_SEL_MASK (0xf << 0)
  984. #define RT5670_AD_MONOR_CLK_SEL_SFT 0
  985. /* ASRC Control 4 (0x89) */
  986. #define RT5670_I2S1_PD_MASK (0x7 << 12)
  987. #define RT5670_I2S1_PD_SFT 12
  988. #define RT5670_I2S2_PD_MASK (0x7 << 8)
  989. #define RT5670_I2S2_PD_SFT 8
  990. /* HPOUT Over Current Detection (0x8b) */
  991. #define RT5670_HP_OVCD_MASK (0x1 << 10)
  992. #define RT5670_HP_OVCD_SFT 10
  993. #define RT5670_HP_OVCD_DIS (0x0 << 10)
  994. #define RT5670_HP_OVCD_EN (0x1 << 10)
  995. #define RT5670_HP_OC_TH_MASK (0x3 << 8)
  996. #define RT5670_HP_OC_TH_SFT 8
  997. #define RT5670_HP_OC_TH_90 (0x0 << 8)
  998. #define RT5670_HP_OC_TH_105 (0x1 << 8)
  999. #define RT5670_HP_OC_TH_120 (0x2 << 8)
  1000. #define RT5670_HP_OC_TH_135 (0x3 << 8)
  1001. /* Class D Over Current Control (0x8c) */
  1002. #define RT5670_CLSD_OC_MASK (0x1 << 9)
  1003. #define RT5670_CLSD_OC_SFT 9
  1004. #define RT5670_CLSD_OC_PU (0x0 << 9)
  1005. #define RT5670_CLSD_OC_PD (0x1 << 9)
  1006. #define RT5670_AUTO_PD_MASK (0x1 << 8)
  1007. #define RT5670_AUTO_PD_SFT 8
  1008. #define RT5670_AUTO_PD_DIS (0x0 << 8)
  1009. #define RT5670_AUTO_PD_EN (0x1 << 8)
  1010. #define RT5670_CLSD_OC_TH_MASK (0x3f)
  1011. #define RT5670_CLSD_OC_TH_SFT 0
  1012. /* Class D Output Control (0x8d) */
  1013. #define RT5670_CLSD_RATIO_MASK (0xf << 12)
  1014. #define RT5670_CLSD_RATIO_SFT 12
  1015. #define RT5670_CLSD_OM_MASK (0x1 << 11)
  1016. #define RT5670_CLSD_OM_SFT 11
  1017. #define RT5670_CLSD_OM_MONO (0x0 << 11)
  1018. #define RT5670_CLSD_OM_STO (0x1 << 11)
  1019. #define RT5670_CLSD_SCH_MASK (0x1 << 10)
  1020. #define RT5670_CLSD_SCH_SFT 10
  1021. #define RT5670_CLSD_SCH_L (0x0 << 10)
  1022. #define RT5670_CLSD_SCH_S (0x1 << 10)
  1023. /* Depop Mode Control 1 (0x8e) */
  1024. #define RT5670_SMT_TRIG_MASK (0x1 << 15)
  1025. #define RT5670_SMT_TRIG_SFT 15
  1026. #define RT5670_SMT_TRIG_DIS (0x0 << 15)
  1027. #define RT5670_SMT_TRIG_EN (0x1 << 15)
  1028. #define RT5670_HP_L_SMT_MASK (0x1 << 9)
  1029. #define RT5670_HP_L_SMT_SFT 9
  1030. #define RT5670_HP_L_SMT_DIS (0x0 << 9)
  1031. #define RT5670_HP_L_SMT_EN (0x1 << 9)
  1032. #define RT5670_HP_R_SMT_MASK (0x1 << 8)
  1033. #define RT5670_HP_R_SMT_SFT 8
  1034. #define RT5670_HP_R_SMT_DIS (0x0 << 8)
  1035. #define RT5670_HP_R_SMT_EN (0x1 << 8)
  1036. #define RT5670_HP_CD_PD_MASK (0x1 << 7)
  1037. #define RT5670_HP_CD_PD_SFT 7
  1038. #define RT5670_HP_CD_PD_DIS (0x0 << 7)
  1039. #define RT5670_HP_CD_PD_EN (0x1 << 7)
  1040. #define RT5670_RSTN_MASK (0x1 << 6)
  1041. #define RT5670_RSTN_SFT 6
  1042. #define RT5670_RSTN_DIS (0x0 << 6)
  1043. #define RT5670_RSTN_EN (0x1 << 6)
  1044. #define RT5670_RSTP_MASK (0x1 << 5)
  1045. #define RT5670_RSTP_SFT 5
  1046. #define RT5670_RSTP_DIS (0x0 << 5)
  1047. #define RT5670_RSTP_EN (0x1 << 5)
  1048. #define RT5670_HP_CO_MASK (0x1 << 4)
  1049. #define RT5670_HP_CO_SFT 4
  1050. #define RT5670_HP_CO_DIS (0x0 << 4)
  1051. #define RT5670_HP_CO_EN (0x1 << 4)
  1052. #define RT5670_HP_CP_MASK (0x1 << 3)
  1053. #define RT5670_HP_CP_SFT 3
  1054. #define RT5670_HP_CP_PD (0x0 << 3)
  1055. #define RT5670_HP_CP_PU (0x1 << 3)
  1056. #define RT5670_HP_SG_MASK (0x1 << 2)
  1057. #define RT5670_HP_SG_SFT 2
  1058. #define RT5670_HP_SG_DIS (0x0 << 2)
  1059. #define RT5670_HP_SG_EN (0x1 << 2)
  1060. #define RT5670_HP_DP_MASK (0x1 << 1)
  1061. #define RT5670_HP_DP_SFT 1
  1062. #define RT5670_HP_DP_PD (0x0 << 1)
  1063. #define RT5670_HP_DP_PU (0x1 << 1)
  1064. #define RT5670_HP_CB_MASK (0x1)
  1065. #define RT5670_HP_CB_SFT 0
  1066. #define RT5670_HP_CB_PD (0x0)
  1067. #define RT5670_HP_CB_PU (0x1)
  1068. /* Depop Mode Control 2 (0x8f) */
  1069. #define RT5670_DEPOP_MASK (0x1 << 13)
  1070. #define RT5670_DEPOP_SFT 13
  1071. #define RT5670_DEPOP_AUTO (0x0 << 13)
  1072. #define RT5670_DEPOP_MAN (0x1 << 13)
  1073. #define RT5670_RAMP_MASK (0x1 << 12)
  1074. #define RT5670_RAMP_SFT 12
  1075. #define RT5670_RAMP_DIS (0x0 << 12)
  1076. #define RT5670_RAMP_EN (0x1 << 12)
  1077. #define RT5670_BPS_MASK (0x1 << 11)
  1078. #define RT5670_BPS_SFT 11
  1079. #define RT5670_BPS_DIS (0x0 << 11)
  1080. #define RT5670_BPS_EN (0x1 << 11)
  1081. #define RT5670_FAST_UPDN_MASK (0x1 << 10)
  1082. #define RT5670_FAST_UPDN_SFT 10
  1083. #define RT5670_FAST_UPDN_DIS (0x0 << 10)
  1084. #define RT5670_FAST_UPDN_EN (0x1 << 10)
  1085. #define RT5670_MRES_MASK (0x3 << 8)
  1086. #define RT5670_MRES_SFT 8
  1087. #define RT5670_MRES_15MO (0x0 << 8)
  1088. #define RT5670_MRES_25MO (0x1 << 8)
  1089. #define RT5670_MRES_35MO (0x2 << 8)
  1090. #define RT5670_MRES_45MO (0x3 << 8)
  1091. #define RT5670_VLO_MASK (0x1 << 7)
  1092. #define RT5670_VLO_SFT 7
  1093. #define RT5670_VLO_3V (0x0 << 7)
  1094. #define RT5670_VLO_32V (0x1 << 7)
  1095. #define RT5670_DIG_DP_MASK (0x1 << 6)
  1096. #define RT5670_DIG_DP_SFT 6
  1097. #define RT5670_DIG_DP_DIS (0x0 << 6)
  1098. #define RT5670_DIG_DP_EN (0x1 << 6)
  1099. #define RT5670_DP_TH_MASK (0x3 << 4)
  1100. #define RT5670_DP_TH_SFT 4
  1101. /* Depop Mode Control 3 (0x90) */
  1102. #define RT5670_CP_SYS_MASK (0x7 << 12)
  1103. #define RT5670_CP_SYS_SFT 12
  1104. #define RT5670_CP_FQ1_MASK (0x7 << 8)
  1105. #define RT5670_CP_FQ1_SFT 8
  1106. #define RT5670_CP_FQ2_MASK (0x7 << 4)
  1107. #define RT5670_CP_FQ2_SFT 4
  1108. #define RT5670_CP_FQ3_MASK (0x7)
  1109. #define RT5670_CP_FQ3_SFT 0
  1110. #define RT5670_CP_FQ_1_5_KHZ 0
  1111. #define RT5670_CP_FQ_3_KHZ 1
  1112. #define RT5670_CP_FQ_6_KHZ 2
  1113. #define RT5670_CP_FQ_12_KHZ 3
  1114. #define RT5670_CP_FQ_24_KHZ 4
  1115. #define RT5670_CP_FQ_48_KHZ 5
  1116. #define RT5670_CP_FQ_96_KHZ 6
  1117. #define RT5670_CP_FQ_192_KHZ 7
  1118. /* HPOUT charge pump (0x91) */
  1119. #define RT5670_OSW_L_MASK (0x1 << 11)
  1120. #define RT5670_OSW_L_SFT 11
  1121. #define RT5670_OSW_L_DIS (0x0 << 11)
  1122. #define RT5670_OSW_L_EN (0x1 << 11)
  1123. #define RT5670_OSW_R_MASK (0x1 << 10)
  1124. #define RT5670_OSW_R_SFT 10
  1125. #define RT5670_OSW_R_DIS (0x0 << 10)
  1126. #define RT5670_OSW_R_EN (0x1 << 10)
  1127. #define RT5670_PM_HP_MASK (0x3 << 8)
  1128. #define RT5670_PM_HP_SFT 8
  1129. #define RT5670_PM_HP_LV (0x0 << 8)
  1130. #define RT5670_PM_HP_MV (0x1 << 8)
  1131. #define RT5670_PM_HP_HV (0x2 << 8)
  1132. #define RT5670_IB_HP_MASK (0x3 << 6)
  1133. #define RT5670_IB_HP_SFT 6
  1134. #define RT5670_IB_HP_125IL (0x0 << 6)
  1135. #define RT5670_IB_HP_25IL (0x1 << 6)
  1136. #define RT5670_IB_HP_5IL (0x2 << 6)
  1137. #define RT5670_IB_HP_1IL (0x3 << 6)
  1138. /* PV detection and SPK gain control (0x92) */
  1139. #define RT5670_PVDD_DET_MASK (0x1 << 15)
  1140. #define RT5670_PVDD_DET_SFT 15
  1141. #define RT5670_PVDD_DET_DIS (0x0 << 15)
  1142. #define RT5670_PVDD_DET_EN (0x1 << 15)
  1143. #define RT5670_SPK_AG_MASK (0x1 << 14)
  1144. #define RT5670_SPK_AG_SFT 14
  1145. #define RT5670_SPK_AG_DIS (0x0 << 14)
  1146. #define RT5670_SPK_AG_EN (0x1 << 14)
  1147. /* Micbias Control (0x93) */
  1148. #define RT5670_MIC1_BS_MASK (0x1 << 15)
  1149. #define RT5670_MIC1_BS_SFT 15
  1150. #define RT5670_MIC1_BS_9AV (0x0 << 15)
  1151. #define RT5670_MIC1_BS_75AV (0x1 << 15)
  1152. #define RT5670_MIC2_BS_MASK (0x1 << 14)
  1153. #define RT5670_MIC2_BS_SFT 14
  1154. #define RT5670_MIC2_BS_9AV (0x0 << 14)
  1155. #define RT5670_MIC2_BS_75AV (0x1 << 14)
  1156. #define RT5670_MIC1_CLK_MASK (0x1 << 13)
  1157. #define RT5670_MIC1_CLK_SFT 13
  1158. #define RT5670_MIC1_CLK_DIS (0x0 << 13)
  1159. #define RT5670_MIC1_CLK_EN (0x1 << 13)
  1160. #define RT5670_MIC2_CLK_MASK (0x1 << 12)
  1161. #define RT5670_MIC2_CLK_SFT 12
  1162. #define RT5670_MIC2_CLK_DIS (0x0 << 12)
  1163. #define RT5670_MIC2_CLK_EN (0x1 << 12)
  1164. #define RT5670_MIC1_OVCD_MASK (0x1 << 11)
  1165. #define RT5670_MIC1_OVCD_SFT 11
  1166. #define RT5670_MIC1_OVCD_DIS (0x0 << 11)
  1167. #define RT5670_MIC1_OVCD_EN (0x1 << 11)
  1168. #define RT5670_MIC1_OVTH_MASK (0x3 << 9)
  1169. #define RT5670_MIC1_OVTH_SFT 9
  1170. #define RT5670_MIC1_OVTH_600UA (0x0 << 9)
  1171. #define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
  1172. #define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
  1173. #define RT5670_MIC2_OVCD_MASK (0x1 << 8)
  1174. #define RT5670_MIC2_OVCD_SFT 8
  1175. #define RT5670_MIC2_OVCD_DIS (0x0 << 8)
  1176. #define RT5670_MIC2_OVCD_EN (0x1 << 8)
  1177. #define RT5670_MIC2_OVTH_MASK (0x3 << 6)
  1178. #define RT5670_MIC2_OVTH_SFT 6
  1179. #define RT5670_MIC2_OVTH_600UA (0x0 << 6)
  1180. #define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
  1181. #define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
  1182. #define RT5670_PWR_MB_MASK (0x1 << 5)
  1183. #define RT5670_PWR_MB_SFT 5
  1184. #define RT5670_PWR_MB_PD (0x0 << 5)
  1185. #define RT5670_PWR_MB_PU (0x1 << 5)
  1186. #define RT5670_PWR_CLK25M_MASK (0x1 << 4)
  1187. #define RT5670_PWR_CLK25M_SFT 4
  1188. #define RT5670_PWR_CLK25M_PD (0x0 << 4)
  1189. #define RT5670_PWR_CLK25M_PU (0x1 << 4)
  1190. /* Analog JD Control 1 (0x94) */
  1191. #define RT5670_JD1_MODE_MASK (0x3 << 0)
  1192. #define RT5670_JD1_MODE_0 (0x0 << 0)
  1193. #define RT5670_JD1_MODE_1 (0x1 << 0)
  1194. #define RT5670_JD1_MODE_2 (0x2 << 0)
  1195. /* VAD Control 4 (0x9d) */
  1196. #define RT5670_VAD_SEL_MASK (0x3 << 8)
  1197. #define RT5670_VAD_SEL_SFT 8
  1198. /* EQ Control 1 (0xb0) */
  1199. #define RT5670_EQ_SRC_MASK (0x1 << 15)
  1200. #define RT5670_EQ_SRC_SFT 15
  1201. #define RT5670_EQ_SRC_DAC (0x0 << 15)
  1202. #define RT5670_EQ_SRC_ADC (0x1 << 15)
  1203. #define RT5670_EQ_UPD (0x1 << 14)
  1204. #define RT5670_EQ_UPD_BIT 14
  1205. #define RT5670_EQ_CD_MASK (0x1 << 13)
  1206. #define RT5670_EQ_CD_SFT 13
  1207. #define RT5670_EQ_CD_DIS (0x0 << 13)
  1208. #define RT5670_EQ_CD_EN (0x1 << 13)
  1209. #define RT5670_EQ_DITH_MASK (0x3 << 8)
  1210. #define RT5670_EQ_DITH_SFT 8
  1211. #define RT5670_EQ_DITH_NOR (0x0 << 8)
  1212. #define RT5670_EQ_DITH_LSB (0x1 << 8)
  1213. #define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
  1214. #define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
  1215. /* EQ Control 2 (0xb1) */
  1216. #define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
  1217. #define RT5670_EQ_HPF1_M_SFT 8
  1218. #define RT5670_EQ_HPF1_M_HI (0x0 << 8)
  1219. #define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
  1220. #define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
  1221. #define RT5670_EQ_LPF1_M_SFT 7
  1222. #define RT5670_EQ_LPF1_M_LO (0x0 << 7)
  1223. #define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
  1224. #define RT5670_EQ_HPF2_MASK (0x1 << 6)
  1225. #define RT5670_EQ_HPF2_SFT 6
  1226. #define RT5670_EQ_HPF2_DIS (0x0 << 6)
  1227. #define RT5670_EQ_HPF2_EN (0x1 << 6)
  1228. #define RT5670_EQ_HPF1_MASK (0x1 << 5)
  1229. #define RT5670_EQ_HPF1_SFT 5
  1230. #define RT5670_EQ_HPF1_DIS (0x0 << 5)
  1231. #define RT5670_EQ_HPF1_EN (0x1 << 5)
  1232. #define RT5670_EQ_BPF4_MASK (0x1 << 4)
  1233. #define RT5670_EQ_BPF4_SFT 4
  1234. #define RT5670_EQ_BPF4_DIS (0x0 << 4)
  1235. #define RT5670_EQ_BPF4_EN (0x1 << 4)
  1236. #define RT5670_EQ_BPF3_MASK (0x1 << 3)
  1237. #define RT5670_EQ_BPF3_SFT 3
  1238. #define RT5670_EQ_BPF3_DIS (0x0 << 3)
  1239. #define RT5670_EQ_BPF3_EN (0x1 << 3)
  1240. #define RT5670_EQ_BPF2_MASK (0x1 << 2)
  1241. #define RT5670_EQ_BPF2_SFT 2
  1242. #define RT5670_EQ_BPF2_DIS (0x0 << 2)
  1243. #define RT5670_EQ_BPF2_EN (0x1 << 2)
  1244. #define RT5670_EQ_BPF1_MASK (0x1 << 1)
  1245. #define RT5670_EQ_BPF1_SFT 1
  1246. #define RT5670_EQ_BPF1_DIS (0x0 << 1)
  1247. #define RT5670_EQ_BPF1_EN (0x1 << 1)
  1248. #define RT5670_EQ_LPF_MASK (0x1)
  1249. #define RT5670_EQ_LPF_SFT 0
  1250. #define RT5670_EQ_LPF_DIS (0x0)
  1251. #define RT5670_EQ_LPF_EN (0x1)
  1252. #define RT5670_EQ_CTRL_MASK (0x7f)
  1253. /* Memory Test (0xb2) */
  1254. #define RT5670_MT_MASK (0x1 << 15)
  1255. #define RT5670_MT_SFT 15
  1256. #define RT5670_MT_DIS (0x0 << 15)
  1257. #define RT5670_MT_EN (0x1 << 15)
  1258. /* DRC/AGC Control 1 (0xb4) */
  1259. #define RT5670_DRC_AGC_P_MASK (0x1 << 15)
  1260. #define RT5670_DRC_AGC_P_SFT 15
  1261. #define RT5670_DRC_AGC_P_DAC (0x0 << 15)
  1262. #define RT5670_DRC_AGC_P_ADC (0x1 << 15)
  1263. #define RT5670_DRC_AGC_MASK (0x1 << 14)
  1264. #define RT5670_DRC_AGC_SFT 14
  1265. #define RT5670_DRC_AGC_DIS (0x0 << 14)
  1266. #define RT5670_DRC_AGC_EN (0x1 << 14)
  1267. #define RT5670_DRC_AGC_UPD (0x1 << 13)
  1268. #define RT5670_DRC_AGC_UPD_BIT 13
  1269. #define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
  1270. #define RT5670_DRC_AGC_AR_SFT 8
  1271. #define RT5670_DRC_AGC_R_MASK (0x7 << 5)
  1272. #define RT5670_DRC_AGC_R_SFT 5
  1273. #define RT5670_DRC_AGC_R_48K (0x1 << 5)
  1274. #define RT5670_DRC_AGC_R_96K (0x2 << 5)
  1275. #define RT5670_DRC_AGC_R_192K (0x3 << 5)
  1276. #define RT5670_DRC_AGC_R_441K (0x5 << 5)
  1277. #define RT5670_DRC_AGC_R_882K (0x6 << 5)
  1278. #define RT5670_DRC_AGC_R_1764K (0x7 << 5)
  1279. #define RT5670_DRC_AGC_RC_MASK (0x1f)
  1280. #define RT5670_DRC_AGC_RC_SFT 0
  1281. /* DRC/AGC Control 2 (0xb5) */
  1282. #define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
  1283. #define RT5670_DRC_AGC_POB_SFT 8
  1284. #define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
  1285. #define RT5670_DRC_AGC_CP_SFT 7
  1286. #define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
  1287. #define RT5670_DRC_AGC_CP_EN (0x1 << 7)
  1288. #define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
  1289. #define RT5670_DRC_AGC_CPR_SFT 5
  1290. #define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
  1291. #define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
  1292. #define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
  1293. #define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
  1294. #define RT5670_DRC_AGC_PRB_MASK (0x1f)
  1295. #define RT5670_DRC_AGC_PRB_SFT 0
  1296. /* DRC/AGC Control 3 (0xb6) */
  1297. #define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
  1298. #define RT5670_DRC_AGC_NGB_SFT 12
  1299. #define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
  1300. #define RT5670_DRC_AGC_TAR_SFT 7
  1301. #define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
  1302. #define RT5670_DRC_AGC_NG_SFT 6
  1303. #define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
  1304. #define RT5670_DRC_AGC_NG_EN (0x1 << 6)
  1305. #define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
  1306. #define RT5670_DRC_AGC_NGH_SFT 5
  1307. #define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
  1308. #define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
  1309. #define RT5670_DRC_AGC_NGT_MASK (0x1f)
  1310. #define RT5670_DRC_AGC_NGT_SFT 0
  1311. /* Jack Detect Control (0xbb) */
  1312. #define RT5670_JD_MASK (0x7 << 13)
  1313. #define RT5670_JD_SFT 13
  1314. #define RT5670_JD_DIS (0x0 << 13)
  1315. #define RT5670_JD_GPIO1 (0x1 << 13)
  1316. #define RT5670_JD_JD1_IN4P (0x2 << 13)
  1317. #define RT5670_JD_JD2_IN4N (0x3 << 13)
  1318. #define RT5670_JD_GPIO2 (0x4 << 13)
  1319. #define RT5670_JD_GPIO3 (0x5 << 13)
  1320. #define RT5670_JD_GPIO4 (0x6 << 13)
  1321. #define RT5670_JD_HP_MASK (0x1 << 11)
  1322. #define RT5670_JD_HP_SFT 11
  1323. #define RT5670_JD_HP_DIS (0x0 << 11)
  1324. #define RT5670_JD_HP_EN (0x1 << 11)
  1325. #define RT5670_JD_HP_TRG_MASK (0x1 << 10)
  1326. #define RT5670_JD_HP_TRG_SFT 10
  1327. #define RT5670_JD_HP_TRG_LO (0x0 << 10)
  1328. #define RT5670_JD_HP_TRG_HI (0x1 << 10)
  1329. #define RT5670_JD_SPL_MASK (0x1 << 9)
  1330. #define RT5670_JD_SPL_SFT 9
  1331. #define RT5670_JD_SPL_DIS (0x0 << 9)
  1332. #define RT5670_JD_SPL_EN (0x1 << 9)
  1333. #define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
  1334. #define RT5670_JD_SPL_TRG_SFT 8
  1335. #define RT5670_JD_SPL_TRG_LO (0x0 << 8)
  1336. #define RT5670_JD_SPL_TRG_HI (0x1 << 8)
  1337. #define RT5670_JD_SPR_MASK (0x1 << 7)
  1338. #define RT5670_JD_SPR_SFT 7
  1339. #define RT5670_JD_SPR_DIS (0x0 << 7)
  1340. #define RT5670_JD_SPR_EN (0x1 << 7)
  1341. #define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
  1342. #define RT5670_JD_SPR_TRG_SFT 6
  1343. #define RT5670_JD_SPR_TRG_LO (0x0 << 6)
  1344. #define RT5670_JD_SPR_TRG_HI (0x1 << 6)
  1345. #define RT5670_JD_MO_MASK (0x1 << 5)
  1346. #define RT5670_JD_MO_SFT 5
  1347. #define RT5670_JD_MO_DIS (0x0 << 5)
  1348. #define RT5670_JD_MO_EN (0x1 << 5)
  1349. #define RT5670_JD_MO_TRG_MASK (0x1 << 4)
  1350. #define RT5670_JD_MO_TRG_SFT 4
  1351. #define RT5670_JD_MO_TRG_LO (0x0 << 4)
  1352. #define RT5670_JD_MO_TRG_HI (0x1 << 4)
  1353. #define RT5670_JD_LO_MASK (0x1 << 3)
  1354. #define RT5670_JD_LO_SFT 3
  1355. #define RT5670_JD_LO_DIS (0x0 << 3)
  1356. #define RT5670_JD_LO_EN (0x1 << 3)
  1357. #define RT5670_JD_LO_TRG_MASK (0x1 << 2)
  1358. #define RT5670_JD_LO_TRG_SFT 2
  1359. #define RT5670_JD_LO_TRG_LO (0x0 << 2)
  1360. #define RT5670_JD_LO_TRG_HI (0x1 << 2)
  1361. #define RT5670_JD1_IN4P_MASK (0x1 << 1)
  1362. #define RT5670_JD1_IN4P_SFT 1
  1363. #define RT5670_JD1_IN4P_DIS (0x0 << 1)
  1364. #define RT5670_JD1_IN4P_EN (0x1 << 1)
  1365. #define RT5670_JD2_IN4N_MASK (0x1)
  1366. #define RT5670_JD2_IN4N_SFT 0
  1367. #define RT5670_JD2_IN4N_DIS (0x0)
  1368. #define RT5670_JD2_IN4N_EN (0x1)
  1369. /* IRQ Control 1 (0xbd) */
  1370. #define RT5670_IRQ_JD_MASK (0x1 << 15)
  1371. #define RT5670_IRQ_JD_SFT 15
  1372. #define RT5670_IRQ_JD_BP (0x0 << 15)
  1373. #define RT5670_IRQ_JD_NOR (0x1 << 15)
  1374. #define RT5670_IRQ_OT_MASK (0x1 << 14)
  1375. #define RT5670_IRQ_OT_SFT 14
  1376. #define RT5670_IRQ_OT_BP (0x0 << 14)
  1377. #define RT5670_IRQ_OT_NOR (0x1 << 14)
  1378. #define RT5670_JD_STKY_MASK (0x1 << 13)
  1379. #define RT5670_JD_STKY_SFT 13
  1380. #define RT5670_JD_STKY_DIS (0x0 << 13)
  1381. #define RT5670_JD_STKY_EN (0x1 << 13)
  1382. #define RT5670_OT_STKY_MASK (0x1 << 12)
  1383. #define RT5670_OT_STKY_SFT 12
  1384. #define RT5670_OT_STKY_DIS (0x0 << 12)
  1385. #define RT5670_OT_STKY_EN (0x1 << 12)
  1386. #define RT5670_JD_P_MASK (0x1 << 11)
  1387. #define RT5670_JD_P_SFT 11
  1388. #define RT5670_JD_P_NOR (0x0 << 11)
  1389. #define RT5670_JD_P_INV (0x1 << 11)
  1390. #define RT5670_OT_P_MASK (0x1 << 10)
  1391. #define RT5670_OT_P_SFT 10
  1392. #define RT5670_OT_P_NOR (0x0 << 10)
  1393. #define RT5670_OT_P_INV (0x1 << 10)
  1394. #define RT5670_JD1_1_EN_MASK (0x1 << 9)
  1395. #define RT5670_JD1_1_EN_SFT 9
  1396. #define RT5670_JD1_1_DIS (0x0 << 9)
  1397. #define RT5670_JD1_1_EN (0x1 << 9)
  1398. /* IRQ Control 2 (0xbe) */
  1399. #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
  1400. #define RT5670_IRQ_MB1_OC_SFT 15
  1401. #define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
  1402. #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
  1403. #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
  1404. #define RT5670_IRQ_MB2_OC_SFT 14
  1405. #define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
  1406. #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
  1407. #define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
  1408. #define RT5670_MB1_OC_STKY_SFT 11
  1409. #define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
  1410. #define RT5670_MB1_OC_STKY_EN (0x1 << 11)
  1411. #define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
  1412. #define RT5670_MB2_OC_STKY_SFT 10
  1413. #define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
  1414. #define RT5670_MB2_OC_STKY_EN (0x1 << 10)
  1415. #define RT5670_MB1_OC_P_MASK (0x1 << 7)
  1416. #define RT5670_MB1_OC_P_SFT 7
  1417. #define RT5670_MB1_OC_P_NOR (0x0 << 7)
  1418. #define RT5670_MB1_OC_P_INV (0x1 << 7)
  1419. #define RT5670_MB2_OC_P_MASK (0x1 << 6)
  1420. #define RT5670_MB2_OC_P_SFT 6
  1421. #define RT5670_MB2_OC_P_NOR (0x0 << 6)
  1422. #define RT5670_MB2_OC_P_INV (0x1 << 6)
  1423. #define RT5670_MB1_OC_CLR (0x1 << 3)
  1424. #define RT5670_MB1_OC_CLR_SFT 3
  1425. #define RT5670_MB2_OC_CLR (0x1 << 2)
  1426. #define RT5670_MB2_OC_CLR_SFT 2
  1427. /* GPIO Control 1 (0xc0) */
  1428. #define RT5670_GP1_PIN_MASK (0x1 << 15)
  1429. #define RT5670_GP1_PIN_SFT 15
  1430. #define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
  1431. #define RT5670_GP1_PIN_IRQ (0x1 << 15)
  1432. #define RT5670_GP2_PIN_MASK (0x1 << 14)
  1433. #define RT5670_GP2_PIN_SFT 14
  1434. #define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
  1435. #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
  1436. #define RT5670_GP3_PIN_MASK (0x3 << 12)
  1437. #define RT5670_GP3_PIN_SFT 12
  1438. #define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
  1439. #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
  1440. #define RT5670_GP3_PIN_IRQ (0x2 << 12)
  1441. #define RT5670_GP4_PIN_MASK (0x1 << 11)
  1442. #define RT5670_GP4_PIN_SFT 11
  1443. #define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
  1444. #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
  1445. #define RT5670_DP_SIG_MASK (0x1 << 10)
  1446. #define RT5670_DP_SIG_SFT 10
  1447. #define RT5670_DP_SIG_TEST (0x0 << 10)
  1448. #define RT5670_DP_SIG_AP (0x1 << 10)
  1449. #define RT5670_GPIO_M_MASK (0x1 << 9)
  1450. #define RT5670_GPIO_M_SFT 9
  1451. #define RT5670_GPIO_M_FLT (0x0 << 9)
  1452. #define RT5670_GPIO_M_PH (0x1 << 9)
  1453. #define RT5670_I2S2_PIN_MASK (0x1 << 8)
  1454. #define RT5670_I2S2_PIN_SFT 8
  1455. #define RT5670_I2S2_PIN_I2S (0x0 << 8)
  1456. #define RT5670_I2S2_PIN_GPIO (0x1 << 8)
  1457. #define RT5670_GP5_PIN_MASK (0x1 << 7)
  1458. #define RT5670_GP5_PIN_SFT 7
  1459. #define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
  1460. #define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
  1461. #define RT5670_GP6_PIN_MASK (0x1 << 6)
  1462. #define RT5670_GP6_PIN_SFT 6
  1463. #define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
  1464. #define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
  1465. #define RT5670_GP7_PIN_MASK (0x3 << 4)
  1466. #define RT5670_GP7_PIN_SFT 4
  1467. #define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
  1468. #define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
  1469. #define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
  1470. #define RT5670_GP8_PIN_MASK (0x1 << 3)
  1471. #define RT5670_GP8_PIN_SFT 3
  1472. #define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
  1473. #define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
  1474. #define RT5670_GP9_PIN_MASK (0x1 << 2)
  1475. #define RT5670_GP9_PIN_SFT 2
  1476. #define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
  1477. #define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
  1478. #define RT5670_GP10_PIN_MASK (0x3)
  1479. #define RT5670_GP10_PIN_SFT 0
  1480. #define RT5670_GP10_PIN_GPIO9 (0x0)
  1481. #define RT5670_GP10_PIN_DMIC3_SDA (0x1)
  1482. #define RT5670_GP10_PIN_PDM_ADT2 (0x2)
  1483. /* GPIO Control 2 (0xc1) */
  1484. #define RT5670_GP4_PF_MASK (0x1 << 11)
  1485. #define RT5670_GP4_PF_SFT 11
  1486. #define RT5670_GP4_PF_IN (0x0 << 11)
  1487. #define RT5670_GP4_PF_OUT (0x1 << 11)
  1488. #define RT5670_GP4_OUT_MASK (0x1 << 10)
  1489. #define RT5670_GP4_OUT_SFT 10
  1490. #define RT5670_GP4_OUT_LO (0x0 << 10)
  1491. #define RT5670_GP4_OUT_HI (0x1 << 10)
  1492. #define RT5670_GP4_P_MASK (0x1 << 9)
  1493. #define RT5670_GP4_P_SFT 9
  1494. #define RT5670_GP4_P_NOR (0x0 << 9)
  1495. #define RT5670_GP4_P_INV (0x1 << 9)
  1496. #define RT5670_GP3_PF_MASK (0x1 << 8)
  1497. #define RT5670_GP3_PF_SFT 8
  1498. #define RT5670_GP3_PF_IN (0x0 << 8)
  1499. #define RT5670_GP3_PF_OUT (0x1 << 8)
  1500. #define RT5670_GP3_OUT_MASK (0x1 << 7)
  1501. #define RT5670_GP3_OUT_SFT 7
  1502. #define RT5670_GP3_OUT_LO (0x0 << 7)
  1503. #define RT5670_GP3_OUT_HI (0x1 << 7)
  1504. #define RT5670_GP3_P_MASK (0x1 << 6)
  1505. #define RT5670_GP3_P_SFT 6
  1506. #define RT5670_GP3_P_NOR (0x0 << 6)
  1507. #define RT5670_GP3_P_INV (0x1 << 6)
  1508. #define RT5670_GP2_PF_MASK (0x1 << 5)
  1509. #define RT5670_GP2_PF_SFT 5
  1510. #define RT5670_GP2_PF_IN (0x0 << 5)
  1511. #define RT5670_GP2_PF_OUT (0x1 << 5)
  1512. #define RT5670_GP2_OUT_MASK (0x1 << 4)
  1513. #define RT5670_GP2_OUT_SFT 4
  1514. #define RT5670_GP2_OUT_LO (0x0 << 4)
  1515. #define RT5670_GP2_OUT_HI (0x1 << 4)
  1516. #define RT5670_GP2_P_MASK (0x1 << 3)
  1517. #define RT5670_GP2_P_SFT 3
  1518. #define RT5670_GP2_P_NOR (0x0 << 3)
  1519. #define RT5670_GP2_P_INV (0x1 << 3)
  1520. #define RT5670_GP1_PF_MASK (0x1 << 2)
  1521. #define RT5670_GP1_PF_SFT 2
  1522. #define RT5670_GP1_PF_IN (0x0 << 2)
  1523. #define RT5670_GP1_PF_OUT (0x1 << 2)
  1524. #define RT5670_GP1_OUT_MASK (0x1 << 1)
  1525. #define RT5670_GP1_OUT_SFT 1
  1526. #define RT5670_GP1_OUT_LO (0x0 << 1)
  1527. #define RT5670_GP1_OUT_HI (0x1 << 1)
  1528. #define RT5670_GP1_P_MASK (0x1)
  1529. #define RT5670_GP1_P_SFT 0
  1530. #define RT5670_GP1_P_NOR (0x0)
  1531. #define RT5670_GP1_P_INV (0x1)
  1532. /* Scramble Function (0xcd) */
  1533. #define RT5670_SCB_KEY_MASK (0xff)
  1534. #define RT5670_SCB_KEY_SFT 0
  1535. /* Scramble Control (0xce) */
  1536. #define RT5670_SCB_SWAP_MASK (0x1 << 15)
  1537. #define RT5670_SCB_SWAP_SFT 15
  1538. #define RT5670_SCB_SWAP_DIS (0x0 << 15)
  1539. #define RT5670_SCB_SWAP_EN (0x1 << 15)
  1540. #define RT5670_SCB_MASK (0x1 << 14)
  1541. #define RT5670_SCB_SFT 14
  1542. #define RT5670_SCB_DIS (0x0 << 14)
  1543. #define RT5670_SCB_EN (0x1 << 14)
  1544. /* Baseback Control (0xcf) */
  1545. #define RT5670_BB_MASK (0x1 << 15)
  1546. #define RT5670_BB_SFT 15
  1547. #define RT5670_BB_DIS (0x0 << 15)
  1548. #define RT5670_BB_EN (0x1 << 15)
  1549. #define RT5670_BB_CT_MASK (0x7 << 12)
  1550. #define RT5670_BB_CT_SFT 12
  1551. #define RT5670_BB_CT_A (0x0 << 12)
  1552. #define RT5670_BB_CT_B (0x1 << 12)
  1553. #define RT5670_BB_CT_C (0x2 << 12)
  1554. #define RT5670_BB_CT_D (0x3 << 12)
  1555. #define RT5670_M_BB_L_MASK (0x1 << 9)
  1556. #define RT5670_M_BB_L_SFT 9
  1557. #define RT5670_M_BB_R_MASK (0x1 << 8)
  1558. #define RT5670_M_BB_R_SFT 8
  1559. #define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
  1560. #define RT5670_M_BB_HPF_L_SFT 7
  1561. #define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
  1562. #define RT5670_M_BB_HPF_R_SFT 6
  1563. #define RT5670_G_BB_BST_MASK (0x3f)
  1564. #define RT5670_G_BB_BST_SFT 0
  1565. /* MP3 Plus Control 1 (0xd0) */
  1566. #define RT5670_M_MP3_L_MASK (0x1 << 15)
  1567. #define RT5670_M_MP3_L_SFT 15
  1568. #define RT5670_M_MP3_R_MASK (0x1 << 14)
  1569. #define RT5670_M_MP3_R_SFT 14
  1570. #define RT5670_M_MP3_MASK (0x1 << 13)
  1571. #define RT5670_M_MP3_SFT 13
  1572. #define RT5670_M_MP3_DIS (0x0 << 13)
  1573. #define RT5670_M_MP3_EN (0x1 << 13)
  1574. #define RT5670_EG_MP3_MASK (0x1f << 8)
  1575. #define RT5670_EG_MP3_SFT 8
  1576. #define RT5670_MP3_HLP_MASK (0x1 << 7)
  1577. #define RT5670_MP3_HLP_SFT 7
  1578. #define RT5670_MP3_HLP_DIS (0x0 << 7)
  1579. #define RT5670_MP3_HLP_EN (0x1 << 7)
  1580. #define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
  1581. #define RT5670_M_MP3_ORG_L_SFT 6
  1582. #define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
  1583. #define RT5670_M_MP3_ORG_R_SFT 5
  1584. /* MP3 Plus Control 2 (0xd1) */
  1585. #define RT5670_MP3_WT_MASK (0x1 << 13)
  1586. #define RT5670_MP3_WT_SFT 13
  1587. #define RT5670_MP3_WT_1_4 (0x0 << 13)
  1588. #define RT5670_MP3_WT_1_2 (0x1 << 13)
  1589. #define RT5670_OG_MP3_MASK (0x1f << 8)
  1590. #define RT5670_OG_MP3_SFT 8
  1591. #define RT5670_HG_MP3_MASK (0x3f)
  1592. #define RT5670_HG_MP3_SFT 0
  1593. /* 3D HP Control 1 (0xd2) */
  1594. #define RT5670_3D_CF_MASK (0x1 << 15)
  1595. #define RT5670_3D_CF_SFT 15
  1596. #define RT5670_3D_CF_DIS (0x0 << 15)
  1597. #define RT5670_3D_CF_EN (0x1 << 15)
  1598. #define RT5670_3D_HP_MASK (0x1 << 14)
  1599. #define RT5670_3D_HP_SFT 14
  1600. #define RT5670_3D_HP_DIS (0x0 << 14)
  1601. #define RT5670_3D_HP_EN (0x1 << 14)
  1602. #define RT5670_3D_BT_MASK (0x1 << 13)
  1603. #define RT5670_3D_BT_SFT 13
  1604. #define RT5670_3D_BT_DIS (0x0 << 13)
  1605. #define RT5670_3D_BT_EN (0x1 << 13)
  1606. #define RT5670_3D_1F_MIX_MASK (0x3 << 11)
  1607. #define RT5670_3D_1F_MIX_SFT 11
  1608. #define RT5670_3D_HP_M_MASK (0x1 << 10)
  1609. #define RT5670_3D_HP_M_SFT 10
  1610. #define RT5670_3D_HP_M_SUR (0x0 << 10)
  1611. #define RT5670_3D_HP_M_FRO (0x1 << 10)
  1612. #define RT5670_M_3D_HRTF_MASK (0x1 << 9)
  1613. #define RT5670_M_3D_HRTF_SFT 9
  1614. #define RT5670_M_3D_D2H_MASK (0x1 << 8)
  1615. #define RT5670_M_3D_D2H_SFT 8
  1616. #define RT5670_M_3D_D2R_MASK (0x1 << 7)
  1617. #define RT5670_M_3D_D2R_SFT 7
  1618. #define RT5670_M_3D_REVB_MASK (0x1 << 6)
  1619. #define RT5670_M_3D_REVB_SFT 6
  1620. /* Adjustable high pass filter control 1 (0xd3) */
  1621. #define RT5670_2ND_HPF_MASK (0x1 << 15)
  1622. #define RT5670_2ND_HPF_SFT 15
  1623. #define RT5670_2ND_HPF_DIS (0x0 << 15)
  1624. #define RT5670_2ND_HPF_EN (0x1 << 15)
  1625. #define RT5670_HPF_CF_L_MASK (0x7 << 12)
  1626. #define RT5670_HPF_CF_L_SFT 12
  1627. #define RT5670_1ST_HPF_MASK (0x1 << 11)
  1628. #define RT5670_1ST_HPF_SFT 11
  1629. #define RT5670_1ST_HPF_DIS (0x0 << 11)
  1630. #define RT5670_1ST_HPF_EN (0x1 << 11)
  1631. #define RT5670_HPF_CF_R_MASK (0x7 << 8)
  1632. #define RT5670_HPF_CF_R_SFT 8
  1633. #define RT5670_ZD_T_MASK (0x3 << 6)
  1634. #define RT5670_ZD_T_SFT 6
  1635. #define RT5670_ZD_F_MASK (0x3 << 4)
  1636. #define RT5670_ZD_F_SFT 4
  1637. #define RT5670_ZD_F_IM (0x0 << 4)
  1638. #define RT5670_ZD_F_ZC_IM (0x1 << 4)
  1639. #define RT5670_ZD_F_ZC_IOD (0x2 << 4)
  1640. #define RT5670_ZD_F_UN (0x3 << 4)
  1641. /* HP calibration control and Amp detection (0xd6) */
  1642. #define RT5670_SI_DAC_MASK (0x1 << 11)
  1643. #define RT5670_SI_DAC_SFT 11
  1644. #define RT5670_SI_DAC_AUTO (0x0 << 11)
  1645. #define RT5670_SI_DAC_TEST (0x1 << 11)
  1646. #define RT5670_DC_CAL_M_MASK (0x1 << 10)
  1647. #define RT5670_DC_CAL_M_SFT 10
  1648. #define RT5670_DC_CAL_M_CAL (0x0 << 10)
  1649. #define RT5670_DC_CAL_M_NOR (0x1 << 10)
  1650. #define RT5670_DC_CAL_MASK (0x1 << 9)
  1651. #define RT5670_DC_CAL_SFT 9
  1652. #define RT5670_DC_CAL_DIS (0x0 << 9)
  1653. #define RT5670_DC_CAL_EN (0x1 << 9)
  1654. #define RT5670_HPD_RCV_MASK (0x7 << 6)
  1655. #define RT5670_HPD_RCV_SFT 6
  1656. #define RT5670_HPD_PS_MASK (0x1 << 5)
  1657. #define RT5670_HPD_PS_SFT 5
  1658. #define RT5670_HPD_PS_DIS (0x0 << 5)
  1659. #define RT5670_HPD_PS_EN (0x1 << 5)
  1660. #define RT5670_CAL_M_MASK (0x1 << 4)
  1661. #define RT5670_CAL_M_SFT 4
  1662. #define RT5670_CAL_M_DEP (0x0 << 4)
  1663. #define RT5670_CAL_M_CAL (0x1 << 4)
  1664. #define RT5670_CAL_MASK (0x1 << 3)
  1665. #define RT5670_CAL_SFT 3
  1666. #define RT5670_CAL_DIS (0x0 << 3)
  1667. #define RT5670_CAL_EN (0x1 << 3)
  1668. #define RT5670_CAL_TEST_MASK (0x1 << 2)
  1669. #define RT5670_CAL_TEST_SFT 2
  1670. #define RT5670_CAL_TEST_DIS (0x0 << 2)
  1671. #define RT5670_CAL_TEST_EN (0x1 << 2)
  1672. #define RT5670_CAL_P_MASK (0x3)
  1673. #define RT5670_CAL_P_SFT 0
  1674. #define RT5670_CAL_P_NONE (0x0)
  1675. #define RT5670_CAL_P_CAL (0x1)
  1676. #define RT5670_CAL_P_DAC_CAL (0x2)
  1677. /* Soft volume and zero cross control 1 (0xd9) */
  1678. #define RT5670_SV_MASK (0x1 << 15)
  1679. #define RT5670_SV_SFT 15
  1680. #define RT5670_SV_DIS (0x0 << 15)
  1681. #define RT5670_SV_EN (0x1 << 15)
  1682. #define RT5670_SPO_SV_MASK (0x1 << 14)
  1683. #define RT5670_SPO_SV_SFT 14
  1684. #define RT5670_SPO_SV_DIS (0x0 << 14)
  1685. #define RT5670_SPO_SV_EN (0x1 << 14)
  1686. #define RT5670_OUT_SV_MASK (0x1 << 13)
  1687. #define RT5670_OUT_SV_SFT 13
  1688. #define RT5670_OUT_SV_DIS (0x0 << 13)
  1689. #define RT5670_OUT_SV_EN (0x1 << 13)
  1690. #define RT5670_HP_SV_MASK (0x1 << 12)
  1691. #define RT5670_HP_SV_SFT 12
  1692. #define RT5670_HP_SV_DIS (0x0 << 12)
  1693. #define RT5670_HP_SV_EN (0x1 << 12)
  1694. #define RT5670_ZCD_DIG_MASK (0x1 << 11)
  1695. #define RT5670_ZCD_DIG_SFT 11
  1696. #define RT5670_ZCD_DIG_DIS (0x0 << 11)
  1697. #define RT5670_ZCD_DIG_EN (0x1 << 11)
  1698. #define RT5670_ZCD_MASK (0x1 << 10)
  1699. #define RT5670_ZCD_SFT 10
  1700. #define RT5670_ZCD_PD (0x0 << 10)
  1701. #define RT5670_ZCD_PU (0x1 << 10)
  1702. #define RT5670_M_ZCD_MASK (0x3f << 4)
  1703. #define RT5670_M_ZCD_SFT 4
  1704. #define RT5670_M_ZCD_RM_L (0x1 << 9)
  1705. #define RT5670_M_ZCD_RM_R (0x1 << 8)
  1706. #define RT5670_M_ZCD_SM_L (0x1 << 7)
  1707. #define RT5670_M_ZCD_SM_R (0x1 << 6)
  1708. #define RT5670_M_ZCD_OM_L (0x1 << 5)
  1709. #define RT5670_M_ZCD_OM_R (0x1 << 4)
  1710. #define RT5670_SV_DLY_MASK (0xf)
  1711. #define RT5670_SV_DLY_SFT 0
  1712. /* Soft volume and zero cross control 2 (0xda) */
  1713. #define RT5670_ZCD_HP_MASK (0x1 << 15)
  1714. #define RT5670_ZCD_HP_SFT 15
  1715. #define RT5670_ZCD_HP_DIS (0x0 << 15)
  1716. #define RT5670_ZCD_HP_EN (0x1 << 15)
  1717. /* General Control 3 (0xfc) */
  1718. #define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
  1719. #define RT5670_TDM_DATA_MODE_NOR (0x0 << 11)
  1720. #define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
  1721. /* Codec Private Register definition */
  1722. /* 3D Speaker Control (0x63) */
  1723. #define RT5670_3D_SPK_MASK (0x1 << 15)
  1724. #define RT5670_3D_SPK_SFT 15
  1725. #define RT5670_3D_SPK_DIS (0x0 << 15)
  1726. #define RT5670_3D_SPK_EN (0x1 << 15)
  1727. #define RT5670_3D_SPK_M_MASK (0x3 << 13)
  1728. #define RT5670_3D_SPK_M_SFT 13
  1729. #define RT5670_3D_SPK_CG_MASK (0x1f << 8)
  1730. #define RT5670_3D_SPK_CG_SFT 8
  1731. #define RT5670_3D_SPK_SG_MASK (0x1f)
  1732. #define RT5670_3D_SPK_SG_SFT 0
  1733. /* Wind Noise Detection Control 1 (0x6c) */
  1734. #define RT5670_WND_MASK (0x1 << 15)
  1735. #define RT5670_WND_SFT 15
  1736. #define RT5670_WND_DIS (0x0 << 15)
  1737. #define RT5670_WND_EN (0x1 << 15)
  1738. /* Wind Noise Detection Control 2 (0x6d) */
  1739. #define RT5670_WND_FC_NW_MASK (0x3f << 10)
  1740. #define RT5670_WND_FC_NW_SFT 10
  1741. #define RT5670_WND_FC_WK_MASK (0x3f << 4)
  1742. #define RT5670_WND_FC_WK_SFT 4
  1743. /* Wind Noise Detection Control 3 (0x6e) */
  1744. #define RT5670_HPF_FC_MASK (0x3f << 6)
  1745. #define RT5670_HPF_FC_SFT 6
  1746. #define RT5670_WND_FC_ST_MASK (0x3f)
  1747. #define RT5670_WND_FC_ST_SFT 0
  1748. /* Wind Noise Detection Control 4 (0x6f) */
  1749. #define RT5670_WND_TH_LO_MASK (0x3ff)
  1750. #define RT5670_WND_TH_LO_SFT 0
  1751. /* Wind Noise Detection Control 5 (0x70) */
  1752. #define RT5670_WND_TH_HI_MASK (0x3ff)
  1753. #define RT5670_WND_TH_HI_SFT 0
  1754. /* Wind Noise Detection Control 8 (0x73) */
  1755. #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
  1756. #define RT5670_WND_WIND_SFT 13
  1757. #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
  1758. #define RT5670_WND_STRONG_SFT 12
  1759. enum {
  1760. RT5670_NO_WIND,
  1761. RT5670_BREEZE,
  1762. RT5670_STORM,
  1763. };
  1764. /* Dipole Speaker Interface (0x75) */
  1765. #define RT5670_DP_ATT_MASK (0x3 << 14)
  1766. #define RT5670_DP_ATT_SFT 14
  1767. #define RT5670_DP_SPK_MASK (0x1 << 10)
  1768. #define RT5670_DP_SPK_SFT 10
  1769. #define RT5670_DP_SPK_DIS (0x0 << 10)
  1770. #define RT5670_DP_SPK_EN (0x1 << 10)
  1771. /* EQ Pre Volume Control (0xb3) */
  1772. #define RT5670_EQ_PRE_VOL_MASK (0xffff)
  1773. #define RT5670_EQ_PRE_VOL_SFT 0
  1774. /* EQ Post Volume Control (0xb4) */
  1775. #define RT5670_EQ_PST_VOL_MASK (0xffff)
  1776. #define RT5670_EQ_PST_VOL_SFT 0
  1777. /* Jack Detect Control 3 (0xf8) */
  1778. #define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
  1779. #define RT5670_JD_CBJ_EN (0x1 << 7)
  1780. #define RT5670_JD_CBJ_POL (0x1 << 6)
  1781. #define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
  1782. #define RT5670_JD_TRI_CBJ_SEL_SFT (3)
  1783. #define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
  1784. #define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
  1785. #define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
  1786. #define RT5670_JD_CBJ_JD2 (0x3 << 3)
  1787. #define RT5670_JD_CBJ_JD3 (0x4 << 3)
  1788. #define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
  1789. #define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
  1790. #define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
  1791. #define RT5670_JD_TRI_HPO_SEL_SFT (0)
  1792. #define RT5670_JD_HPO_GPIO_JD1 (0x0)
  1793. #define RT5670_JD_HPO_JD1_1 (0x1)
  1794. #define RT5670_JD_HPO_JD1_2 (0x2)
  1795. #define RT5670_JD_HPO_JD2 (0x3)
  1796. #define RT5670_JD_HPO_JD3 (0x4)
  1797. #define RT5670_JD_HPO_GPIO_JD2 (0x5)
  1798. #define RT5670_JD_HPO_MX0B_12 (0x6)
  1799. /* Digital Misc Control (0xfa) */
  1800. #define RT5670_RST_DSP (0x1 << 13)
  1801. #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
  1802. #define RT5670_IF1_ADC1_IN1_SFT 12
  1803. #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
  1804. #define RT5670_IF1_ADC1_IN2_SFT 11
  1805. #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
  1806. #define RT5670_IF1_ADC2_IN1_SFT 10
  1807. #define RT5670_MCLK_DET (0x1 << 3)
  1808. /* General Control2 (0xfb) */
  1809. #define RT5670_RXDC_SRC_MASK (0x1 << 7)
  1810. #define RT5670_RXDC_SRC_STO (0x0 << 7)
  1811. #define RT5670_RXDC_SRC_MONO (0x1 << 7)
  1812. #define RT5670_RXDC_SRC_SFT (7)
  1813. #define RT5670_RXDP2_SEL_MASK (0x1 << 3)
  1814. #define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
  1815. #define RT5670_RXDP2_SEL_ADC (0x1 << 3)
  1816. #define RT5670_RXDP2_SEL_SFT (3)
  1817. /* System Clock Source */
  1818. enum {
  1819. RT5670_SCLK_S_MCLK,
  1820. RT5670_SCLK_S_PLL1,
  1821. RT5670_SCLK_S_RCCLK,
  1822. };
  1823. /* PLL1 Source */
  1824. enum {
  1825. RT5670_PLL1_S_MCLK,
  1826. RT5670_PLL1_S_BCLK1,
  1827. RT5670_PLL1_S_BCLK2,
  1828. RT5670_PLL1_S_BCLK3,
  1829. RT5670_PLL1_S_BCLK4,
  1830. };
  1831. enum {
  1832. RT5670_AIF1,
  1833. RT5670_AIF2,
  1834. RT5670_AIF3,
  1835. RT5670_AIF4,
  1836. RT5670_AIFS,
  1837. };
  1838. enum {
  1839. RT5670_DMIC1_DISABLED,
  1840. RT5670_DMIC_DATA_GPIO6,
  1841. RT5670_DMIC_DATA_IN2P,
  1842. RT5670_DMIC_DATA_GPIO7,
  1843. };
  1844. enum {
  1845. RT5670_DMIC2_DISABLED,
  1846. RT5670_DMIC_DATA_GPIO8,
  1847. RT5670_DMIC_DATA_IN3N,
  1848. };
  1849. enum {
  1850. RT5670_DMIC3_DISABLED,
  1851. RT5670_DMIC_DATA_GPIO9,
  1852. RT5670_DMIC_DATA_GPIO10,
  1853. RT5670_DMIC_DATA_GPIO5,
  1854. };
  1855. /* filter mask */
  1856. enum {
  1857. RT5670_DA_STEREO_FILTER = 0x1,
  1858. RT5670_DA_MONO_L_FILTER = (0x1 << 1),
  1859. RT5670_DA_MONO_R_FILTER = (0x1 << 2),
  1860. RT5670_AD_STEREO_FILTER = (0x1 << 3),
  1861. RT5670_AD_MONO_L_FILTER = (0x1 << 4),
  1862. RT5670_AD_MONO_R_FILTER = (0x1 << 5),
  1863. RT5670_UP_RATE_FILTER = (0x1 << 6),
  1864. RT5670_DOWN_RATE_FILTER = (0x1 << 7),
  1865. };
  1866. int rt5670_sel_asrc_clk_src(struct snd_soc_component *component,
  1867. unsigned int filter_mask, unsigned int clk_src);
  1868. struct rt5670_priv {
  1869. struct snd_soc_component *component;
  1870. struct regmap *regmap;
  1871. struct snd_soc_jack *jack;
  1872. struct snd_soc_jack_gpio hp_gpio;
  1873. int jd_mode;
  1874. bool in2_diff;
  1875. bool gpio1_is_irq;
  1876. bool gpio1_is_ext_spk_en;
  1877. bool dmic_en;
  1878. unsigned int dmic1_data_pin;
  1879. /* 0 = GPIO6; 1 = IN2P; 3 = GPIO7*/
  1880. unsigned int dmic2_data_pin;
  1881. /* 0 = GPIO8; 1 = IN3N; */
  1882. unsigned int dmic3_data_pin;
  1883. /* 0 = GPIO9; 1 = GPIO10; 2 = GPIO5*/
  1884. int sysclk;
  1885. int sysclk_src;
  1886. int lrck[RT5670_AIFS];
  1887. int bclk[RT5670_AIFS];
  1888. int master[RT5670_AIFS];
  1889. int pll_src;
  1890. int pll_in;
  1891. int pll_out;
  1892. int dsp_sw; /* expected parameter setting */
  1893. int dsp_rate;
  1894. int jack_type;
  1895. int jack_type_saved;
  1896. };
  1897. void rt5670_jack_suspend(struct snd_soc_component *component);
  1898. void rt5670_jack_resume(struct snd_soc_component *component);
  1899. int rt5670_set_jack_detect(struct snd_soc_component *component,
  1900. struct snd_soc_jack *jack);
  1901. #endif /* __RT5670_H__ */