rt5668.h 46 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5668.h -- RT5668/RT5658 ALSA SoC audio driver
  4. *
  5. * Copyright 2018 Realtek Microelectronics
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #ifndef __RT5668_H__
  9. #define __RT5668_H__
  10. #include <sound/rt5668.h>
  11. #define DEVICE_ID 0x6530
  12. /* Info */
  13. #define RT5668_RESET 0x0000
  14. #define RT5668_VERSION_ID 0x00fd
  15. #define RT5668_VENDOR_ID 0x00fe
  16. #define RT5668_DEVICE_ID 0x00ff
  17. /* I/O - Output */
  18. #define RT5668_HP_CTRL_1 0x0002
  19. #define RT5668_HP_CTRL_2 0x0003
  20. #define RT5668_HPL_GAIN 0x0005
  21. #define RT5668_HPR_GAIN 0x0006
  22. #define RT5668_I2C_CTRL 0x0008
  23. /* I/O - Input */
  24. #define RT5668_CBJ_BST_CTRL 0x000b
  25. #define RT5668_CBJ_CTRL_1 0x0010
  26. #define RT5668_CBJ_CTRL_2 0x0011
  27. #define RT5668_CBJ_CTRL_3 0x0012
  28. #define RT5668_CBJ_CTRL_4 0x0013
  29. #define RT5668_CBJ_CTRL_5 0x0014
  30. #define RT5668_CBJ_CTRL_6 0x0015
  31. #define RT5668_CBJ_CTRL_7 0x0016
  32. /* I/O - ADC/DAC/DMIC */
  33. #define RT5668_DAC1_DIG_VOL 0x0019
  34. #define RT5668_STO1_ADC_DIG_VOL 0x001c
  35. #define RT5668_STO1_ADC_BOOST 0x001f
  36. #define RT5668_HP_IMP_GAIN_1 0x0022
  37. #define RT5668_HP_IMP_GAIN_2 0x0023
  38. /* Mixer - D-D */
  39. #define RT5668_SIDETONE_CTRL 0x0024
  40. #define RT5668_STO1_ADC_MIXER 0x0026
  41. #define RT5668_AD_DA_MIXER 0x0029
  42. #define RT5668_STO1_DAC_MIXER 0x002a
  43. #define RT5668_A_DAC1_MUX 0x002b
  44. #define RT5668_DIG_INF2_DATA 0x0030
  45. /* Mixer - ADC */
  46. #define RT5668_REC_MIXER 0x003c
  47. #define RT5668_CAL_REC 0x0044
  48. #define RT5668_ALC_BACK_GAIN 0x0049
  49. /* Power */
  50. #define RT5668_PWR_DIG_1 0x0061
  51. #define RT5668_PWR_DIG_2 0x0062
  52. #define RT5668_PWR_ANLG_1 0x0063
  53. #define RT5668_PWR_ANLG_2 0x0064
  54. #define RT5668_PWR_ANLG_3 0x0065
  55. #define RT5668_PWR_MIXER 0x0066
  56. #define RT5668_PWR_VOL 0x0067
  57. /* Clock Detect */
  58. #define RT5668_CLK_DET 0x006b
  59. /* Filter Auto Reset */
  60. #define RT5668_RESET_LPF_CTRL 0x006c
  61. #define RT5668_RESET_HPF_CTRL 0x006d
  62. /* DMIC */
  63. #define RT5668_DMIC_CTRL_1 0x006e
  64. /* Format - ADC/DAC */
  65. #define RT5668_I2S1_SDP 0x0070
  66. #define RT5668_I2S2_SDP 0x0071
  67. #define RT5668_ADDA_CLK_1 0x0073
  68. #define RT5668_ADDA_CLK_2 0x0074
  69. #define RT5668_I2S1_F_DIV_CTRL_1 0x0075
  70. #define RT5668_I2S1_F_DIV_CTRL_2 0x0076
  71. /* Format - TDM Control */
  72. #define RT5668_TDM_CTRL 0x0079
  73. #define RT5668_TDM_ADDA_CTRL_1 0x007a
  74. #define RT5668_TDM_ADDA_CTRL_2 0x007b
  75. #define RT5668_DATA_SEL_CTRL_1 0x007c
  76. #define RT5668_TDM_TCON_CTRL 0x007e
  77. /* Function - Analog */
  78. #define RT5668_GLB_CLK 0x0080
  79. #define RT5668_PLL_CTRL_1 0x0081
  80. #define RT5668_PLL_CTRL_2 0x0082
  81. #define RT5668_PLL_TRACK_1 0x0083
  82. #define RT5668_PLL_TRACK_2 0x0084
  83. #define RT5668_PLL_TRACK_3 0x0085
  84. #define RT5668_PLL_TRACK_4 0x0086
  85. #define RT5668_PLL_TRACK_5 0x0087
  86. #define RT5668_PLL_TRACK_6 0x0088
  87. #define RT5668_PLL_TRACK_11 0x008c
  88. #define RT5668_SDW_REF_CLK 0x008d
  89. #define RT5668_DEPOP_1 0x008e
  90. #define RT5668_DEPOP_2 0x008f
  91. #define RT5668_HP_CHARGE_PUMP_1 0x0091
  92. #define RT5668_HP_CHARGE_PUMP_2 0x0092
  93. #define RT5668_MICBIAS_1 0x0093
  94. #define RT5668_MICBIAS_2 0x0094
  95. #define RT5668_PLL_TRACK_12 0x0098
  96. #define RT5668_PLL_TRACK_14 0x009a
  97. #define RT5668_PLL2_CTRL_1 0x009b
  98. #define RT5668_PLL2_CTRL_2 0x009c
  99. #define RT5668_PLL2_CTRL_3 0x009d
  100. #define RT5668_PLL2_CTRL_4 0x009e
  101. #define RT5668_RC_CLK_CTRL 0x009f
  102. #define RT5668_I2S_M_CLK_CTRL_1 0x00a0
  103. #define RT5668_I2S2_F_DIV_CTRL_1 0x00a3
  104. #define RT5668_I2S2_F_DIV_CTRL_2 0x00a4
  105. /* Function - Digital */
  106. #define RT5668_EQ_CTRL_1 0x00ae
  107. #define RT5668_EQ_CTRL_2 0x00af
  108. #define RT5668_IRQ_CTRL_1 0x00b6
  109. #define RT5668_IRQ_CTRL_2 0x00b7
  110. #define RT5668_IRQ_CTRL_3 0x00b8
  111. #define RT5668_IRQ_CTRL_4 0x00b9
  112. #define RT5668_INT_ST_1 0x00be
  113. #define RT5668_GPIO_CTRL_1 0x00c0
  114. #define RT5668_GPIO_CTRL_2 0x00c1
  115. #define RT5668_GPIO_CTRL_3 0x00c2
  116. #define RT5668_HP_AMP_DET_CTRL_1 0x00d0
  117. #define RT5668_HP_AMP_DET_CTRL_2 0x00d1
  118. #define RT5668_MID_HP_AMP_DET 0x00d2
  119. #define RT5668_LOW_HP_AMP_DET 0x00d3
  120. #define RT5668_DELAY_BUF_CTRL 0x00d4
  121. #define RT5668_SV_ZCD_1 0x00d9
  122. #define RT5668_SV_ZCD_2 0x00da
  123. #define RT5668_IL_CMD_1 0x00db
  124. #define RT5668_IL_CMD_2 0x00dc
  125. #define RT5668_IL_CMD_3 0x00dd
  126. #define RT5668_IL_CMD_4 0x00de
  127. #define RT5668_IL_CMD_5 0x00df
  128. #define RT5668_IL_CMD_6 0x00e0
  129. #define RT5668_4BTN_IL_CMD_1 0x00e2
  130. #define RT5668_4BTN_IL_CMD_2 0x00e3
  131. #define RT5668_4BTN_IL_CMD_3 0x00e4
  132. #define RT5668_4BTN_IL_CMD_4 0x00e5
  133. #define RT5668_4BTN_IL_CMD_5 0x00e6
  134. #define RT5668_4BTN_IL_CMD_6 0x00e7
  135. #define RT5668_4BTN_IL_CMD_7 0x00e8
  136. #define RT5668_ADC_STO1_HP_CTRL_1 0x00ea
  137. #define RT5668_ADC_STO1_HP_CTRL_2 0x00eb
  138. #define RT5668_AJD1_CTRL 0x00f0
  139. #define RT5668_JD1_THD 0x00f1
  140. #define RT5668_JD2_THD 0x00f2
  141. #define RT5668_JD_CTRL_1 0x00f6
  142. /* General Control */
  143. #define RT5668_DUMMY_1 0x00fa
  144. #define RT5668_DUMMY_2 0x00fb
  145. #define RT5668_DUMMY_3 0x00fc
  146. #define RT5668_DAC_ADC_DIG_VOL1 0x0100
  147. #define RT5668_BIAS_CUR_CTRL_2 0x010b
  148. #define RT5668_BIAS_CUR_CTRL_3 0x010c
  149. #define RT5668_BIAS_CUR_CTRL_4 0x010d
  150. #define RT5668_BIAS_CUR_CTRL_5 0x010e
  151. #define RT5668_BIAS_CUR_CTRL_6 0x010f
  152. #define RT5668_BIAS_CUR_CTRL_7 0x0110
  153. #define RT5668_BIAS_CUR_CTRL_8 0x0111
  154. #define RT5668_BIAS_CUR_CTRL_9 0x0112
  155. #define RT5668_BIAS_CUR_CTRL_10 0x0113
  156. #define RT5668_VREF_REC_OP_FB_CAP_CTRL 0x0117
  157. #define RT5668_CHARGE_PUMP_1 0x0125
  158. #define RT5668_DIG_IN_CTRL_1 0x0132
  159. #define RT5668_PAD_DRIVING_CTRL 0x0136
  160. #define RT5668_SOFT_RAMP_DEPOP 0x0138
  161. #define RT5668_CHOP_DAC 0x013a
  162. #define RT5668_CHOP_ADC 0x013b
  163. #define RT5668_CALIB_ADC_CTRL 0x013c
  164. #define RT5668_VOL_TEST 0x013f
  165. #define RT5668_SPKVDD_DET_STA 0x0142
  166. #define RT5668_TEST_MODE_CTRL_1 0x0145
  167. #define RT5668_TEST_MODE_CTRL_2 0x0146
  168. #define RT5668_TEST_MODE_CTRL_3 0x0147
  169. #define RT5668_TEST_MODE_CTRL_4 0x0148
  170. #define RT5668_TEST_MODE_CTRL_5 0x0149
  171. #define RT5668_PLL1_INTERNAL 0x0150
  172. #define RT5668_PLL2_INTERNAL 0x0151
  173. #define RT5668_STO_NG2_CTRL_1 0x0160
  174. #define RT5668_STO_NG2_CTRL_2 0x0161
  175. #define RT5668_STO_NG2_CTRL_3 0x0162
  176. #define RT5668_STO_NG2_CTRL_4 0x0163
  177. #define RT5668_STO_NG2_CTRL_5 0x0164
  178. #define RT5668_STO_NG2_CTRL_6 0x0165
  179. #define RT5668_STO_NG2_CTRL_7 0x0166
  180. #define RT5668_STO_NG2_CTRL_8 0x0167
  181. #define RT5668_STO_NG2_CTRL_9 0x0168
  182. #define RT5668_STO_NG2_CTRL_10 0x0169
  183. #define RT5668_STO1_DAC_SIL_DET 0x0190
  184. #define RT5668_SIL_PSV_CTRL1 0x0194
  185. #define RT5668_SIL_PSV_CTRL2 0x0195
  186. #define RT5668_SIL_PSV_CTRL3 0x0197
  187. #define RT5668_SIL_PSV_CTRL4 0x0198
  188. #define RT5668_SIL_PSV_CTRL5 0x0199
  189. #define RT5668_HP_IMP_SENS_CTRL_01 0x01af
  190. #define RT5668_HP_IMP_SENS_CTRL_02 0x01b0
  191. #define RT5668_HP_IMP_SENS_CTRL_03 0x01b1
  192. #define RT5668_HP_IMP_SENS_CTRL_04 0x01b2
  193. #define RT5668_HP_IMP_SENS_CTRL_05 0x01b3
  194. #define RT5668_HP_IMP_SENS_CTRL_06 0x01b4
  195. #define RT5668_HP_IMP_SENS_CTRL_07 0x01b5
  196. #define RT5668_HP_IMP_SENS_CTRL_08 0x01b6
  197. #define RT5668_HP_IMP_SENS_CTRL_09 0x01b7
  198. #define RT5668_HP_IMP_SENS_CTRL_10 0x01b8
  199. #define RT5668_HP_IMP_SENS_CTRL_11 0x01b9
  200. #define RT5668_HP_IMP_SENS_CTRL_12 0x01ba
  201. #define RT5668_HP_IMP_SENS_CTRL_13 0x01bb
  202. #define RT5668_HP_IMP_SENS_CTRL_14 0x01bc
  203. #define RT5668_HP_IMP_SENS_CTRL_15 0x01bd
  204. #define RT5668_HP_IMP_SENS_CTRL_16 0x01be
  205. #define RT5668_HP_IMP_SENS_CTRL_17 0x01bf
  206. #define RT5668_HP_IMP_SENS_CTRL_18 0x01c0
  207. #define RT5668_HP_IMP_SENS_CTRL_19 0x01c1
  208. #define RT5668_HP_IMP_SENS_CTRL_20 0x01c2
  209. #define RT5668_HP_IMP_SENS_CTRL_21 0x01c3
  210. #define RT5668_HP_IMP_SENS_CTRL_22 0x01c4
  211. #define RT5668_HP_IMP_SENS_CTRL_23 0x01c5
  212. #define RT5668_HP_IMP_SENS_CTRL_24 0x01c6
  213. #define RT5668_HP_IMP_SENS_CTRL_25 0x01c7
  214. #define RT5668_HP_IMP_SENS_CTRL_26 0x01c8
  215. #define RT5668_HP_IMP_SENS_CTRL_27 0x01c9
  216. #define RT5668_HP_IMP_SENS_CTRL_28 0x01ca
  217. #define RT5668_HP_IMP_SENS_CTRL_29 0x01cb
  218. #define RT5668_HP_IMP_SENS_CTRL_30 0x01cc
  219. #define RT5668_HP_IMP_SENS_CTRL_31 0x01cd
  220. #define RT5668_HP_IMP_SENS_CTRL_32 0x01ce
  221. #define RT5668_HP_IMP_SENS_CTRL_33 0x01cf
  222. #define RT5668_HP_IMP_SENS_CTRL_34 0x01d0
  223. #define RT5668_HP_IMP_SENS_CTRL_35 0x01d1
  224. #define RT5668_HP_IMP_SENS_CTRL_36 0x01d2
  225. #define RT5668_HP_IMP_SENS_CTRL_37 0x01d3
  226. #define RT5668_HP_IMP_SENS_CTRL_38 0x01d4
  227. #define RT5668_HP_IMP_SENS_CTRL_39 0x01d5
  228. #define RT5668_HP_IMP_SENS_CTRL_40 0x01d6
  229. #define RT5668_HP_IMP_SENS_CTRL_41 0x01d7
  230. #define RT5668_HP_IMP_SENS_CTRL_42 0x01d8
  231. #define RT5668_HP_IMP_SENS_CTRL_43 0x01d9
  232. #define RT5668_HP_LOGIC_CTRL_1 0x01da
  233. #define RT5668_HP_LOGIC_CTRL_2 0x01db
  234. #define RT5668_HP_LOGIC_CTRL_3 0x01dc
  235. #define RT5668_HP_CALIB_CTRL_1 0x01de
  236. #define RT5668_HP_CALIB_CTRL_2 0x01df
  237. #define RT5668_HP_CALIB_CTRL_3 0x01e0
  238. #define RT5668_HP_CALIB_CTRL_4 0x01e1
  239. #define RT5668_HP_CALIB_CTRL_5 0x01e2
  240. #define RT5668_HP_CALIB_CTRL_6 0x01e3
  241. #define RT5668_HP_CALIB_CTRL_7 0x01e4
  242. #define RT5668_HP_CALIB_CTRL_9 0x01e6
  243. #define RT5668_HP_CALIB_CTRL_10 0x01e7
  244. #define RT5668_HP_CALIB_CTRL_11 0x01e8
  245. #define RT5668_HP_CALIB_STA_1 0x01ea
  246. #define RT5668_HP_CALIB_STA_2 0x01eb
  247. #define RT5668_HP_CALIB_STA_3 0x01ec
  248. #define RT5668_HP_CALIB_STA_4 0x01ed
  249. #define RT5668_HP_CALIB_STA_5 0x01ee
  250. #define RT5668_HP_CALIB_STA_6 0x01ef
  251. #define RT5668_HP_CALIB_STA_7 0x01f0
  252. #define RT5668_HP_CALIB_STA_8 0x01f1
  253. #define RT5668_HP_CALIB_STA_9 0x01f2
  254. #define RT5668_HP_CALIB_STA_10 0x01f3
  255. #define RT5668_HP_CALIB_STA_11 0x01f4
  256. #define RT5668_SAR_IL_CMD_1 0x0210
  257. #define RT5668_SAR_IL_CMD_2 0x0211
  258. #define RT5668_SAR_IL_CMD_3 0x0212
  259. #define RT5668_SAR_IL_CMD_4 0x0213
  260. #define RT5668_SAR_IL_CMD_5 0x0214
  261. #define RT5668_SAR_IL_CMD_6 0x0215
  262. #define RT5668_SAR_IL_CMD_7 0x0216
  263. #define RT5668_SAR_IL_CMD_8 0x0217
  264. #define RT5668_SAR_IL_CMD_9 0x0218
  265. #define RT5668_SAR_IL_CMD_10 0x0219
  266. #define RT5668_SAR_IL_CMD_11 0x021a
  267. #define RT5668_SAR_IL_CMD_12 0x021b
  268. #define RT5668_SAR_IL_CMD_13 0x021c
  269. #define RT5668_EFUSE_CTRL_1 0x0250
  270. #define RT5668_EFUSE_CTRL_2 0x0251
  271. #define RT5668_EFUSE_CTRL_3 0x0252
  272. #define RT5668_EFUSE_CTRL_4 0x0253
  273. #define RT5668_EFUSE_CTRL_5 0x0254
  274. #define RT5668_EFUSE_CTRL_6 0x0255
  275. #define RT5668_EFUSE_CTRL_7 0x0256
  276. #define RT5668_EFUSE_CTRL_8 0x0257
  277. #define RT5668_EFUSE_CTRL_9 0x0258
  278. #define RT5668_EFUSE_CTRL_10 0x0259
  279. #define RT5668_EFUSE_CTRL_11 0x025a
  280. #define RT5668_JD_TOP_VC_VTRL 0x0270
  281. #define RT5668_DRC1_CTRL_0 0x02ff
  282. #define RT5668_DRC1_CTRL_1 0x0300
  283. #define RT5668_DRC1_CTRL_2 0x0301
  284. #define RT5668_DRC1_CTRL_3 0x0302
  285. #define RT5668_DRC1_CTRL_4 0x0303
  286. #define RT5668_DRC1_CTRL_5 0x0304
  287. #define RT5668_DRC1_CTRL_6 0x0305
  288. #define RT5668_DRC1_HARD_LMT_CTRL_1 0x0306
  289. #define RT5668_DRC1_HARD_LMT_CTRL_2 0x0307
  290. #define RT5668_DRC1_PRIV_1 0x0310
  291. #define RT5668_DRC1_PRIV_2 0x0311
  292. #define RT5668_DRC1_PRIV_3 0x0312
  293. #define RT5668_DRC1_PRIV_4 0x0313
  294. #define RT5668_DRC1_PRIV_5 0x0314
  295. #define RT5668_DRC1_PRIV_6 0x0315
  296. #define RT5668_DRC1_PRIV_7 0x0316
  297. #define RT5668_DRC1_PRIV_8 0x0317
  298. #define RT5668_EQ_AUTO_RCV_CTRL1 0x03c0
  299. #define RT5668_EQ_AUTO_RCV_CTRL2 0x03c1
  300. #define RT5668_EQ_AUTO_RCV_CTRL3 0x03c2
  301. #define RT5668_EQ_AUTO_RCV_CTRL4 0x03c3
  302. #define RT5668_EQ_AUTO_RCV_CTRL5 0x03c4
  303. #define RT5668_EQ_AUTO_RCV_CTRL6 0x03c5
  304. #define RT5668_EQ_AUTO_RCV_CTRL7 0x03c6
  305. #define RT5668_EQ_AUTO_RCV_CTRL8 0x03c7
  306. #define RT5668_EQ_AUTO_RCV_CTRL9 0x03c8
  307. #define RT5668_EQ_AUTO_RCV_CTRL10 0x03c9
  308. #define RT5668_EQ_AUTO_RCV_CTRL11 0x03ca
  309. #define RT5668_EQ_AUTO_RCV_CTRL12 0x03cb
  310. #define RT5668_EQ_AUTO_RCV_CTRL13 0x03cc
  311. #define RT5668_ADC_L_EQ_LPF1_A1 0x03d0
  312. #define RT5668_R_EQ_LPF1_A1 0x03d1
  313. #define RT5668_L_EQ_LPF1_H0 0x03d2
  314. #define RT5668_R_EQ_LPF1_H0 0x03d3
  315. #define RT5668_L_EQ_BPF1_A1 0x03d4
  316. #define RT5668_R_EQ_BPF1_A1 0x03d5
  317. #define RT5668_L_EQ_BPF1_A2 0x03d6
  318. #define RT5668_R_EQ_BPF1_A2 0x03d7
  319. #define RT5668_L_EQ_BPF1_H0 0x03d8
  320. #define RT5668_R_EQ_BPF1_H0 0x03d9
  321. #define RT5668_L_EQ_BPF2_A1 0x03da
  322. #define RT5668_R_EQ_BPF2_A1 0x03db
  323. #define RT5668_L_EQ_BPF2_A2 0x03dc
  324. #define RT5668_R_EQ_BPF2_A2 0x03dd
  325. #define RT5668_L_EQ_BPF2_H0 0x03de
  326. #define RT5668_R_EQ_BPF2_H0 0x03df
  327. #define RT5668_L_EQ_BPF3_A1 0x03e0
  328. #define RT5668_R_EQ_BPF3_A1 0x03e1
  329. #define RT5668_L_EQ_BPF3_A2 0x03e2
  330. #define RT5668_R_EQ_BPF3_A2 0x03e3
  331. #define RT5668_L_EQ_BPF3_H0 0x03e4
  332. #define RT5668_R_EQ_BPF3_H0 0x03e5
  333. #define RT5668_L_EQ_BPF4_A1 0x03e6
  334. #define RT5668_R_EQ_BPF4_A1 0x03e7
  335. #define RT5668_L_EQ_BPF4_A2 0x03e8
  336. #define RT5668_R_EQ_BPF4_A2 0x03e9
  337. #define RT5668_L_EQ_BPF4_H0 0x03ea
  338. #define RT5668_R_EQ_BPF4_H0 0x03eb
  339. #define RT5668_L_EQ_HPF1_A1 0x03ec
  340. #define RT5668_R_EQ_HPF1_A1 0x03ed
  341. #define RT5668_L_EQ_HPF1_H0 0x03ee
  342. #define RT5668_R_EQ_HPF1_H0 0x03ef
  343. #define RT5668_L_EQ_PRE_VOL 0x03f0
  344. #define RT5668_R_EQ_PRE_VOL 0x03f1
  345. #define RT5668_L_EQ_POST_VOL 0x03f2
  346. #define RT5668_R_EQ_POST_VOL 0x03f3
  347. #define RT5668_I2C_MODE 0xffff
  348. /* global definition */
  349. #define RT5668_L_MUTE (0x1 << 15)
  350. #define RT5668_L_MUTE_SFT 15
  351. #define RT5668_VOL_L_MUTE (0x1 << 14)
  352. #define RT5668_VOL_L_SFT 14
  353. #define RT5668_R_MUTE (0x1 << 7)
  354. #define RT5668_R_MUTE_SFT 7
  355. #define RT5668_VOL_R_MUTE (0x1 << 6)
  356. #define RT5668_VOL_R_SFT 6
  357. #define RT5668_L_VOL_MASK (0x3f << 8)
  358. #define RT5668_L_VOL_SFT 8
  359. #define RT5668_R_VOL_MASK (0x3f)
  360. #define RT5668_R_VOL_SFT 0
  361. /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
  362. #define RT5668_G_HP (0xf << 8)
  363. #define RT5668_G_HP_SFT 8
  364. #define RT5668_G_STO_DA_DMIX (0xf)
  365. #define RT5668_G_STO_DA_SFT 0
  366. /* CBJ Control (0x000b) */
  367. #define RT5668_BST_CBJ_MASK (0xf << 8)
  368. #define RT5668_BST_CBJ_SFT 8
  369. /* Embeeded Jack and Type Detection Control 1 (0x0010) */
  370. #define RT5668_EMB_JD_EN (0x1 << 15)
  371. #define RT5668_EMB_JD_EN_SFT 15
  372. #define RT5668_EMB_JD_RST (0x1 << 14)
  373. #define RT5668_JD_MODE (0x1 << 13)
  374. #define RT5668_JD_MODE_SFT 13
  375. #define RT5668_DET_TYPE (0x1 << 12)
  376. #define RT5668_DET_TYPE_SFT 12
  377. #define RT5668_POLA_EXT_JD_MASK (0x1 << 11)
  378. #define RT5668_POLA_EXT_JD_LOW (0x1 << 11)
  379. #define RT5668_POLA_EXT_JD_HIGH (0x0 << 11)
  380. #define RT5668_EXT_JD_DIG (0x1 << 9)
  381. #define RT5668_POL_FAST_OFF_MASK (0x1 << 8)
  382. #define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)
  383. #define RT5668_POL_FAST_OFF_LOW (0x0 << 8)
  384. #define RT5668_FAST_OFF_MASK (0x1 << 7)
  385. #define RT5668_FAST_OFF_EN (0x1 << 7)
  386. #define RT5668_FAST_OFF_DIS (0x0 << 7)
  387. #define RT5668_VREF_POW_MASK (0x1 << 6)
  388. #define RT5668_VREF_POW_FSM (0x0 << 6)
  389. #define RT5668_VREF_POW_REG (0x1 << 6)
  390. #define RT5668_MB1_PATH_MASK (0x1 << 5)
  391. #define RT5668_CTRL_MB1_REG (0x1 << 5)
  392. #define RT5668_CTRL_MB1_FSM (0x0 << 5)
  393. #define RT5668_MB2_PATH_MASK (0x1 << 4)
  394. #define RT5668_CTRL_MB2_REG (0x1 << 4)
  395. #define RT5668_CTRL_MB2_FSM (0x0 << 4)
  396. #define RT5668_TRIG_JD_MASK (0x1 << 3)
  397. #define RT5668_TRIG_JD_HIGH (0x1 << 3)
  398. #define RT5668_TRIG_JD_LOW (0x0 << 3)
  399. #define RT5668_MIC_CAP_MASK (0x1 << 1)
  400. #define RT5668_MIC_CAP_HS (0x1 << 1)
  401. #define RT5668_MIC_CAP_HP (0x0 << 1)
  402. #define RT5668_MIC_CAP_SRC_MASK (0x1)
  403. #define RT5668_MIC_CAP_SRC_REG (0x1)
  404. #define RT5668_MIC_CAP_SRC_ANA (0x0)
  405. /* Embeeded Jack and Type Detection Control 2 (0x0011) */
  406. #define RT5668_EXT_JD_SRC (0x7 << 4)
  407. #define RT5668_EXT_JD_SRC_SFT 4
  408. #define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
  409. #define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
  410. #define RT5668_EXT_JD_SRC_JDH (0x2 << 4)
  411. #define RT5668_EXT_JD_SRC_JDL (0x3 << 4)
  412. #define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4)
  413. #define RT5668_JACK_TYPE_MASK (0x3)
  414. /* Combo Jack and Type Detection Control 3 (0x0012) */
  415. #define RT5668_CBJ_IN_BUF_EN (0x1 << 7)
  416. /* Combo Jack and Type Detection Control 4 (0x0013) */
  417. #define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12)
  418. #define RT5668_SEL_SHT_MID_TON_2 (0x0 << 12)
  419. #define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12)
  420. #define RT5668_CBJ_JD_TEST_MASK (0x1 << 6)
  421. #define RT5668_CBJ_JD_TEST_NORM (0x0 << 6)
  422. #define RT5668_CBJ_JD_TEST_MODE (0x1 << 6)
  423. /* DAC1 Digital Volume (0x0019) */
  424. #define RT5668_DAC_L1_VOL_MASK (0xff << 8)
  425. #define RT5668_DAC_L1_VOL_SFT 8
  426. #define RT5668_DAC_R1_VOL_MASK (0xff)
  427. #define RT5668_DAC_R1_VOL_SFT 0
  428. /* ADC Digital Volume Control (0x001c) */
  429. #define RT5668_ADC_L_VOL_MASK (0x7f << 8)
  430. #define RT5668_ADC_L_VOL_SFT 8
  431. #define RT5668_ADC_R_VOL_MASK (0x7f)
  432. #define RT5668_ADC_R_VOL_SFT 0
  433. /* Stereo1 ADC Boost Gain Control (0x001f) */
  434. #define RT5668_STO1_ADC_L_BST_MASK (0x3 << 14)
  435. #define RT5668_STO1_ADC_L_BST_SFT 14
  436. #define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12)
  437. #define RT5668_STO1_ADC_R_BST_SFT 12
  438. /* Sidetone Control (0x0024) */
  439. #define RT5668_ST_SRC_SEL (0x1 << 8)
  440. #define RT5668_ST_SRC_SFT 8
  441. #define RT5668_ST_EN_MASK (0x1 << 6)
  442. #define RT5668_ST_DIS (0x0 << 6)
  443. #define RT5668_ST_EN (0x1 << 6)
  444. #define RT5668_ST_EN_SFT 6
  445. /* Stereo1 ADC Mixer Control (0x0026) */
  446. #define RT5668_M_STO1_ADC_L1 (0x1 << 15)
  447. #define RT5668_M_STO1_ADC_L1_SFT 15
  448. #define RT5668_M_STO1_ADC_L2 (0x1 << 14)
  449. #define RT5668_M_STO1_ADC_L2_SFT 14
  450. #define RT5668_STO1_ADC1L_SRC_MASK (0x1 << 13)
  451. #define RT5668_STO1_ADC1L_SRC_SFT 13
  452. #define RT5668_STO1_ADC1_SRC_ADC (0x1 << 13)
  453. #define RT5668_STO1_ADC1_SRC_DACMIX (0x0 << 13)
  454. #define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12)
  455. #define RT5668_STO1_ADC2L_SRC_SFT 12
  456. #define RT5668_STO1_ADCL_SRC_MASK (0x3 << 10)
  457. #define RT5668_STO1_ADCL_SRC_SFT 10
  458. #define RT5668_STO1_DD_L_SRC_MASK (0x1 << 9)
  459. #define RT5668_STO1_DD_L_SRC_SFT 9
  460. #define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8)
  461. #define RT5668_STO1_DMIC_SRC_SFT 8
  462. #define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
  463. #define RT5668_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
  464. #define RT5668_M_STO1_ADC_R1 (0x1 << 7)
  465. #define RT5668_M_STO1_ADC_R1_SFT 7
  466. #define RT5668_M_STO1_ADC_R2 (0x1 << 6)
  467. #define RT5668_M_STO1_ADC_R2_SFT 6
  468. #define RT5668_STO1_ADC1R_SRC_MASK (0x1 << 5)
  469. #define RT5668_STO1_ADC1R_SRC_SFT 5
  470. #define RT5668_STO1_ADC2R_SRC_MASK (0x1 << 4)
  471. #define RT5668_STO1_ADC2R_SRC_SFT 4
  472. #define RT5668_STO1_ADCR_SRC_MASK (0x3 << 2)
  473. #define RT5668_STO1_ADCR_SRC_SFT 2
  474. /* ADC Mixer to DAC Mixer Control (0x0029) */
  475. #define RT5668_M_ADCMIX_L (0x1 << 15)
  476. #define RT5668_M_ADCMIX_L_SFT 15
  477. #define RT5668_M_DAC1_L (0x1 << 14)
  478. #define RT5668_M_DAC1_L_SFT 14
  479. #define RT5668_DAC1_R_SEL_MASK (0x1 << 10)
  480. #define RT5668_DAC1_R_SEL_SFT 10
  481. #define RT5668_DAC1_L_SEL_MASK (0x1 << 8)
  482. #define RT5668_DAC1_L_SEL_SFT 8
  483. #define RT5668_M_ADCMIX_R (0x1 << 7)
  484. #define RT5668_M_ADCMIX_R_SFT 7
  485. #define RT5668_M_DAC1_R (0x1 << 6)
  486. #define RT5668_M_DAC1_R_SFT 6
  487. /* Stereo1 DAC Mixer Control (0x002a) */
  488. #define RT5668_M_DAC_L1_STO_L (0x1 << 15)
  489. #define RT5668_M_DAC_L1_STO_L_SFT 15
  490. #define RT5668_G_DAC_L1_STO_L_MASK (0x1 << 14)
  491. #define RT5668_G_DAC_L1_STO_L_SFT 14
  492. #define RT5668_M_DAC_R1_STO_L (0x1 << 13)
  493. #define RT5668_M_DAC_R1_STO_L_SFT 13
  494. #define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12)
  495. #define RT5668_G_DAC_R1_STO_L_SFT 12
  496. #define RT5668_M_DAC_L1_STO_R (0x1 << 7)
  497. #define RT5668_M_DAC_L1_STO_R_SFT 7
  498. #define RT5668_G_DAC_L1_STO_R_MASK (0x1 << 6)
  499. #define RT5668_G_DAC_L1_STO_R_SFT 6
  500. #define RT5668_M_DAC_R1_STO_R (0x1 << 5)
  501. #define RT5668_M_DAC_R1_STO_R_SFT 5
  502. #define RT5668_G_DAC_R1_STO_R_MASK (0x1 << 4)
  503. #define RT5668_G_DAC_R1_STO_R_SFT 4
  504. /* Analog DAC1 Input Source Control (0x002b) */
  505. #define RT5668_M_ST_STO_L (0x1 << 9)
  506. #define RT5668_M_ST_STO_L_SFT 9
  507. #define RT5668_M_ST_STO_R (0x1 << 8)
  508. #define RT5668_M_ST_STO_R_SFT 8
  509. #define RT5668_DAC_L1_SRC_MASK (0x3 << 4)
  510. #define RT5668_A_DACL1_SFT 4
  511. #define RT5668_DAC_R1_SRC_MASK (0x3)
  512. #define RT5668_A_DACR1_SFT 0
  513. /* Digital Interface Data Control (0x0030) */
  514. #define RT5668_IF2_ADC_SEL_MASK (0x3 << 0)
  515. #define RT5668_IF2_ADC_SEL_SFT 0
  516. /* REC Left Mixer Control 2 (0x003c) */
  517. #define RT5668_G_CBJ_RM1_L (0x7 << 10)
  518. #define RT5668_G_CBJ_RM1_L_SFT 10
  519. #define RT5668_M_CBJ_RM1_L (0x1 << 7)
  520. #define RT5668_M_CBJ_RM1_L_SFT 7
  521. /* Power Management for Digital 1 (0x0061) */
  522. #define RT5668_PWR_I2S1 (0x1 << 15)
  523. #define RT5668_PWR_I2S1_BIT 15
  524. #define RT5668_PWR_I2S2 (0x1 << 14)
  525. #define RT5668_PWR_I2S2_BIT 14
  526. #define RT5668_PWR_DAC_L1 (0x1 << 11)
  527. #define RT5668_PWR_DAC_L1_BIT 11
  528. #define RT5668_PWR_DAC_R1 (0x1 << 10)
  529. #define RT5668_PWR_DAC_R1_BIT 10
  530. #define RT5668_PWR_LDO (0x1 << 8)
  531. #define RT5668_PWR_LDO_BIT 8
  532. #define RT5668_PWR_ADC_L1 (0x1 << 4)
  533. #define RT5668_PWR_ADC_L1_BIT 4
  534. #define RT5668_PWR_ADC_R1 (0x1 << 3)
  535. #define RT5668_PWR_ADC_R1_BIT 3
  536. #define RT5668_DIG_GATE_CTRL (0x1 << 0)
  537. #define RT5668_DIG_GATE_CTRL_SFT 0
  538. /* Power Management for Digital 2 (0x0062) */
  539. #define RT5668_PWR_ADC_S1F (0x1 << 15)
  540. #define RT5668_PWR_ADC_S1F_BIT 15
  541. #define RT5668_PWR_DAC_S1F (0x1 << 10)
  542. #define RT5668_PWR_DAC_S1F_BIT 10
  543. /* Power Management for Analog 1 (0x0063) */
  544. #define RT5668_PWR_VREF1 (0x1 << 15)
  545. #define RT5668_PWR_VREF1_BIT 15
  546. #define RT5668_PWR_FV1 (0x1 << 14)
  547. #define RT5668_PWR_FV1_BIT 14
  548. #define RT5668_PWR_VREF2 (0x1 << 13)
  549. #define RT5668_PWR_VREF2_BIT 13
  550. #define RT5668_PWR_FV2 (0x1 << 12)
  551. #define RT5668_PWR_FV2_BIT 12
  552. #define RT5668_LDO1_DBG_MASK (0x3 << 10)
  553. #define RT5668_PWR_MB (0x1 << 9)
  554. #define RT5668_PWR_MB_BIT 9
  555. #define RT5668_PWR_BG (0x1 << 7)
  556. #define RT5668_PWR_BG_BIT 7
  557. #define RT5668_LDO1_BYPASS_MASK (0x1 << 6)
  558. #define RT5668_LDO1_BYPASS (0x1 << 6)
  559. #define RT5668_LDO1_NOT_BYPASS (0x0 << 6)
  560. #define RT5668_PWR_MA_BIT 6
  561. #define RT5668_LDO1_DVO_MASK (0x3 << 4)
  562. #define RT5668_LDO1_DVO_09 (0x0 << 4)
  563. #define RT5668_LDO1_DVO_10 (0x1 << 4)
  564. #define RT5668_LDO1_DVO_12 (0x2 << 4)
  565. #define RT5668_LDO1_DVO_14 (0x3 << 4)
  566. #define RT5668_HP_DRIVER_MASK (0x3 << 2)
  567. #define RT5668_HP_DRIVER_1X (0x0 << 2)
  568. #define RT5668_HP_DRIVER_3X (0x1 << 2)
  569. #define RT5668_HP_DRIVER_5X (0x3 << 2)
  570. #define RT5668_PWR_HA_L (0x1 << 1)
  571. #define RT5668_PWR_HA_L_BIT 1
  572. #define RT5668_PWR_HA_R (0x1 << 0)
  573. #define RT5668_PWR_HA_R_BIT 0
  574. /* Power Management for Analog 2 (0x0064) */
  575. #define RT5668_PWR_MB1 (0x1 << 11)
  576. #define RT5668_PWR_MB1_PWR_DOWN (0x0 << 11)
  577. #define RT5668_PWR_MB1_BIT 11
  578. #define RT5668_PWR_MB2 (0x1 << 10)
  579. #define RT5668_PWR_MB2_PWR_DOWN (0x0 << 10)
  580. #define RT5668_PWR_MB2_BIT 10
  581. #define RT5668_PWR_JDH (0x1 << 3)
  582. #define RT5668_PWR_JDH_BIT 3
  583. #define RT5668_PWR_JDL (0x1 << 2)
  584. #define RT5668_PWR_JDL_BIT 2
  585. #define RT5668_PWR_RM1_L (0x1 << 1)
  586. #define RT5668_PWR_RM1_L_BIT 1
  587. /* Power Management for Analog 3 (0x0065) */
  588. #define RT5668_PWR_CBJ (0x1 << 9)
  589. #define RT5668_PWR_CBJ_BIT 9
  590. #define RT5668_PWR_PLL (0x1 << 6)
  591. #define RT5668_PWR_PLL_BIT 6
  592. #define RT5668_PWR_PLL2B (0x1 << 5)
  593. #define RT5668_PWR_PLL2B_BIT 5
  594. #define RT5668_PWR_PLL2F (0x1 << 4)
  595. #define RT5668_PWR_PLL2F_BIT 4
  596. #define RT5668_PWR_LDO2 (0x1 << 2)
  597. #define RT5668_PWR_LDO2_BIT 2
  598. #define RT5668_PWR_DET_SPKVDD (0x1 << 1)
  599. #define RT5668_PWR_DET_SPKVDD_BIT 1
  600. /* Power Management for Mixer (0x0066) */
  601. #define RT5668_PWR_STO1_DAC_L (0x1 << 5)
  602. #define RT5668_PWR_STO1_DAC_L_BIT 5
  603. #define RT5668_PWR_STO1_DAC_R (0x1 << 4)
  604. #define RT5668_PWR_STO1_DAC_R_BIT 4
  605. /* MCLK and System Clock Detection Control (0x006b) */
  606. #define RT5668_SYS_CLK_DET (0x1 << 15)
  607. #define RT5668_SYS_CLK_DET_SFT 15
  608. #define RT5668_PLL1_CLK_DET (0x1 << 14)
  609. #define RT5668_PLL1_CLK_DET_SFT 14
  610. #define RT5668_PLL2_CLK_DET (0x1 << 13)
  611. #define RT5668_PLL2_CLK_DET_SFT 13
  612. #define RT5668_POW_CLK_DET2_SFT 8
  613. #define RT5668_POW_CLK_DET_SFT 0
  614. /* Digital Microphone Control 1 (0x006e) */
  615. #define RT5668_DMIC_1_EN_MASK (0x1 << 15)
  616. #define RT5668_DMIC_1_EN_SFT 15
  617. #define RT5668_DMIC_1_DIS (0x0 << 15)
  618. #define RT5668_DMIC_1_EN (0x1 << 15)
  619. #define RT5668_DMIC_1_DP_MASK (0x3 << 4)
  620. #define RT5668_DMIC_1_DP_SFT 4
  621. #define RT5668_DMIC_1_DP_GPIO2 (0x0 << 4)
  622. #define RT5668_DMIC_1_DP_GPIO5 (0x1 << 4)
  623. #define RT5668_DMIC_CLK_MASK (0xf << 0)
  624. #define RT5668_DMIC_CLK_SFT 0
  625. /* I2S1 Audio Serial Data Port Control (0x0070) */
  626. #define RT5668_SEL_ADCDAT_MASK (0x1 << 15)
  627. #define RT5668_SEL_ADCDAT_OUT (0x0 << 15)
  628. #define RT5668_SEL_ADCDAT_IN (0x1 << 15)
  629. #define RT5668_SEL_ADCDAT_SFT 15
  630. #define RT5668_I2S1_TX_CHL_MASK (0x7 << 12)
  631. #define RT5668_I2S1_TX_CHL_SFT 12
  632. #define RT5668_I2S1_TX_CHL_16 (0x0 << 12)
  633. #define RT5668_I2S1_TX_CHL_20 (0x1 << 12)
  634. #define RT5668_I2S1_TX_CHL_24 (0x2 << 12)
  635. #define RT5668_I2S1_TX_CHL_32 (0x3 << 12)
  636. #define RT5668_I2S1_TX_CHL_8 (0x4 << 12)
  637. #define RT5668_I2S1_RX_CHL_MASK (0x7 << 8)
  638. #define RT5668_I2S1_RX_CHL_SFT 8
  639. #define RT5668_I2S1_RX_CHL_16 (0x0 << 8)
  640. #define RT5668_I2S1_RX_CHL_20 (0x1 << 8)
  641. #define RT5668_I2S1_RX_CHL_24 (0x2 << 8)
  642. #define RT5668_I2S1_RX_CHL_32 (0x3 << 8)
  643. #define RT5668_I2S1_RX_CHL_8 (0x4 << 8)
  644. #define RT5668_I2S1_MONO_MASK (0x1 << 7)
  645. #define RT5668_I2S1_MONO_EN (0x1 << 7)
  646. #define RT5668_I2S1_MONO_DIS (0x0 << 7)
  647. #define RT5668_I2S2_MONO_MASK (0x1 << 6)
  648. #define RT5668_I2S2_MONO_EN (0x1 << 6)
  649. #define RT5668_I2S2_MONO_DIS (0x0 << 6)
  650. #define RT5668_I2S1_DL_MASK (0x7 << 4)
  651. #define RT5668_I2S1_DL_SFT 4
  652. #define RT5668_I2S1_DL_16 (0x0 << 4)
  653. #define RT5668_I2S1_DL_20 (0x1 << 4)
  654. #define RT5668_I2S1_DL_24 (0x2 << 4)
  655. #define RT5668_I2S1_DL_32 (0x3 << 4)
  656. #define RT5668_I2S1_DL_8 (0x4 << 4)
  657. /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */
  658. #define RT5668_I2S2_MS_MASK (0x1 << 15)
  659. #define RT5668_I2S2_MS_SFT 15
  660. #define RT5668_I2S2_MS_M (0x0 << 15)
  661. #define RT5668_I2S2_MS_S (0x1 << 15)
  662. #define RT5668_I2S2_PIN_CFG_MASK (0x1 << 14)
  663. #define RT5668_I2S2_PIN_CFG_SFT 14
  664. #define RT5668_I2S2_CLK_SEL_MASK (0x1 << 11)
  665. #define RT5668_I2S2_CLK_SEL_SFT 11
  666. #define RT5668_I2S2_OUT_MASK (0x1 << 9)
  667. #define RT5668_I2S2_OUT_SFT 9
  668. #define RT5668_I2S2_OUT_UM (0x0 << 9)
  669. #define RT5668_I2S2_OUT_M (0x1 << 9)
  670. #define RT5668_I2S_BP_MASK (0x1 << 8)
  671. #define RT5668_I2S_BP_SFT 8
  672. #define RT5668_I2S_BP_NOR (0x0 << 8)
  673. #define RT5668_I2S_BP_INV (0x1 << 8)
  674. #define RT5668_I2S2_MONO_EN (0x1 << 6)
  675. #define RT5668_I2S2_MONO_DIS (0x0 << 6)
  676. #define RT5668_I2S2_DL_MASK (0x3 << 4)
  677. #define RT5668_I2S2_DL_SFT 4
  678. #define RT5668_I2S2_DL_16 (0x0 << 4)
  679. #define RT5668_I2S2_DL_20 (0x1 << 4)
  680. #define RT5668_I2S2_DL_24 (0x2 << 4)
  681. #define RT5668_I2S2_DL_8 (0x3 << 4)
  682. #define RT5668_I2S_DF_MASK (0x7)
  683. #define RT5668_I2S_DF_SFT 0
  684. #define RT5668_I2S_DF_I2S (0x0)
  685. #define RT5668_I2S_DF_LEFT (0x1)
  686. #define RT5668_I2S_DF_PCM_A (0x2)
  687. #define RT5668_I2S_DF_PCM_B (0x3)
  688. #define RT5668_I2S_DF_PCM_A_N (0x6)
  689. #define RT5668_I2S_DF_PCM_B_N (0x7)
  690. /* ADC/DAC Clock Control 1 (0x0073) */
  691. #define RT5668_ADC_OSR_MASK (0xf << 12)
  692. #define RT5668_ADC_OSR_SFT 12
  693. #define RT5668_ADC_OSR_D_1 (0x0 << 12)
  694. #define RT5668_ADC_OSR_D_2 (0x1 << 12)
  695. #define RT5668_ADC_OSR_D_4 (0x2 << 12)
  696. #define RT5668_ADC_OSR_D_6 (0x3 << 12)
  697. #define RT5668_ADC_OSR_D_8 (0x4 << 12)
  698. #define RT5668_ADC_OSR_D_12 (0x5 << 12)
  699. #define RT5668_ADC_OSR_D_16 (0x6 << 12)
  700. #define RT5668_ADC_OSR_D_24 (0x7 << 12)
  701. #define RT5668_ADC_OSR_D_32 (0x8 << 12)
  702. #define RT5668_ADC_OSR_D_48 (0x9 << 12)
  703. #define RT5668_I2S_M_DIV_MASK (0xf << 12)
  704. #define RT5668_I2S_M_DIV_SFT 8
  705. #define RT5668_I2S_M_D_1 (0x0 << 8)
  706. #define RT5668_I2S_M_D_2 (0x1 << 8)
  707. #define RT5668_I2S_M_D_3 (0x2 << 8)
  708. #define RT5668_I2S_M_D_4 (0x3 << 8)
  709. #define RT5668_I2S_M_D_6 (0x4 << 8)
  710. #define RT5668_I2S_M_D_8 (0x5 << 8)
  711. #define RT5668_I2S_M_D_12 (0x6 << 8)
  712. #define RT5668_I2S_M_D_16 (0x7 << 8)
  713. #define RT5668_I2S_M_D_24 (0x8 << 8)
  714. #define RT5668_I2S_M_D_32 (0x9 << 8)
  715. #define RT5668_I2S_M_D_48 (0x10 << 8)
  716. #define RT5668_I2S_CLK_SRC_MASK (0x7 << 4)
  717. #define RT5668_I2S_CLK_SRC_SFT 4
  718. #define RT5668_I2S_CLK_SRC_MCLK (0x0 << 4)
  719. #define RT5668_I2S_CLK_SRC_PLL1 (0x1 << 4)
  720. #define RT5668_I2S_CLK_SRC_PLL2 (0x2 << 4)
  721. #define RT5668_I2S_CLK_SRC_SDW (0x3 << 4)
  722. #define RT5668_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */
  723. #define RT5668_DAC_OSR_MASK (0xf << 0)
  724. #define RT5668_DAC_OSR_SFT 0
  725. #define RT5668_DAC_OSR_D_1 (0x0 << 0)
  726. #define RT5668_DAC_OSR_D_2 (0x1 << 0)
  727. #define RT5668_DAC_OSR_D_4 (0x2 << 0)
  728. #define RT5668_DAC_OSR_D_6 (0x3 << 0)
  729. #define RT5668_DAC_OSR_D_8 (0x4 << 0)
  730. #define RT5668_DAC_OSR_D_12 (0x5 << 0)
  731. #define RT5668_DAC_OSR_D_16 (0x6 << 0)
  732. #define RT5668_DAC_OSR_D_24 (0x7 << 0)
  733. #define RT5668_DAC_OSR_D_32 (0x8 << 0)
  734. #define RT5668_DAC_OSR_D_48 (0x9 << 0)
  735. /* ADC/DAC Clock Control 2 (0x0074) */
  736. #define RT5668_I2S2_BCLK_MS2_MASK (0x1 << 11)
  737. #define RT5668_I2S2_BCLK_MS2_SFT 11
  738. #define RT5668_I2S2_BCLK_MS2_32 (0x0 << 11)
  739. #define RT5668_I2S2_BCLK_MS2_64 (0x1 << 11)
  740. /* TDM control 1 (0x0079) */
  741. #define RT5668_TDM_TX_CH_MASK (0x3 << 12)
  742. #define RT5668_TDM_TX_CH_2 (0x0 << 12)
  743. #define RT5668_TDM_TX_CH_4 (0x1 << 12)
  744. #define RT5668_TDM_TX_CH_6 (0x2 << 12)
  745. #define RT5668_TDM_TX_CH_8 (0x3 << 12)
  746. #define RT5668_TDM_RX_CH_MASK (0x3 << 8)
  747. #define RT5668_TDM_RX_CH_2 (0x0 << 8)
  748. #define RT5668_TDM_RX_CH_4 (0x1 << 8)
  749. #define RT5668_TDM_RX_CH_6 (0x2 << 8)
  750. #define RT5668_TDM_RX_CH_8 (0x3 << 8)
  751. #define RT5668_TDM_ADC_LCA_MASK (0xf << 4)
  752. #define RT5668_TDM_ADC_LCA_SFT 4
  753. #define RT5668_TDM_ADC_DL_SFT 0
  754. /* TDM control 3 (0x007a) */
  755. #define RT5668_IF1_ADC1_SEL_SFT 14
  756. #define RT5668_IF1_ADC2_SEL_SFT 12
  757. #define RT5668_IF1_ADC3_SEL_SFT 10
  758. #define RT5668_IF1_ADC4_SEL_SFT 8
  759. #define RT5668_TDM_ADC_SEL_SFT 4
  760. /* TDM/I2S control (0x007e) */
  761. #define RT5668_TDM_S_BP_MASK (0x1 << 15)
  762. #define RT5668_TDM_S_BP_SFT 15
  763. #define RT5668_TDM_S_BP_NOR (0x0 << 15)
  764. #define RT5668_TDM_S_BP_INV (0x1 << 15)
  765. #define RT5668_TDM_S_LP_MASK (0x1 << 14)
  766. #define RT5668_TDM_S_LP_SFT 14
  767. #define RT5668_TDM_S_LP_NOR (0x0 << 14)
  768. #define RT5668_TDM_S_LP_INV (0x1 << 14)
  769. #define RT5668_TDM_DF_MASK (0x7 << 11)
  770. #define RT5668_TDM_DF_SFT 11
  771. #define RT5668_TDM_DF_I2S (0x0 << 11)
  772. #define RT5668_TDM_DF_LEFT (0x1 << 11)
  773. #define RT5668_TDM_DF_PCM_A (0x2 << 11)
  774. #define RT5668_TDM_DF_PCM_B (0x3 << 11)
  775. #define RT5668_TDM_DF_PCM_A_N (0x6 << 11)
  776. #define RT5668_TDM_DF_PCM_B_N (0x7 << 11)
  777. #define RT5668_TDM_CL_MASK (0x3 << 4)
  778. #define RT5668_TDM_CL_16 (0x0 << 4)
  779. #define RT5668_TDM_CL_20 (0x1 << 4)
  780. #define RT5668_TDM_CL_24 (0x2 << 4)
  781. #define RT5668_TDM_CL_32 (0x3 << 4)
  782. #define RT5668_TDM_M_BP_MASK (0x1 << 2)
  783. #define RT5668_TDM_M_BP_SFT 2
  784. #define RT5668_TDM_M_BP_NOR (0x0 << 2)
  785. #define RT5668_TDM_M_BP_INV (0x1 << 2)
  786. #define RT5668_TDM_M_LP_MASK (0x1 << 1)
  787. #define RT5668_TDM_M_LP_SFT 1
  788. #define RT5668_TDM_M_LP_NOR (0x0 << 1)
  789. #define RT5668_TDM_M_LP_INV (0x1 << 1)
  790. #define RT5668_TDM_MS_MASK (0x1 << 0)
  791. #define RT5668_TDM_MS_SFT 0
  792. #define RT5668_TDM_MS_M (0x0 << 0)
  793. #define RT5668_TDM_MS_S (0x1 << 0)
  794. /* Global Clock Control (0x0080) */
  795. #define RT5668_SCLK_SRC_MASK (0x7 << 13)
  796. #define RT5668_SCLK_SRC_SFT 13
  797. #define RT5668_SCLK_SRC_MCLK (0x0 << 13)
  798. #define RT5668_SCLK_SRC_PLL1 (0x1 << 13)
  799. #define RT5668_SCLK_SRC_PLL2 (0x2 << 13)
  800. #define RT5668_SCLK_SRC_SDW (0x3 << 13)
  801. #define RT5668_SCLK_SRC_RCCLK (0x4 << 13)
  802. #define RT5668_PLL1_SRC_MASK (0x3 << 10)
  803. #define RT5668_PLL1_SRC_SFT 10
  804. #define RT5668_PLL1_SRC_MCLK (0x0 << 10)
  805. #define RT5668_PLL1_SRC_BCLK1 (0x1 << 10)
  806. #define RT5668_PLL1_SRC_SDW (0x2 << 10)
  807. #define RT5668_PLL1_SRC_RC (0x3 << 10)
  808. #define RT5668_PLL2_SRC_MASK (0x3 << 8)
  809. #define RT5668_PLL2_SRC_SFT 8
  810. #define RT5668_PLL2_SRC_MCLK (0x0 << 8)
  811. #define RT5668_PLL2_SRC_BCLK1 (0x1 << 8)
  812. #define RT5668_PLL2_SRC_SDW (0x2 << 8)
  813. #define RT5668_PLL2_SRC_RC (0x3 << 8)
  814. #define RT5668_PLL_INP_MAX 40000000
  815. #define RT5668_PLL_INP_MIN 256000
  816. /* PLL M/N/K Code Control 1 (0x0081) */
  817. #define RT5668_PLL_N_MAX 0x001ff
  818. #define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
  819. #define RT5668_PLL_N_SFT 7
  820. #define RT5668_PLL_K_MAX 0x001f
  821. #define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
  822. #define RT5668_PLL_K_SFT 0
  823. /* PLL M/N/K Code Control 2 (0x0082) */
  824. #define RT5668_PLL_M_MAX 0x00f
  825. #define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
  826. #define RT5668_PLL_M_SFT 12
  827. #define RT5668_PLL_M_BP (0x1 << 11)
  828. #define RT5668_PLL_M_BP_SFT 11
  829. #define RT5668_PLL_K_BP (0x1 << 10)
  830. #define RT5668_PLL_K_BP_SFT 10
  831. /* PLL tracking mode 1 (0x0083) */
  832. #define RT5668_DA_ASRC_MASK (0x1 << 13)
  833. #define RT5668_DA_ASRC_SFT 13
  834. #define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
  835. #define RT5668_DAC_STO1_ASRC_SFT 12
  836. #define RT5668_AD_ASRC_MASK (0x1 << 8)
  837. #define RT5668_AD_ASRC_SFT 8
  838. #define RT5668_AD_ASRC_SEL_MASK (0x1 << 4)
  839. #define RT5668_AD_ASRC_SEL_SFT 4
  840. #define RT5668_DMIC_ASRC_MASK (0x1 << 3)
  841. #define RT5668_DMIC_ASRC_SFT 3
  842. #define RT5668_ADC_STO1_ASRC_MASK (0x1 << 2)
  843. #define RT5668_ADC_STO1_ASRC_SFT 2
  844. #define RT5668_DA_ASRC_SEL_MASK (0x1 << 0)
  845. #define RT5668_DA_ASRC_SEL_SFT 0
  846. /* PLL tracking mode 2 3 (0x0084)(0x0085)*/
  847. #define RT5668_FILTER_CLK_SEL_MASK (0x7 << 12)
  848. #define RT5668_FILTER_CLK_SEL_SFT 12
  849. /* ASRC Control 4 (0x0086) */
  850. #define RT5668_ASRCIN_FTK_N1_MASK (0x3 << 14)
  851. #define RT5668_ASRCIN_FTK_N1_SFT 14
  852. #define RT5668_ASRCIN_FTK_N2_MASK (0x3 << 12)
  853. #define RT5668_ASRCIN_FTK_N2_SFT 12
  854. #define RT5668_ASRCIN_FTK_M1_MASK (0x7 << 8)
  855. #define RT5668_ASRCIN_FTK_M1_SFT 8
  856. #define RT5668_ASRCIN_FTK_M2_MASK (0x7 << 4)
  857. #define RT5668_ASRCIN_FTK_M2_SFT 4
  858. /* SoundWire reference clk (0x008d) */
  859. #define RT5668_PLL2_OUT_MASK (0x1 << 8)
  860. #define RT5668_PLL2_OUT_98M (0x0 << 8)
  861. #define RT5668_PLL2_OUT_49M (0x1 << 8)
  862. #define RT5668_SDW_REF_2_MASK (0xf << 4)
  863. #define RT5668_SDW_REF_2_SFT 4
  864. #define RT5668_SDW_REF_2_48K (0x0 << 4)
  865. #define RT5668_SDW_REF_2_96K (0x1 << 4)
  866. #define RT5668_SDW_REF_2_192K (0x2 << 4)
  867. #define RT5668_SDW_REF_2_32K (0x3 << 4)
  868. #define RT5668_SDW_REF_2_24K (0x4 << 4)
  869. #define RT5668_SDW_REF_2_16K (0x5 << 4)
  870. #define RT5668_SDW_REF_2_12K (0x6 << 4)
  871. #define RT5668_SDW_REF_2_8K (0x7 << 4)
  872. #define RT5668_SDW_REF_2_44K (0x8 << 4)
  873. #define RT5668_SDW_REF_2_88K (0x9 << 4)
  874. #define RT5668_SDW_REF_2_176K (0xa << 4)
  875. #define RT5668_SDW_REF_2_353K (0xb << 4)
  876. #define RT5668_SDW_REF_2_22K (0xc << 4)
  877. #define RT5668_SDW_REF_2_384K (0xd << 4)
  878. #define RT5668_SDW_REF_2_11K (0xe << 4)
  879. #define RT5668_SDW_REF_1_MASK (0xf << 0)
  880. #define RT5668_SDW_REF_1_SFT 0
  881. #define RT5668_SDW_REF_1_48K (0x0 << 0)
  882. #define RT5668_SDW_REF_1_96K (0x1 << 0)
  883. #define RT5668_SDW_REF_1_192K (0x2 << 0)
  884. #define RT5668_SDW_REF_1_32K (0x3 << 0)
  885. #define RT5668_SDW_REF_1_24K (0x4 << 0)
  886. #define RT5668_SDW_REF_1_16K (0x5 << 0)
  887. #define RT5668_SDW_REF_1_12K (0x6 << 0)
  888. #define RT5668_SDW_REF_1_8K (0x7 << 0)
  889. #define RT5668_SDW_REF_1_44K (0x8 << 0)
  890. #define RT5668_SDW_REF_1_88K (0x9 << 0)
  891. #define RT5668_SDW_REF_1_176K (0xa << 0)
  892. #define RT5668_SDW_REF_1_353K (0xb << 0)
  893. #define RT5668_SDW_REF_1_22K (0xc << 0)
  894. #define RT5668_SDW_REF_1_384K (0xd << 0)
  895. #define RT5668_SDW_REF_1_11K (0xe << 0)
  896. /* Depop Mode Control 1 (0x008e) */
  897. #define RT5668_PUMP_EN (0x1 << 3)
  898. #define RT5668_PUMP_EN_SFT 3
  899. #define RT5668_CAPLESS_EN (0x1 << 0)
  900. #define RT5668_CAPLESS_EN_SFT 0
  901. /* Depop Mode Control 2 (0x8f) */
  902. #define RT5668_RAMP_MASK (0x1 << 12)
  903. #define RT5668_RAMP_SFT 12
  904. #define RT5668_RAMP_DIS (0x0 << 12)
  905. #define RT5668_RAMP_EN (0x1 << 12)
  906. #define RT5668_BPS_MASK (0x1 << 11)
  907. #define RT5668_BPS_SFT 11
  908. #define RT5668_BPS_DIS (0x0 << 11)
  909. #define RT5668_BPS_EN (0x1 << 11)
  910. #define RT5668_FAST_UPDN_MASK (0x1 << 10)
  911. #define RT5668_FAST_UPDN_SFT 10
  912. #define RT5668_FAST_UPDN_DIS (0x0 << 10)
  913. #define RT5668_FAST_UPDN_EN (0x1 << 10)
  914. #define RT5668_VLO_MASK (0x1 << 7)
  915. #define RT5668_VLO_SFT 7
  916. #define RT5668_VLO_3V (0x0 << 7)
  917. #define RT5668_VLO_33V (0x1 << 7)
  918. /* HPOUT charge pump 1 (0x0091) */
  919. #define RT5668_OSW_L_MASK (0x1 << 11)
  920. #define RT5668_OSW_L_SFT 11
  921. #define RT5668_OSW_L_DIS (0x0 << 11)
  922. #define RT5668_OSW_L_EN (0x1 << 11)
  923. #define RT5668_OSW_R_MASK (0x1 << 10)
  924. #define RT5668_OSW_R_SFT 10
  925. #define RT5668_OSW_R_DIS (0x0 << 10)
  926. #define RT5668_OSW_R_EN (0x1 << 10)
  927. #define RT5668_PM_HP_MASK (0x3 << 8)
  928. #define RT5668_PM_HP_SFT 8
  929. #define RT5668_PM_HP_LV (0x0 << 8)
  930. #define RT5668_PM_HP_MV (0x1 << 8)
  931. #define RT5668_PM_HP_HV (0x2 << 8)
  932. #define RT5668_IB_HP_MASK (0x3 << 6)
  933. #define RT5668_IB_HP_SFT 6
  934. #define RT5668_IB_HP_125IL (0x0 << 6)
  935. #define RT5668_IB_HP_25IL (0x1 << 6)
  936. #define RT5668_IB_HP_5IL (0x2 << 6)
  937. #define RT5668_IB_HP_1IL (0x3 << 6)
  938. /* Micbias Control1 (0x93) */
  939. #define RT5668_MIC1_OV_MASK (0x3 << 14)
  940. #define RT5668_MIC1_OV_SFT 14
  941. #define RT5668_MIC1_OV_2V7 (0x0 << 14)
  942. #define RT5668_MIC1_OV_2V4 (0x1 << 14)
  943. #define RT5668_MIC1_OV_2V25 (0x3 << 14)
  944. #define RT5668_MIC1_OV_1V8 (0x4 << 14)
  945. #define RT5668_MIC1_CLK_MASK (0x1 << 13)
  946. #define RT5668_MIC1_CLK_SFT 13
  947. #define RT5668_MIC1_CLK_DIS (0x0 << 13)
  948. #define RT5668_MIC1_CLK_EN (0x1 << 13)
  949. #define RT5668_MIC1_OVCD_MASK (0x1 << 12)
  950. #define RT5668_MIC1_OVCD_SFT 12
  951. #define RT5668_MIC1_OVCD_DIS (0x0 << 12)
  952. #define RT5668_MIC1_OVCD_EN (0x1 << 12)
  953. #define RT5668_MIC1_OVTH_MASK (0x3 << 10)
  954. #define RT5668_MIC1_OVTH_SFT 10
  955. #define RT5668_MIC1_OVTH_768UA (0x0 << 10)
  956. #define RT5668_MIC1_OVTH_960UA (0x1 << 10)
  957. #define RT5668_MIC1_OVTH_1152UA (0x2 << 10)
  958. #define RT5668_MIC1_OVTH_1960UA (0x3 << 10)
  959. #define RT5668_MIC2_OV_MASK (0x3 << 8)
  960. #define RT5668_MIC2_OV_SFT 8
  961. #define RT5668_MIC2_OV_2V7 (0x0 << 8)
  962. #define RT5668_MIC2_OV_2V4 (0x1 << 8)
  963. #define RT5668_MIC2_OV_2V25 (0x3 << 8)
  964. #define RT5668_MIC2_OV_1V8 (0x4 << 8)
  965. #define RT5668_MIC2_CLK_MASK (0x1 << 7)
  966. #define RT5668_MIC2_CLK_SFT 7
  967. #define RT5668_MIC2_CLK_DIS (0x0 << 7)
  968. #define RT5668_MIC2_CLK_EN (0x1 << 7)
  969. #define RT5668_MIC2_OVTH_MASK (0x3 << 4)
  970. #define RT5668_MIC2_OVTH_SFT 4
  971. #define RT5668_MIC2_OVTH_768UA (0x0 << 4)
  972. #define RT5668_MIC2_OVTH_960UA (0x1 << 4)
  973. #define RT5668_MIC2_OVTH_1152UA (0x2 << 4)
  974. #define RT5668_MIC2_OVTH_1960UA (0x3 << 4)
  975. #define RT5668_PWR_MB_MASK (0x1 << 3)
  976. #define RT5668_PWR_MB_SFT 3
  977. #define RT5668_PWR_MB_PD (0x0 << 3)
  978. #define RT5668_PWR_MB_PU (0x1 << 3)
  979. /* Micbias Control2 (0x0094) */
  980. #define RT5668_PWR_CLK25M_MASK (0x1 << 9)
  981. #define RT5668_PWR_CLK25M_SFT 9
  982. #define RT5668_PWR_CLK25M_PD (0x0 << 9)
  983. #define RT5668_PWR_CLK25M_PU (0x1 << 9)
  984. #define RT5668_PWR_CLK1M_MASK (0x1 << 8)
  985. #define RT5668_PWR_CLK1M_SFT 8
  986. #define RT5668_PWR_CLK1M_PD (0x0 << 8)
  987. #define RT5668_PWR_CLK1M_PU (0x1 << 8)
  988. /* RC Clock Control (0x009f) */
  989. #define RT5668_POW_IRQ (0x1 << 15)
  990. #define RT5668_POW_JDH (0x1 << 14)
  991. #define RT5668_POW_JDL (0x1 << 13)
  992. #define RT5668_POW_ANA (0x1 << 12)
  993. /* I2S Master Mode Clock Control 1 (0x00a0) */
  994. #define RT5668_CLK_SRC_MCLK (0x0)
  995. #define RT5668_CLK_SRC_PLL1 (0x1)
  996. #define RT5668_CLK_SRC_PLL2 (0x2)
  997. #define RT5668_CLK_SRC_SDW (0x3)
  998. #define RT5668_CLK_SRC_RCCLK (0x4)
  999. #define RT5668_I2S_PD_1 (0x0)
  1000. #define RT5668_I2S_PD_2 (0x1)
  1001. #define RT5668_I2S_PD_3 (0x2)
  1002. #define RT5668_I2S_PD_4 (0x3)
  1003. #define RT5668_I2S_PD_6 (0x4)
  1004. #define RT5668_I2S_PD_8 (0x5)
  1005. #define RT5668_I2S_PD_12 (0x6)
  1006. #define RT5668_I2S_PD_16 (0x7)
  1007. #define RT5668_I2S_PD_24 (0x8)
  1008. #define RT5668_I2S_PD_32 (0x9)
  1009. #define RT5668_I2S_PD_48 (0xa)
  1010. #define RT5668_I2S2_SRC_MASK (0x3 << 4)
  1011. #define RT5668_I2S2_SRC_SFT 4
  1012. #define RT5668_I2S2_M_PD_MASK (0xf << 0)
  1013. #define RT5668_I2S2_M_PD_SFT 0
  1014. /* IRQ Control 1 (0x00b6) */
  1015. #define RT5668_JD1_PULSE_EN_MASK (0x1 << 10)
  1016. #define RT5668_JD1_PULSE_EN_SFT 10
  1017. #define RT5668_JD1_PULSE_DIS (0x0 << 10)
  1018. #define RT5668_JD1_PULSE_EN (0x1 << 10)
  1019. /* IRQ Control 2 (0x00b7) */
  1020. #define RT5668_JD1_EN_MASK (0x1 << 15)
  1021. #define RT5668_JD1_EN_SFT 15
  1022. #define RT5668_JD1_DIS (0x0 << 15)
  1023. #define RT5668_JD1_EN (0x1 << 15)
  1024. #define RT5668_JD1_POL_MASK (0x1 << 13)
  1025. #define RT5668_JD1_POL_NOR (0x0 << 13)
  1026. #define RT5668_JD1_POL_INV (0x1 << 13)
  1027. /* IRQ Control 3 (0x00b8) */
  1028. #define RT5668_IL_IRQ_MASK (0x1 << 7)
  1029. #define RT5668_IL_IRQ_DIS (0x0 << 7)
  1030. #define RT5668_IL_IRQ_EN (0x1 << 7)
  1031. /* GPIO Control 1 (0x00c0) */
  1032. #define RT5668_GP1_PIN_MASK (0x3 << 14)
  1033. #define RT5668_GP1_PIN_SFT 14
  1034. #define RT5668_GP1_PIN_GPIO1 (0x0 << 14)
  1035. #define RT5668_GP1_PIN_IRQ (0x1 << 14)
  1036. #define RT5668_GP1_PIN_DMIC_CLK (0x2 << 14)
  1037. #define RT5668_GP2_PIN_MASK (0x3 << 12)
  1038. #define RT5668_GP2_PIN_SFT 12
  1039. #define RT5668_GP2_PIN_GPIO2 (0x0 << 12)
  1040. #define RT5668_GP2_PIN_LRCK2 (0x1 << 12)
  1041. #define RT5668_GP2_PIN_DMIC_SDA (0x2 << 12)
  1042. #define RT5668_GP3_PIN_MASK (0x3 << 10)
  1043. #define RT5668_GP3_PIN_SFT 10
  1044. #define RT5668_GP3_PIN_GPIO3 (0x0 << 10)
  1045. #define RT5668_GP3_PIN_BCLK2 (0x1 << 10)
  1046. #define RT5668_GP3_PIN_DMIC_CLK (0x2 << 10)
  1047. #define RT5668_GP4_PIN_MASK (0x3 << 8)
  1048. #define RT5668_GP4_PIN_SFT 8
  1049. #define RT5668_GP4_PIN_GPIO4 (0x0 << 8)
  1050. #define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8)
  1051. #define RT5668_GP4_PIN_DMIC_CLK (0x2 << 8)
  1052. #define RT5668_GP4_PIN_ADCDAT2 (0x3 << 8)
  1053. #define RT5668_GP5_PIN_MASK (0x3 << 6)
  1054. #define RT5668_GP5_PIN_SFT 6
  1055. #define RT5668_GP5_PIN_GPIO5 (0x0 << 6)
  1056. #define RT5668_GP5_PIN_DACDAT1 (0x1 << 6)
  1057. #define RT5668_GP5_PIN_DMIC_SDA (0x2 << 6)
  1058. #define RT5668_GP6_PIN_MASK (0x1 << 5)
  1059. #define RT5668_GP6_PIN_SFT 5
  1060. #define RT5668_GP6_PIN_GPIO6 (0x0 << 5)
  1061. #define RT5668_GP6_PIN_LRCK1 (0x1 << 5)
  1062. /* GPIO Control 2 (0x00c1)*/
  1063. #define RT5668_GP1_PF_MASK (0x1 << 15)
  1064. #define RT5668_GP1_PF_IN (0x0 << 15)
  1065. #define RT5668_GP1_PF_OUT (0x1 << 15)
  1066. #define RT5668_GP1_OUT_MASK (0x1 << 14)
  1067. #define RT5668_GP1_OUT_L (0x0 << 14)
  1068. #define RT5668_GP1_OUT_H (0x1 << 14)
  1069. #define RT5668_GP2_PF_MASK (0x1 << 13)
  1070. #define RT5668_GP2_PF_IN (0x0 << 13)
  1071. #define RT5668_GP2_PF_OUT (0x1 << 13)
  1072. #define RT5668_GP2_OUT_MASK (0x1 << 12)
  1073. #define RT5668_GP2_OUT_L (0x0 << 12)
  1074. #define RT5668_GP2_OUT_H (0x1 << 12)
  1075. #define RT5668_GP3_PF_MASK (0x1 << 11)
  1076. #define RT5668_GP3_PF_IN (0x0 << 11)
  1077. #define RT5668_GP3_PF_OUT (0x1 << 11)
  1078. #define RT5668_GP3_OUT_MASK (0x1 << 10)
  1079. #define RT5668_GP3_OUT_L (0x0 << 10)
  1080. #define RT5668_GP3_OUT_H (0x1 << 10)
  1081. #define RT5668_GP4_PF_MASK (0x1 << 9)
  1082. #define RT5668_GP4_PF_IN (0x0 << 9)
  1083. #define RT5668_GP4_PF_OUT (0x1 << 9)
  1084. #define RT5668_GP4_OUT_MASK (0x1 << 8)
  1085. #define RT5668_GP4_OUT_L (0x0 << 8)
  1086. #define RT5668_GP4_OUT_H (0x1 << 8)
  1087. #define RT5668_GP5_PF_MASK (0x1 << 7)
  1088. #define RT5668_GP5_PF_IN (0x0 << 7)
  1089. #define RT5668_GP5_PF_OUT (0x1 << 7)
  1090. #define RT5668_GP5_OUT_MASK (0x1 << 6)
  1091. #define RT5668_GP5_OUT_L (0x0 << 6)
  1092. #define RT5668_GP5_OUT_H (0x1 << 6)
  1093. #define RT5668_GP6_PF_MASK (0x1 << 5)
  1094. #define RT5668_GP6_PF_IN (0x0 << 5)
  1095. #define RT5668_GP6_PF_OUT (0x1 << 5)
  1096. #define RT5668_GP6_OUT_MASK (0x1 << 4)
  1097. #define RT5668_GP6_OUT_L (0x0 << 4)
  1098. #define RT5668_GP6_OUT_H (0x1 << 4)
  1099. /* GPIO Status (0x00c2) */
  1100. #define RT5668_GP6_STA (0x1 << 6)
  1101. #define RT5668_GP5_STA (0x1 << 5)
  1102. #define RT5668_GP4_STA (0x1 << 4)
  1103. #define RT5668_GP3_STA (0x1 << 3)
  1104. #define RT5668_GP2_STA (0x1 << 2)
  1105. #define RT5668_GP1_STA (0x1 << 1)
  1106. /* Soft volume and zero cross control 1 (0x00d9) */
  1107. #define RT5668_SV_MASK (0x1 << 15)
  1108. #define RT5668_SV_SFT 15
  1109. #define RT5668_SV_DIS (0x0 << 15)
  1110. #define RT5668_SV_EN (0x1 << 15)
  1111. #define RT5668_ZCD_MASK (0x1 << 10)
  1112. #define RT5668_ZCD_SFT 10
  1113. #define RT5668_ZCD_PD (0x0 << 10)
  1114. #define RT5668_ZCD_PU (0x1 << 10)
  1115. #define RT5668_SV_DLY_MASK (0xf)
  1116. #define RT5668_SV_DLY_SFT 0
  1117. /* Soft volume and zero cross control 2 (0x00da) */
  1118. #define RT5668_ZCD_BST1_CBJ_MASK (0x1 << 7)
  1119. #define RT5668_ZCD_BST1_CBJ_SFT 7
  1120. #define RT5668_ZCD_BST1_CBJ_DIS (0x0 << 7)
  1121. #define RT5668_ZCD_BST1_CBJ_EN (0x1 << 7)
  1122. #define RT5668_ZCD_RECMIX_MASK (0x1)
  1123. #define RT5668_ZCD_RECMIX_SFT 0
  1124. #define RT5668_ZCD_RECMIX_DIS (0x0)
  1125. #define RT5668_ZCD_RECMIX_EN (0x1)
  1126. /* 4 Button Inline Command Control 2 (0x00e3) */
  1127. #define RT5668_4BTN_IL_MASK (0x1 << 15)
  1128. #define RT5668_4BTN_IL_EN (0x1 << 15)
  1129. #define RT5668_4BTN_IL_DIS (0x0 << 15)
  1130. #define RT5668_4BTN_IL_RST_MASK (0x1 << 14)
  1131. #define RT5668_4BTN_IL_NOR (0x1 << 14)
  1132. #define RT5668_4BTN_IL_RST (0x0 << 14)
  1133. /* Analog JD Control (0x00f0) */
  1134. #define RT5668_JDH_RS_MASK (0x1 << 4)
  1135. #define RT5668_JDH_NO_PLUG (0x1 << 4)
  1136. #define RT5668_JDH_PLUG (0x0 << 4)
  1137. /* Chopper and Clock control for DAC (0x013a)*/
  1138. #define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
  1139. #define RT5668_CKXEN_DAC1_SFT 13
  1140. #define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
  1141. #define RT5668_CKGEN_DAC1_SFT 12
  1142. /* Chopper and Clock control for ADC (0x013b)*/
  1143. #define RT5668_CKXEN_ADC1_MASK (0x1 << 13)
  1144. #define RT5668_CKXEN_ADC1_SFT 13
  1145. #define RT5668_CKGEN_ADC1_MASK (0x1 << 12)
  1146. #define RT5668_CKGEN_ADC1_SFT 12
  1147. /* Volume test (0x013f)*/
  1148. #define RT5668_SEL_CLK_VOL_MASK (0x1 << 15)
  1149. #define RT5668_SEL_CLK_VOL_EN (0x1 << 15)
  1150. #define RT5668_SEL_CLK_VOL_DIS (0x0 << 15)
  1151. /* Test Mode Control 1 (0x0145) */
  1152. #define RT5668_AD2DA_LB_MASK (0x1 << 10)
  1153. #define RT5668_AD2DA_LB_SFT 10
  1154. /* Stereo Noise Gate Control 1 (0x0160) */
  1155. #define RT5668_NG2_EN_MASK (0x1 << 15)
  1156. #define RT5668_NG2_EN (0x1 << 15)
  1157. #define RT5668_NG2_DIS (0x0 << 15)
  1158. /* Stereo1 DAC Silence Detection Control (0x0190) */
  1159. #define RT5668_DEB_STO_DAC_MASK (0x7 << 4)
  1160. #define RT5668_DEB_80_MS (0x0 << 4)
  1161. /* SAR ADC Inline Command Control 1 (0x0210) */
  1162. #define RT5668_SAR_BUTT_DET_MASK (0x1 << 15)
  1163. #define RT5668_SAR_BUTT_DET_EN (0x1 << 15)
  1164. #define RT5668_SAR_BUTT_DET_DIS (0x0 << 15)
  1165. #define RT5668_SAR_BUTDET_MODE_MASK (0x1 << 14)
  1166. #define RT5668_SAR_BUTDET_POW_SAV (0x1 << 14)
  1167. #define RT5668_SAR_BUTDET_POW_NORM (0x0 << 14)
  1168. #define RT5668_SAR_BUTDET_RST_MASK (0x1 << 13)
  1169. #define RT5668_SAR_BUTDET_RST_NORMAL (0x1 << 13)
  1170. #define RT5668_SAR_BUTDET_RST (0x0 << 13)
  1171. #define RT5668_SAR_POW_MASK (0x1 << 12)
  1172. #define RT5668_SAR_POW_EN (0x1 << 12)
  1173. #define RT5668_SAR_POW_DIS (0x0 << 12)
  1174. #define RT5668_SAR_RST_MASK (0x1 << 11)
  1175. #define RT5668_SAR_RST_NORMAL (0x1 << 11)
  1176. #define RT5668_SAR_RST (0x0 << 11)
  1177. #define RT5668_SAR_BYPASS_MASK (0x1 << 10)
  1178. #define RT5668_SAR_BYPASS_EN (0x1 << 10)
  1179. #define RT5668_SAR_BYPASS_DIS (0x0 << 10)
  1180. #define RT5668_SAR_SEL_MB1_MASK (0x1 << 9)
  1181. #define RT5668_SAR_SEL_MB1_SEL (0x1 << 9)
  1182. #define RT5668_SAR_SEL_MB1_NOSEL (0x0 << 9)
  1183. #define RT5668_SAR_SEL_MB2_MASK (0x1 << 8)
  1184. #define RT5668_SAR_SEL_MB2_SEL (0x1 << 8)
  1185. #define RT5668_SAR_SEL_MB2_NOSEL (0x0 << 8)
  1186. #define RT5668_SAR_SEL_MODE_MASK (0x1 << 7)
  1187. #define RT5668_SAR_SEL_MODE_CMP (0x1 << 7)
  1188. #define RT5668_SAR_SEL_MODE_ADC (0x0 << 7)
  1189. #define RT5668_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
  1190. #define RT5668_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
  1191. #define RT5668_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
  1192. #define RT5668_SAR_SEL_SIGNAL_MASK (0x1 << 4)
  1193. #define RT5668_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
  1194. #define RT5668_SAR_SEL_SIGNAL_MANU (0x0 << 4)
  1195. /* SAR ADC Inline Command Control 13 (0x021c) */
  1196. #define RT5668_SAR_SOUR_MASK (0x3f)
  1197. #define RT5668_SAR_SOUR_BTN (0x3f)
  1198. #define RT5668_SAR_SOUR_TYPE (0x0)
  1199. /* System Clock Source */
  1200. enum {
  1201. RT5668_SCLK_S_MCLK,
  1202. RT5668_SCLK_S_PLL1,
  1203. RT5668_SCLK_S_PLL2,
  1204. RT5668_SCLK_S_RCCLK,
  1205. };
  1206. /* PLL Source */
  1207. enum {
  1208. RT5668_PLL1_S_MCLK,
  1209. RT5668_PLL1_S_BCLK1,
  1210. RT5668_PLL1_S_RCCLK,
  1211. };
  1212. enum {
  1213. RT5668_AIF1,
  1214. RT5668_AIF2,
  1215. RT5668_AIFS
  1216. };
  1217. /* filter mask */
  1218. enum {
  1219. RT5668_DA_STEREO1_FILTER = 0x1,
  1220. RT5668_AD_STEREO1_FILTER = (0x1 << 1),
  1221. };
  1222. enum {
  1223. RT5668_CLK_SEL_SYS,
  1224. RT5668_CLK_SEL_I2S1_ASRC,
  1225. RT5668_CLK_SEL_I2S2_ASRC,
  1226. };
  1227. int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
  1228. unsigned int filter_mask, unsigned int clk_src);
  1229. #endif /* __RT5668_H__ */