rt5665.h 70 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Realtek Microelectronics
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #ifndef __RT5665_H__
  9. #define __RT5665_H__
  10. #include <sound/rt5665.h>
  11. #define DEVICE_ID 0x6451
  12. /* Info */
  13. #define RT5665_RESET 0x0000
  14. #define RT5665_VENDOR_ID 0x00fd
  15. #define RT5665_VENDOR_ID_1 0x00fe
  16. #define RT5665_DEVICE_ID 0x00ff
  17. /* I/O - Output */
  18. #define RT5665_LOUT 0x0001
  19. #define RT5665_HP_CTRL_1 0x0002
  20. #define RT5665_HP_CTRL_2 0x0003
  21. #define RT5665_MONO_OUT 0x0004
  22. #define RT5665_HPL_GAIN 0x0005
  23. #define RT5665_HPR_GAIN 0x0006
  24. #define RT5665_MONO_GAIN 0x0007
  25. /* I/O - Input */
  26. #define RT5665_CAL_BST_CTRL 0x000a
  27. #define RT5665_CBJ_BST_CTRL 0x000b
  28. #define RT5665_IN1_IN2 0x000c
  29. #define RT5665_IN3_IN4 0x000d
  30. #define RT5665_INL1_INR1_VOL 0x000f
  31. /* I/O - Speaker */
  32. #define RT5665_EJD_CTRL_1 0x0010
  33. #define RT5665_EJD_CTRL_2 0x0011
  34. #define RT5665_EJD_CTRL_3 0x0012
  35. #define RT5665_EJD_CTRL_4 0x0013
  36. #define RT5665_EJD_CTRL_5 0x0014
  37. #define RT5665_EJD_CTRL_6 0x0015
  38. #define RT5665_EJD_CTRL_7 0x0016
  39. /* I/O - ADC/DAC/DMIC */
  40. #define RT5665_DAC2_CTRL 0x0017
  41. #define RT5665_DAC2_DIG_VOL 0x0018
  42. #define RT5665_DAC1_DIG_VOL 0x0019
  43. #define RT5665_DAC3_DIG_VOL 0x001a
  44. #define RT5665_DAC3_CTRL 0x001b
  45. #define RT5665_STO1_ADC_DIG_VOL 0x001c
  46. #define RT5665_MONO_ADC_DIG_VOL 0x001d
  47. #define RT5665_STO2_ADC_DIG_VOL 0x001e
  48. #define RT5665_STO1_ADC_BOOST 0x001f
  49. #define RT5665_MONO_ADC_BOOST 0x0020
  50. #define RT5665_STO2_ADC_BOOST 0x0021
  51. #define RT5665_HP_IMP_GAIN_1 0x0022
  52. #define RT5665_HP_IMP_GAIN_2 0x0023
  53. /* Mixer - D-D */
  54. #define RT5665_STO1_ADC_MIXER 0x0026
  55. #define RT5665_MONO_ADC_MIXER 0x0027
  56. #define RT5665_STO2_ADC_MIXER 0x0028
  57. #define RT5665_AD_DA_MIXER 0x0029
  58. #define RT5665_STO1_DAC_MIXER 0x002a
  59. #define RT5665_MONO_DAC_MIXER 0x002b
  60. #define RT5665_STO2_DAC_MIXER 0x002c
  61. #define RT5665_A_DAC1_MUX 0x002d
  62. #define RT5665_A_DAC2_MUX 0x002e
  63. #define RT5665_DIG_INF2_DATA 0x002f
  64. #define RT5665_DIG_INF3_DATA 0x0030
  65. /* Mixer - PDM */
  66. #define RT5665_PDM_OUT_CTRL 0x0031
  67. #define RT5665_PDM_DATA_CTRL_1 0x0032
  68. #define RT5665_PDM_DATA_CTRL_2 0x0033
  69. #define RT5665_PDM_DATA_CTRL_3 0x0034
  70. #define RT5665_PDM_DATA_CTRL_4 0x0035
  71. /* Mixer - ADC */
  72. #define RT5665_REC1_GAIN 0x003a
  73. #define RT5665_REC1_L1_MIXER 0x003b
  74. #define RT5665_REC1_L2_MIXER 0x003c
  75. #define RT5665_REC1_R1_MIXER 0x003d
  76. #define RT5665_REC1_R2_MIXER 0x003e
  77. #define RT5665_REC2_GAIN 0x003f
  78. #define RT5665_REC2_L1_MIXER 0x0040
  79. #define RT5665_REC2_L2_MIXER 0x0041
  80. #define RT5665_REC2_R1_MIXER 0x0042
  81. #define RT5665_REC2_R2_MIXER 0x0043
  82. #define RT5665_CAL_REC 0x0044
  83. /* Mixer - DAC */
  84. #define RT5665_ALC_BACK_GAIN 0x0049
  85. #define RT5665_MONOMIX_GAIN 0x004a
  86. #define RT5665_MONOMIX_IN_GAIN 0x004b
  87. #define RT5665_OUT_L_GAIN 0x004d
  88. #define RT5665_OUT_L_MIXER 0x004e
  89. #define RT5665_OUT_R_GAIN 0x004f
  90. #define RT5665_OUT_R_MIXER 0x0050
  91. #define RT5665_LOUT_MIXER 0x0052
  92. /* Power */
  93. #define RT5665_PWR_DIG_1 0x0061
  94. #define RT5665_PWR_DIG_2 0x0062
  95. #define RT5665_PWR_ANLG_1 0x0063
  96. #define RT5665_PWR_ANLG_2 0x0064
  97. #define RT5665_PWR_ANLG_3 0x0065
  98. #define RT5665_PWR_MIXER 0x0066
  99. #define RT5665_PWR_VOL 0x0067
  100. /* Clock Detect */
  101. #define RT5665_CLK_DET 0x006b
  102. /* Filter */
  103. #define RT5665_HPF_CTRL1 0x006d
  104. /* DMIC */
  105. #define RT5665_DMIC_CTRL_1 0x006e
  106. #define RT5665_DMIC_CTRL_2 0x006f
  107. /* Format - ADC/DAC */
  108. #define RT5665_I2S1_SDP 0x0070
  109. #define RT5665_I2S2_SDP 0x0071
  110. #define RT5665_I2S3_SDP 0x0072
  111. #define RT5665_ADDA_CLK_1 0x0073
  112. #define RT5665_ADDA_CLK_2 0x0074
  113. #define RT5665_I2S1_F_DIV_CTRL_1 0x0075
  114. #define RT5665_I2S1_F_DIV_CTRL_2 0x0076
  115. /* Format - TDM Control */
  116. #define RT5665_TDM_CTRL_1 0x0078
  117. #define RT5665_TDM_CTRL_2 0x0079
  118. #define RT5665_TDM_CTRL_3 0x007a
  119. #define RT5665_TDM_CTRL_4 0x007b
  120. #define RT5665_TDM_CTRL_5 0x007c
  121. #define RT5665_TDM_CTRL_6 0x007d
  122. #define RT5665_TDM_CTRL_7 0x007e
  123. #define RT5665_TDM_CTRL_8 0x007f
  124. /* Function - Analog */
  125. #define RT5665_GLB_CLK 0x0080
  126. #define RT5665_PLL_CTRL_1 0x0081
  127. #define RT5665_PLL_CTRL_2 0x0082
  128. #define RT5665_ASRC_1 0x0083
  129. #define RT5665_ASRC_2 0x0084
  130. #define RT5665_ASRC_3 0x0085
  131. #define RT5665_ASRC_4 0x0086
  132. #define RT5665_ASRC_5 0x0087
  133. #define RT5665_ASRC_6 0x0088
  134. #define RT5665_ASRC_7 0x0089
  135. #define RT5665_ASRC_8 0x008a
  136. #define RT5665_ASRC_9 0x008b
  137. #define RT5665_ASRC_10 0x008c
  138. #define RT5665_DEPOP_1 0x008e
  139. #define RT5665_DEPOP_2 0x008f
  140. #define RT5665_HP_CHARGE_PUMP_1 0x0091
  141. #define RT5665_HP_CHARGE_PUMP_2 0x0092
  142. #define RT5665_MICBIAS_1 0x0093
  143. #define RT5665_MICBIAS_2 0x0094
  144. #define RT5665_ASRC_12 0x0098
  145. #define RT5665_ASRC_13 0x0099
  146. #define RT5665_ASRC_14 0x009a
  147. #define RT5665_RC_CLK_CTRL 0x009f
  148. #define RT5665_I2S_M_CLK_CTRL_1 0x00a0
  149. #define RT5665_I2S2_F_DIV_CTRL_1 0x00a1
  150. #define RT5665_I2S2_F_DIV_CTRL_2 0x00a2
  151. #define RT5665_I2S3_F_DIV_CTRL_1 0x00a3
  152. #define RT5665_I2S3_F_DIV_CTRL_2 0x00a4
  153. /* Function - Digital */
  154. #define RT5665_EQ_CTRL_1 0x00ae
  155. #define RT5665_EQ_CTRL_2 0x00af
  156. #define RT5665_IRQ_CTRL_1 0x00b6
  157. #define RT5665_IRQ_CTRL_2 0x00b7
  158. #define RT5665_IRQ_CTRL_3 0x00b8
  159. #define RT5665_IRQ_CTRL_4 0x00b9
  160. #define RT5665_IRQ_CTRL_5 0x00ba
  161. #define RT5665_IRQ_CTRL_6 0x00bb
  162. #define RT5665_INT_ST_1 0x00be
  163. #define RT5665_GPIO_CTRL_1 0x00c0
  164. #define RT5665_GPIO_CTRL_2 0x00c1
  165. #define RT5665_GPIO_CTRL_3 0x00c2
  166. #define RT5665_GPIO_CTRL_4 0x00c3
  167. #define RT5665_GPIO_STA 0x00c4
  168. #define RT5665_HP_AMP_DET_CTRL_1 0x00d0
  169. #define RT5665_HP_AMP_DET_CTRL_2 0x00d1
  170. #define RT5665_MID_HP_AMP_DET 0x00d3
  171. #define RT5665_LOW_HP_AMP_DET 0x00d4
  172. #define RT5665_SV_ZCD_1 0x00d9
  173. #define RT5665_SV_ZCD_2 0x00da
  174. #define RT5665_IL_CMD_1 0x00db
  175. #define RT5665_IL_CMD_2 0x00dc
  176. #define RT5665_IL_CMD_3 0x00dd
  177. #define RT5665_IL_CMD_4 0x00de
  178. #define RT5665_4BTN_IL_CMD_1 0x00df
  179. #define RT5665_4BTN_IL_CMD_2 0x00e0
  180. #define RT5665_4BTN_IL_CMD_3 0x00e1
  181. #define RT5665_PSV_IL_CMD_1 0x00e2
  182. #define RT5665_ADC_STO1_HP_CTRL_1 0x00ea
  183. #define RT5665_ADC_STO1_HP_CTRL_2 0x00eb
  184. #define RT5665_ADC_MONO_HP_CTRL_1 0x00ec
  185. #define RT5665_ADC_MONO_HP_CTRL_2 0x00ed
  186. #define RT5665_ADC_STO2_HP_CTRL_1 0x00ee
  187. #define RT5665_ADC_STO2_HP_CTRL_2 0x00ef
  188. #define RT5665_AJD1_CTRL 0x00f0
  189. #define RT5665_JD1_THD 0x00f1
  190. #define RT5665_JD2_THD 0x00f2
  191. #define RT5665_JD_CTRL_1 0x00f6
  192. #define RT5665_JD_CTRL_2 0x00f7
  193. #define RT5665_JD_CTRL_3 0x00f8
  194. /* General Control */
  195. #define RT5665_DIG_MISC 0x00fa
  196. #define RT5665_DUMMY_2 0x00fb
  197. #define RT5665_DUMMY_3 0x00fc
  198. #define RT5665_DAC_ADC_DIG_VOL1 0x0100
  199. #define RT5665_DAC_ADC_DIG_VOL2 0x0101
  200. #define RT5665_BIAS_CUR_CTRL_1 0x010a
  201. #define RT5665_BIAS_CUR_CTRL_2 0x010b
  202. #define RT5665_BIAS_CUR_CTRL_3 0x010c
  203. #define RT5665_BIAS_CUR_CTRL_4 0x010d
  204. #define RT5665_BIAS_CUR_CTRL_5 0x010e
  205. #define RT5665_BIAS_CUR_CTRL_6 0x010f
  206. #define RT5665_BIAS_CUR_CTRL_7 0x0110
  207. #define RT5665_BIAS_CUR_CTRL_8 0x0111
  208. #define RT5665_BIAS_CUR_CTRL_9 0x0112
  209. #define RT5665_BIAS_CUR_CTRL_10 0x0113
  210. #define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117
  211. #define RT5665_CHARGE_PUMP_1 0x0125
  212. #define RT5665_DIG_IN_CTRL_1 0x0132
  213. #define RT5665_DIG_IN_CTRL_2 0x0133
  214. #define RT5665_PAD_DRIVING_CTRL 0x0137
  215. #define RT5665_SOFT_RAMP_DEPOP 0x0138
  216. #define RT5665_PLL 0x0139
  217. #define RT5665_CHOP_DAC 0x013a
  218. #define RT5665_CHOP_ADC 0x013b
  219. #define RT5665_CALIB_ADC_CTRL 0x013c
  220. #define RT5665_VOL_TEST 0x013f
  221. #define RT5665_TEST_MODE_CTRL_1 0x0145
  222. #define RT5665_TEST_MODE_CTRL_2 0x0146
  223. #define RT5665_TEST_MODE_CTRL_3 0x0147
  224. #define RT5665_TEST_MODE_CTRL_4 0x0148
  225. #define RT5665_BASSBACK_CTRL 0x0150
  226. #define RT5665_STO_NG2_CTRL_1 0x0160
  227. #define RT5665_STO_NG2_CTRL_2 0x0161
  228. #define RT5665_STO_NG2_CTRL_3 0x0162
  229. #define RT5665_STO_NG2_CTRL_4 0x0163
  230. #define RT5665_STO_NG2_CTRL_5 0x0164
  231. #define RT5665_STO_NG2_CTRL_6 0x0165
  232. #define RT5665_STO_NG2_CTRL_7 0x0166
  233. #define RT5665_STO_NG2_CTRL_8 0x0167
  234. #define RT5665_MONO_NG2_CTRL_1 0x0170
  235. #define RT5665_MONO_NG2_CTRL_2 0x0171
  236. #define RT5665_MONO_NG2_CTRL_3 0x0172
  237. #define RT5665_MONO_NG2_CTRL_4 0x0173
  238. #define RT5665_MONO_NG2_CTRL_5 0x0174
  239. #define RT5665_MONO_NG2_CTRL_6 0x0175
  240. #define RT5665_STO1_DAC_SIL_DET 0x0190
  241. #define RT5665_MONOL_DAC_SIL_DET 0x0191
  242. #define RT5665_MONOR_DAC_SIL_DET 0x0192
  243. #define RT5665_STO2_DAC_SIL_DET 0x0193
  244. #define RT5665_SIL_PSV_CTRL1 0x0194
  245. #define RT5665_SIL_PSV_CTRL2 0x0195
  246. #define RT5665_SIL_PSV_CTRL3 0x0196
  247. #define RT5665_SIL_PSV_CTRL4 0x0197
  248. #define RT5665_SIL_PSV_CTRL5 0x0198
  249. #define RT5665_SIL_PSV_CTRL6 0x0199
  250. #define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0
  251. #define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1
  252. #define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2
  253. #define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3
  254. #define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4
  255. #define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5
  256. #define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6
  257. #define RT5665_MONO_AMP_CALIB_STA1 0x01a7
  258. #define RT5665_MONO_AMP_CALIB_STA2 0x01a8
  259. #define RT5665_MONO_AMP_CALIB_STA3 0x01a9
  260. #define RT5665_MONO_AMP_CALIB_STA4 0x01aa
  261. #define RT5665_MONO_AMP_CALIB_STA6 0x01ab
  262. #define RT5665_HP_IMP_SENS_CTRL_01 0x01b5
  263. #define RT5665_HP_IMP_SENS_CTRL_02 0x01b6
  264. #define RT5665_HP_IMP_SENS_CTRL_03 0x01b7
  265. #define RT5665_HP_IMP_SENS_CTRL_04 0x01b8
  266. #define RT5665_HP_IMP_SENS_CTRL_05 0x01b9
  267. #define RT5665_HP_IMP_SENS_CTRL_06 0x01ba
  268. #define RT5665_HP_IMP_SENS_CTRL_07 0x01bb
  269. #define RT5665_HP_IMP_SENS_CTRL_08 0x01bc
  270. #define RT5665_HP_IMP_SENS_CTRL_09 0x01bd
  271. #define RT5665_HP_IMP_SENS_CTRL_10 0x01be
  272. #define RT5665_HP_IMP_SENS_CTRL_11 0x01bf
  273. #define RT5665_HP_IMP_SENS_CTRL_12 0x01c0
  274. #define RT5665_HP_IMP_SENS_CTRL_13 0x01c1
  275. #define RT5665_HP_IMP_SENS_CTRL_14 0x01c2
  276. #define RT5665_HP_IMP_SENS_CTRL_15 0x01c3
  277. #define RT5665_HP_IMP_SENS_CTRL_16 0x01c4
  278. #define RT5665_HP_IMP_SENS_CTRL_17 0x01c5
  279. #define RT5665_HP_IMP_SENS_CTRL_18 0x01c6
  280. #define RT5665_HP_IMP_SENS_CTRL_19 0x01c7
  281. #define RT5665_HP_IMP_SENS_CTRL_20 0x01c8
  282. #define RT5665_HP_IMP_SENS_CTRL_21 0x01c9
  283. #define RT5665_HP_IMP_SENS_CTRL_22 0x01ca
  284. #define RT5665_HP_IMP_SENS_CTRL_23 0x01cb
  285. #define RT5665_HP_IMP_SENS_CTRL_24 0x01cc
  286. #define RT5665_HP_IMP_SENS_CTRL_25 0x01cd
  287. #define RT5665_HP_IMP_SENS_CTRL_26 0x01ce
  288. #define RT5665_HP_IMP_SENS_CTRL_27 0x01cf
  289. #define RT5665_HP_IMP_SENS_CTRL_28 0x01d0
  290. #define RT5665_HP_IMP_SENS_CTRL_29 0x01d1
  291. #define RT5665_HP_IMP_SENS_CTRL_30 0x01d2
  292. #define RT5665_HP_IMP_SENS_CTRL_31 0x01d3
  293. #define RT5665_HP_IMP_SENS_CTRL_32 0x01d4
  294. #define RT5665_HP_IMP_SENS_CTRL_33 0x01d5
  295. #define RT5665_HP_IMP_SENS_CTRL_34 0x01d6
  296. #define RT5665_HP_LOGIC_CTRL_1 0x01da
  297. #define RT5665_HP_LOGIC_CTRL_2 0x01db
  298. #define RT5665_HP_LOGIC_CTRL_3 0x01dc
  299. #define RT5665_HP_CALIB_CTRL_1 0x01de
  300. #define RT5665_HP_CALIB_CTRL_2 0x01df
  301. #define RT5665_HP_CALIB_CTRL_3 0x01e0
  302. #define RT5665_HP_CALIB_CTRL_4 0x01e1
  303. #define RT5665_HP_CALIB_CTRL_5 0x01e2
  304. #define RT5665_HP_CALIB_CTRL_6 0x01e3
  305. #define RT5665_HP_CALIB_CTRL_7 0x01e4
  306. #define RT5665_HP_CALIB_CTRL_9 0x01e6
  307. #define RT5665_HP_CALIB_CTRL_10 0x01e7
  308. #define RT5665_HP_CALIB_CTRL_11 0x01e8
  309. #define RT5665_HP_CALIB_STA_1 0x01ea
  310. #define RT5665_HP_CALIB_STA_2 0x01eb
  311. #define RT5665_HP_CALIB_STA_3 0x01ec
  312. #define RT5665_HP_CALIB_STA_4 0x01ed
  313. #define RT5665_HP_CALIB_STA_5 0x01ee
  314. #define RT5665_HP_CALIB_STA_6 0x01ef
  315. #define RT5665_HP_CALIB_STA_7 0x01f0
  316. #define RT5665_HP_CALIB_STA_8 0x01f1
  317. #define RT5665_HP_CALIB_STA_9 0x01f2
  318. #define RT5665_HP_CALIB_STA_10 0x01f3
  319. #define RT5665_HP_CALIB_STA_11 0x01f4
  320. #define RT5665_PGM_TAB_CTRL1 0x0200
  321. #define RT5665_PGM_TAB_CTRL2 0x0201
  322. #define RT5665_PGM_TAB_CTRL3 0x0202
  323. #define RT5665_PGM_TAB_CTRL4 0x0203
  324. #define RT5665_PGM_TAB_CTRL5 0x0204
  325. #define RT5665_PGM_TAB_CTRL6 0x0205
  326. #define RT5665_PGM_TAB_CTRL7 0x0206
  327. #define RT5665_PGM_TAB_CTRL8 0x0207
  328. #define RT5665_PGM_TAB_CTRL9 0x0208
  329. #define RT5665_SAR_IL_CMD_1 0x0210
  330. #define RT5665_SAR_IL_CMD_2 0x0211
  331. #define RT5665_SAR_IL_CMD_3 0x0212
  332. #define RT5665_SAR_IL_CMD_4 0x0213
  333. #define RT5665_SAR_IL_CMD_5 0x0214
  334. #define RT5665_SAR_IL_CMD_6 0x0215
  335. #define RT5665_SAR_IL_CMD_7 0x0216
  336. #define RT5665_SAR_IL_CMD_8 0x0217
  337. #define RT5665_SAR_IL_CMD_9 0x0218
  338. #define RT5665_SAR_IL_CMD_10 0x0219
  339. #define RT5665_SAR_IL_CMD_11 0x021a
  340. #define RT5665_SAR_IL_CMD_12 0x021b
  341. #define RT5665_DRC1_CTRL_0 0x02ff
  342. #define RT5665_DRC1_CTRL_1 0x0300
  343. #define RT5665_DRC1_CTRL_2 0x0301
  344. #define RT5665_DRC1_CTRL_3 0x0302
  345. #define RT5665_DRC1_CTRL_4 0x0303
  346. #define RT5665_DRC1_CTRL_5 0x0304
  347. #define RT5665_DRC1_CTRL_6 0x0305
  348. #define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306
  349. #define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307
  350. #define RT5665_DRC1_PRIV_1 0x0310
  351. #define RT5665_DRC1_PRIV_2 0x0311
  352. #define RT5665_DRC1_PRIV_3 0x0312
  353. #define RT5665_DRC1_PRIV_4 0x0313
  354. #define RT5665_DRC1_PRIV_5 0x0314
  355. #define RT5665_DRC1_PRIV_6 0x0315
  356. #define RT5665_DRC1_PRIV_7 0x0316
  357. #define RT5665_DRC1_PRIV_8 0x0317
  358. #define RT5665_ALC_PGA_CTRL_1 0x0330
  359. #define RT5665_ALC_PGA_CTRL_2 0x0331
  360. #define RT5665_ALC_PGA_CTRL_3 0x0332
  361. #define RT5665_ALC_PGA_CTRL_4 0x0333
  362. #define RT5665_ALC_PGA_CTRL_5 0x0334
  363. #define RT5665_ALC_PGA_CTRL_6 0x0335
  364. #define RT5665_ALC_PGA_CTRL_7 0x0336
  365. #define RT5665_ALC_PGA_CTRL_8 0x0337
  366. #define RT5665_ALC_PGA_STA_1 0x0338
  367. #define RT5665_ALC_PGA_STA_2 0x0339
  368. #define RT5665_ALC_PGA_STA_3 0x033a
  369. #define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0
  370. #define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1
  371. #define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2
  372. #define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3
  373. #define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4
  374. #define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5
  375. #define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6
  376. #define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7
  377. #define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8
  378. #define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9
  379. #define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca
  380. #define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb
  381. #define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc
  382. #define RT5665_ADC_L_EQ_LPF1_A1 0x03d0
  383. #define RT5665_R_EQ_LPF1_A1 0x03d1
  384. #define RT5665_L_EQ_LPF1_H0 0x03d2
  385. #define RT5665_R_EQ_LPF1_H0 0x03d3
  386. #define RT5665_L_EQ_BPF1_A1 0x03d4
  387. #define RT5665_R_EQ_BPF1_A1 0x03d5
  388. #define RT5665_L_EQ_BPF1_A2 0x03d6
  389. #define RT5665_R_EQ_BPF1_A2 0x03d7
  390. #define RT5665_L_EQ_BPF1_H0 0x03d8
  391. #define RT5665_R_EQ_BPF1_H0 0x03d9
  392. #define RT5665_L_EQ_BPF2_A1 0x03da
  393. #define RT5665_R_EQ_BPF2_A1 0x03db
  394. #define RT5665_L_EQ_BPF2_A2 0x03dc
  395. #define RT5665_R_EQ_BPF2_A2 0x03dd
  396. #define RT5665_L_EQ_BPF2_H0 0x03de
  397. #define RT5665_R_EQ_BPF2_H0 0x03df
  398. #define RT5665_L_EQ_BPF3_A1 0x03e0
  399. #define RT5665_R_EQ_BPF3_A1 0x03e1
  400. #define RT5665_L_EQ_BPF3_A2 0x03e2
  401. #define RT5665_R_EQ_BPF3_A2 0x03e3
  402. #define RT5665_L_EQ_BPF3_H0 0x03e4
  403. #define RT5665_R_EQ_BPF3_H0 0x03e5
  404. #define RT5665_L_EQ_BPF4_A1 0x03e6
  405. #define RT5665_R_EQ_BPF4_A1 0x03e7
  406. #define RT5665_L_EQ_BPF4_A2 0x03e8
  407. #define RT5665_R_EQ_BPF4_A2 0x03e9
  408. #define RT5665_L_EQ_BPF4_H0 0x03ea
  409. #define RT5665_R_EQ_BPF4_H0 0x03eb
  410. #define RT5665_L_EQ_HPF1_A1 0x03ec
  411. #define RT5665_R_EQ_HPF1_A1 0x03ed
  412. #define RT5665_L_EQ_HPF1_H0 0x03ee
  413. #define RT5665_R_EQ_HPF1_H0 0x03ef
  414. #define RT5665_L_EQ_PRE_VOL 0x03f0
  415. #define RT5665_R_EQ_PRE_VOL 0x03f1
  416. #define RT5665_L_EQ_POST_VOL 0x03f2
  417. #define RT5665_R_EQ_POST_VOL 0x03f3
  418. #define RT5665_SCAN_MODE_CTRL 0x07f0
  419. #define RT5665_I2C_MODE 0x07fa
  420. /* global definition */
  421. #define RT5665_L_MUTE (0x1 << 15)
  422. #define RT5665_L_MUTE_SFT 15
  423. #define RT5665_VOL_L_MUTE (0x1 << 14)
  424. #define RT5665_VOL_L_SFT 14
  425. #define RT5665_R_MUTE (0x1 << 7)
  426. #define RT5665_R_MUTE_SFT 7
  427. #define RT5665_VOL_R_MUTE (0x1 << 6)
  428. #define RT5665_VOL_R_SFT 6
  429. #define RT5665_L_VOL_MASK (0x3f << 8)
  430. #define RT5665_L_VOL_SFT 8
  431. #define RT5665_R_VOL_MASK (0x3f)
  432. #define RT5665_R_VOL_SFT 0
  433. /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
  434. #define RT5665_G_HP (0xf << 8)
  435. #define RT5665_G_HP_SFT 8
  436. #define RT5665_G_STO_DA_DMIX (0xf)
  437. #define RT5665_G_STO_DA_SFT 0
  438. /* CBJ Control (0x000b) */
  439. #define RT5665_BST_CBJ_MASK (0xf << 8)
  440. #define RT5665_BST_CBJ_SFT 8
  441. /* IN1/IN2 Control (0x000c) */
  442. #define RT5665_IN1_DF_MASK (0x1 << 15)
  443. #define RT5665_IN1_DF 15
  444. #define RT5665_BST1_MASK (0x7f << 8)
  445. #define RT5665_BST1_SFT 8
  446. #define RT5665_IN2_DF_MASK (0x1 << 7)
  447. #define RT5665_IN2_DF 7
  448. #define RT5665_BST2_MASK (0x7f)
  449. #define RT5665_BST2_SFT 0
  450. /* IN3/IN4 Control (0x000d) */
  451. #define RT5665_IN3_DF_MASK (0x1 << 15)
  452. #define RT5665_IN3_DF 15
  453. #define RT5665_BST3_MASK (0x7f << 8)
  454. #define RT5665_BST3_SFT 8
  455. #define RT5665_IN4_DF_MASK (0x1 << 7)
  456. #define RT5665_IN4_DF 7
  457. #define RT5665_BST4_MASK (0x7f)
  458. #define RT5665_BST4_SFT 0
  459. /* INL and INR Volume Control (0x000f) */
  460. #define RT5665_INL_VOL_MASK (0x1f << 8)
  461. #define RT5665_INL_VOL_SFT 8
  462. #define RT5665_INR_VOL_MASK (0x1f)
  463. #define RT5665_INR_VOL_SFT 0
  464. /* Embeeded Jack and Type Detection Control 1 (0x0010) */
  465. #define RT5665_EMB_JD_EN (0x1 << 15)
  466. #define RT5665_EMB_JD_EN_SFT 15
  467. #define RT5665_JD_MODE (0x1 << 13)
  468. #define RT5665_JD_MODE_SFT 13
  469. #define RT5665_POLA_EXT_JD_MASK (0x1 << 11)
  470. #define RT5665_POLA_EXT_JD_LOW (0x1 << 11)
  471. #define RT5665_POLA_EXT_JD_HIGH (0x0 << 11)
  472. #define RT5665_EXT_JD_DIG (0x1 << 9)
  473. #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
  474. #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
  475. #define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
  476. #define RT5665_VREF_POW_MASK (0x1 << 6)
  477. #define RT5665_VREF_POW_FSM (0x0 << 6)
  478. #define RT5665_VREF_POW_REG (0x1 << 6)
  479. #define RT5665_MB1_PATH_MASK (0x1 << 5)
  480. #define RT5665_CTRL_MB1_REG (0x1 << 5)
  481. #define RT5665_CTRL_MB1_FSM (0x0 << 5)
  482. #define RT5665_MB2_PATH_MASK (0x1 << 4)
  483. #define RT5665_CTRL_MB2_REG (0x1 << 4)
  484. #define RT5665_CTRL_MB2_FSM (0x0 << 4)
  485. #define RT5665_TRIG_JD_MASK (0x1 << 3)
  486. #define RT5665_TRIG_JD_HIGH (0x1 << 3)
  487. #define RT5665_TRIG_JD_LOW (0x0 << 3)
  488. /* Embeeded Jack and Type Detection Control 2 (0x0011) */
  489. #define RT5665_EXT_JD_SRC (0x7 << 4)
  490. #define RT5665_EXT_JD_SRC_SFT 4
  491. #define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
  492. #define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
  493. #define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)
  494. #define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
  495. #define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)
  496. #define RT5665_EXT_JD_SRC_JD3 (0x5 << 4)
  497. #define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4)
  498. /* Combo Jack and Type Detection Control 4 (0x0013) */
  499. #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
  500. #define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
  501. #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
  502. #define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)
  503. #define RT5665_CBJ_JD_TEST_NORM (0x0 << 6)
  504. #define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)
  505. /* Slience Detection Control (0x0015) */
  506. #define RT5665_SIL_DET_MASK (0x1 << 15)
  507. #define RT5665_SIL_DET_DIS (0x0 << 15)
  508. #define RT5665_SIL_DET_EN (0x1 << 15)
  509. /* DAC2 Control (0x0017) */
  510. #define RT5665_M_DAC2_L_VOL (0x1 << 13)
  511. #define RT5665_M_DAC2_L_VOL_SFT 13
  512. #define RT5665_M_DAC2_R_VOL (0x1 << 12)
  513. #define RT5665_M_DAC2_R_VOL_SFT 12
  514. #define RT5665_DAC_L2_SEL_MASK (0x7 << 4)
  515. #define RT5665_DAC_L2_SEL_SFT 4
  516. #define RT5665_DAC_R2_SEL_MASK (0x7 << 0)
  517. #define RT5665_DAC_R2_SEL_SFT 0
  518. /* Sidetone Control (0x0018) */
  519. #define RT5665_ST_SEL_MASK (0x7 << 9)
  520. #define RT5665_ST_SEL_SFT 9
  521. #define RT5665_ST_EN (0x1 << 6)
  522. #define RT5665_ST_EN_SFT 6
  523. /* DAC1 Digital Volume (0x0019) */
  524. #define RT5665_DAC_L1_VOL_MASK (0xff << 8)
  525. #define RT5665_DAC_L1_VOL_SFT 8
  526. #define RT5665_DAC_R1_VOL_MASK (0xff)
  527. #define RT5665_DAC_R1_VOL_SFT 0
  528. /* DAC2 Digital Volume (0x001a) */
  529. #define RT5665_DAC_L2_VOL_MASK (0xff << 8)
  530. #define RT5665_DAC_L2_VOL_SFT 8
  531. #define RT5665_DAC_R2_VOL_MASK (0xff)
  532. #define RT5665_DAC_R2_VOL_SFT 0
  533. /* DAC3 Control (0x001b) */
  534. #define RT5665_M_DAC3_L_VOL (0x1 << 13)
  535. #define RT5665_M_DAC3_L_VOL_SFT 13
  536. #define RT5665_M_DAC3_R_VOL (0x1 << 12)
  537. #define RT5665_M_DAC3_R_VOL_SFT 12
  538. #define RT5665_DAC_L3_SEL_MASK (0x7 << 4)
  539. #define RT5665_DAC_L3_SEL_SFT 4
  540. #define RT5665_DAC_R3_SEL_MASK (0x7 << 0)
  541. #define RT5665_DAC_R3_SEL_SFT 0
  542. /* ADC Digital Volume Control (0x001c) */
  543. #define RT5665_ADC_L_VOL_MASK (0x7f << 8)
  544. #define RT5665_ADC_L_VOL_SFT 8
  545. #define RT5665_ADC_R_VOL_MASK (0x7f)
  546. #define RT5665_ADC_R_VOL_SFT 0
  547. /* Mono ADC Digital Volume Control (0x001d) */
  548. #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
  549. #define RT5665_MONO_ADC_L_VOL_SFT 8
  550. #define RT5665_MONO_ADC_R_VOL_MASK (0x7f)
  551. #define RT5665_MONO_ADC_R_VOL_SFT 0
  552. /* Stereo1 ADC Boost Gain Control (0x001f) */
  553. #define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)
  554. #define RT5665_STO1_ADC_L_BST_SFT 14
  555. #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
  556. #define RT5665_STO1_ADC_R_BST_SFT 12
  557. /* Mono ADC Boost Gain Control (0x0020) */
  558. #define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)
  559. #define RT5665_MONO_ADC_L_BST_SFT 14
  560. #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
  561. #define RT5665_MONO_ADC_R_BST_SFT 12
  562. /* Stereo1 ADC Boost Gain Control (0x001f) */
  563. #define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)
  564. #define RT5665_STO2_ADC_L_BST_SFT 14
  565. #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
  566. #define RT5665_STO2_ADC_R_BST_SFT 12
  567. /* Stereo1 ADC Mixer Control (0x0026) */
  568. #define RT5665_M_STO1_ADC_L1 (0x1 << 15)
  569. #define RT5665_M_STO1_ADC_L1_SFT 15
  570. #define RT5665_M_STO1_ADC_L2 (0x1 << 14)
  571. #define RT5665_M_STO1_ADC_L2_SFT 14
  572. #define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
  573. #define RT5665_STO1_ADC1L_SRC_SFT 13
  574. #define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
  575. #define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)
  576. #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
  577. #define RT5665_STO1_ADC2L_SRC_SFT 12
  578. #define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)
  579. #define RT5665_STO1_ADCL_SRC_SFT 10
  580. #define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
  581. #define RT5665_STO1_DD_L_SRC_SFT 9
  582. #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
  583. #define RT5665_STO1_DMIC_SRC_SFT 8
  584. #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
  585. #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
  586. #define RT5665_M_STO1_ADC_R1 (0x1 << 7)
  587. #define RT5665_M_STO1_ADC_R1_SFT 7
  588. #define RT5665_M_STO1_ADC_R2 (0x1 << 6)
  589. #define RT5665_M_STO1_ADC_R2_SFT 6
  590. #define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)
  591. #define RT5665_STO1_ADC1R_SRC_SFT 5
  592. #define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)
  593. #define RT5665_STO1_ADC2R_SRC_SFT 4
  594. #define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2)
  595. #define RT5665_STO1_ADCR_SRC_SFT 2
  596. #define RT5665_STO1_DD_R_SRC_MASK (0x3)
  597. #define RT5665_STO1_DD_R_SRC_SFT 0
  598. /* Mono1 ADC Mixer control (0x0027) */
  599. #define RT5665_M_MONO_ADC_L1 (0x1 << 15)
  600. #define RT5665_M_MONO_ADC_L1_SFT 15
  601. #define RT5665_M_MONO_ADC_L2 (0x1 << 14)
  602. #define RT5665_M_MONO_ADC_L2_SFT 14
  603. #define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
  604. #define RT5665_MONO_ADC_L1_SRC_SFT 13
  605. #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
  606. #define RT5665_MONO_ADC_L2_SRC_SFT 12
  607. #define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10)
  608. #define RT5665_MONO_ADC_L_SRC_SFT 10
  609. #define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
  610. #define RT5665_MONO_DD_L_SRC_SFT 9
  611. #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
  612. #define RT5665_MONO_DMIC_L_SRC_SFT 8
  613. #define RT5665_M_MONO_ADC_R1 (0x1 << 7)
  614. #define RT5665_M_MONO_ADC_R1_SFT 7
  615. #define RT5665_M_MONO_ADC_R2 (0x1 << 6)
  616. #define RT5665_M_MONO_ADC_R2_SFT 6
  617. #define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)
  618. #define RT5665_MONO_ADC_R1_SRC_SFT 5
  619. #define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)
  620. #define RT5665_MONO_ADC_R2_SRC_SFT 4
  621. #define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2)
  622. #define RT5665_MONO_ADC_R_SRC_SFT 2
  623. #define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)
  624. #define RT5665_MONO_DD_R_SRC_SFT 1
  625. #define RT5665_MONO_DMIC_R_SRC_MASK 0x1
  626. #define RT5665_MONO_DMIC_R_SRC_SFT 0
  627. /* Stereo2 ADC Mixer Control (0x0028) */
  628. #define RT5665_M_STO2_ADC_L1 (0x1 << 15)
  629. #define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
  630. #define RT5665_M_STO2_ADC_L1_SFT 15
  631. #define RT5665_M_STO2_ADC_L2 (0x1 << 14)
  632. #define RT5665_M_STO2_ADC_L2_SFT 14
  633. #define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
  634. #define RT5665_STO2_ADC1L_SRC_SFT 13
  635. #define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
  636. #define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)
  637. #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
  638. #define RT5665_STO2_ADC2L_SRC_SFT 12
  639. #define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10)
  640. #define RT5665_STO2_ADCL_SRC_SFT 10
  641. #define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
  642. #define RT5665_STO2_DD_L_SRC_SFT 9
  643. #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
  644. #define RT5665_STO2_DMIC_SRC_SFT 8
  645. #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
  646. #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
  647. #define RT5665_M_STO2_ADC_R1 (0x1 << 7)
  648. #define RT5665_M_STO2_ADC_R1_UN (0x0 << 7)
  649. #define RT5665_M_STO2_ADC_R1_SFT 7
  650. #define RT5665_M_STO2_ADC_R2 (0x1 << 6)
  651. #define RT5665_M_STO2_ADC_R2_SFT 6
  652. #define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)
  653. #define RT5665_STO2_ADC1R_SRC_SFT 5
  654. #define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)
  655. #define RT5665_STO2_ADC2R_SRC_SFT 4
  656. #define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2)
  657. #define RT5665_STO2_ADCR_SRC_SFT 2
  658. #define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)
  659. #define RT5665_STO2_DD_R_SRC_SFT 1
  660. /* ADC Mixer to DAC Mixer Control (0x0029) */
  661. #define RT5665_M_ADCMIX_L (0x1 << 15)
  662. #define RT5665_M_ADCMIX_L_SFT 15
  663. #define RT5665_M_DAC1_L (0x1 << 14)
  664. #define RT5665_M_DAC1_L_SFT 14
  665. #define RT5665_DAC1_R_SEL_MASK (0x3 << 10)
  666. #define RT5665_DAC1_R_SEL_SFT 10
  667. #define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
  668. #define RT5665_DAC1_L_SEL_SFT 8
  669. #define RT5665_M_ADCMIX_R (0x1 << 7)
  670. #define RT5665_M_ADCMIX_R_SFT 7
  671. #define RT5665_M_DAC1_R (0x1 << 6)
  672. #define RT5665_M_DAC1_R_SFT 6
  673. /* Stereo1 DAC Mixer Control (0x002a) */
  674. #define RT5665_M_DAC_L1_STO_L (0x1 << 15)
  675. #define RT5665_M_DAC_L1_STO_L_SFT 15
  676. #define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)
  677. #define RT5665_G_DAC_L1_STO_L_SFT 14
  678. #define RT5665_M_DAC_R1_STO_L (0x1 << 13)
  679. #define RT5665_M_DAC_R1_STO_L_SFT 13
  680. #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
  681. #define RT5665_G_DAC_R1_STO_L_SFT 12
  682. #define RT5665_M_DAC_L2_STO_L (0x1 << 11)
  683. #define RT5665_M_DAC_L2_STO_L_SFT 11
  684. #define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)
  685. #define RT5665_G_DAC_L2_STO_L_SFT 10
  686. #define RT5665_M_DAC_R2_STO_L (0x1 << 9)
  687. #define RT5665_M_DAC_R2_STO_L_SFT 9
  688. #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
  689. #define RT5665_G_DAC_R2_STO_L_SFT 8
  690. #define RT5665_M_DAC_L1_STO_R (0x1 << 7)
  691. #define RT5665_M_DAC_L1_STO_R_SFT 7
  692. #define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)
  693. #define RT5665_G_DAC_L1_STO_R_SFT 6
  694. #define RT5665_M_DAC_R1_STO_R (0x1 << 5)
  695. #define RT5665_M_DAC_R1_STO_R_SFT 5
  696. #define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)
  697. #define RT5665_G_DAC_R1_STO_R_SFT 4
  698. #define RT5665_M_DAC_L2_STO_R (0x1 << 3)
  699. #define RT5665_M_DAC_L2_STO_R_SFT 3
  700. #define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)
  701. #define RT5665_G_DAC_L2_STO_R_SFT 2
  702. #define RT5665_M_DAC_R2_STO_R (0x1 << 1)
  703. #define RT5665_M_DAC_R2_STO_R_SFT 1
  704. #define RT5665_G_DAC_R2_STO_R_MASK (0x1)
  705. #define RT5665_G_DAC_R2_STO_R_SFT 0
  706. /* Mono DAC Mixer Control (0x002b) */
  707. #define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
  708. #define RT5665_M_DAC_L1_MONO_L_SFT 15
  709. #define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)
  710. #define RT5665_G_DAC_L1_MONO_L_SFT 14
  711. #define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
  712. #define RT5665_M_DAC_R1_MONO_L_SFT 13
  713. #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
  714. #define RT5665_G_DAC_R1_MONO_L_SFT 12
  715. #define RT5665_M_DAC_L2_MONO_L (0x1 << 11)
  716. #define RT5665_M_DAC_L2_MONO_L_SFT 11
  717. #define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)
  718. #define RT5665_G_DAC_L2_MONO_L_SFT 10
  719. #define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
  720. #define RT5665_M_DAC_R2_MONO_L_SFT 9
  721. #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
  722. #define RT5665_G_DAC_R2_MONO_L_SFT 8
  723. #define RT5665_M_DAC_L1_MONO_R (0x1 << 7)
  724. #define RT5665_M_DAC_L1_MONO_R_SFT 7
  725. #define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)
  726. #define RT5665_G_DAC_L1_MONO_R_SFT 6
  727. #define RT5665_M_DAC_R1_MONO_R (0x1 << 5)
  728. #define RT5665_M_DAC_R1_MONO_R_SFT 5
  729. #define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)
  730. #define RT5665_G_DAC_R1_MONO_R_SFT 4
  731. #define RT5665_M_DAC_L2_MONO_R (0x1 << 3)
  732. #define RT5665_M_DAC_L2_MONO_R_SFT 3
  733. #define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)
  734. #define RT5665_G_DAC_L2_MONO_R_SFT 2
  735. #define RT5665_M_DAC_R2_MONO_R (0x1 << 1)
  736. #define RT5665_M_DAC_R2_MONO_R_SFT 1
  737. #define RT5665_G_DAC_R2_MONO_R_MASK (0x1)
  738. #define RT5665_G_DAC_R2_MONO_R_SFT 0
  739. /* Stereo2 DAC Mixer Control (0x002c) */
  740. #define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
  741. #define RT5665_M_DAC_L1_STO2_L_SFT 15
  742. #define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)
  743. #define RT5665_G_DAC_L1_STO2_L_SFT 14
  744. #define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
  745. #define RT5665_M_DAC_L2_STO2_L_SFT 13
  746. #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
  747. #define RT5665_G_DAC_L2_STO2_L_SFT 12
  748. #define RT5665_M_DAC_L3_STO2_L (0x1 << 11)
  749. #define RT5665_M_DAC_L3_STO2_L_SFT 11
  750. #define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)
  751. #define RT5665_G_DAC_L3_STO2_L_SFT 10
  752. #define RT5665_M_ST_DAC_L1 (0x1 << 9)
  753. #define RT5665_M_ST_DAC_L1_SFT 9
  754. #define RT5665_M_ST_DAC_R1 (0x1 << 8)
  755. #define RT5665_M_ST_DAC_R1_SFT 8
  756. #define RT5665_M_DAC_R1_STO2_R (0x1 << 7)
  757. #define RT5665_M_DAC_R1_STO2_R_SFT 7
  758. #define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)
  759. #define RT5665_G_DAC_R1_STO2_R_SFT 6
  760. #define RT5665_M_DAC_R2_STO2_R (0x1 << 5)
  761. #define RT5665_M_DAC_R2_STO2_R_SFT 5
  762. #define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)
  763. #define RT5665_G_DAC_R2_STO2_R_SFT 4
  764. #define RT5665_M_DAC_R3_STO2_R (0x1 << 3)
  765. #define RT5665_M_DAC_R3_STO2_R_SFT 3
  766. #define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)
  767. #define RT5665_G_DAC_R3_STO2_R_SFT 2
  768. /* Analog DAC1 Input Source Control (0x002d) */
  769. #define RT5665_DAC_MIX_L_MASK (0x3 << 12)
  770. #define RT5665_DAC_MIX_L_SFT 12
  771. #define RT5665_DAC_MIX_R_MASK (0x3 << 8)
  772. #define RT5665_DAC_MIX_R_SFT 8
  773. #define RT5665_DAC_L1_SRC_MASK (0x3 << 4)
  774. #define RT5665_A_DACL1_SFT 4
  775. #define RT5665_DAC_R1_SRC_MASK (0x3)
  776. #define RT5665_A_DACR1_SFT 0
  777. /* Analog DAC Input Source Control (0x002e) */
  778. #define RT5665_A_DACL2_SEL (0x1 << 4)
  779. #define RT5665_A_DACL2_SFT 4
  780. #define RT5665_A_DACR2_SEL (0x1 << 0)
  781. #define RT5665_A_DACR2_SFT 0
  782. /* Digital Interface Data Control (0x002f) */
  783. #define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
  784. #define RT5665_IF2_1_ADC_IN_SFT 12
  785. #define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10)
  786. #define RT5665_IF2_1_DAC_SEL_SFT 10
  787. #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
  788. #define RT5665_IF2_1_ADC_SEL_SFT 8
  789. #define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4)
  790. #define RT5665_IF2_2_ADC_IN_SFT 4
  791. #define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2)
  792. #define RT5665_IF2_2_DAC_SEL_SFT 2
  793. #define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0)
  794. #define RT5665_IF2_2_ADC_SEL_SFT 0
  795. /* Digital Interface Data Control (0x0030) */
  796. #define RT5665_IF3_ADC_IN_MASK (0x7 << 4)
  797. #define RT5665_IF3_ADC_IN_SFT 4
  798. #define RT5665_IF3_DAC_SEL_MASK (0x3 << 2)
  799. #define RT5665_IF3_DAC_SEL_SFT 2
  800. #define RT5665_IF3_ADC_SEL_MASK (0x3 << 0)
  801. #define RT5665_IF3_ADC_SEL_SFT 0
  802. /* PDM Output Control (0x0031) */
  803. #define RT5665_M_PDM1_L (0x1 << 14)
  804. #define RT5665_M_PDM1_L_SFT 14
  805. #define RT5665_M_PDM1_R (0x1 << 12)
  806. #define RT5665_M_PDM1_R_SFT 12
  807. #define RT5665_PDM1_L_MASK (0x3 << 10)
  808. #define RT5665_PDM1_L_SFT 10
  809. #define RT5665_PDM1_R_MASK (0x3 << 8)
  810. #define RT5665_PDM1_R_SFT 8
  811. #define RT5665_PDM1_BUSY (0x1 << 6)
  812. #define RT5665_PDM_PATTERN (0x1 << 5)
  813. #define RT5665_PDM_GAIN (0x1 << 4)
  814. #define RT5665_LRCK_PDM_PI2C (0x1 << 3)
  815. #define RT5665_PDM_DIV_MASK (0x3)
  816. /*S/PDIF Output Control (0x0036) */
  817. #define RT5665_SPDIF_SEL_MASK (0x3 << 0)
  818. #define RT5665_SPDIF_SEL_SFT 0
  819. /* REC Left Mixer Control 2 (0x003c) */
  820. #define RT5665_M_CBJ_RM1_L (0x1 << 7)
  821. #define RT5665_M_CBJ_RM1_L_SFT 7
  822. #define RT5665_M_BST1_RM1_L (0x1 << 5)
  823. #define RT5665_M_BST1_RM1_L_SFT 5
  824. #define RT5665_M_BST2_RM1_L (0x1 << 4)
  825. #define RT5665_M_BST2_RM1_L_SFT 4
  826. #define RT5665_M_BST3_RM1_L (0x1 << 3)
  827. #define RT5665_M_BST3_RM1_L_SFT 3
  828. #define RT5665_M_BST4_RM1_L (0x1 << 2)
  829. #define RT5665_M_BST4_RM1_L_SFT 2
  830. #define RT5665_M_INL_RM1_L (0x1 << 1)
  831. #define RT5665_M_INL_RM1_L_SFT 1
  832. #define RT5665_M_INR_RM1_L (0x1)
  833. #define RT5665_M_INR_RM1_L_SFT 0
  834. /* REC Right Mixer Control 2 (0x003e) */
  835. #define RT5665_M_AEC_REF_RM1_R (0x1 << 7)
  836. #define RT5665_M_AEC_REF_RM1_R_SFT 7
  837. #define RT5665_M_BST1_RM1_R (0x1 << 5)
  838. #define RT5665_M_BST1_RM1_R_SFT 5
  839. #define RT5665_M_BST2_RM1_R (0x1 << 4)
  840. #define RT5665_M_BST2_RM1_R_SFT 4
  841. #define RT5665_M_BST3_RM1_R (0x1 << 3)
  842. #define RT5665_M_BST3_RM1_R_SFT 3
  843. #define RT5665_M_BST4_RM1_R (0x1 << 2)
  844. #define RT5665_M_BST4_RM1_R_SFT 2
  845. #define RT5665_M_INR_RM1_R (0x1 << 1)
  846. #define RT5665_M_INR_RM1_R_SFT 1
  847. #define RT5665_M_MONOVOL_RM1_R (0x1)
  848. #define RT5665_M_MONOVOL_RM1_R_SFT 0
  849. /* REC Mixer 2 Left Control 2 (0x0041) */
  850. #define RT5665_M_CBJ_RM2_L (0x1 << 7)
  851. #define RT5665_M_CBJ_RM2_L_SFT 7
  852. #define RT5665_M_BST1_RM2_L (0x1 << 5)
  853. #define RT5665_M_BST1_RM2_L_SFT 5
  854. #define RT5665_M_BST2_RM2_L (0x1 << 4)
  855. #define RT5665_M_BST2_RM2_L_SFT 4
  856. #define RT5665_M_BST3_RM2_L (0x1 << 3)
  857. #define RT5665_M_BST3_RM2_L_SFT 3
  858. #define RT5665_M_BST4_RM2_L (0x1 << 2)
  859. #define RT5665_M_BST4_RM2_L_SFT 2
  860. #define RT5665_M_INL_RM2_L (0x1 << 1)
  861. #define RT5665_M_INL_RM2_L_SFT 1
  862. #define RT5665_M_INR_RM2_L (0x1)
  863. #define RT5665_M_INR_RM2_L_SFT 0
  864. /* REC Mixer 2 Right Control 2 (0x0043) */
  865. #define RT5665_M_MONOVOL_RM2_R (0x1 << 7)
  866. #define RT5665_M_MONOVOL_RM2_R_SFT 7
  867. #define RT5665_M_BST1_RM2_R (0x1 << 5)
  868. #define RT5665_M_BST1_RM2_R_SFT 5
  869. #define RT5665_M_BST2_RM2_R (0x1 << 4)
  870. #define RT5665_M_BST2_RM2_R_SFT 4
  871. #define RT5665_M_BST3_RM2_R (0x1 << 3)
  872. #define RT5665_M_BST3_RM2_R_SFT 3
  873. #define RT5665_M_BST4_RM2_R (0x1 << 2)
  874. #define RT5665_M_BST4_RM2_R_SFT 2
  875. #define RT5665_M_INL_RM2_R (0x1 << 1)
  876. #define RT5665_M_INL_RM2_R_SFT 1
  877. #define RT5665_M_INR_RM2_R (0x1)
  878. #define RT5665_M_INR_RM2_R_SFT 0
  879. /* SPK Left Mixer Control (0x0046) */
  880. #define RT5665_M_BST3_SM_L (0x1 << 4)
  881. #define RT5665_M_BST3_SM_L_SFT 4
  882. #define RT5665_M_IN_R_SM_L (0x1 << 3)
  883. #define RT5665_M_IN_R_SM_L_SFT 3
  884. #define RT5665_M_IN_L_SM_L (0x1 << 2)
  885. #define RT5665_M_IN_L_SM_L_SFT 2
  886. #define RT5665_M_BST1_SM_L (0x1 << 1)
  887. #define RT5665_M_BST1_SM_L_SFT 1
  888. #define RT5665_M_DAC_L2_SM_L (0x1)
  889. #define RT5665_M_DAC_L2_SM_L_SFT 0
  890. /* SPK Right Mixer Control (0x0047) */
  891. #define RT5665_M_BST3_SM_R (0x1 << 4)
  892. #define RT5665_M_BST3_SM_R_SFT 4
  893. #define RT5665_M_IN_R_SM_R (0x1 << 3)
  894. #define RT5665_M_IN_R_SM_R_SFT 3
  895. #define RT5665_M_IN_L_SM_R (0x1 << 2)
  896. #define RT5665_M_IN_L_SM_R_SFT 2
  897. #define RT5665_M_BST4_SM_R (0x1 << 1)
  898. #define RT5665_M_BST4_SM_R_SFT 1
  899. #define RT5665_M_DAC_R2_SM_R (0x1)
  900. #define RT5665_M_DAC_R2_SM_R_SFT 0
  901. /* SPO Amp Input and Gain Control (0x0048) */
  902. #define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
  903. #define RT5665_M_DAC_L2_SPKOMIX_SFT 13
  904. #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
  905. #define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
  906. #define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
  907. #define RT5665_M_DAC_R2_SPKOMIX_SFT 9
  908. #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
  909. #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
  910. /* MONOMIX Input and Gain Control (0x004b) */
  911. #define RT5665_G_MONOVOL_MA (0x1 << 10)
  912. #define RT5665_G_MONOVOL_MA_SFT 10
  913. #define RT5665_M_MONOVOL_MA (0x1 << 9)
  914. #define RT5665_M_MONOVOL_MA_SFT 9
  915. #define RT5665_M_DAC_L2_MA (0x1 << 8)
  916. #define RT5665_M_DAC_L2_MA_SFT 8
  917. #define RT5665_M_BST3_MM (0x1 << 4)
  918. #define RT5665_M_BST3_MM_SFT 4
  919. #define RT5665_M_BST2_MM (0x1 << 3)
  920. #define RT5665_M_BST2_MM_SFT 3
  921. #define RT5665_M_BST1_MM (0x1 << 2)
  922. #define RT5665_M_BST1_MM_SFT 2
  923. #define RT5665_M_RECMIC2L_MM (0x1 << 1)
  924. #define RT5665_M_RECMIC2L_MM_SFT 1
  925. #define RT5665_M_DAC_L2_MM (0x1)
  926. #define RT5665_M_DAC_L2_MM_SFT 0
  927. /* Output Left Mixer Control 1 (0x004d) */
  928. #define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
  929. #define RT5665_G_BST3_OM_L_SFT 12
  930. #define RT5665_G_BST2_OM_L_MASK (0x7 << 9)
  931. #define RT5665_G_BST2_OM_L_SFT 9
  932. #define RT5665_G_BST1_OM_L_MASK (0x7 << 6)
  933. #define RT5665_G_BST1_OM_L_SFT 6
  934. #define RT5665_G_IN_L_OM_L_MASK (0x7 << 3)
  935. #define RT5665_G_IN_L_OM_L_SFT 3
  936. #define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0)
  937. #define RT5665_G_DAC_L2_OM_L_SFT 0
  938. /* Output Left Mixer Input Control (0x004e) */
  939. #define RT5665_M_BST3_OM_L (0x1 << 4)
  940. #define RT5665_M_BST3_OM_L_SFT 4
  941. #define RT5665_M_BST2_OM_L (0x1 << 3)
  942. #define RT5665_M_BST2_OM_L_SFT 3
  943. #define RT5665_M_BST1_OM_L (0x1 << 2)
  944. #define RT5665_M_BST1_OM_L_SFT 2
  945. #define RT5665_M_IN_L_OM_L (0x1 << 1)
  946. #define RT5665_M_IN_L_OM_L_SFT 1
  947. #define RT5665_M_DAC_L2_OM_L (0x1)
  948. #define RT5665_M_DAC_L2_OM_L_SFT 0
  949. /* Output Right Mixer Input Control (0x0050) */
  950. #define RT5665_M_BST4_OM_R (0x1 << 4)
  951. #define RT5665_M_BST4_OM_R_SFT 4
  952. #define RT5665_M_BST3_OM_R (0x1 << 3)
  953. #define RT5665_M_BST3_OM_R_SFT 3
  954. #define RT5665_M_BST2_OM_R (0x1 << 2)
  955. #define RT5665_M_BST2_OM_R_SFT 2
  956. #define RT5665_M_IN_R_OM_R (0x1 << 1)
  957. #define RT5665_M_IN_R_OM_R_SFT 1
  958. #define RT5665_M_DAC_R2_OM_R (0x1)
  959. #define RT5665_M_DAC_R2_OM_R_SFT 0
  960. /* LOUT Mixer Control (0x0052) */
  961. #define RT5665_M_DAC_L2_LM (0x1 << 15)
  962. #define RT5665_M_DAC_L2_LM_SFT 15
  963. #define RT5665_M_DAC_R2_LM (0x1 << 14)
  964. #define RT5665_M_DAC_R2_LM_SFT 14
  965. #define RT5665_M_OV_L_LM (0x1 << 13)
  966. #define RT5665_M_OV_L_LM_SFT 13
  967. #define RT5665_M_OV_R_LM (0x1 << 12)
  968. #define RT5665_M_OV_R_LM_SFT 12
  969. #define RT5665_LOUT_BST_SFT 11
  970. #define RT5665_LOUT_DF (0x1 << 11)
  971. #define RT5665_LOUT_DF_SFT 11
  972. /* Power Management for Digital 1 (0x0061) */
  973. #define RT5665_PWR_I2S1_1 (0x1 << 15)
  974. #define RT5665_PWR_I2S1_1_BIT 15
  975. #define RT5665_PWR_I2S1_2 (0x1 << 14)
  976. #define RT5665_PWR_I2S1_2_BIT 14
  977. #define RT5665_PWR_I2S2_1 (0x1 << 13)
  978. #define RT5665_PWR_I2S2_1_BIT 13
  979. #define RT5665_PWR_I2S2_2 (0x1 << 12)
  980. #define RT5665_PWR_I2S2_2_BIT 12
  981. #define RT5665_PWR_DAC_L1 (0x1 << 11)
  982. #define RT5665_PWR_DAC_L1_BIT 11
  983. #define RT5665_PWR_DAC_R1 (0x1 << 10)
  984. #define RT5665_PWR_DAC_R1_BIT 10
  985. #define RT5665_PWR_I2S3 (0x1 << 9)
  986. #define RT5665_PWR_I2S3_BIT 9
  987. #define RT5665_PWR_LDO (0x1 << 8)
  988. #define RT5665_PWR_LDO_BIT 8
  989. #define RT5665_PWR_DAC_L2 (0x1 << 7)
  990. #define RT5665_PWR_DAC_L2_BIT 7
  991. #define RT5665_PWR_DAC_R2 (0x1 << 6)
  992. #define RT5665_PWR_DAC_R2_BIT 6
  993. #define RT5665_PWR_ADC_L1 (0x1 << 4)
  994. #define RT5665_PWR_ADC_L1_BIT 4
  995. #define RT5665_PWR_ADC_R1 (0x1 << 3)
  996. #define RT5665_PWR_ADC_R1_BIT 3
  997. #define RT5665_PWR_ADC_L2 (0x1 << 2)
  998. #define RT5665_PWR_ADC_L2_BIT 2
  999. #define RT5665_PWR_ADC_R2 (0x1 << 1)
  1000. #define RT5665_PWR_ADC_R2_BIT 1
  1001. /* Power Management for Digital 2 (0x0062) */
  1002. #define RT5665_PWR_ADC_S1F (0x1 << 15)
  1003. #define RT5665_PWR_ADC_S1F_BIT 15
  1004. #define RT5665_PWR_ADC_S2F (0x1 << 14)
  1005. #define RT5665_PWR_ADC_S2F_BIT 14
  1006. #define RT5665_PWR_ADC_MF_L (0x1 << 13)
  1007. #define RT5665_PWR_ADC_MF_L_BIT 13
  1008. #define RT5665_PWR_ADC_MF_R (0x1 << 12)
  1009. #define RT5665_PWR_ADC_MF_R_BIT 12
  1010. #define RT5665_PWR_DAC_S2F (0x1 << 11)
  1011. #define RT5665_PWR_DAC_S2F_BIT 11
  1012. #define RT5665_PWR_DAC_S1F (0x1 << 10)
  1013. #define RT5665_PWR_DAC_S1F_BIT 10
  1014. #define RT5665_PWR_DAC_MF_L (0x1 << 9)
  1015. #define RT5665_PWR_DAC_MF_L_BIT 9
  1016. #define RT5665_PWR_DAC_MF_R (0x1 << 8)
  1017. #define RT5665_PWR_DAC_MF_R_BIT 8
  1018. #define RT5665_PWR_PDM1 (0x1 << 7)
  1019. #define RT5665_PWR_PDM1_BIT 7
  1020. /* Power Management for Analog 1 (0x0063) */
  1021. #define RT5665_PWR_VREF1 (0x1 << 15)
  1022. #define RT5665_PWR_VREF1_BIT 15
  1023. #define RT5665_PWR_FV1 (0x1 << 14)
  1024. #define RT5665_PWR_FV1_BIT 14
  1025. #define RT5665_PWR_VREF2 (0x1 << 13)
  1026. #define RT5665_PWR_VREF2_BIT 13
  1027. #define RT5665_PWR_FV2 (0x1 << 12)
  1028. #define RT5665_PWR_FV2_BIT 12
  1029. #define RT5665_PWR_VREF3 (0x1 << 11)
  1030. #define RT5665_PWR_VREF3_BIT 11
  1031. #define RT5665_PWR_FV3 (0x1 << 10)
  1032. #define RT5665_PWR_FV3_BIT 10
  1033. #define RT5665_PWR_MB (0x1 << 9)
  1034. #define RT5665_PWR_MB_BIT 9
  1035. #define RT5665_PWR_LM (0x1 << 8)
  1036. #define RT5665_PWR_LM_BIT 8
  1037. #define RT5665_PWR_BG (0x1 << 7)
  1038. #define RT5665_PWR_BG_BIT 7
  1039. #define RT5665_PWR_MA (0x1 << 6)
  1040. #define RT5665_PWR_MA_BIT 6
  1041. #define RT5665_PWR_HA_L (0x1 << 5)
  1042. #define RT5665_PWR_HA_L_BIT 5
  1043. #define RT5665_PWR_HA_R (0x1 << 4)
  1044. #define RT5665_PWR_HA_R_BIT 4
  1045. #define RT5665_HP_DRIVER_MASK (0x3 << 2)
  1046. #define RT5665_HP_DRIVER_1X (0x0 << 2)
  1047. #define RT5665_HP_DRIVER_3X (0x1 << 2)
  1048. #define RT5665_HP_DRIVER_5X (0x3 << 2)
  1049. #define RT5665_LDO1_DVO_MASK (0x3)
  1050. #define RT5665_LDO1_DVO_09 (0x0)
  1051. #define RT5665_LDO1_DVO_10 (0x1)
  1052. #define RT5665_LDO1_DVO_12 (0x2)
  1053. #define RT5665_LDO1_DVO_14 (0x3)
  1054. /* Power Management for Analog 2 (0x0064) */
  1055. #define RT5665_PWR_BST1 (0x1 << 15)
  1056. #define RT5665_PWR_BST1_BIT 15
  1057. #define RT5665_PWR_BST2 (0x1 << 14)
  1058. #define RT5665_PWR_BST2_BIT 14
  1059. #define RT5665_PWR_BST3 (0x1 << 13)
  1060. #define RT5665_PWR_BST3_BIT 13
  1061. #define RT5665_PWR_BST4 (0x1 << 12)
  1062. #define RT5665_PWR_BST4_BIT 12
  1063. #define RT5665_PWR_MB1 (0x1 << 11)
  1064. #define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11)
  1065. #define RT5665_PWR_MB1_BIT 11
  1066. #define RT5665_PWR_MB2 (0x1 << 10)
  1067. #define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10)
  1068. #define RT5665_PWR_MB2_BIT 10
  1069. #define RT5665_PWR_MB3 (0x1 << 9)
  1070. #define RT5665_PWR_MB3_BIT 9
  1071. #define RT5665_PWR_BST1_P (0x1 << 7)
  1072. #define RT5665_PWR_BST1_P_BIT 7
  1073. #define RT5665_PWR_BST2_P (0x1 << 6)
  1074. #define RT5665_PWR_BST2_P_BIT 6
  1075. #define RT5665_PWR_BST3_P (0x1 << 5)
  1076. #define RT5665_PWR_BST3_P_BIT 5
  1077. #define RT5665_PWR_BST4_P (0x1 << 4)
  1078. #define RT5665_PWR_BST4_P_BIT 4
  1079. #define RT5665_PWR_JD1 (0x1 << 3)
  1080. #define RT5665_PWR_JD1_BIT 3
  1081. #define RT5665_PWR_JD2 (0x1 << 2)
  1082. #define RT5665_PWR_JD2_BIT 2
  1083. #define RT5665_PWR_RM1_L (0x1 << 1)
  1084. #define RT5665_PWR_RM1_L_BIT 1
  1085. #define RT5665_PWR_RM1_R (0x1)
  1086. #define RT5665_PWR_RM1_R_BIT 0
  1087. /* Power Management for Analog 3 (0x0065) */
  1088. #define RT5665_PWR_CBJ (0x1 << 9)
  1089. #define RT5665_PWR_CBJ_BIT 9
  1090. #define RT5665_PWR_BST_L (0x1 << 8)
  1091. #define RT5665_PWR_BST_L_BIT 8
  1092. #define RT5665_PWR_BST_R (0x1 << 7)
  1093. #define RT5665_PWR_BST_R_BIT 7
  1094. #define RT5665_PWR_PLL (0x1 << 6)
  1095. #define RT5665_PWR_PLL_BIT 6
  1096. #define RT5665_PWR_LDO2 (0x1 << 2)
  1097. #define RT5665_PWR_LDO2_BIT 2
  1098. #define RT5665_PWR_SVD (0x1 << 1)
  1099. #define RT5665_PWR_SVD_BIT 1
  1100. /* Power Management for Mixer (0x0066) */
  1101. #define RT5665_PWR_RM2_L (0x1 << 15)
  1102. #define RT5665_PWR_RM2_L_BIT 15
  1103. #define RT5665_PWR_RM2_R (0x1 << 14)
  1104. #define RT5665_PWR_RM2_R_BIT 14
  1105. #define RT5665_PWR_OM_L (0x1 << 13)
  1106. #define RT5665_PWR_OM_L_BIT 13
  1107. #define RT5665_PWR_OM_R (0x1 << 12)
  1108. #define RT5665_PWR_OM_R_BIT 12
  1109. #define RT5665_PWR_MM (0x1 << 11)
  1110. #define RT5665_PWR_MM_BIT 11
  1111. #define RT5665_PWR_AEC_REF (0x1 << 6)
  1112. #define RT5665_PWR_AEC_REF_BIT 6
  1113. #define RT5665_PWR_STO1_DAC_L (0x1 << 5)
  1114. #define RT5665_PWR_STO1_DAC_L_BIT 5
  1115. #define RT5665_PWR_STO1_DAC_R (0x1 << 4)
  1116. #define RT5665_PWR_STO1_DAC_R_BIT 4
  1117. #define RT5665_PWR_MONO_DAC_L (0x1 << 3)
  1118. #define RT5665_PWR_MONO_DAC_L_BIT 3
  1119. #define RT5665_PWR_MONO_DAC_R (0x1 << 2)
  1120. #define RT5665_PWR_MONO_DAC_R_BIT 2
  1121. #define RT5665_PWR_STO2_DAC_L (0x1 << 1)
  1122. #define RT5665_PWR_STO2_DAC_L_BIT 1
  1123. #define RT5665_PWR_STO2_DAC_R (0x1)
  1124. #define RT5665_PWR_STO2_DAC_R_BIT 0
  1125. /* Power Management for Volume (0x0067) */
  1126. #define RT5665_PWR_OV_L (0x1 << 13)
  1127. #define RT5665_PWR_OV_L_BIT 13
  1128. #define RT5665_PWR_OV_R (0x1 << 12)
  1129. #define RT5665_PWR_OV_R_BIT 12
  1130. #define RT5665_PWR_IN_L (0x1 << 9)
  1131. #define RT5665_PWR_IN_L_BIT 9
  1132. #define RT5665_PWR_IN_R (0x1 << 8)
  1133. #define RT5665_PWR_IN_R_BIT 8
  1134. #define RT5665_PWR_MV (0x1 << 7)
  1135. #define RT5665_PWR_MV_BIT 7
  1136. #define RT5665_PWR_MIC_DET (0x1 << 5)
  1137. #define RT5665_PWR_MIC_DET_BIT 5
  1138. /* (0x006b) */
  1139. #define RT5665_SYS_CLK_DET 15
  1140. #define RT5665_HP_CLK_DET 14
  1141. #define RT5665_MONO_CLK_DET 13
  1142. #define RT5665_LOUT_CLK_DET 12
  1143. #define RT5665_POW_CLK_DET 0
  1144. /* Digital Microphone Control 1 (0x006e) */
  1145. #define RT5665_DMIC_1_EN_MASK (0x1 << 15)
  1146. #define RT5665_DMIC_1_EN_SFT 15
  1147. #define RT5665_DMIC_1_DIS (0x0 << 15)
  1148. #define RT5665_DMIC_1_EN (0x1 << 15)
  1149. #define RT5665_DMIC_2_EN_MASK (0x1 << 14)
  1150. #define RT5665_DMIC_2_EN_SFT 14
  1151. #define RT5665_DMIC_2_DIS (0x0 << 14)
  1152. #define RT5665_DMIC_2_EN (0x1 << 14)
  1153. #define RT5665_DMIC_2_DP_MASK (0x1 << 9)
  1154. #define RT5665_DMIC_2_DP_SFT 9
  1155. #define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)
  1156. #define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
  1157. #define RT5665_DMIC_CLK_MASK (0x7 << 5)
  1158. #define RT5665_DMIC_CLK_SFT 5
  1159. #define RT5665_DMIC_1_DP_MASK (0x1 << 1)
  1160. #define RT5665_DMIC_1_DP_SFT 1
  1161. #define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1)
  1162. #define RT5665_DMIC_1_DP_IN2N (0x1 << 1)
  1163. /* Digital Microphone Control 1 (0x006f) */
  1164. #define RT5665_DMIC_2L_LH_MASK (0x1 << 3)
  1165. #define RT5665_DMIC_2L_LH_SFT 3
  1166. #define RT5665_DMIC_2L_LH_RISING (0x0 << 3)
  1167. #define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)
  1168. #define RT5665_DMIC_2R_LH_MASK (0x1 << 2)
  1169. #define RT5665_DMIC_2R_LH_SFT 2
  1170. #define RT5665_DMIC_2R_LH_RISING (0x0 << 2)
  1171. #define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)
  1172. #define RT5665_DMIC_1L_LH_MASK (0x1 << 1)
  1173. #define RT5665_DMIC_1L_LH_SFT 1
  1174. #define RT5665_DMIC_1L_LH_RISING (0x0 << 1)
  1175. #define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)
  1176. #define RT5665_DMIC_1R_LH_MASK (0x1 << 0)
  1177. #define RT5665_DMIC_1R_LH_SFT 0
  1178. #define RT5665_DMIC_1R_LH_RISING (0x0)
  1179. #define RT5665_DMIC_1R_LH_FALLING (0x1)
  1180. /* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
  1181. #define RT5665_I2S_MS_MASK (0x1 << 15)
  1182. #define RT5665_I2S_MS_SFT 15
  1183. #define RT5665_I2S_MS_M (0x0 << 15)
  1184. #define RT5665_I2S_MS_S (0x1 << 15)
  1185. #define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)
  1186. #define RT5665_I2S_PIN_CFG_SFT 14
  1187. #define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)
  1188. #define RT5665_I2S_CLK_SEL_SFT 11
  1189. #define RT5665_I2S_BP_MASK (0x1 << 8)
  1190. #define RT5665_I2S_BP_SFT 8
  1191. #define RT5665_I2S_BP_NOR (0x0 << 8)
  1192. #define RT5665_I2S_BP_INV (0x1 << 8)
  1193. #define RT5665_I2S_DL_MASK (0x3 << 4)
  1194. #define RT5665_I2S_DL_SFT 4
  1195. #define RT5665_I2S_DL_16 (0x0 << 4)
  1196. #define RT5665_I2S_DL_20 (0x1 << 4)
  1197. #define RT5665_I2S_DL_24 (0x2 << 4)
  1198. #define RT5665_I2S_DL_8 (0x3 << 4)
  1199. #define RT5665_I2S_DF_MASK (0x7)
  1200. #define RT5665_I2S_DF_SFT 0
  1201. #define RT5665_I2S_DF_I2S (0x0)
  1202. #define RT5665_I2S_DF_LEFT (0x1)
  1203. #define RT5665_I2S_DF_PCM_A (0x2)
  1204. #define RT5665_I2S_DF_PCM_B (0x3)
  1205. #define RT5665_I2S_DF_PCM_A_N (0x6)
  1206. #define RT5665_I2S_DF_PCM_B_N (0x7)
  1207. /* ADC/DAC Clock Control 1 (0x0073) */
  1208. #define RT5665_I2S_PD1_MASK (0x7 << 12)
  1209. #define RT5665_I2S_PD1_SFT 12
  1210. #define RT5665_I2S_PD1_1 (0x0 << 12)
  1211. #define RT5665_I2S_PD1_2 (0x1 << 12)
  1212. #define RT5665_I2S_PD1_3 (0x2 << 12)
  1213. #define RT5665_I2S_PD1_4 (0x3 << 12)
  1214. #define RT5665_I2S_PD1_6 (0x4 << 12)
  1215. #define RT5665_I2S_PD1_8 (0x5 << 12)
  1216. #define RT5665_I2S_PD1_12 (0x6 << 12)
  1217. #define RT5665_I2S_PD1_16 (0x7 << 12)
  1218. #define RT5665_I2S_M_PD2_MASK (0x7 << 8)
  1219. #define RT5665_I2S_M_PD2_SFT 8
  1220. #define RT5665_I2S_M_PD2_1 (0x0 << 8)
  1221. #define RT5665_I2S_M_PD2_2 (0x1 << 8)
  1222. #define RT5665_I2S_M_PD2_3 (0x2 << 8)
  1223. #define RT5665_I2S_M_PD2_4 (0x3 << 8)
  1224. #define RT5665_I2S_M_PD2_6 (0x4 << 8)
  1225. #define RT5665_I2S_M_PD2_8 (0x5 << 8)
  1226. #define RT5665_I2S_M_PD2_12 (0x6 << 8)
  1227. #define RT5665_I2S_M_PD2_16 (0x7 << 8)
  1228. #define RT5665_I2S_CLK_SRC_MASK (0x3 << 4)
  1229. #define RT5665_I2S_CLK_SRC_SFT 4
  1230. #define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4)
  1231. #define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)
  1232. #define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4)
  1233. #define RT5665_DAC_OSR_MASK (0x3 << 2)
  1234. #define RT5665_DAC_OSR_SFT 2
  1235. #define RT5665_DAC_OSR_128 (0x0 << 2)
  1236. #define RT5665_DAC_OSR_64 (0x1 << 2)
  1237. #define RT5665_DAC_OSR_32 (0x2 << 2)
  1238. #define RT5665_ADC_OSR_MASK (0x3)
  1239. #define RT5665_ADC_OSR_SFT 0
  1240. #define RT5665_ADC_OSR_128 (0x0)
  1241. #define RT5665_ADC_OSR_64 (0x1)
  1242. #define RT5665_ADC_OSR_32 (0x2)
  1243. /* ADC/DAC Clock Control 2 (0x0074) */
  1244. #define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
  1245. #define RT5665_I2S_BCLK_MS2_SFT 15
  1246. #define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
  1247. #define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
  1248. #define RT5665_I2S_PD2_MASK (0x7 << 12)
  1249. #define RT5665_I2S_PD2_SFT 12
  1250. #define RT5665_I2S_PD2_1 (0x0 << 12)
  1251. #define RT5665_I2S_PD2_2 (0x1 << 12)
  1252. #define RT5665_I2S_PD2_3 (0x2 << 12)
  1253. #define RT5665_I2S_PD2_4 (0x3 << 12)
  1254. #define RT5665_I2S_PD2_6 (0x4 << 12)
  1255. #define RT5665_I2S_PD2_8 (0x5 << 12)
  1256. #define RT5665_I2S_PD2_12 (0x6 << 12)
  1257. #define RT5665_I2S_PD2_16 (0x7 << 12)
  1258. #define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)
  1259. #define RT5665_I2S_BCLK_MS3_SFT 11
  1260. #define RT5665_I2S_BCLK_MS3_32 (0x0 << 11)
  1261. #define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)
  1262. #define RT5665_I2S_PD3_MASK (0x7 << 8)
  1263. #define RT5665_I2S_PD3_SFT 8
  1264. #define RT5665_I2S_PD3_1 (0x0 << 8)
  1265. #define RT5665_I2S_PD3_2 (0x1 << 8)
  1266. #define RT5665_I2S_PD3_3 (0x2 << 8)
  1267. #define RT5665_I2S_PD3_4 (0x3 << 8)
  1268. #define RT5665_I2S_PD3_6 (0x4 << 8)
  1269. #define RT5665_I2S_PD3_8 (0x5 << 8)
  1270. #define RT5665_I2S_PD3_12 (0x6 << 8)
  1271. #define RT5665_I2S_PD3_16 (0x7 << 8)
  1272. #define RT5665_I2S_PD4_MASK (0x7 << 4)
  1273. #define RT5665_I2S_PD4_SFT 4
  1274. #define RT5665_I2S_PD4_1 (0x0 << 4)
  1275. #define RT5665_I2S_PD4_2 (0x1 << 4)
  1276. #define RT5665_I2S_PD4_3 (0x2 << 4)
  1277. #define RT5665_I2S_PD4_4 (0x3 << 4)
  1278. #define RT5665_I2S_PD4_6 (0x4 << 4)
  1279. #define RT5665_I2S_PD4_8 (0x5 << 4)
  1280. #define RT5665_I2S_PD4_12 (0x6 << 4)
  1281. #define RT5665_I2S_PD4_16 (0x7 << 4)
  1282. /* TDM control 1 (0x0078) */
  1283. #define RT5665_I2S1_MODE_MASK (0x1 << 15)
  1284. #define RT5665_I2S1_MODE_I2S (0x0 << 15)
  1285. #define RT5665_I2S1_MODE_TDM (0x1 << 15)
  1286. #define RT5665_TDM_IN_CH_MASK (0x3 << 10)
  1287. #define RT5665_TDM_IN_CH_2 (0x0 << 10)
  1288. #define RT5665_TDM_IN_CH_4 (0x1 << 10)
  1289. #define RT5665_TDM_IN_CH_6 (0x2 << 10)
  1290. #define RT5665_TDM_IN_CH_8 (0x3 << 10)
  1291. #define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
  1292. #define RT5665_TDM_OUT_CH_2 (0x0 << 8)
  1293. #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
  1294. #define RT5665_TDM_OUT_CH_6 (0x2 << 8)
  1295. #define RT5665_TDM_OUT_CH_8 (0x3 << 8)
  1296. #define RT5665_TDM_IN_LEN_MASK (0x3 << 6)
  1297. #define RT5665_TDM_IN_LEN_16 (0x0 << 6)
  1298. #define RT5665_TDM_IN_LEN_20 (0x1 << 6)
  1299. #define RT5665_TDM_IN_LEN_24 (0x2 << 6)
  1300. #define RT5665_TDM_IN_LEN_32 (0x3 << 6)
  1301. #define RT5665_TDM_OUT_LEN_MASK (0x3 << 4)
  1302. #define RT5665_TDM_OUT_LEN_16 (0x0 << 4)
  1303. #define RT5665_TDM_OUT_LEN_20 (0x1 << 4)
  1304. #define RT5665_TDM_OUT_LEN_24 (0x2 << 4)
  1305. #define RT5665_TDM_OUT_LEN_32 (0x3 << 4)
  1306. /* TDM control 2 (0x0079) */
  1307. #define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 14
  1308. #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
  1309. #define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 10
  1310. #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
  1311. #define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 6
  1312. #define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 4
  1313. #define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 2
  1314. #define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 0
  1315. /* TDM control 3/4 (0x007a) (0x007b) */
  1316. #define RT5665_IF1_ADC1_SEL_SFT 10
  1317. #define RT5665_IF1_ADC2_SEL_SFT 9
  1318. #define RT5665_IF1_ADC3_SEL_SFT 8
  1319. #define RT5665_IF1_ADC4_SEL_SFT 7
  1320. #define RT5665_TDM_ADC_SEL_SFT 0
  1321. #define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0)
  1322. #define RT5665_TDM_ADC_DATA_06 (0x6 << 0)
  1323. /* Global Clock Control (0x0080) */
  1324. #define RT5665_SCLK_SRC_MASK (0x3 << 14)
  1325. #define RT5665_SCLK_SRC_SFT 14
  1326. #define RT5665_SCLK_SRC_MCLK (0x0 << 14)
  1327. #define RT5665_SCLK_SRC_PLL1 (0x1 << 14)
  1328. #define RT5665_SCLK_SRC_RCCLK (0x2 << 14)
  1329. #define RT5665_PLL1_SRC_MASK (0x7 << 8)
  1330. #define RT5665_PLL1_SRC_SFT 8
  1331. #define RT5665_PLL1_SRC_MCLK (0x0 << 8)
  1332. #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
  1333. #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
  1334. #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
  1335. #define RT5665_PLL1_PD_MASK (0x7 << 4)
  1336. #define RT5665_PLL1_PD_SFT 4
  1337. #define RT5665_PLL_INP_MAX 40000000
  1338. #define RT5665_PLL_INP_MIN 256000
  1339. /* PLL M/N/K Code Control 1 (0x0081) */
  1340. #define RT5665_PLL_N_MAX 0x001ff
  1341. #define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7)
  1342. #define RT5665_PLL_N_SFT 7
  1343. #define RT5665_PLL_K_MAX 0x001f
  1344. #define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX)
  1345. #define RT5665_PLL_K_SFT 0
  1346. /* PLL M/N/K Code Control 2 (0x0082) */
  1347. #define RT5665_PLL_M_MAX 0x00f
  1348. #define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
  1349. #define RT5665_PLL_M_SFT 12
  1350. #define RT5665_PLL_M_BP (0x1 << 11)
  1351. #define RT5665_PLL_M_BP_SFT 11
  1352. #define RT5665_PLL_K_BP (0x1 << 10)
  1353. #define RT5665_PLL_K_BP_SFT 10
  1354. /* PLL tracking mode 1 (0x0083) */
  1355. #define RT5665_I2S3_ASRC_MASK (0x1 << 15)
  1356. #define RT5665_I2S3_ASRC_SFT 15
  1357. #define RT5665_I2S2_ASRC_MASK (0x1 << 14)
  1358. #define RT5665_I2S2_ASRC_SFT 14
  1359. #define RT5665_I2S1_ASRC_MASK (0x1 << 13)
  1360. #define RT5665_I2S1_ASRC_SFT 13
  1361. #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
  1362. #define RT5665_DAC_STO1_ASRC_SFT 12
  1363. #define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)
  1364. #define RT5665_DAC_STO2_ASRC_SFT 11
  1365. #define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)
  1366. #define RT5665_DAC_MONO_L_ASRC_SFT 10
  1367. #define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
  1368. #define RT5665_DAC_MONO_R_ASRC_SFT 9
  1369. #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
  1370. #define RT5665_DMIC_STO1_ASRC_SFT 8
  1371. #define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)
  1372. #define RT5665_DMIC_STO2_ASRC_SFT 7
  1373. #define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)
  1374. #define RT5665_DMIC_MONO_L_ASRC_SFT 6
  1375. #define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)
  1376. #define RT5665_DMIC_MONO_R_ASRC_SFT 5
  1377. #define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)
  1378. #define RT5665_ADC_STO1_ASRC_SFT 4
  1379. #define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)
  1380. #define RT5665_ADC_STO2_ASRC_SFT 3
  1381. #define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)
  1382. #define RT5665_ADC_MONO_L_ASRC_SFT 2
  1383. #define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)
  1384. #define RT5665_ADC_MONO_R_ASRC_SFT 1
  1385. /* PLL tracking mode 2 (0x0084)*/
  1386. #define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
  1387. #define RT5665_DA_STO1_CLK_SEL_SFT 12
  1388. #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
  1389. #define RT5665_DA_STO2_CLK_SEL_SFT 8
  1390. #define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4)
  1391. #define RT5665_DA_MONOL_CLK_SEL_SFT 4
  1392. #define RT5665_DA_MONOR_CLK_SEL_MASK (0x7)
  1393. #define RT5665_DA_MONOR_CLK_SEL_SFT 0
  1394. /* PLL tracking mode 3 (0x0085)*/
  1395. #define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
  1396. #define RT5665_AD_STO1_CLK_SEL_SFT 12
  1397. #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
  1398. #define RT5665_AD_STO2_CLK_SEL_SFT 8
  1399. #define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4)
  1400. #define RT5665_AD_MONOL_CLK_SEL_SFT 4
  1401. #define RT5665_AD_MONOR_CLK_SEL_MASK (0x7)
  1402. #define RT5665_AD_MONOR_CLK_SEL_SFT 0
  1403. /* ASRC Control 4 (0x0086) */
  1404. #define RT5665_I2S1_RATE_MASK (0xf << 12)
  1405. #define RT5665_I2S1_RATE_SFT 12
  1406. #define RT5665_I2S2_RATE_MASK (0xf << 8)
  1407. #define RT5665_I2S2_RATE_SFT 8
  1408. #define RT5665_I2S3_RATE_MASK (0xf << 4)
  1409. #define RT5665_I2S3_RATE_SFT 4
  1410. /* Depop Mode Control 1 (0x008e) */
  1411. #define RT5665_PUMP_EN (0x1 << 3)
  1412. /* Depop Mode Control 2 (0x8f) */
  1413. #define RT5665_DEPOP_MASK (0x1 << 13)
  1414. #define RT5665_DEPOP_SFT 13
  1415. #define RT5665_DEPOP_AUTO (0x0 << 13)
  1416. #define RT5665_DEPOP_MAN (0x1 << 13)
  1417. #define RT5665_RAMP_MASK (0x1 << 12)
  1418. #define RT5665_RAMP_SFT 12
  1419. #define RT5665_RAMP_DIS (0x0 << 12)
  1420. #define RT5665_RAMP_EN (0x1 << 12)
  1421. #define RT5665_BPS_MASK (0x1 << 11)
  1422. #define RT5665_BPS_SFT 11
  1423. #define RT5665_BPS_DIS (0x0 << 11)
  1424. #define RT5665_BPS_EN (0x1 << 11)
  1425. #define RT5665_FAST_UPDN_MASK (0x1 << 10)
  1426. #define RT5665_FAST_UPDN_SFT 10
  1427. #define RT5665_FAST_UPDN_DIS (0x0 << 10)
  1428. #define RT5665_FAST_UPDN_EN (0x1 << 10)
  1429. #define RT5665_MRES_MASK (0x3 << 8)
  1430. #define RT5665_MRES_SFT 8
  1431. #define RT5665_MRES_15MO (0x0 << 8)
  1432. #define RT5665_MRES_25MO (0x1 << 8)
  1433. #define RT5665_MRES_35MO (0x2 << 8)
  1434. #define RT5665_MRES_45MO (0x3 << 8)
  1435. #define RT5665_VLO_MASK (0x1 << 7)
  1436. #define RT5665_VLO_SFT 7
  1437. #define RT5665_VLO_3V (0x0 << 7)
  1438. #define RT5665_VLO_32V (0x1 << 7)
  1439. #define RT5665_DIG_DP_MASK (0x1 << 6)
  1440. #define RT5665_DIG_DP_SFT 6
  1441. #define RT5665_DIG_DP_DIS (0x0 << 6)
  1442. #define RT5665_DIG_DP_EN (0x1 << 6)
  1443. #define RT5665_DP_TH_MASK (0x3 << 4)
  1444. #define RT5665_DP_TH_SFT 4
  1445. /* Depop Mode Control 3 (0x90) */
  1446. #define RT5665_CP_SYS_MASK (0x7 << 12)
  1447. #define RT5665_CP_SYS_SFT 12
  1448. #define RT5665_CP_FQ1_MASK (0x7 << 8)
  1449. #define RT5665_CP_FQ1_SFT 8
  1450. #define RT5665_CP_FQ2_MASK (0x7 << 4)
  1451. #define RT5665_CP_FQ2_SFT 4
  1452. #define RT5665_CP_FQ3_MASK (0x7)
  1453. #define RT5665_CP_FQ3_SFT 0
  1454. #define RT5665_CP_FQ_1_5_KHZ 0
  1455. #define RT5665_CP_FQ_3_KHZ 1
  1456. #define RT5665_CP_FQ_6_KHZ 2
  1457. #define RT5665_CP_FQ_12_KHZ 3
  1458. #define RT5665_CP_FQ_24_KHZ 4
  1459. #define RT5665_CP_FQ_48_KHZ 5
  1460. #define RT5665_CP_FQ_96_KHZ 6
  1461. #define RT5665_CP_FQ_192_KHZ 7
  1462. /* HPOUT charge pump 1 (0x0091) */
  1463. #define RT5665_OSW_L_MASK (0x1 << 11)
  1464. #define RT5665_OSW_L_SFT 11
  1465. #define RT5665_OSW_L_DIS (0x0 << 11)
  1466. #define RT5665_OSW_L_EN (0x1 << 11)
  1467. #define RT5665_OSW_R_MASK (0x1 << 10)
  1468. #define RT5665_OSW_R_SFT 10
  1469. #define RT5665_OSW_R_DIS (0x0 << 10)
  1470. #define RT5665_OSW_R_EN (0x1 << 10)
  1471. #define RT5665_PM_HP_MASK (0x3 << 8)
  1472. #define RT5665_PM_HP_SFT 8
  1473. #define RT5665_PM_HP_LV (0x0 << 8)
  1474. #define RT5665_PM_HP_MV (0x1 << 8)
  1475. #define RT5665_PM_HP_HV (0x2 << 8)
  1476. #define RT5665_IB_HP_MASK (0x3 << 6)
  1477. #define RT5665_IB_HP_SFT 6
  1478. #define RT5665_IB_HP_125IL (0x0 << 6)
  1479. #define RT5665_IB_HP_25IL (0x1 << 6)
  1480. #define RT5665_IB_HP_5IL (0x2 << 6)
  1481. #define RT5665_IB_HP_1IL (0x3 << 6)
  1482. /* PV detection and SPK gain control (0x92) */
  1483. #define RT5665_PVDD_DET_MASK (0x1 << 15)
  1484. #define RT5665_PVDD_DET_SFT 15
  1485. #define RT5665_PVDD_DET_DIS (0x0 << 15)
  1486. #define RT5665_PVDD_DET_EN (0x1 << 15)
  1487. #define RT5665_SPK_AG_MASK (0x1 << 14)
  1488. #define RT5665_SPK_AG_SFT 14
  1489. #define RT5665_SPK_AG_DIS (0x0 << 14)
  1490. #define RT5665_SPK_AG_EN (0x1 << 14)
  1491. /* Micbias Control1 (0x93) */
  1492. #define RT5665_MIC1_BS_MASK (0x1 << 15)
  1493. #define RT5665_MIC1_BS_SFT 15
  1494. #define RT5665_MIC1_BS_9AV (0x0 << 15)
  1495. #define RT5665_MIC1_BS_75AV (0x1 << 15)
  1496. #define RT5665_MIC2_BS_MASK (0x1 << 14)
  1497. #define RT5665_MIC2_BS_SFT 14
  1498. #define RT5665_MIC2_BS_9AV (0x0 << 14)
  1499. #define RT5665_MIC2_BS_75AV (0x1 << 14)
  1500. #define RT5665_MIC1_CLK_MASK (0x1 << 13)
  1501. #define RT5665_MIC1_CLK_SFT 13
  1502. #define RT5665_MIC1_CLK_DIS (0x0 << 13)
  1503. #define RT5665_MIC1_CLK_EN (0x1 << 13)
  1504. #define RT5665_MIC2_CLK_MASK (0x1 << 12)
  1505. #define RT5665_MIC2_CLK_SFT 12
  1506. #define RT5665_MIC2_CLK_DIS (0x0 << 12)
  1507. #define RT5665_MIC2_CLK_EN (0x1 << 12)
  1508. #define RT5665_MIC1_OVCD_MASK (0x1 << 11)
  1509. #define RT5665_MIC1_OVCD_SFT 11
  1510. #define RT5665_MIC1_OVCD_DIS (0x0 << 11)
  1511. #define RT5665_MIC1_OVCD_EN (0x1 << 11)
  1512. #define RT5665_MIC1_OVTH_MASK (0x3 << 9)
  1513. #define RT5665_MIC1_OVTH_SFT 9
  1514. #define RT5665_MIC1_OVTH_600UA (0x0 << 9)
  1515. #define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
  1516. #define RT5665_MIC1_OVTH_2000UA (0x2 << 9)
  1517. #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
  1518. #define RT5665_MIC2_OVCD_SFT 8
  1519. #define RT5665_MIC2_OVCD_DIS (0x0 << 8)
  1520. #define RT5665_MIC2_OVCD_EN (0x1 << 8)
  1521. #define RT5665_MIC2_OVTH_MASK (0x3 << 6)
  1522. #define RT5665_MIC2_OVTH_SFT 6
  1523. #define RT5665_MIC2_OVTH_600UA (0x0 << 6)
  1524. #define RT5665_MIC2_OVTH_1500UA (0x1 << 6)
  1525. #define RT5665_MIC2_OVTH_2000UA (0x2 << 6)
  1526. #define RT5665_PWR_MB_MASK (0x1 << 5)
  1527. #define RT5665_PWR_MB_SFT 5
  1528. #define RT5665_PWR_MB_PD (0x0 << 5)
  1529. #define RT5665_PWR_MB_PU (0x1 << 5)
  1530. /* Micbias Control2 (0x94) */
  1531. #define RT5665_PWR_CLK25M_MASK (0x1 << 9)
  1532. #define RT5665_PWR_CLK25M_SFT 9
  1533. #define RT5665_PWR_CLK25M_PD (0x0 << 9)
  1534. #define RT5665_PWR_CLK25M_PU (0x1 << 9)
  1535. #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
  1536. #define RT5665_PWR_CLK1M_SFT 8
  1537. #define RT5665_PWR_CLK1M_PD (0x0 << 8)
  1538. #define RT5665_PWR_CLK1M_PU (0x1 << 8)
  1539. /* I2S Master Mode Clock Control 1 (0x00a0) */
  1540. #define RT5665_CLK_SRC_MCLK (0x0)
  1541. #define RT5665_CLK_SRC_PLL1 (0x1)
  1542. #define RT5665_CLK_SRC_RCCLK (0x2)
  1543. #define RT5665_I2S_PD_1 (0x0)
  1544. #define RT5665_I2S_PD_2 (0x1)
  1545. #define RT5665_I2S_PD_3 (0x2)
  1546. #define RT5665_I2S_PD_4 (0x3)
  1547. #define RT5665_I2S_PD_6 (0x4)
  1548. #define RT5665_I2S_PD_8 (0x5)
  1549. #define RT5665_I2S_PD_12 (0x6)
  1550. #define RT5665_I2S_PD_16 (0x7)
  1551. #define RT5665_I2S2_SRC_MASK (0x3 << 12)
  1552. #define RT5665_I2S2_SRC_SFT 12
  1553. #define RT5665_I2S2_M_PD_MASK (0x7 << 8)
  1554. #define RT5665_I2S2_M_PD_SFT 8
  1555. #define RT5665_I2S3_SRC_MASK (0x3 << 4)
  1556. #define RT5665_I2S3_SRC_SFT 4
  1557. #define RT5665_I2S3_M_PD_MASK (0x7 << 0)
  1558. #define RT5665_I2S3_M_PD_SFT 0
  1559. /* EQ Control 1 (0x00b0) */
  1560. #define RT5665_EQ_SRC_DAC (0x0 << 15)
  1561. #define RT5665_EQ_SRC_ADC (0x1 << 15)
  1562. #define RT5665_EQ_UPD (0x1 << 14)
  1563. #define RT5665_EQ_UPD_BIT 14
  1564. #define RT5665_EQ_CD_MASK (0x1 << 13)
  1565. #define RT5665_EQ_CD_SFT 13
  1566. #define RT5665_EQ_CD_DIS (0x0 << 13)
  1567. #define RT5665_EQ_CD_EN (0x1 << 13)
  1568. #define RT5665_EQ_DITH_MASK (0x3 << 8)
  1569. #define RT5665_EQ_DITH_SFT 8
  1570. #define RT5665_EQ_DITH_NOR (0x0 << 8)
  1571. #define RT5665_EQ_DITH_LSB (0x1 << 8)
  1572. #define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
  1573. #define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
  1574. /* IRQ Control 1 (0x00b7) */
  1575. #define RT5665_JD1_1_EN_MASK (0x1 << 15)
  1576. #define RT5665_JD1_1_EN_SFT 15
  1577. #define RT5665_JD1_1_DIS (0x0 << 15)
  1578. #define RT5665_JD1_1_EN (0x1 << 15)
  1579. #define RT5665_JD1_2_EN_MASK (0x1 << 12)
  1580. #define RT5665_JD1_2_EN_SFT 12
  1581. #define RT5665_JD1_2_DIS (0x0 << 12)
  1582. #define RT5665_JD1_2_EN (0x1 << 12)
  1583. /* IRQ Control 2 (0x00b8) */
  1584. #define RT5665_IL_IRQ_MASK (0x1 << 6)
  1585. #define RT5665_IL_IRQ_DIS (0x0 << 6)
  1586. #define RT5665_IL_IRQ_EN (0x1 << 6)
  1587. /* IRQ Control 5 (0x00ba) */
  1588. #define RT5665_IRQ_JD_EN (0x1 << 3)
  1589. #define RT5665_IRQ_JD_EN_SFT 3
  1590. /* GPIO Control 1 (0x00c0) */
  1591. #define RT5665_GP1_PIN_MASK (0x1 << 15)
  1592. #define RT5665_GP1_PIN_SFT 15
  1593. #define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
  1594. #define RT5665_GP1_PIN_IRQ (0x1 << 15)
  1595. #define RT5665_GP2_PIN_MASK (0x3 << 13)
  1596. #define RT5665_GP2_PIN_SFT 13
  1597. #define RT5665_GP2_PIN_GPIO2 (0x0 << 13)
  1598. #define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
  1599. #define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)
  1600. #define RT5665_GP3_PIN_MASK (0x3 << 11)
  1601. #define RT5665_GP3_PIN_SFT 11
  1602. #define RT5665_GP3_PIN_GPIO3 (0x0 << 11)
  1603. #define RT5665_GP3_PIN_LRCK2 (0x1 << 11)
  1604. #define RT5665_GP3_PIN_PDM_SDA (0x2 << 11)
  1605. #define RT5665_GP4_PIN_MASK (0x3 << 9)
  1606. #define RT5665_GP4_PIN_SFT 9
  1607. #define RT5665_GP4_PIN_GPIO4 (0x0 << 9)
  1608. #define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
  1609. #define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)
  1610. #define RT5665_GP5_PIN_MASK (0x3 << 7)
  1611. #define RT5665_GP5_PIN_SFT 7
  1612. #define RT5665_GP5_PIN_GPIO5 (0x0 << 7)
  1613. #define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)
  1614. #define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7)
  1615. #define RT5665_GP6_PIN_MASK (0x3 << 5)
  1616. #define RT5665_GP6_PIN_SFT 5
  1617. #define RT5665_GP6_PIN_GPIO6 (0x0 << 5)
  1618. #define RT5665_GP6_PIN_BCLK3 (0x1 << 5)
  1619. #define RT5665_GP6_PIN_PDM_SCL (0x2 << 5)
  1620. #define RT5665_GP7_PIN_MASK (0x3 << 3)
  1621. #define RT5665_GP7_PIN_SFT 3
  1622. #define RT5665_GP7_PIN_GPIO7 (0x0 << 3)
  1623. #define RT5665_GP7_PIN_LRCK3 (0x1 << 3)
  1624. #define RT5665_GP7_PIN_PDM_SDA (0x2 << 3)
  1625. #define RT5665_GP8_PIN_MASK (0x3 << 1)
  1626. #define RT5665_GP8_PIN_SFT 1
  1627. #define RT5665_GP8_PIN_GPIO8 (0x0 << 1)
  1628. #define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)
  1629. #define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1)
  1630. #define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1)
  1631. /* GPIO Control 2 (0x00c1)*/
  1632. #define RT5665_GP9_PIN_MASK (0x3 << 14)
  1633. #define RT5665_GP9_PIN_SFT 14
  1634. #define RT5665_GP9_PIN_GPIO9 (0x0 << 14)
  1635. #define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)
  1636. #define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14)
  1637. #define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14)
  1638. #define RT5665_GP10_PIN_MASK (0x3 << 12)
  1639. #define RT5665_GP10_PIN_SFT 12
  1640. #define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
  1641. #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
  1642. #define RT5665_GP10_PIN_LPD (0x2 << 12)
  1643. #define RT5665_GP1_PF_MASK (0x1 << 11)
  1644. #define RT5665_GP1_PF_IN (0x0 << 11)
  1645. #define RT5665_GP1_PF_OUT (0x1 << 11)
  1646. #define RT5665_GP1_OUT_MASK (0x1 << 10)
  1647. #define RT5665_GP1_OUT_H (0x0 << 10)
  1648. #define RT5665_GP1_OUT_L (0x1 << 10)
  1649. #define RT5665_GP2_PF_MASK (0x1 << 9)
  1650. #define RT5665_GP2_PF_IN (0x0 << 9)
  1651. #define RT5665_GP2_PF_OUT (0x1 << 9)
  1652. #define RT5665_GP2_OUT_MASK (0x1 << 8)
  1653. #define RT5665_GP2_OUT_H (0x0 << 8)
  1654. #define RT5665_GP2_OUT_L (0x1 << 8)
  1655. #define RT5665_GP3_PF_MASK (0x1 << 7)
  1656. #define RT5665_GP3_PF_IN (0x0 << 7)
  1657. #define RT5665_GP3_PF_OUT (0x1 << 7)
  1658. #define RT5665_GP3_OUT_MASK (0x1 << 6)
  1659. #define RT5665_GP3_OUT_H (0x0 << 6)
  1660. #define RT5665_GP3_OUT_L (0x1 << 6)
  1661. #define RT5665_GP4_PF_MASK (0x1 << 5)
  1662. #define RT5665_GP4_PF_IN (0x0 << 5)
  1663. #define RT5665_GP4_PF_OUT (0x1 << 5)
  1664. #define RT5665_GP4_OUT_MASK (0x1 << 4)
  1665. #define RT5665_GP4_OUT_H (0x0 << 4)
  1666. #define RT5665_GP4_OUT_L (0x1 << 4)
  1667. #define RT5665_GP5_PF_MASK (0x1 << 3)
  1668. #define RT5665_GP5_PF_IN (0x0 << 3)
  1669. #define RT5665_GP5_PF_OUT (0x1 << 3)
  1670. #define RT5665_GP5_OUT_MASK (0x1 << 2)
  1671. #define RT5665_GP5_OUT_H (0x0 << 2)
  1672. #define RT5665_GP5_OUT_L (0x1 << 2)
  1673. #define RT5665_GP6_PF_MASK (0x1 << 1)
  1674. #define RT5665_GP6_PF_IN (0x0 << 1)
  1675. #define RT5665_GP6_PF_OUT (0x1 << 1)
  1676. #define RT5665_GP6_OUT_MASK (0x1)
  1677. #define RT5665_GP6_OUT_H (0x0)
  1678. #define RT5665_GP6_OUT_L (0x1)
  1679. /* GPIO Control 3 (0x00c2) */
  1680. #define RT5665_GP7_PF_MASK (0x1 << 15)
  1681. #define RT5665_GP7_PF_IN (0x0 << 15)
  1682. #define RT5665_GP7_PF_OUT (0x1 << 15)
  1683. #define RT5665_GP7_OUT_MASK (0x1 << 14)
  1684. #define RT5665_GP7_OUT_H (0x0 << 14)
  1685. #define RT5665_GP7_OUT_L (0x1 << 14)
  1686. #define RT5665_GP8_PF_MASK (0x1 << 13)
  1687. #define RT5665_GP8_PF_IN (0x0 << 13)
  1688. #define RT5665_GP8_PF_OUT (0x1 << 13)
  1689. #define RT5665_GP8_OUT_MASK (0x1 << 12)
  1690. #define RT5665_GP8_OUT_H (0x0 << 12)
  1691. #define RT5665_GP8_OUT_L (0x1 << 12)
  1692. #define RT5665_GP9_PF_MASK (0x1 << 11)
  1693. #define RT5665_GP9_PF_IN (0x0 << 11)
  1694. #define RT5665_GP9_PF_OUT (0x1 << 11)
  1695. #define RT5665_GP9_OUT_MASK (0x1 << 10)
  1696. #define RT5665_GP9_OUT_H (0x0 << 10)
  1697. #define RT5665_GP9_OUT_L (0x1 << 10)
  1698. #define RT5665_GP10_PF_MASK (0x1 << 9)
  1699. #define RT5665_GP10_PF_IN (0x0 << 9)
  1700. #define RT5665_GP10_PF_OUT (0x1 << 9)
  1701. #define RT5665_GP10_OUT_MASK (0x1 << 8)
  1702. #define RT5665_GP10_OUT_H (0x0 << 8)
  1703. #define RT5665_GP10_OUT_L (0x1 << 8)
  1704. #define RT5665_GP11_PF_MASK (0x1 << 7)
  1705. #define RT5665_GP11_PF_IN (0x0 << 7)
  1706. #define RT5665_GP11_PF_OUT (0x1 << 7)
  1707. #define RT5665_GP11_OUT_MASK (0x1 << 6)
  1708. #define RT5665_GP11_OUT_H (0x0 << 6)
  1709. #define RT5665_GP11_OUT_L (0x1 << 6)
  1710. /* Soft volume and zero cross control 1 (0x00d9) */
  1711. #define RT5665_SV_MASK (0x1 << 15)
  1712. #define RT5665_SV_SFT 15
  1713. #define RT5665_SV_DIS (0x0 << 15)
  1714. #define RT5665_SV_EN (0x1 << 15)
  1715. #define RT5665_OUT_SV_MASK (0x1 << 13)
  1716. #define RT5665_OUT_SV_SFT 13
  1717. #define RT5665_OUT_SV_DIS (0x0 << 13)
  1718. #define RT5665_OUT_SV_EN (0x1 << 13)
  1719. #define RT5665_HP_SV_MASK (0x1 << 12)
  1720. #define RT5665_HP_SV_SFT 12
  1721. #define RT5665_HP_SV_DIS (0x0 << 12)
  1722. #define RT5665_HP_SV_EN (0x1 << 12)
  1723. #define RT5665_ZCD_DIG_MASK (0x1 << 11)
  1724. #define RT5665_ZCD_DIG_SFT 11
  1725. #define RT5665_ZCD_DIG_DIS (0x0 << 11)
  1726. #define RT5665_ZCD_DIG_EN (0x1 << 11)
  1727. #define RT5665_ZCD_MASK (0x1 << 10)
  1728. #define RT5665_ZCD_SFT 10
  1729. #define RT5665_ZCD_PD (0x0 << 10)
  1730. #define RT5665_ZCD_PU (0x1 << 10)
  1731. #define RT5665_SV_DLY_MASK (0xf)
  1732. #define RT5665_SV_DLY_SFT 0
  1733. /* Soft volume and zero cross control 2 (0x00da) */
  1734. #define RT5665_ZCD_HP_MASK (0x1 << 15)
  1735. #define RT5665_ZCD_HP_SFT 15
  1736. #define RT5665_ZCD_HP_DIS (0x0 << 15)
  1737. #define RT5665_ZCD_HP_EN (0x1 << 15)
  1738. /* 4 Button Inline Command Control 2 (0x00e0) */
  1739. #define RT5665_4BTN_IL_MASK (0x1 << 15)
  1740. #define RT5665_4BTN_IL_EN (0x1 << 15)
  1741. #define RT5665_4BTN_IL_DIS (0x0 << 15)
  1742. #define RT5665_4BTN_IL_RST_MASK (0x1 << 14)
  1743. #define RT5665_4BTN_IL_NOR (0x1 << 14)
  1744. #define RT5665_4BTN_IL_RST (0x0 << 14)
  1745. /* Analog JD Control 1 (0x00f0) */
  1746. #define RT5665_JD1_MODE_MASK (0x3 << 0)
  1747. #define RT5665_JD1_MODE_0 (0x0 << 0)
  1748. #define RT5665_JD1_MODE_1 (0x1 << 0)
  1749. #define RT5665_JD1_MODE_2 (0x2 << 0)
  1750. /* Jack Detect Control 3 (0x00f8) */
  1751. #define RT5665_JD_TRI_HPO_SEL_MASK (0x7)
  1752. #define RT5665_JD_TRI_HPO_SEL_SFT (0)
  1753. #define RT5665_JD_HPO_GPIO_JD1 (0x0)
  1754. #define RT5665_JD_HPO_JD1_1 (0x1)
  1755. #define RT5665_JD_HPO_JD1_2 (0x2)
  1756. #define RT5665_JD_HPO_JD2 (0x3)
  1757. #define RT5665_JD_HPO_GPIO_JD2 (0x4)
  1758. #define RT5665_JD_HPO_JD3 (0x5)
  1759. #define RT5665_JD_HPO_JD_D (0x6)
  1760. /* Digital Misc Control (0x00fa) */
  1761. #define RT5665_AM_MASK (0x1 << 7)
  1762. #define RT5665_AM_EN (0x1 << 7)
  1763. #define RT5665_AM_DIS (0x1 << 7)
  1764. #define RT5665_DIG_GATE_CTRL 0x1
  1765. #define RT5665_DIG_GATE_CTRL_SFT (0)
  1766. /* Chopper and Clock control for ADC (0x011c)*/
  1767. #define RT5665_M_RF_DIG_MASK (0x1 << 12)
  1768. #define RT5665_M_RF_DIG_SFT 12
  1769. #define RT5665_M_RI_DIG (0x1 << 11)
  1770. /* Chopper and Clock control for DAC (0x013a)*/
  1771. #define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
  1772. #define RT5665_CKXEN_DAC1_SFT 13
  1773. #define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
  1774. #define RT5665_CKGEN_DAC1_SFT 12
  1775. #define RT5665_CKXEN_DAC2_MASK (0x1 << 5)
  1776. #define RT5665_CKXEN_DAC2_SFT 5
  1777. #define RT5665_CKGEN_DAC2_MASK (0x1 << 4)
  1778. #define RT5665_CKGEN_DAC2_SFT 4
  1779. /* Chopper and Clock control for ADC (0x013b)*/
  1780. #define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
  1781. #define RT5665_CKXEN_ADC1_SFT 13
  1782. #define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
  1783. #define RT5665_CKGEN_ADC1_SFT 12
  1784. #define RT5665_CKXEN_ADC2_MASK (0x1 << 5)
  1785. #define RT5665_CKXEN_ADC2_SFT 5
  1786. #define RT5665_CKGEN_ADC2_MASK (0x1 << 4)
  1787. #define RT5665_CKGEN_ADC2_SFT 4
  1788. /* Volume test (0x013f)*/
  1789. #define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
  1790. #define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
  1791. #define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
  1792. /* Test Mode Control 1 (0x0145) */
  1793. #define RT5665_AD2DA_LB_MASK (0x1 << 9)
  1794. #define RT5665_AD2DA_LB_SFT 9
  1795. /* Stereo Noise Gate Control 1 (0x0160) */
  1796. #define RT5665_NG2_EN_MASK (0x1 << 15)
  1797. #define RT5665_NG2_EN (0x1 << 15)
  1798. #define RT5665_NG2_DIS (0x0 << 15)
  1799. /* Stereo1 DAC Silence Detection Control (0x0190) */
  1800. #define RT5665_DEB_STO_DAC_MASK (0x7 << 4)
  1801. #define RT5665_DEB_80_MS (0x0 << 4)
  1802. /* SAR ADC Inline Command Control 1 (0x0210) */
  1803. #define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
  1804. #define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
  1805. #define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
  1806. #define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)
  1807. #define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)
  1808. #define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14)
  1809. #define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
  1810. #define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
  1811. #define RT5665_SAR_BUTDET_RST (0x0 << 13)
  1812. #define RT5665_SAR_POW_MASK (0x1 << 12)
  1813. #define RT5665_SAR_POW_EN (0x1 << 12)
  1814. #define RT5665_SAR_POW_DIS (0x0 << 12)
  1815. #define RT5665_SAR_RST_MASK (0x1 << 11)
  1816. #define RT5665_SAR_RST_NORMAL (0x1 << 11)
  1817. #define RT5665_SAR_RST (0x0 << 11)
  1818. #define RT5665_SAR_BYPASS_MASK (0x1 << 10)
  1819. #define RT5665_SAR_BYPASS_EN (0x1 << 10)
  1820. #define RT5665_SAR_BYPASS_DIS (0x0 << 10)
  1821. #define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
  1822. #define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
  1823. #define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)
  1824. #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
  1825. #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
  1826. #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)
  1827. #define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)
  1828. #define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)
  1829. #define RT5665_SAR_SEL_MODE_ADC (0x0 << 7)
  1830. #define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
  1831. #define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
  1832. #define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
  1833. #define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)
  1834. #define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
  1835. #define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4)
  1836. /* System Clock Source */
  1837. enum {
  1838. RT5665_SCLK_S_MCLK,
  1839. RT5665_SCLK_S_PLL1,
  1840. RT5665_SCLK_S_RCCLK,
  1841. };
  1842. /* PLL1 Source */
  1843. enum {
  1844. RT5665_PLL1_S_MCLK,
  1845. RT5665_PLL1_S_BCLK1,
  1846. RT5665_PLL1_S_BCLK2,
  1847. RT5665_PLL1_S_BCLK3,
  1848. RT5665_PLL1_S_BCLK4,
  1849. };
  1850. enum {
  1851. RT5665_AIF1_1,
  1852. RT5665_AIF1_2,
  1853. RT5665_AIF2_1,
  1854. RT5665_AIF2_2,
  1855. RT5665_AIF3,
  1856. RT5665_AIFS
  1857. };
  1858. enum {
  1859. CODEC_5665,
  1860. CODEC_5666,
  1861. };
  1862. /* filter mask */
  1863. enum {
  1864. RT5665_DA_STEREO1_FILTER = 0x1,
  1865. RT5665_DA_STEREO2_FILTER = (0x1 << 1),
  1866. RT5665_DA_MONO_L_FILTER = (0x1 << 2),
  1867. RT5665_DA_MONO_R_FILTER = (0x1 << 3),
  1868. RT5665_AD_STEREO1_FILTER = (0x1 << 4),
  1869. RT5665_AD_STEREO2_FILTER = (0x1 << 5),
  1870. RT5665_AD_MONO_L_FILTER = (0x1 << 6),
  1871. RT5665_AD_MONO_R_FILTER = (0x1 << 7),
  1872. };
  1873. enum {
  1874. RT5665_CLK_SEL_SYS,
  1875. RT5665_CLK_SEL_I2S1_ASRC,
  1876. RT5665_CLK_SEL_I2S2_ASRC,
  1877. RT5665_CLK_SEL_I2S3_ASRC,
  1878. RT5665_CLK_SEL_SYS2,
  1879. RT5665_CLK_SEL_SYS3,
  1880. RT5665_CLK_SEL_SYS4,
  1881. };
  1882. int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,
  1883. unsigned int filter_mask, unsigned int clk_src);
  1884. #endif /* __RT5665_H__ */