rt5665.c 157 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2016 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/acpi.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/mutex.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/jack.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <sound/rt5665.h>
  30. #include "rl6231.h"
  31. #include "rt5665.h"
  32. #define RT5665_NUM_SUPPLIES 3
  33. static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
  34. "AVDD",
  35. "MICVDD",
  36. "VBAT",
  37. };
  38. struct rt5665_priv {
  39. struct snd_soc_component *component;
  40. struct rt5665_platform_data pdata;
  41. struct regmap *regmap;
  42. struct gpio_desc *gpiod_ldo1_en;
  43. struct gpio_desc *gpiod_reset;
  44. struct snd_soc_jack *hs_jack;
  45. struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
  46. struct delayed_work jack_detect_work;
  47. struct delayed_work calibrate_work;
  48. struct delayed_work jd_check_work;
  49. struct mutex calibrate_mutex;
  50. int sysclk;
  51. int sysclk_src;
  52. int lrck[RT5665_AIFS];
  53. int bclk[RT5665_AIFS];
  54. int master[RT5665_AIFS];
  55. int id;
  56. int pll_src;
  57. int pll_in;
  58. int pll_out;
  59. int jack_type;
  60. int irq_work_delay_time;
  61. unsigned int sar_adc_value;
  62. bool calibration_done;
  63. };
  64. static const struct reg_default rt5665_reg[] = {
  65. {0x0000, 0x0000},
  66. {0x0001, 0xc8c8},
  67. {0x0002, 0x8080},
  68. {0x0003, 0x8000},
  69. {0x0004, 0xc80a},
  70. {0x0005, 0x0000},
  71. {0x0006, 0x0000},
  72. {0x0007, 0x0000},
  73. {0x000a, 0x0000},
  74. {0x000b, 0x0000},
  75. {0x000c, 0x0000},
  76. {0x000d, 0x0000},
  77. {0x000f, 0x0808},
  78. {0x0010, 0x4040},
  79. {0x0011, 0x0000},
  80. {0x0012, 0x1404},
  81. {0x0013, 0x1000},
  82. {0x0014, 0xa00a},
  83. {0x0015, 0x0404},
  84. {0x0016, 0x0404},
  85. {0x0017, 0x0011},
  86. {0x0018, 0xafaf},
  87. {0x0019, 0xafaf},
  88. {0x001a, 0xafaf},
  89. {0x001b, 0x0011},
  90. {0x001c, 0x2f2f},
  91. {0x001d, 0x2f2f},
  92. {0x001e, 0x2f2f},
  93. {0x001f, 0x0000},
  94. {0x0020, 0x0000},
  95. {0x0021, 0x0000},
  96. {0x0022, 0x5757},
  97. {0x0023, 0x0039},
  98. {0x0026, 0xc0c0},
  99. {0x0027, 0xc0c0},
  100. {0x0028, 0xc0c0},
  101. {0x0029, 0x8080},
  102. {0x002a, 0xaaaa},
  103. {0x002b, 0xaaaa},
  104. {0x002c, 0xaba8},
  105. {0x002d, 0x0000},
  106. {0x002e, 0x0000},
  107. {0x002f, 0x0000},
  108. {0x0030, 0x0000},
  109. {0x0031, 0x5000},
  110. {0x0032, 0x0000},
  111. {0x0033, 0x0000},
  112. {0x0034, 0x0000},
  113. {0x0035, 0x0000},
  114. {0x003a, 0x0000},
  115. {0x003b, 0x0000},
  116. {0x003c, 0x00ff},
  117. {0x003d, 0x0000},
  118. {0x003e, 0x00ff},
  119. {0x003f, 0x0000},
  120. {0x0040, 0x0000},
  121. {0x0041, 0x00ff},
  122. {0x0042, 0x0000},
  123. {0x0043, 0x00ff},
  124. {0x0044, 0x0c0c},
  125. {0x0049, 0xc00b},
  126. {0x004a, 0x0000},
  127. {0x004b, 0x031f},
  128. {0x004d, 0x0000},
  129. {0x004e, 0x001f},
  130. {0x004f, 0x0000},
  131. {0x0050, 0x001f},
  132. {0x0052, 0xf000},
  133. {0x0061, 0x0000},
  134. {0x0062, 0x0000},
  135. {0x0063, 0x003e},
  136. {0x0064, 0x0000},
  137. {0x0065, 0x0000},
  138. {0x0066, 0x003f},
  139. {0x0067, 0x0000},
  140. {0x006b, 0x0000},
  141. {0x006d, 0xff00},
  142. {0x006e, 0x2808},
  143. {0x006f, 0x000a},
  144. {0x0070, 0x8000},
  145. {0x0071, 0x8000},
  146. {0x0072, 0x8000},
  147. {0x0073, 0x7000},
  148. {0x0074, 0x7770},
  149. {0x0075, 0x0002},
  150. {0x0076, 0x0001},
  151. {0x0078, 0x00f0},
  152. {0x0079, 0x0000},
  153. {0x007a, 0x0000},
  154. {0x007b, 0x0000},
  155. {0x007c, 0x0000},
  156. {0x007d, 0x0123},
  157. {0x007e, 0x4500},
  158. {0x007f, 0x8003},
  159. {0x0080, 0x0000},
  160. {0x0081, 0x0000},
  161. {0x0082, 0x0000},
  162. {0x0083, 0x0000},
  163. {0x0084, 0x0000},
  164. {0x0085, 0x0000},
  165. {0x0086, 0x0008},
  166. {0x0087, 0x0000},
  167. {0x0088, 0x0000},
  168. {0x0089, 0x0000},
  169. {0x008a, 0x0000},
  170. {0x008b, 0x0000},
  171. {0x008c, 0x0003},
  172. {0x008e, 0x0060},
  173. {0x008f, 0x1000},
  174. {0x0091, 0x0c26},
  175. {0x0092, 0x0073},
  176. {0x0093, 0x0000},
  177. {0x0094, 0x0080},
  178. {0x0098, 0x0000},
  179. {0x0099, 0x0000},
  180. {0x009a, 0x0007},
  181. {0x009f, 0x0000},
  182. {0x00a0, 0x0000},
  183. {0x00a1, 0x0002},
  184. {0x00a2, 0x0001},
  185. {0x00a3, 0x0002},
  186. {0x00a4, 0x0001},
  187. {0x00ae, 0x2040},
  188. {0x00af, 0x0000},
  189. {0x00b6, 0x0000},
  190. {0x00b7, 0x0000},
  191. {0x00b8, 0x0000},
  192. {0x00b9, 0x0000},
  193. {0x00ba, 0x0002},
  194. {0x00bb, 0x0000},
  195. {0x00be, 0x0000},
  196. {0x00c0, 0x0000},
  197. {0x00c1, 0x0aaa},
  198. {0x00c2, 0xaa80},
  199. {0x00c3, 0x0003},
  200. {0x00c4, 0x0000},
  201. {0x00d0, 0x0000},
  202. {0x00d1, 0x2244},
  203. {0x00d3, 0x3300},
  204. {0x00d4, 0x2200},
  205. {0x00d9, 0x0809},
  206. {0x00da, 0x0000},
  207. {0x00db, 0x0008},
  208. {0x00dc, 0x00c0},
  209. {0x00dd, 0x6724},
  210. {0x00de, 0x3131},
  211. {0x00df, 0x0008},
  212. {0x00e0, 0x4000},
  213. {0x00e1, 0x3131},
  214. {0x00e2, 0x600c},
  215. {0x00ea, 0xb320},
  216. {0x00eb, 0x0000},
  217. {0x00ec, 0xb300},
  218. {0x00ed, 0x0000},
  219. {0x00ee, 0xb320},
  220. {0x00ef, 0x0000},
  221. {0x00f0, 0x0201},
  222. {0x00f1, 0x0ddd},
  223. {0x00f2, 0x0ddd},
  224. {0x00f6, 0x0000},
  225. {0x00f7, 0x0000},
  226. {0x00f8, 0x0000},
  227. {0x00fa, 0x0000},
  228. {0x00fb, 0x0000},
  229. {0x00fc, 0x0000},
  230. {0x00fd, 0x0000},
  231. {0x00fe, 0x10ec},
  232. {0x00ff, 0x6451},
  233. {0x0100, 0xaaaa},
  234. {0x0101, 0x000a},
  235. {0x010a, 0xaaaa},
  236. {0x010b, 0xa0a0},
  237. {0x010c, 0xaeae},
  238. {0x010d, 0xaaaa},
  239. {0x010e, 0xaaaa},
  240. {0x010f, 0xaaaa},
  241. {0x0110, 0xe002},
  242. {0x0111, 0xa402},
  243. {0x0112, 0xaaaa},
  244. {0x0113, 0x2000},
  245. {0x0117, 0x0f00},
  246. {0x0125, 0x0410},
  247. {0x0132, 0x0000},
  248. {0x0133, 0x0000},
  249. {0x0137, 0x5540},
  250. {0x0138, 0x3700},
  251. {0x0139, 0x79a1},
  252. {0x013a, 0x2020},
  253. {0x013b, 0x2020},
  254. {0x013c, 0x2005},
  255. {0x013f, 0x0000},
  256. {0x0145, 0x0002},
  257. {0x0146, 0x0000},
  258. {0x0147, 0x0000},
  259. {0x0148, 0x0000},
  260. {0x0150, 0x0000},
  261. {0x0160, 0x4eff},
  262. {0x0161, 0x0080},
  263. {0x0162, 0x0200},
  264. {0x0163, 0x0800},
  265. {0x0164, 0x0000},
  266. {0x0165, 0x0000},
  267. {0x0166, 0x0000},
  268. {0x0167, 0x000f},
  269. {0x0170, 0x4e87},
  270. {0x0171, 0x0080},
  271. {0x0172, 0x0200},
  272. {0x0173, 0x0800},
  273. {0x0174, 0x00ff},
  274. {0x0175, 0x0000},
  275. {0x0190, 0x413d},
  276. {0x0191, 0x4139},
  277. {0x0192, 0x4135},
  278. {0x0193, 0x413d},
  279. {0x0194, 0x0000},
  280. {0x0195, 0x0000},
  281. {0x0196, 0x0000},
  282. {0x0197, 0x0000},
  283. {0x0198, 0x0000},
  284. {0x0199, 0x0000},
  285. {0x01a0, 0x1e64},
  286. {0x01a1, 0x06a3},
  287. {0x01a2, 0x0000},
  288. {0x01a3, 0x0000},
  289. {0x01a4, 0x0000},
  290. {0x01a5, 0x0000},
  291. {0x01a6, 0x0000},
  292. {0x01a7, 0x8000},
  293. {0x01a8, 0x0000},
  294. {0x01a9, 0x0000},
  295. {0x01aa, 0x0000},
  296. {0x01ab, 0x0000},
  297. {0x01b5, 0x0000},
  298. {0x01b6, 0x01c3},
  299. {0x01b7, 0x02a0},
  300. {0x01b8, 0x03e9},
  301. {0x01b9, 0x1389},
  302. {0x01ba, 0xc351},
  303. {0x01bb, 0x0009},
  304. {0x01bc, 0x0018},
  305. {0x01bd, 0x002a},
  306. {0x01be, 0x004c},
  307. {0x01bf, 0x0097},
  308. {0x01c0, 0x433d},
  309. {0x01c1, 0x0000},
  310. {0x01c2, 0x0000},
  311. {0x01c3, 0x0000},
  312. {0x01c4, 0x0000},
  313. {0x01c5, 0x0000},
  314. {0x01c6, 0x0000},
  315. {0x01c7, 0x0000},
  316. {0x01c8, 0x40af},
  317. {0x01c9, 0x0702},
  318. {0x01ca, 0x0000},
  319. {0x01cb, 0x0000},
  320. {0x01cc, 0x5757},
  321. {0x01cd, 0x5757},
  322. {0x01ce, 0x5757},
  323. {0x01cf, 0x5757},
  324. {0x01d0, 0x5757},
  325. {0x01d1, 0x5757},
  326. {0x01d2, 0x5757},
  327. {0x01d3, 0x5757},
  328. {0x01d4, 0x5757},
  329. {0x01d5, 0x5757},
  330. {0x01d6, 0x003c},
  331. {0x01da, 0x0000},
  332. {0x01db, 0x0000},
  333. {0x01dc, 0x0000},
  334. {0x01de, 0x7c00},
  335. {0x01df, 0x0320},
  336. {0x01e0, 0x06a1},
  337. {0x01e1, 0x0000},
  338. {0x01e2, 0x0000},
  339. {0x01e3, 0x0000},
  340. {0x01e4, 0x0000},
  341. {0x01e6, 0x0001},
  342. {0x01e7, 0x0000},
  343. {0x01e8, 0x0000},
  344. {0x01ea, 0xbf3f},
  345. {0x01eb, 0x0000},
  346. {0x01ec, 0x0000},
  347. {0x01ed, 0x0000},
  348. {0x01ee, 0x0000},
  349. {0x01ef, 0x0000},
  350. {0x01f0, 0x0000},
  351. {0x01f1, 0x0000},
  352. {0x01f2, 0x0000},
  353. {0x01f3, 0x0000},
  354. {0x01f4, 0x0000},
  355. {0x0200, 0x0000},
  356. {0x0201, 0x0000},
  357. {0x0202, 0x0000},
  358. {0x0203, 0x0000},
  359. {0x0204, 0x0000},
  360. {0x0205, 0x0000},
  361. {0x0206, 0x0000},
  362. {0x0207, 0x0000},
  363. {0x0208, 0x0000},
  364. {0x0210, 0x60b1},
  365. {0x0211, 0xa005},
  366. {0x0212, 0x024c},
  367. {0x0213, 0xf7ff},
  368. {0x0214, 0x024c},
  369. {0x0215, 0x0102},
  370. {0x0216, 0x00a3},
  371. {0x0217, 0x0048},
  372. {0x0218, 0xa2c0},
  373. {0x0219, 0x0400},
  374. {0x021a, 0x00c8},
  375. {0x021b, 0x00c0},
  376. {0x02ff, 0x0110},
  377. {0x0300, 0x001f},
  378. {0x0301, 0x032c},
  379. {0x0302, 0x5f21},
  380. {0x0303, 0x4000},
  381. {0x0304, 0x4000},
  382. {0x0305, 0x06d5},
  383. {0x0306, 0x8000},
  384. {0x0307, 0x0700},
  385. {0x0310, 0x4560},
  386. {0x0311, 0xa4a8},
  387. {0x0312, 0x7418},
  388. {0x0313, 0x0000},
  389. {0x0314, 0x0006},
  390. {0x0315, 0xffff},
  391. {0x0316, 0xc400},
  392. {0x0317, 0x0000},
  393. {0x0330, 0x00a6},
  394. {0x0331, 0x04c3},
  395. {0x0332, 0x27c8},
  396. {0x0333, 0xbf50},
  397. {0x0334, 0x0045},
  398. {0x0335, 0x0007},
  399. {0x0336, 0x7418},
  400. {0x0337, 0x0501},
  401. {0x0338, 0x0000},
  402. {0x0339, 0x0010},
  403. {0x033a, 0x1010},
  404. {0x03c0, 0x7e00},
  405. {0x03c1, 0x8000},
  406. {0x03c2, 0x8000},
  407. {0x03c3, 0x8000},
  408. {0x03c4, 0x8000},
  409. {0x03c5, 0x8000},
  410. {0x03c6, 0x8000},
  411. {0x03c7, 0x8000},
  412. {0x03c8, 0x8000},
  413. {0x03c9, 0x8000},
  414. {0x03ca, 0x8000},
  415. {0x03cb, 0x8000},
  416. {0x03cc, 0x8000},
  417. {0x03d0, 0x0000},
  418. {0x03d1, 0x0000},
  419. {0x03d2, 0x0000},
  420. {0x03d3, 0x0000},
  421. {0x03d4, 0x2000},
  422. {0x03d5, 0x2000},
  423. {0x03d6, 0x0000},
  424. {0x03d7, 0x0000},
  425. {0x03d8, 0x2000},
  426. {0x03d9, 0x2000},
  427. {0x03da, 0x2000},
  428. {0x03db, 0x2000},
  429. {0x03dc, 0x0000},
  430. {0x03dd, 0x0000},
  431. {0x03de, 0x0000},
  432. {0x03df, 0x2000},
  433. {0x03e0, 0x0000},
  434. {0x03e1, 0x0000},
  435. {0x03e2, 0x0000},
  436. {0x03e3, 0x0000},
  437. {0x03e4, 0x0000},
  438. {0x03e5, 0x0000},
  439. {0x03e6, 0x0000},
  440. {0x03e7, 0x0000},
  441. {0x03e8, 0x0000},
  442. {0x03e9, 0x0000},
  443. {0x03ea, 0x0000},
  444. {0x03eb, 0x0000},
  445. {0x03ec, 0x0000},
  446. {0x03ed, 0x0000},
  447. {0x03ee, 0x0000},
  448. {0x03ef, 0x0000},
  449. {0x03f0, 0x0800},
  450. {0x03f1, 0x0800},
  451. {0x03f2, 0x0800},
  452. {0x03f3, 0x0800},
  453. };
  454. static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
  455. {
  456. switch (reg) {
  457. case RT5665_RESET:
  458. case RT5665_EJD_CTRL_2:
  459. case RT5665_GPIO_STA:
  460. case RT5665_INT_ST_1:
  461. case RT5665_IL_CMD_1:
  462. case RT5665_4BTN_IL_CMD_1:
  463. case RT5665_PSV_IL_CMD_1:
  464. case RT5665_AJD1_CTRL:
  465. case RT5665_JD_CTRL_3:
  466. case RT5665_STO_NG2_CTRL_1:
  467. case RT5665_SAR_IL_CMD_4:
  468. case RT5665_DEVICE_ID:
  469. case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
  470. case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
  471. case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
  472. case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
  473. return true;
  474. default:
  475. return false;
  476. }
  477. }
  478. static bool rt5665_readable_register(struct device *dev, unsigned int reg)
  479. {
  480. switch (reg) {
  481. case RT5665_RESET:
  482. case RT5665_VENDOR_ID:
  483. case RT5665_VENDOR_ID_1:
  484. case RT5665_DEVICE_ID:
  485. case RT5665_LOUT:
  486. case RT5665_HP_CTRL_1:
  487. case RT5665_HP_CTRL_2:
  488. case RT5665_MONO_OUT:
  489. case RT5665_HPL_GAIN:
  490. case RT5665_HPR_GAIN:
  491. case RT5665_MONO_GAIN:
  492. case RT5665_CAL_BST_CTRL:
  493. case RT5665_CBJ_BST_CTRL:
  494. case RT5665_IN1_IN2:
  495. case RT5665_IN3_IN4:
  496. case RT5665_INL1_INR1_VOL:
  497. case RT5665_EJD_CTRL_1:
  498. case RT5665_EJD_CTRL_2:
  499. case RT5665_EJD_CTRL_3:
  500. case RT5665_EJD_CTRL_4:
  501. case RT5665_EJD_CTRL_5:
  502. case RT5665_EJD_CTRL_6:
  503. case RT5665_EJD_CTRL_7:
  504. case RT5665_DAC2_CTRL:
  505. case RT5665_DAC2_DIG_VOL:
  506. case RT5665_DAC1_DIG_VOL:
  507. case RT5665_DAC3_DIG_VOL:
  508. case RT5665_DAC3_CTRL:
  509. case RT5665_STO1_ADC_DIG_VOL:
  510. case RT5665_MONO_ADC_DIG_VOL:
  511. case RT5665_STO2_ADC_DIG_VOL:
  512. case RT5665_STO1_ADC_BOOST:
  513. case RT5665_MONO_ADC_BOOST:
  514. case RT5665_STO2_ADC_BOOST:
  515. case RT5665_HP_IMP_GAIN_1:
  516. case RT5665_HP_IMP_GAIN_2:
  517. case RT5665_STO1_ADC_MIXER:
  518. case RT5665_MONO_ADC_MIXER:
  519. case RT5665_STO2_ADC_MIXER:
  520. case RT5665_AD_DA_MIXER:
  521. case RT5665_STO1_DAC_MIXER:
  522. case RT5665_MONO_DAC_MIXER:
  523. case RT5665_STO2_DAC_MIXER:
  524. case RT5665_A_DAC1_MUX:
  525. case RT5665_A_DAC2_MUX:
  526. case RT5665_DIG_INF2_DATA:
  527. case RT5665_DIG_INF3_DATA:
  528. case RT5665_PDM_OUT_CTRL:
  529. case RT5665_PDM_DATA_CTRL_1:
  530. case RT5665_PDM_DATA_CTRL_2:
  531. case RT5665_PDM_DATA_CTRL_3:
  532. case RT5665_PDM_DATA_CTRL_4:
  533. case RT5665_REC1_GAIN:
  534. case RT5665_REC1_L1_MIXER:
  535. case RT5665_REC1_L2_MIXER:
  536. case RT5665_REC1_R1_MIXER:
  537. case RT5665_REC1_R2_MIXER:
  538. case RT5665_REC2_GAIN:
  539. case RT5665_REC2_L1_MIXER:
  540. case RT5665_REC2_L2_MIXER:
  541. case RT5665_REC2_R1_MIXER:
  542. case RT5665_REC2_R2_MIXER:
  543. case RT5665_CAL_REC:
  544. case RT5665_ALC_BACK_GAIN:
  545. case RT5665_MONOMIX_GAIN:
  546. case RT5665_MONOMIX_IN_GAIN:
  547. case RT5665_OUT_L_GAIN:
  548. case RT5665_OUT_L_MIXER:
  549. case RT5665_OUT_R_GAIN:
  550. case RT5665_OUT_R_MIXER:
  551. case RT5665_LOUT_MIXER:
  552. case RT5665_PWR_DIG_1:
  553. case RT5665_PWR_DIG_2:
  554. case RT5665_PWR_ANLG_1:
  555. case RT5665_PWR_ANLG_2:
  556. case RT5665_PWR_ANLG_3:
  557. case RT5665_PWR_MIXER:
  558. case RT5665_PWR_VOL:
  559. case RT5665_CLK_DET:
  560. case RT5665_HPF_CTRL1:
  561. case RT5665_DMIC_CTRL_1:
  562. case RT5665_DMIC_CTRL_2:
  563. case RT5665_I2S1_SDP:
  564. case RT5665_I2S2_SDP:
  565. case RT5665_I2S3_SDP:
  566. case RT5665_ADDA_CLK_1:
  567. case RT5665_ADDA_CLK_2:
  568. case RT5665_I2S1_F_DIV_CTRL_1:
  569. case RT5665_I2S1_F_DIV_CTRL_2:
  570. case RT5665_TDM_CTRL_1:
  571. case RT5665_TDM_CTRL_2:
  572. case RT5665_TDM_CTRL_3:
  573. case RT5665_TDM_CTRL_4:
  574. case RT5665_TDM_CTRL_5:
  575. case RT5665_TDM_CTRL_6:
  576. case RT5665_TDM_CTRL_7:
  577. case RT5665_TDM_CTRL_8:
  578. case RT5665_GLB_CLK:
  579. case RT5665_PLL_CTRL_1:
  580. case RT5665_PLL_CTRL_2:
  581. case RT5665_ASRC_1:
  582. case RT5665_ASRC_2:
  583. case RT5665_ASRC_3:
  584. case RT5665_ASRC_4:
  585. case RT5665_ASRC_5:
  586. case RT5665_ASRC_6:
  587. case RT5665_ASRC_7:
  588. case RT5665_ASRC_8:
  589. case RT5665_ASRC_9:
  590. case RT5665_ASRC_10:
  591. case RT5665_DEPOP_1:
  592. case RT5665_DEPOP_2:
  593. case RT5665_HP_CHARGE_PUMP_1:
  594. case RT5665_HP_CHARGE_PUMP_2:
  595. case RT5665_MICBIAS_1:
  596. case RT5665_MICBIAS_2:
  597. case RT5665_ASRC_12:
  598. case RT5665_ASRC_13:
  599. case RT5665_ASRC_14:
  600. case RT5665_RC_CLK_CTRL:
  601. case RT5665_I2S_M_CLK_CTRL_1:
  602. case RT5665_I2S2_F_DIV_CTRL_1:
  603. case RT5665_I2S2_F_DIV_CTRL_2:
  604. case RT5665_I2S3_F_DIV_CTRL_1:
  605. case RT5665_I2S3_F_DIV_CTRL_2:
  606. case RT5665_EQ_CTRL_1:
  607. case RT5665_EQ_CTRL_2:
  608. case RT5665_IRQ_CTRL_1:
  609. case RT5665_IRQ_CTRL_2:
  610. case RT5665_IRQ_CTRL_3:
  611. case RT5665_IRQ_CTRL_4:
  612. case RT5665_IRQ_CTRL_5:
  613. case RT5665_IRQ_CTRL_6:
  614. case RT5665_INT_ST_1:
  615. case RT5665_GPIO_CTRL_1:
  616. case RT5665_GPIO_CTRL_2:
  617. case RT5665_GPIO_CTRL_3:
  618. case RT5665_GPIO_CTRL_4:
  619. case RT5665_GPIO_STA:
  620. case RT5665_HP_AMP_DET_CTRL_1:
  621. case RT5665_HP_AMP_DET_CTRL_2:
  622. case RT5665_MID_HP_AMP_DET:
  623. case RT5665_LOW_HP_AMP_DET:
  624. case RT5665_SV_ZCD_1:
  625. case RT5665_SV_ZCD_2:
  626. case RT5665_IL_CMD_1:
  627. case RT5665_IL_CMD_2:
  628. case RT5665_IL_CMD_3:
  629. case RT5665_IL_CMD_4:
  630. case RT5665_4BTN_IL_CMD_1:
  631. case RT5665_4BTN_IL_CMD_2:
  632. case RT5665_4BTN_IL_CMD_3:
  633. case RT5665_PSV_IL_CMD_1:
  634. case RT5665_ADC_STO1_HP_CTRL_1:
  635. case RT5665_ADC_STO1_HP_CTRL_2:
  636. case RT5665_ADC_MONO_HP_CTRL_1:
  637. case RT5665_ADC_MONO_HP_CTRL_2:
  638. case RT5665_ADC_STO2_HP_CTRL_1:
  639. case RT5665_ADC_STO2_HP_CTRL_2:
  640. case RT5665_AJD1_CTRL:
  641. case RT5665_JD1_THD:
  642. case RT5665_JD2_THD:
  643. case RT5665_JD_CTRL_1:
  644. case RT5665_JD_CTRL_2:
  645. case RT5665_JD_CTRL_3:
  646. case RT5665_DIG_MISC:
  647. case RT5665_DUMMY_2:
  648. case RT5665_DUMMY_3:
  649. case RT5665_DAC_ADC_DIG_VOL1:
  650. case RT5665_DAC_ADC_DIG_VOL2:
  651. case RT5665_BIAS_CUR_CTRL_1:
  652. case RT5665_BIAS_CUR_CTRL_2:
  653. case RT5665_BIAS_CUR_CTRL_3:
  654. case RT5665_BIAS_CUR_CTRL_4:
  655. case RT5665_BIAS_CUR_CTRL_5:
  656. case RT5665_BIAS_CUR_CTRL_6:
  657. case RT5665_BIAS_CUR_CTRL_7:
  658. case RT5665_BIAS_CUR_CTRL_8:
  659. case RT5665_BIAS_CUR_CTRL_9:
  660. case RT5665_BIAS_CUR_CTRL_10:
  661. case RT5665_VREF_REC_OP_FB_CAP_CTRL:
  662. case RT5665_CHARGE_PUMP_1:
  663. case RT5665_DIG_IN_CTRL_1:
  664. case RT5665_DIG_IN_CTRL_2:
  665. case RT5665_PAD_DRIVING_CTRL:
  666. case RT5665_SOFT_RAMP_DEPOP:
  667. case RT5665_PLL:
  668. case RT5665_CHOP_DAC:
  669. case RT5665_CHOP_ADC:
  670. case RT5665_CALIB_ADC_CTRL:
  671. case RT5665_VOL_TEST:
  672. case RT5665_TEST_MODE_CTRL_1:
  673. case RT5665_TEST_MODE_CTRL_2:
  674. case RT5665_TEST_MODE_CTRL_3:
  675. case RT5665_TEST_MODE_CTRL_4:
  676. case RT5665_BASSBACK_CTRL:
  677. case RT5665_STO_NG2_CTRL_1:
  678. case RT5665_STO_NG2_CTRL_2:
  679. case RT5665_STO_NG2_CTRL_3:
  680. case RT5665_STO_NG2_CTRL_4:
  681. case RT5665_STO_NG2_CTRL_5:
  682. case RT5665_STO_NG2_CTRL_6:
  683. case RT5665_STO_NG2_CTRL_7:
  684. case RT5665_STO_NG2_CTRL_8:
  685. case RT5665_MONO_NG2_CTRL_1:
  686. case RT5665_MONO_NG2_CTRL_2:
  687. case RT5665_MONO_NG2_CTRL_3:
  688. case RT5665_MONO_NG2_CTRL_4:
  689. case RT5665_MONO_NG2_CTRL_5:
  690. case RT5665_MONO_NG2_CTRL_6:
  691. case RT5665_STO1_DAC_SIL_DET:
  692. case RT5665_MONOL_DAC_SIL_DET:
  693. case RT5665_MONOR_DAC_SIL_DET:
  694. case RT5665_STO2_DAC_SIL_DET:
  695. case RT5665_SIL_PSV_CTRL1:
  696. case RT5665_SIL_PSV_CTRL2:
  697. case RT5665_SIL_PSV_CTRL3:
  698. case RT5665_SIL_PSV_CTRL4:
  699. case RT5665_SIL_PSV_CTRL5:
  700. case RT5665_SIL_PSV_CTRL6:
  701. case RT5665_MONO_AMP_CALIB_CTRL_1:
  702. case RT5665_MONO_AMP_CALIB_CTRL_2:
  703. case RT5665_MONO_AMP_CALIB_CTRL_3:
  704. case RT5665_MONO_AMP_CALIB_CTRL_4:
  705. case RT5665_MONO_AMP_CALIB_CTRL_5:
  706. case RT5665_MONO_AMP_CALIB_CTRL_6:
  707. case RT5665_MONO_AMP_CALIB_CTRL_7:
  708. case RT5665_MONO_AMP_CALIB_STA1:
  709. case RT5665_MONO_AMP_CALIB_STA2:
  710. case RT5665_MONO_AMP_CALIB_STA3:
  711. case RT5665_MONO_AMP_CALIB_STA4:
  712. case RT5665_MONO_AMP_CALIB_STA6:
  713. case RT5665_HP_IMP_SENS_CTRL_01:
  714. case RT5665_HP_IMP_SENS_CTRL_02:
  715. case RT5665_HP_IMP_SENS_CTRL_03:
  716. case RT5665_HP_IMP_SENS_CTRL_04:
  717. case RT5665_HP_IMP_SENS_CTRL_05:
  718. case RT5665_HP_IMP_SENS_CTRL_06:
  719. case RT5665_HP_IMP_SENS_CTRL_07:
  720. case RT5665_HP_IMP_SENS_CTRL_08:
  721. case RT5665_HP_IMP_SENS_CTRL_09:
  722. case RT5665_HP_IMP_SENS_CTRL_10:
  723. case RT5665_HP_IMP_SENS_CTRL_11:
  724. case RT5665_HP_IMP_SENS_CTRL_12:
  725. case RT5665_HP_IMP_SENS_CTRL_13:
  726. case RT5665_HP_IMP_SENS_CTRL_14:
  727. case RT5665_HP_IMP_SENS_CTRL_15:
  728. case RT5665_HP_IMP_SENS_CTRL_16:
  729. case RT5665_HP_IMP_SENS_CTRL_17:
  730. case RT5665_HP_IMP_SENS_CTRL_18:
  731. case RT5665_HP_IMP_SENS_CTRL_19:
  732. case RT5665_HP_IMP_SENS_CTRL_20:
  733. case RT5665_HP_IMP_SENS_CTRL_21:
  734. case RT5665_HP_IMP_SENS_CTRL_22:
  735. case RT5665_HP_IMP_SENS_CTRL_23:
  736. case RT5665_HP_IMP_SENS_CTRL_24:
  737. case RT5665_HP_IMP_SENS_CTRL_25:
  738. case RT5665_HP_IMP_SENS_CTRL_26:
  739. case RT5665_HP_IMP_SENS_CTRL_27:
  740. case RT5665_HP_IMP_SENS_CTRL_28:
  741. case RT5665_HP_IMP_SENS_CTRL_29:
  742. case RT5665_HP_IMP_SENS_CTRL_30:
  743. case RT5665_HP_IMP_SENS_CTRL_31:
  744. case RT5665_HP_IMP_SENS_CTRL_32:
  745. case RT5665_HP_IMP_SENS_CTRL_33:
  746. case RT5665_HP_IMP_SENS_CTRL_34:
  747. case RT5665_HP_LOGIC_CTRL_1:
  748. case RT5665_HP_LOGIC_CTRL_2:
  749. case RT5665_HP_LOGIC_CTRL_3:
  750. case RT5665_HP_CALIB_CTRL_1:
  751. case RT5665_HP_CALIB_CTRL_2:
  752. case RT5665_HP_CALIB_CTRL_3:
  753. case RT5665_HP_CALIB_CTRL_4:
  754. case RT5665_HP_CALIB_CTRL_5:
  755. case RT5665_HP_CALIB_CTRL_6:
  756. case RT5665_HP_CALIB_CTRL_7:
  757. case RT5665_HP_CALIB_CTRL_9:
  758. case RT5665_HP_CALIB_CTRL_10:
  759. case RT5665_HP_CALIB_CTRL_11:
  760. case RT5665_HP_CALIB_STA_1:
  761. case RT5665_HP_CALIB_STA_2:
  762. case RT5665_HP_CALIB_STA_3:
  763. case RT5665_HP_CALIB_STA_4:
  764. case RT5665_HP_CALIB_STA_5:
  765. case RT5665_HP_CALIB_STA_6:
  766. case RT5665_HP_CALIB_STA_7:
  767. case RT5665_HP_CALIB_STA_8:
  768. case RT5665_HP_CALIB_STA_9:
  769. case RT5665_HP_CALIB_STA_10:
  770. case RT5665_HP_CALIB_STA_11:
  771. case RT5665_PGM_TAB_CTRL1:
  772. case RT5665_PGM_TAB_CTRL2:
  773. case RT5665_PGM_TAB_CTRL3:
  774. case RT5665_PGM_TAB_CTRL4:
  775. case RT5665_PGM_TAB_CTRL5:
  776. case RT5665_PGM_TAB_CTRL6:
  777. case RT5665_PGM_TAB_CTRL7:
  778. case RT5665_PGM_TAB_CTRL8:
  779. case RT5665_PGM_TAB_CTRL9:
  780. case RT5665_SAR_IL_CMD_1:
  781. case RT5665_SAR_IL_CMD_2:
  782. case RT5665_SAR_IL_CMD_3:
  783. case RT5665_SAR_IL_CMD_4:
  784. case RT5665_SAR_IL_CMD_5:
  785. case RT5665_SAR_IL_CMD_6:
  786. case RT5665_SAR_IL_CMD_7:
  787. case RT5665_SAR_IL_CMD_8:
  788. case RT5665_SAR_IL_CMD_9:
  789. case RT5665_SAR_IL_CMD_10:
  790. case RT5665_SAR_IL_CMD_11:
  791. case RT5665_SAR_IL_CMD_12:
  792. case RT5665_DRC1_CTRL_0:
  793. case RT5665_DRC1_CTRL_1:
  794. case RT5665_DRC1_CTRL_2:
  795. case RT5665_DRC1_CTRL_3:
  796. case RT5665_DRC1_CTRL_4:
  797. case RT5665_DRC1_CTRL_5:
  798. case RT5665_DRC1_CTRL_6:
  799. case RT5665_DRC1_HARD_LMT_CTRL_1:
  800. case RT5665_DRC1_HARD_LMT_CTRL_2:
  801. case RT5665_DRC1_PRIV_1:
  802. case RT5665_DRC1_PRIV_2:
  803. case RT5665_DRC1_PRIV_3:
  804. case RT5665_DRC1_PRIV_4:
  805. case RT5665_DRC1_PRIV_5:
  806. case RT5665_DRC1_PRIV_6:
  807. case RT5665_DRC1_PRIV_7:
  808. case RT5665_DRC1_PRIV_8:
  809. case RT5665_ALC_PGA_CTRL_1:
  810. case RT5665_ALC_PGA_CTRL_2:
  811. case RT5665_ALC_PGA_CTRL_3:
  812. case RT5665_ALC_PGA_CTRL_4:
  813. case RT5665_ALC_PGA_CTRL_5:
  814. case RT5665_ALC_PGA_CTRL_6:
  815. case RT5665_ALC_PGA_CTRL_7:
  816. case RT5665_ALC_PGA_CTRL_8:
  817. case RT5665_ALC_PGA_STA_1:
  818. case RT5665_ALC_PGA_STA_2:
  819. case RT5665_ALC_PGA_STA_3:
  820. case RT5665_EQ_AUTO_RCV_CTRL1:
  821. case RT5665_EQ_AUTO_RCV_CTRL2:
  822. case RT5665_EQ_AUTO_RCV_CTRL3:
  823. case RT5665_EQ_AUTO_RCV_CTRL4:
  824. case RT5665_EQ_AUTO_RCV_CTRL5:
  825. case RT5665_EQ_AUTO_RCV_CTRL6:
  826. case RT5665_EQ_AUTO_RCV_CTRL7:
  827. case RT5665_EQ_AUTO_RCV_CTRL8:
  828. case RT5665_EQ_AUTO_RCV_CTRL9:
  829. case RT5665_EQ_AUTO_RCV_CTRL10:
  830. case RT5665_EQ_AUTO_RCV_CTRL11:
  831. case RT5665_EQ_AUTO_RCV_CTRL12:
  832. case RT5665_EQ_AUTO_RCV_CTRL13:
  833. case RT5665_ADC_L_EQ_LPF1_A1:
  834. case RT5665_R_EQ_LPF1_A1:
  835. case RT5665_L_EQ_LPF1_H0:
  836. case RT5665_R_EQ_LPF1_H0:
  837. case RT5665_L_EQ_BPF1_A1:
  838. case RT5665_R_EQ_BPF1_A1:
  839. case RT5665_L_EQ_BPF1_A2:
  840. case RT5665_R_EQ_BPF1_A2:
  841. case RT5665_L_EQ_BPF1_H0:
  842. case RT5665_R_EQ_BPF1_H0:
  843. case RT5665_L_EQ_BPF2_A1:
  844. case RT5665_R_EQ_BPF2_A1:
  845. case RT5665_L_EQ_BPF2_A2:
  846. case RT5665_R_EQ_BPF2_A2:
  847. case RT5665_L_EQ_BPF2_H0:
  848. case RT5665_R_EQ_BPF2_H0:
  849. case RT5665_L_EQ_BPF3_A1:
  850. case RT5665_R_EQ_BPF3_A1:
  851. case RT5665_L_EQ_BPF3_A2:
  852. case RT5665_R_EQ_BPF3_A2:
  853. case RT5665_L_EQ_BPF3_H0:
  854. case RT5665_R_EQ_BPF3_H0:
  855. case RT5665_L_EQ_BPF4_A1:
  856. case RT5665_R_EQ_BPF4_A1:
  857. case RT5665_L_EQ_BPF4_A2:
  858. case RT5665_R_EQ_BPF4_A2:
  859. case RT5665_L_EQ_BPF4_H0:
  860. case RT5665_R_EQ_BPF4_H0:
  861. case RT5665_L_EQ_HPF1_A1:
  862. case RT5665_R_EQ_HPF1_A1:
  863. case RT5665_L_EQ_HPF1_H0:
  864. case RT5665_R_EQ_HPF1_H0:
  865. case RT5665_L_EQ_PRE_VOL:
  866. case RT5665_R_EQ_PRE_VOL:
  867. case RT5665_L_EQ_POST_VOL:
  868. case RT5665_R_EQ_POST_VOL:
  869. case RT5665_SCAN_MODE_CTRL:
  870. case RT5665_I2C_MODE:
  871. return true;
  872. default:
  873. return false;
  874. }
  875. }
  876. static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
  877. static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
  878. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
  879. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
  880. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
  881. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
  882. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  883. static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
  884. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  885. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  886. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  887. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  888. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  889. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  890. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  891. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  892. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  893. );
  894. /* Interface data select */
  895. static const char * const rt5665_data_select[] = {
  896. "L/R", "R/L", "L/L", "R/R"
  897. };
  898. static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
  899. RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
  900. static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
  901. RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
  902. static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
  903. RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
  904. static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
  905. RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
  906. static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
  907. RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
  908. static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
  909. RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
  910. static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
  911. RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
  912. static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
  913. RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
  914. static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
  915. RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
  916. static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
  917. RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
  918. static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
  919. RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
  920. static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
  921. RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
  922. static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
  923. RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
  924. static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
  925. RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
  926. static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
  927. SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
  928. static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
  929. SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
  930. static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
  931. SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
  932. static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
  933. SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
  934. static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
  935. SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
  936. static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
  937. SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
  938. static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
  939. SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
  940. static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
  941. SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
  942. static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
  943. SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
  944. static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
  945. SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
  946. static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
  947. SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
  948. static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
  949. SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
  950. static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
  951. SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
  952. static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
  953. SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
  954. static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
  955. struct snd_ctl_elem_value *ucontrol)
  956. {
  957. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  958. int ret = snd_soc_put_volsw(kcontrol, ucontrol);
  959. if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
  960. snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
  961. RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
  962. snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
  963. RT5665_NG2_EN_MASK, RT5665_NG2_EN);
  964. }
  965. return ret;
  966. }
  967. static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
  968. struct snd_ctl_elem_value *ucontrol)
  969. {
  970. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  971. int ret = snd_soc_put_volsw(kcontrol, ucontrol);
  972. if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
  973. snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
  974. RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
  975. snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
  976. RT5665_NG2_EN_MASK, RT5665_NG2_EN);
  977. }
  978. return ret;
  979. }
  980. /**
  981. * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
  982. * @component: SoC audio component device.
  983. * @filter_mask: mask of filters.
  984. * @clk_src: clock source
  985. *
  986. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
  987. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  988. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  989. * ASRC function will track i2s clock and generate a corresponding system clock
  990. * for codec. This function provides an API to select the clock source for a
  991. * set of filters specified by the mask. And the codec driver will turn on ASRC
  992. * for these filters if ASRC is selected as their clock source.
  993. */
  994. int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,
  995. unsigned int filter_mask, unsigned int clk_src)
  996. {
  997. unsigned int asrc2_mask = 0;
  998. unsigned int asrc2_value = 0;
  999. unsigned int asrc3_mask = 0;
  1000. unsigned int asrc3_value = 0;
  1001. switch (clk_src) {
  1002. case RT5665_CLK_SEL_SYS:
  1003. case RT5665_CLK_SEL_I2S1_ASRC:
  1004. case RT5665_CLK_SEL_I2S2_ASRC:
  1005. case RT5665_CLK_SEL_I2S3_ASRC:
  1006. case RT5665_CLK_SEL_SYS2:
  1007. case RT5665_CLK_SEL_SYS3:
  1008. case RT5665_CLK_SEL_SYS4:
  1009. break;
  1010. default:
  1011. return -EINVAL;
  1012. }
  1013. if (filter_mask & RT5665_DA_STEREO1_FILTER) {
  1014. asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
  1015. asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
  1016. | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
  1017. }
  1018. if (filter_mask & RT5665_DA_STEREO2_FILTER) {
  1019. asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
  1020. asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
  1021. | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
  1022. }
  1023. if (filter_mask & RT5665_DA_MONO_L_FILTER) {
  1024. asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
  1025. asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
  1026. | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
  1027. }
  1028. if (filter_mask & RT5665_DA_MONO_R_FILTER) {
  1029. asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
  1030. asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
  1031. | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
  1032. }
  1033. if (filter_mask & RT5665_AD_STEREO1_FILTER) {
  1034. asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
  1035. asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
  1036. | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
  1037. }
  1038. if (filter_mask & RT5665_AD_STEREO2_FILTER) {
  1039. asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
  1040. asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
  1041. | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
  1042. }
  1043. if (filter_mask & RT5665_AD_MONO_L_FILTER) {
  1044. asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
  1045. asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
  1046. | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
  1047. }
  1048. if (filter_mask & RT5665_AD_MONO_R_FILTER) {
  1049. asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
  1050. asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
  1051. | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
  1052. }
  1053. if (asrc2_mask)
  1054. snd_soc_component_update_bits(component, RT5665_ASRC_2,
  1055. asrc2_mask, asrc2_value);
  1056. if (asrc3_mask)
  1057. snd_soc_component_update_bits(component, RT5665_ASRC_3,
  1058. asrc3_mask, asrc3_value);
  1059. return 0;
  1060. }
  1061. EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
  1062. static int rt5665_button_detect(struct snd_soc_component *component)
  1063. {
  1064. int btn_type, val;
  1065. val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1);
  1066. btn_type = val & 0xfff0;
  1067. snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val);
  1068. return btn_type;
  1069. }
  1070. static void rt5665_enable_push_button_irq(struct snd_soc_component *component,
  1071. bool enable)
  1072. {
  1073. if (enable) {
  1074. snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003);
  1075. snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
  1076. snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048);
  1077. snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
  1078. RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
  1079. RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
  1080. snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
  1081. RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
  1082. } else {
  1083. snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
  1084. RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
  1085. snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
  1086. RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
  1087. snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
  1088. RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
  1089. }
  1090. }
  1091. /**
  1092. * rt5665_headset_detect - Detect headset.
  1093. * @component: SoC audio component device.
  1094. * @jack_insert: Jack insert or not.
  1095. *
  1096. * Detect whether is headset or not when jack inserted.
  1097. *
  1098. * Returns detect status.
  1099. */
  1100. static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert)
  1101. {
  1102. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  1103. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1104. unsigned int sar_hs_type, val;
  1105. if (jack_insert) {
  1106. snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
  1107. snd_soc_dapm_sync(dapm);
  1108. regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
  1109. 0x100);
  1110. regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
  1111. if (val & 0x4) {
  1112. regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
  1113. 0x100, 0);
  1114. regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
  1115. while (val & 0x4) {
  1116. usleep_range(10000, 15000);
  1117. regmap_read(rt5665->regmap, RT5665_GPIO_STA,
  1118. &val);
  1119. }
  1120. }
  1121. regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
  1122. 0x1a0, 0x120);
  1123. regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
  1124. regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
  1125. regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
  1126. usleep_range(10000, 15000);
  1127. rt5665->sar_adc_value = snd_soc_component_read(rt5665->component,
  1128. RT5665_SAR_IL_CMD_4) & 0x7ff;
  1129. sar_hs_type = rt5665->pdata.sar_hs_type ?
  1130. rt5665->pdata.sar_hs_type : 729;
  1131. if (rt5665->sar_adc_value > sar_hs_type) {
  1132. rt5665->jack_type = SND_JACK_HEADSET;
  1133. rt5665_enable_push_button_irq(component, true);
  1134. } else {
  1135. rt5665->jack_type = SND_JACK_HEADPHONE;
  1136. regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
  1137. 0x2291);
  1138. regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
  1139. 0x100, 0);
  1140. snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
  1141. snd_soc_dapm_sync(dapm);
  1142. }
  1143. } else {
  1144. regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
  1145. regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
  1146. snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
  1147. snd_soc_dapm_sync(dapm);
  1148. if (rt5665->jack_type == SND_JACK_HEADSET)
  1149. rt5665_enable_push_button_irq(component, false);
  1150. rt5665->jack_type = 0;
  1151. }
  1152. dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
  1153. return rt5665->jack_type;
  1154. }
  1155. static irqreturn_t rt5665_irq(int irq, void *data)
  1156. {
  1157. struct rt5665_priv *rt5665 = data;
  1158. mod_delayed_work(system_power_efficient_wq,
  1159. &rt5665->jack_detect_work, msecs_to_jiffies(250));
  1160. return IRQ_HANDLED;
  1161. }
  1162. static void rt5665_jd_check_handler(struct work_struct *work)
  1163. {
  1164. struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
  1165. jd_check_work.work);
  1166. if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
  1167. /* jack out */
  1168. rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
  1169. snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
  1170. SND_JACK_HEADSET |
  1171. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1172. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  1173. } else {
  1174. schedule_delayed_work(&rt5665->jd_check_work, 500);
  1175. }
  1176. }
  1177. static int rt5665_set_jack_detect(struct snd_soc_component *component,
  1178. struct snd_soc_jack *hs_jack, void *data)
  1179. {
  1180. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  1181. switch (rt5665->pdata.jd_src) {
  1182. case RT5665_JD1:
  1183. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
  1184. RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
  1185. regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
  1186. 0xc000, 0xc000);
  1187. regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
  1188. RT5665_PWR_JD1, RT5665_PWR_JD1);
  1189. regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
  1190. break;
  1191. case RT5665_JD_NULL:
  1192. break;
  1193. default:
  1194. dev_warn(component->dev, "Wrong JD source\n");
  1195. break;
  1196. }
  1197. rt5665->hs_jack = hs_jack;
  1198. return 0;
  1199. }
  1200. static void rt5665_jack_detect_handler(struct work_struct *work)
  1201. {
  1202. struct rt5665_priv *rt5665 =
  1203. container_of(work, struct rt5665_priv, jack_detect_work.work);
  1204. int val, btn_type;
  1205. while (!rt5665->component) {
  1206. pr_debug("%s codec = null\n", __func__);
  1207. usleep_range(10000, 15000);
  1208. }
  1209. while (!rt5665->component->card->instantiated) {
  1210. pr_debug("%s\n", __func__);
  1211. usleep_range(10000, 15000);
  1212. }
  1213. while (!rt5665->calibration_done) {
  1214. pr_debug("%s calibration not ready\n", __func__);
  1215. usleep_range(10000, 15000);
  1216. }
  1217. mutex_lock(&rt5665->calibrate_mutex);
  1218. val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
  1219. if (!val) {
  1220. /* jack in */
  1221. if (rt5665->jack_type == 0) {
  1222. /* jack was out, report jack type */
  1223. rt5665->jack_type =
  1224. rt5665_headset_detect(rt5665->component, 1);
  1225. } else {
  1226. /* jack is already in, report button event */
  1227. rt5665->jack_type = SND_JACK_HEADSET;
  1228. btn_type = rt5665_button_detect(rt5665->component);
  1229. /**
  1230. * rt5665 can report three kinds of button behavior,
  1231. * one click, double click and hold. However,
  1232. * currently we will report button pressed/released
  1233. * event. So all the three button behaviors are
  1234. * treated as button pressed.
  1235. */
  1236. switch (btn_type) {
  1237. case 0x8000:
  1238. case 0x4000:
  1239. case 0x2000:
  1240. rt5665->jack_type |= SND_JACK_BTN_0;
  1241. break;
  1242. case 0x1000:
  1243. case 0x0800:
  1244. case 0x0400:
  1245. rt5665->jack_type |= SND_JACK_BTN_1;
  1246. break;
  1247. case 0x0200:
  1248. case 0x0100:
  1249. case 0x0080:
  1250. rt5665->jack_type |= SND_JACK_BTN_2;
  1251. break;
  1252. case 0x0040:
  1253. case 0x0020:
  1254. case 0x0010:
  1255. rt5665->jack_type |= SND_JACK_BTN_3;
  1256. break;
  1257. case 0x0000: /* unpressed */
  1258. break;
  1259. default:
  1260. btn_type = 0;
  1261. dev_err(rt5665->component->dev,
  1262. "Unexpected button code 0x%04x\n",
  1263. btn_type);
  1264. break;
  1265. }
  1266. }
  1267. } else {
  1268. /* jack out */
  1269. rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
  1270. }
  1271. snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
  1272. SND_JACK_HEADSET |
  1273. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1274. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  1275. if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1276. SND_JACK_BTN_2 | SND_JACK_BTN_3))
  1277. schedule_delayed_work(&rt5665->jd_check_work, 0);
  1278. else
  1279. cancel_delayed_work_sync(&rt5665->jd_check_work);
  1280. mutex_unlock(&rt5665->calibrate_mutex);
  1281. }
  1282. static const char * const rt5665_clk_sync[] = {
  1283. "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
  1284. };
  1285. static const struct soc_enum rt5665_enum[] = {
  1286. SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
  1287. SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
  1288. SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
  1289. };
  1290. static const struct snd_kcontrol_new rt5665_snd_controls[] = {
  1291. /* Headphone Output Volume */
  1292. SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
  1293. RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
  1294. rt5665_hp_vol_put, hp_vol_tlv),
  1295. /* Mono Output Volume */
  1296. SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
  1297. RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
  1298. rt5665_mono_vol_put, mono_vol_tlv),
  1299. SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
  1300. RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
  1301. /* Output Volume */
  1302. SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
  1303. RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
  1304. /* DAC Digital Volume */
  1305. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
  1306. RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
  1307. SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
  1308. RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
  1309. SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
  1310. RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
  1311. /* IN1/IN2/IN3/IN4 Volume */
  1312. SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
  1313. RT5665_BST1_SFT, 69, 0, in_bst_tlv),
  1314. SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
  1315. RT5665_BST2_SFT, 69, 0, in_bst_tlv),
  1316. SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
  1317. RT5665_BST3_SFT, 69, 0, in_bst_tlv),
  1318. SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
  1319. RT5665_BST4_SFT, 69, 0, in_bst_tlv),
  1320. SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
  1321. RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
  1322. /* INL/INR Volume Control */
  1323. SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
  1324. RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
  1325. /* ADC Digital Volume Control */
  1326. SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
  1327. RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
  1328. SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
  1329. RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
  1330. SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
  1331. RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
  1332. SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
  1333. RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
  1334. SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
  1335. RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
  1336. SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
  1337. RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
  1338. /* ADC Boost Volume Control */
  1339. SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
  1340. RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
  1341. 3, 0, adc_bst_tlv),
  1342. SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
  1343. RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
  1344. 3, 0, adc_bst_tlv),
  1345. SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
  1346. RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
  1347. 3, 0, adc_bst_tlv),
  1348. /* I2S3 CLK Source */
  1349. SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
  1350. SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
  1351. SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
  1352. };
  1353. /**
  1354. * set_dmic_clk - Set parameter of dmic.
  1355. *
  1356. * @w: DAPM widget.
  1357. * @kcontrol: The kcontrol of this widget.
  1358. * @event: Event id.
  1359. *
  1360. * Choose dmic clock between 1MHz and 3MHz.
  1361. * It is better for clock to approximate 3MHz.
  1362. */
  1363. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  1364. struct snd_kcontrol *kcontrol, int event)
  1365. {
  1366. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1367. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  1368. int pd, idx;
  1369. pd = rl6231_get_pre_div(rt5665->regmap,
  1370. RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
  1371. idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
  1372. if (idx < 0)
  1373. dev_err(component->dev, "Failed to set DMIC clock\n");
  1374. else {
  1375. snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1,
  1376. RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
  1377. }
  1378. return idx;
  1379. }
  1380. static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
  1381. struct snd_kcontrol *kcontrol, int event)
  1382. {
  1383. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1384. switch (event) {
  1385. case SND_SOC_DAPM_PRE_PMU:
  1386. snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
  1387. RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
  1388. RT5665_PM_HP_HV | RT5665_OSW_L_EN);
  1389. break;
  1390. case SND_SOC_DAPM_POST_PMD:
  1391. snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
  1392. RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
  1393. RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
  1394. break;
  1395. default:
  1396. return 0;
  1397. }
  1398. return 0;
  1399. }
  1400. static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
  1401. struct snd_soc_dapm_widget *sink)
  1402. {
  1403. unsigned int val;
  1404. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1405. val = snd_soc_component_read(component, RT5665_GLB_CLK);
  1406. val &= RT5665_SCLK_SRC_MASK;
  1407. if (val == RT5665_SCLK_SRC_PLL1)
  1408. return 1;
  1409. else
  1410. return 0;
  1411. }
  1412. static int is_using_asrc(struct snd_soc_dapm_widget *w,
  1413. struct snd_soc_dapm_widget *sink)
  1414. {
  1415. unsigned int reg, shift, val;
  1416. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1417. switch (w->shift) {
  1418. case RT5665_ADC_MONO_R_ASRC_SFT:
  1419. reg = RT5665_ASRC_3;
  1420. shift = RT5665_AD_MONOR_CLK_SEL_SFT;
  1421. break;
  1422. case RT5665_ADC_MONO_L_ASRC_SFT:
  1423. reg = RT5665_ASRC_3;
  1424. shift = RT5665_AD_MONOL_CLK_SEL_SFT;
  1425. break;
  1426. case RT5665_ADC_STO1_ASRC_SFT:
  1427. reg = RT5665_ASRC_3;
  1428. shift = RT5665_AD_STO1_CLK_SEL_SFT;
  1429. break;
  1430. case RT5665_ADC_STO2_ASRC_SFT:
  1431. reg = RT5665_ASRC_3;
  1432. shift = RT5665_AD_STO2_CLK_SEL_SFT;
  1433. break;
  1434. case RT5665_DAC_MONO_R_ASRC_SFT:
  1435. reg = RT5665_ASRC_2;
  1436. shift = RT5665_DA_MONOR_CLK_SEL_SFT;
  1437. break;
  1438. case RT5665_DAC_MONO_L_ASRC_SFT:
  1439. reg = RT5665_ASRC_2;
  1440. shift = RT5665_DA_MONOL_CLK_SEL_SFT;
  1441. break;
  1442. case RT5665_DAC_STO1_ASRC_SFT:
  1443. reg = RT5665_ASRC_2;
  1444. shift = RT5665_DA_STO1_CLK_SEL_SFT;
  1445. break;
  1446. case RT5665_DAC_STO2_ASRC_SFT:
  1447. reg = RT5665_ASRC_2;
  1448. shift = RT5665_DA_STO2_CLK_SEL_SFT;
  1449. break;
  1450. default:
  1451. return 0;
  1452. }
  1453. val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
  1454. switch (val) {
  1455. case RT5665_CLK_SEL_I2S1_ASRC:
  1456. case RT5665_CLK_SEL_I2S2_ASRC:
  1457. case RT5665_CLK_SEL_I2S3_ASRC:
  1458. /* I2S_Pre_Div1 should be 1 in asrc mode */
  1459. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
  1460. RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
  1461. return 1;
  1462. default:
  1463. return 0;
  1464. }
  1465. }
  1466. /* Digital Mixer */
  1467. static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
  1468. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
  1469. RT5665_M_STO1_ADC_L1_SFT, 1, 1),
  1470. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
  1471. RT5665_M_STO1_ADC_L2_SFT, 1, 1),
  1472. };
  1473. static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
  1474. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
  1475. RT5665_M_STO1_ADC_R1_SFT, 1, 1),
  1476. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
  1477. RT5665_M_STO1_ADC_R2_SFT, 1, 1),
  1478. };
  1479. static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
  1480. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
  1481. RT5665_M_STO2_ADC_L1_SFT, 1, 1),
  1482. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
  1483. RT5665_M_STO2_ADC_L2_SFT, 1, 1),
  1484. };
  1485. static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
  1486. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
  1487. RT5665_M_STO2_ADC_R1_SFT, 1, 1),
  1488. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
  1489. RT5665_M_STO2_ADC_R2_SFT, 1, 1),
  1490. };
  1491. static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
  1492. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
  1493. RT5665_M_MONO_ADC_L1_SFT, 1, 1),
  1494. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
  1495. RT5665_M_MONO_ADC_L2_SFT, 1, 1),
  1496. };
  1497. static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
  1498. SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
  1499. RT5665_M_MONO_ADC_R1_SFT, 1, 1),
  1500. SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
  1501. RT5665_M_MONO_ADC_R2_SFT, 1, 1),
  1502. };
  1503. static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
  1504. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
  1505. RT5665_M_ADCMIX_L_SFT, 1, 1),
  1506. SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
  1507. RT5665_M_DAC1_L_SFT, 1, 1),
  1508. };
  1509. static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
  1510. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
  1511. RT5665_M_ADCMIX_R_SFT, 1, 1),
  1512. SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
  1513. RT5665_M_DAC1_R_SFT, 1, 1),
  1514. };
  1515. static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
  1516. SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
  1517. RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
  1518. SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
  1519. RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
  1520. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
  1521. RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
  1522. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
  1523. RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
  1524. };
  1525. static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
  1526. SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
  1527. RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
  1528. SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
  1529. RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
  1530. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
  1531. RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
  1532. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
  1533. RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
  1534. };
  1535. static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
  1536. SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
  1537. RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
  1538. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
  1539. RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
  1540. SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
  1541. RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
  1542. };
  1543. static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
  1544. SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
  1545. RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
  1546. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
  1547. RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
  1548. SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
  1549. RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
  1550. };
  1551. static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
  1552. SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
  1553. RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
  1554. SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
  1555. RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
  1556. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
  1557. RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
  1558. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
  1559. RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
  1560. };
  1561. static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
  1562. SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
  1563. RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
  1564. SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
  1565. RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
  1566. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
  1567. RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
  1568. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
  1569. RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
  1570. };
  1571. /* Analog Input Mixer */
  1572. static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
  1573. SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
  1574. RT5665_M_CBJ_RM1_L_SFT, 1, 1),
  1575. SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
  1576. RT5665_M_INL_RM1_L_SFT, 1, 1),
  1577. SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
  1578. RT5665_M_INR_RM1_L_SFT, 1, 1),
  1579. SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
  1580. RT5665_M_BST4_RM1_L_SFT, 1, 1),
  1581. SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
  1582. RT5665_M_BST3_RM1_L_SFT, 1, 1),
  1583. SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
  1584. RT5665_M_BST2_RM1_L_SFT, 1, 1),
  1585. SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
  1586. RT5665_M_BST1_RM1_L_SFT, 1, 1),
  1587. };
  1588. static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
  1589. SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
  1590. RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
  1591. SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
  1592. RT5665_M_INR_RM1_R_SFT, 1, 1),
  1593. SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
  1594. RT5665_M_BST4_RM1_R_SFT, 1, 1),
  1595. SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
  1596. RT5665_M_BST3_RM1_R_SFT, 1, 1),
  1597. SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
  1598. RT5665_M_BST2_RM1_R_SFT, 1, 1),
  1599. SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
  1600. RT5665_M_BST1_RM1_R_SFT, 1, 1),
  1601. };
  1602. static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
  1603. SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
  1604. RT5665_M_INL_RM2_L_SFT, 1, 1),
  1605. SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
  1606. RT5665_M_INR_RM2_L_SFT, 1, 1),
  1607. SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
  1608. RT5665_M_CBJ_RM2_L_SFT, 1, 1),
  1609. SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
  1610. RT5665_M_BST4_RM2_L_SFT, 1, 1),
  1611. SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
  1612. RT5665_M_BST3_RM2_L_SFT, 1, 1),
  1613. SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
  1614. RT5665_M_BST2_RM2_L_SFT, 1, 1),
  1615. SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
  1616. RT5665_M_BST1_RM2_L_SFT, 1, 1),
  1617. };
  1618. static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
  1619. SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
  1620. RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
  1621. SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
  1622. RT5665_M_INL_RM2_R_SFT, 1, 1),
  1623. SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
  1624. RT5665_M_INR_RM2_R_SFT, 1, 1),
  1625. SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
  1626. RT5665_M_BST4_RM2_R_SFT, 1, 1),
  1627. SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
  1628. RT5665_M_BST3_RM2_R_SFT, 1, 1),
  1629. SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
  1630. RT5665_M_BST2_RM2_R_SFT, 1, 1),
  1631. SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
  1632. RT5665_M_BST1_RM2_R_SFT, 1, 1),
  1633. };
  1634. static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
  1635. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
  1636. RT5665_M_DAC_L2_MM_SFT, 1, 1),
  1637. SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
  1638. RT5665_M_RECMIC2L_MM_SFT, 1, 1),
  1639. SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
  1640. RT5665_M_BST1_MM_SFT, 1, 1),
  1641. SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
  1642. RT5665_M_BST2_MM_SFT, 1, 1),
  1643. SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
  1644. RT5665_M_BST3_MM_SFT, 1, 1),
  1645. };
  1646. static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
  1647. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
  1648. RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
  1649. SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
  1650. RT5665_M_IN_L_OM_L_SFT, 1, 1),
  1651. SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
  1652. RT5665_M_BST1_OM_L_SFT, 1, 1),
  1653. SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
  1654. RT5665_M_BST2_OM_L_SFT, 1, 1),
  1655. SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
  1656. RT5665_M_BST3_OM_L_SFT, 1, 1),
  1657. };
  1658. static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
  1659. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
  1660. RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
  1661. SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
  1662. RT5665_M_IN_R_OM_R_SFT, 1, 1),
  1663. SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
  1664. RT5665_M_BST2_OM_R_SFT, 1, 1),
  1665. SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
  1666. RT5665_M_BST3_OM_R_SFT, 1, 1),
  1667. SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
  1668. RT5665_M_BST4_OM_R_SFT, 1, 1),
  1669. };
  1670. static const struct snd_kcontrol_new rt5665_mono_mix[] = {
  1671. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
  1672. RT5665_M_DAC_L2_MA_SFT, 1, 1),
  1673. SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
  1674. RT5665_M_MONOVOL_MA_SFT, 1, 1),
  1675. };
  1676. static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
  1677. SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
  1678. RT5665_M_DAC_L2_LM_SFT, 1, 1),
  1679. SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
  1680. RT5665_M_OV_L_LM_SFT, 1, 1),
  1681. };
  1682. static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
  1683. SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
  1684. RT5665_M_DAC_R2_LM_SFT, 1, 1),
  1685. SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
  1686. RT5665_M_OV_R_LM_SFT, 1, 1),
  1687. };
  1688. /*DAC L2, DAC R2*/
  1689. /*MX-17 [6:4], MX-17 [2:0]*/
  1690. static const char * const rt5665_dac2_src[] = {
  1691. "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
  1692. };
  1693. static SOC_ENUM_SINGLE_DECL(
  1694. rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
  1695. RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
  1696. static const struct snd_kcontrol_new rt5665_dac_l2_mux =
  1697. SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
  1698. static SOC_ENUM_SINGLE_DECL(
  1699. rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
  1700. RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
  1701. static const struct snd_kcontrol_new rt5665_dac_r2_mux =
  1702. SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
  1703. /*DAC L3, DAC R3*/
  1704. /*MX-1B [6:4], MX-1B [2:0]*/
  1705. static const char * const rt5665_dac3_src[] = {
  1706. "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
  1707. };
  1708. static SOC_ENUM_SINGLE_DECL(
  1709. rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
  1710. RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
  1711. static const struct snd_kcontrol_new rt5665_dac_l3_mux =
  1712. SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
  1713. static SOC_ENUM_SINGLE_DECL(
  1714. rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
  1715. RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
  1716. static const struct snd_kcontrol_new rt5665_dac_r3_mux =
  1717. SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
  1718. /* STO1 ADC1 Source */
  1719. /* MX-26 [13] [5] */
  1720. static const char * const rt5665_sto1_adc1_src[] = {
  1721. "DD Mux", "ADC"
  1722. };
  1723. static SOC_ENUM_SINGLE_DECL(
  1724. rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
  1725. RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
  1726. static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
  1727. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
  1728. static SOC_ENUM_SINGLE_DECL(
  1729. rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
  1730. RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
  1731. static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
  1732. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
  1733. /* STO1 ADC Source */
  1734. /* MX-26 [11:10] [3:2] */
  1735. static const char * const rt5665_sto1_adc_src[] = {
  1736. "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
  1737. };
  1738. static SOC_ENUM_SINGLE_DECL(
  1739. rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
  1740. RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
  1741. static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
  1742. SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
  1743. static SOC_ENUM_SINGLE_DECL(
  1744. rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
  1745. RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
  1746. static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
  1747. SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
  1748. /* STO1 ADC2 Source */
  1749. /* MX-26 [12] [4] */
  1750. static const char * const rt5665_sto1_adc2_src[] = {
  1751. "DAC MIX", "DMIC"
  1752. };
  1753. static SOC_ENUM_SINGLE_DECL(
  1754. rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
  1755. RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
  1756. static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
  1757. SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
  1758. static SOC_ENUM_SINGLE_DECL(
  1759. rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
  1760. RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
  1761. static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
  1762. SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
  1763. /* STO1 DMIC Source */
  1764. /* MX-26 [8] */
  1765. static const char * const rt5665_sto1_dmic_src[] = {
  1766. "DMIC1", "DMIC2"
  1767. };
  1768. static SOC_ENUM_SINGLE_DECL(
  1769. rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
  1770. RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
  1771. static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
  1772. SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
  1773. /* MX-26 [9] */
  1774. static const char * const rt5665_sto1_dd_l_src[] = {
  1775. "STO2 DAC", "MONO DAC"
  1776. };
  1777. static SOC_ENUM_SINGLE_DECL(
  1778. rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
  1779. RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
  1780. static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
  1781. SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
  1782. /* MX-26 [1:0] */
  1783. static const char * const rt5665_sto1_dd_r_src[] = {
  1784. "STO2 DAC", "MONO DAC", "AEC REF"
  1785. };
  1786. static SOC_ENUM_SINGLE_DECL(
  1787. rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
  1788. RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
  1789. static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
  1790. SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
  1791. /* MONO ADC L2 Source */
  1792. /* MX-27 [12] */
  1793. static const char * const rt5665_mono_adc_l2_src[] = {
  1794. "DAC MIXL", "DMIC"
  1795. };
  1796. static SOC_ENUM_SINGLE_DECL(
  1797. rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
  1798. RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
  1799. static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
  1800. SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
  1801. /* MONO ADC L1 Source */
  1802. /* MX-27 [13] */
  1803. static const char * const rt5665_mono_adc_l1_src[] = {
  1804. "DD Mux", "ADC"
  1805. };
  1806. static SOC_ENUM_SINGLE_DECL(
  1807. rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
  1808. RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
  1809. static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
  1810. SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
  1811. /* MX-27 [9][1]*/
  1812. static const char * const rt5665_mono_dd_src[] = {
  1813. "STO2 DAC", "MONO DAC"
  1814. };
  1815. static SOC_ENUM_SINGLE_DECL(
  1816. rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
  1817. RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
  1818. static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
  1819. SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
  1820. static SOC_ENUM_SINGLE_DECL(
  1821. rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
  1822. RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
  1823. static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
  1824. SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
  1825. /* MONO ADC L Source, MONO ADC R Source*/
  1826. /* MX-27 [11:10], MX-27 [3:2] */
  1827. static const char * const rt5665_mono_adc_src[] = {
  1828. "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
  1829. };
  1830. static SOC_ENUM_SINGLE_DECL(
  1831. rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
  1832. RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
  1833. static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
  1834. SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
  1835. static SOC_ENUM_SINGLE_DECL(
  1836. rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
  1837. RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
  1838. static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
  1839. SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
  1840. /* MONO DMIC L Source */
  1841. /* MX-27 [8] */
  1842. static const char * const rt5665_mono_dmic_l_src[] = {
  1843. "DMIC1 L", "DMIC2 L"
  1844. };
  1845. static SOC_ENUM_SINGLE_DECL(
  1846. rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
  1847. RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
  1848. static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
  1849. SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
  1850. /* MONO ADC R2 Source */
  1851. /* MX-27 [4] */
  1852. static const char * const rt5665_mono_adc_r2_src[] = {
  1853. "DAC MIXR", "DMIC"
  1854. };
  1855. static SOC_ENUM_SINGLE_DECL(
  1856. rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
  1857. RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
  1858. static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
  1859. SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
  1860. /* MONO ADC R1 Source */
  1861. /* MX-27 [5] */
  1862. static const char * const rt5665_mono_adc_r1_src[] = {
  1863. "DD Mux", "ADC"
  1864. };
  1865. static SOC_ENUM_SINGLE_DECL(
  1866. rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
  1867. RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
  1868. static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
  1869. SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
  1870. /* MONO DMIC R Source */
  1871. /* MX-27 [0] */
  1872. static const char * const rt5665_mono_dmic_r_src[] = {
  1873. "DMIC1 R", "DMIC2 R"
  1874. };
  1875. static SOC_ENUM_SINGLE_DECL(
  1876. rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
  1877. RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
  1878. static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
  1879. SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
  1880. /* STO2 ADC1 Source */
  1881. /* MX-28 [13] [5] */
  1882. static const char * const rt5665_sto2_adc1_src[] = {
  1883. "DD Mux", "ADC"
  1884. };
  1885. static SOC_ENUM_SINGLE_DECL(
  1886. rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
  1887. RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
  1888. static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
  1889. SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
  1890. static SOC_ENUM_SINGLE_DECL(
  1891. rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
  1892. RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
  1893. static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
  1894. SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
  1895. /* STO2 ADC Source */
  1896. /* MX-28 [11:10] [3:2] */
  1897. static const char * const rt5665_sto2_adc_src[] = {
  1898. "ADC1 L", "ADC1 R", "ADC2 L"
  1899. };
  1900. static SOC_ENUM_SINGLE_DECL(
  1901. rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
  1902. RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
  1903. static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
  1904. SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
  1905. static SOC_ENUM_SINGLE_DECL(
  1906. rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
  1907. RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
  1908. static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
  1909. SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
  1910. /* STO2 ADC2 Source */
  1911. /* MX-28 [12] [4] */
  1912. static const char * const rt5665_sto2_adc2_src[] = {
  1913. "DAC MIX", "DMIC"
  1914. };
  1915. static SOC_ENUM_SINGLE_DECL(
  1916. rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
  1917. RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
  1918. static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
  1919. SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
  1920. static SOC_ENUM_SINGLE_DECL(
  1921. rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
  1922. RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
  1923. static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
  1924. SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
  1925. /* STO2 DMIC Source */
  1926. /* MX-28 [8] */
  1927. static const char * const rt5665_sto2_dmic_src[] = {
  1928. "DMIC1", "DMIC2"
  1929. };
  1930. static SOC_ENUM_SINGLE_DECL(
  1931. rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
  1932. RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
  1933. static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
  1934. SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
  1935. /* MX-28 [9] */
  1936. static const char * const rt5665_sto2_dd_l_src[] = {
  1937. "STO2 DAC", "MONO DAC"
  1938. };
  1939. static SOC_ENUM_SINGLE_DECL(
  1940. rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
  1941. RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
  1942. static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
  1943. SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
  1944. /* MX-28 [1] */
  1945. static const char * const rt5665_sto2_dd_r_src[] = {
  1946. "STO2 DAC", "MONO DAC"
  1947. };
  1948. static SOC_ENUM_SINGLE_DECL(
  1949. rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
  1950. RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
  1951. static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
  1952. SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
  1953. /* DAC R1 Source, DAC L1 Source*/
  1954. /* MX-29 [11:10], MX-29 [9:8]*/
  1955. static const char * const rt5665_dac1_src[] = {
  1956. "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
  1957. };
  1958. static SOC_ENUM_SINGLE_DECL(
  1959. rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
  1960. RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
  1961. static const struct snd_kcontrol_new rt5665_dac_r1_mux =
  1962. SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
  1963. static SOC_ENUM_SINGLE_DECL(
  1964. rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
  1965. RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
  1966. static const struct snd_kcontrol_new rt5665_dac_l1_mux =
  1967. SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
  1968. /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
  1969. /* MX-2D [13:12], MX-2D [9:8]*/
  1970. static const char * const rt5665_dig_dac_mix_src[] = {
  1971. "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
  1972. };
  1973. static SOC_ENUM_SINGLE_DECL(
  1974. rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
  1975. RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
  1976. static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
  1977. SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
  1978. static SOC_ENUM_SINGLE_DECL(
  1979. rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
  1980. RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
  1981. static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
  1982. SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
  1983. /* Analog DAC L1 Source, Analog DAC R1 Source*/
  1984. /* MX-2D [5:4], MX-2D [1:0]*/
  1985. static const char * const rt5665_alg_dac1_src[] = {
  1986. "Stereo1 DAC Mixer", "DAC1", "DMIC1"
  1987. };
  1988. static SOC_ENUM_SINGLE_DECL(
  1989. rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
  1990. RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
  1991. static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
  1992. SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
  1993. static SOC_ENUM_SINGLE_DECL(
  1994. rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
  1995. RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
  1996. static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
  1997. SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
  1998. /* Analog DAC LR Source, Analog DAC R2 Source*/
  1999. /* MX-2E [5:4], MX-2E [0]*/
  2000. static const char * const rt5665_alg_dac2_src[] = {
  2001. "Mono DAC Mixer", "DAC2"
  2002. };
  2003. static SOC_ENUM_SINGLE_DECL(
  2004. rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
  2005. RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
  2006. static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
  2007. SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
  2008. static SOC_ENUM_SINGLE_DECL(
  2009. rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
  2010. RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
  2011. static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
  2012. SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
  2013. /* Interface2 ADC Data Input*/
  2014. /* MX-2F [14:12] */
  2015. static const char * const rt5665_if2_1_adc_in_src[] = {
  2016. "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
  2017. "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
  2018. };
  2019. static SOC_ENUM_SINGLE_DECL(
  2020. rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
  2021. RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
  2022. static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
  2023. SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
  2024. /* MX-2F [6:4] */
  2025. static const char * const rt5665_if2_2_adc_in_src[] = {
  2026. "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
  2027. "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
  2028. };
  2029. static SOC_ENUM_SINGLE_DECL(
  2030. rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
  2031. RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
  2032. static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
  2033. SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
  2034. /* Interface3 ADC Data Input*/
  2035. /* MX-30 [6:4] */
  2036. static const char * const rt5665_if3_adc_in_src[] = {
  2037. "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
  2038. "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
  2039. };
  2040. static SOC_ENUM_SINGLE_DECL(
  2041. rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
  2042. RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
  2043. static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
  2044. SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
  2045. /* PDM 1 L/R*/
  2046. /* MX-31 [11:10] [9:8] */
  2047. static const char * const rt5665_pdm_src[] = {
  2048. "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
  2049. };
  2050. static SOC_ENUM_SINGLE_DECL(
  2051. rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
  2052. RT5665_PDM1_L_SFT, rt5665_pdm_src);
  2053. static const struct snd_kcontrol_new rt5665_pdm_l_mux =
  2054. SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
  2055. static SOC_ENUM_SINGLE_DECL(
  2056. rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
  2057. RT5665_PDM1_R_SFT, rt5665_pdm_src);
  2058. static const struct snd_kcontrol_new rt5665_pdm_r_mux =
  2059. SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
  2060. /* I2S1 TDM ADCDAT Source */
  2061. /* MX-7a[10] */
  2062. static const char * const rt5665_if1_1_adc1_data_src[] = {
  2063. "STO1 ADC", "IF2_1 DAC",
  2064. };
  2065. static SOC_ENUM_SINGLE_DECL(
  2066. rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
  2067. RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
  2068. static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
  2069. SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
  2070. /* MX-7a[9] */
  2071. static const char * const rt5665_if1_1_adc2_data_src[] = {
  2072. "STO2 ADC", "IF2_2 DAC",
  2073. };
  2074. static SOC_ENUM_SINGLE_DECL(
  2075. rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
  2076. RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
  2077. static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
  2078. SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
  2079. /* MX-7a[8] */
  2080. static const char * const rt5665_if1_1_adc3_data_src[] = {
  2081. "MONO ADC", "IF3 DAC",
  2082. };
  2083. static SOC_ENUM_SINGLE_DECL(
  2084. rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
  2085. RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
  2086. static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
  2087. SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
  2088. /* MX-7b[10] */
  2089. static const char * const rt5665_if1_2_adc1_data_src[] = {
  2090. "STO1 ADC", "IF1 DAC",
  2091. };
  2092. static SOC_ENUM_SINGLE_DECL(
  2093. rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
  2094. RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
  2095. static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
  2096. SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
  2097. /* MX-7b[9] */
  2098. static const char * const rt5665_if1_2_adc2_data_src[] = {
  2099. "STO2 ADC", "IF2_1 DAC",
  2100. };
  2101. static SOC_ENUM_SINGLE_DECL(
  2102. rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
  2103. RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
  2104. static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
  2105. SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
  2106. /* MX-7b[8] */
  2107. static const char * const rt5665_if1_2_adc3_data_src[] = {
  2108. "MONO ADC", "IF2_2 DAC",
  2109. };
  2110. static SOC_ENUM_SINGLE_DECL(
  2111. rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
  2112. RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
  2113. static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
  2114. SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
  2115. /* MX-7b[7] */
  2116. static const char * const rt5665_if1_2_adc4_data_src[] = {
  2117. "DAC1", "IF3 DAC",
  2118. };
  2119. static SOC_ENUM_SINGLE_DECL(
  2120. rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
  2121. RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
  2122. static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
  2123. SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
  2124. /* MX-7a[4:0] MX-7b[4:0] */
  2125. static const char * const rt5665_tdm_adc_data_src[] = {
  2126. "1234", "1243", "1324", "1342", "1432", "1423",
  2127. "2134", "2143", "2314", "2341", "2431", "2413",
  2128. "3124", "3142", "3214", "3241", "3412", "3421",
  2129. "4123", "4132", "4213", "4231", "4312", "4321"
  2130. };
  2131. static SOC_ENUM_SINGLE_DECL(
  2132. rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
  2133. RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
  2134. static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
  2135. SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
  2136. static SOC_ENUM_SINGLE_DECL(
  2137. rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
  2138. RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
  2139. static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
  2140. SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
  2141. /* Out Volume Switch */
  2142. static const struct snd_kcontrol_new monovol_switch =
  2143. SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
  2144. static const struct snd_kcontrol_new outvol_l_switch =
  2145. SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
  2146. static const struct snd_kcontrol_new outvol_r_switch =
  2147. SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
  2148. /* Out Switch */
  2149. static const struct snd_kcontrol_new mono_switch =
  2150. SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
  2151. static const struct snd_kcontrol_new hpo_switch =
  2152. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
  2153. RT5665_VOL_L_SFT, 1, 0);
  2154. static const struct snd_kcontrol_new lout_l_switch =
  2155. SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
  2156. static const struct snd_kcontrol_new lout_r_switch =
  2157. SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
  2158. static const struct snd_kcontrol_new pdm_l_switch =
  2159. SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
  2160. RT5665_M_PDM1_L_SFT, 1, 1);
  2161. static const struct snd_kcontrol_new pdm_r_switch =
  2162. SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
  2163. RT5665_M_PDM1_R_SFT, 1, 1);
  2164. static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
  2165. struct snd_kcontrol *kcontrol, int event)
  2166. {
  2167. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2168. switch (event) {
  2169. case SND_SOC_DAPM_PRE_PMU:
  2170. snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
  2171. RT5665_NG2_EN_MASK, RT5665_NG2_EN);
  2172. snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
  2173. 0x0);
  2174. snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10);
  2175. snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20);
  2176. break;
  2177. case SND_SOC_DAPM_POST_PMD:
  2178. snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0);
  2179. snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0);
  2180. snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
  2181. 0x40);
  2182. snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
  2183. RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
  2184. break;
  2185. default:
  2186. return 0;
  2187. }
  2188. return 0;
  2189. }
  2190. static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
  2191. struct snd_kcontrol *kcontrol, int event)
  2192. {
  2193. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2194. switch (event) {
  2195. case SND_SOC_DAPM_PRE_PMU:
  2196. snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
  2197. RT5665_NG2_EN_MASK, RT5665_NG2_EN);
  2198. snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003);
  2199. break;
  2200. case SND_SOC_DAPM_POST_PMD:
  2201. snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002);
  2202. snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
  2203. RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
  2204. break;
  2205. default:
  2206. return 0;
  2207. }
  2208. return 0;
  2209. }
  2210. static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
  2211. struct snd_kcontrol *kcontrol, int event)
  2212. {
  2213. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2214. switch (event) {
  2215. case SND_SOC_DAPM_POST_PMU:
  2216. snd_soc_component_update_bits(component, RT5665_DEPOP_1,
  2217. RT5665_PUMP_EN, RT5665_PUMP_EN);
  2218. break;
  2219. case SND_SOC_DAPM_PRE_PMD:
  2220. snd_soc_component_update_bits(component, RT5665_DEPOP_1,
  2221. RT5665_PUMP_EN, 0);
  2222. break;
  2223. default:
  2224. return 0;
  2225. }
  2226. return 0;
  2227. }
  2228. static int set_dmic_power(struct snd_soc_dapm_widget *w,
  2229. struct snd_kcontrol *kcontrol, int event)
  2230. {
  2231. switch (event) {
  2232. case SND_SOC_DAPM_POST_PMU:
  2233. /*Add delay to avoid pop noise*/
  2234. msleep(150);
  2235. break;
  2236. default:
  2237. return 0;
  2238. }
  2239. return 0;
  2240. }
  2241. static int rt5665_set_verf(struct snd_soc_dapm_widget *w,
  2242. struct snd_kcontrol *kcontrol, int event)
  2243. {
  2244. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2245. switch (event) {
  2246. case SND_SOC_DAPM_PRE_PMU:
  2247. switch (w->shift) {
  2248. case RT5665_PWR_VREF1_BIT:
  2249. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2250. RT5665_PWR_FV1, 0);
  2251. break;
  2252. case RT5665_PWR_VREF2_BIT:
  2253. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2254. RT5665_PWR_FV2, 0);
  2255. break;
  2256. case RT5665_PWR_VREF3_BIT:
  2257. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2258. RT5665_PWR_FV3, 0);
  2259. break;
  2260. default:
  2261. break;
  2262. }
  2263. break;
  2264. case SND_SOC_DAPM_POST_PMU:
  2265. usleep_range(15000, 20000);
  2266. switch (w->shift) {
  2267. case RT5665_PWR_VREF1_BIT:
  2268. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2269. RT5665_PWR_FV1, RT5665_PWR_FV1);
  2270. break;
  2271. case RT5665_PWR_VREF2_BIT:
  2272. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2273. RT5665_PWR_FV2, RT5665_PWR_FV2);
  2274. break;
  2275. case RT5665_PWR_VREF3_BIT:
  2276. snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
  2277. RT5665_PWR_FV3, RT5665_PWR_FV3);
  2278. break;
  2279. default:
  2280. break;
  2281. }
  2282. break;
  2283. default:
  2284. return 0;
  2285. }
  2286. return 0;
  2287. }
  2288. static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
  2289. struct snd_kcontrol *kcontrol, int event)
  2290. {
  2291. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2292. unsigned int val1, val2, mask1 = 0, mask2 = 0;
  2293. switch (w->shift) {
  2294. case RT5665_PWR_I2S2_1_BIT:
  2295. mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
  2296. RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
  2297. val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
  2298. RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
  2299. break;
  2300. case RT5665_PWR_I2S2_2_BIT:
  2301. mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
  2302. RT5665_GP8_PIN_MASK;
  2303. val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
  2304. RT5665_GP8_PIN_DACDAT2_2;
  2305. mask2 = RT5665_GP9_PIN_MASK;
  2306. val2 = RT5665_GP9_PIN_ADCDAT2_2;
  2307. break;
  2308. case RT5665_PWR_I2S3_BIT:
  2309. mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
  2310. RT5665_GP8_PIN_MASK;
  2311. val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
  2312. RT5665_GP8_PIN_DACDAT3;
  2313. mask2 = RT5665_GP9_PIN_MASK;
  2314. val2 = RT5665_GP9_PIN_ADCDAT3;
  2315. break;
  2316. }
  2317. switch (event) {
  2318. case SND_SOC_DAPM_PRE_PMU:
  2319. if (mask1)
  2320. snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
  2321. mask1, val1);
  2322. if (mask2)
  2323. snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
  2324. mask2, val2);
  2325. break;
  2326. case SND_SOC_DAPM_POST_PMD:
  2327. if (mask1)
  2328. snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
  2329. mask1, 0);
  2330. if (mask2)
  2331. snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
  2332. mask2, 0);
  2333. break;
  2334. default:
  2335. return 0;
  2336. }
  2337. return 0;
  2338. }
  2339. static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
  2340. SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
  2341. NULL, 0),
  2342. SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
  2343. NULL, 0),
  2344. SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
  2345. RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
  2346. SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
  2347. rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  2348. SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
  2349. rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  2350. SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
  2351. rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  2352. /* ASRC */
  2353. SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
  2354. RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
  2355. SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
  2356. RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
  2357. SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
  2358. RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
  2359. SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
  2360. RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
  2361. SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
  2362. RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
  2363. SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
  2364. RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
  2365. SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
  2366. RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
  2367. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
  2368. RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
  2369. SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
  2370. RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
  2371. SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
  2372. RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
  2373. SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
  2374. RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
  2375. SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
  2376. RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
  2377. SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
  2378. RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
  2379. SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
  2380. RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
  2381. SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
  2382. RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
  2383. /* Input Side */
  2384. SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
  2385. 0, NULL, 0),
  2386. SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
  2387. 0, NULL, 0),
  2388. SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
  2389. 0, NULL, 0),
  2390. /* Input Lines */
  2391. SND_SOC_DAPM_INPUT("DMIC L1"),
  2392. SND_SOC_DAPM_INPUT("DMIC R1"),
  2393. SND_SOC_DAPM_INPUT("DMIC L2"),
  2394. SND_SOC_DAPM_INPUT("DMIC R2"),
  2395. SND_SOC_DAPM_INPUT("IN1P"),
  2396. SND_SOC_DAPM_INPUT("IN1N"),
  2397. SND_SOC_DAPM_INPUT("IN2P"),
  2398. SND_SOC_DAPM_INPUT("IN2N"),
  2399. SND_SOC_DAPM_INPUT("IN3P"),
  2400. SND_SOC_DAPM_INPUT("IN3N"),
  2401. SND_SOC_DAPM_INPUT("IN4P"),
  2402. SND_SOC_DAPM_INPUT("IN4N"),
  2403. SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2404. SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2405. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  2406. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  2407. SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
  2408. RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
  2409. SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
  2410. RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
  2411. /* Boost */
  2412. SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
  2413. 0, 0, NULL, 0),
  2414. SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
  2415. 0, 0, NULL, 0),
  2416. SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
  2417. 0, 0, NULL, 0),
  2418. SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
  2419. 0, 0, NULL, 0),
  2420. SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
  2421. 0, 0, NULL, 0),
  2422. SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
  2423. RT5665_PWR_BST1_BIT, 0, NULL, 0),
  2424. SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
  2425. RT5665_PWR_BST2_BIT, 0, NULL, 0),
  2426. SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
  2427. RT5665_PWR_BST3_BIT, 0, NULL, 0),
  2428. SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
  2429. RT5665_PWR_BST4_BIT, 0, NULL, 0),
  2430. SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
  2431. RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
  2432. SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
  2433. RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
  2434. SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
  2435. RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
  2436. SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
  2437. RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
  2438. SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
  2439. RT5665_PWR_CBJ_BIT, 0, NULL, 0),
  2440. /* Input Volume */
  2441. SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
  2442. 0, NULL, 0),
  2443. SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
  2444. 0, NULL, 0),
  2445. /* REC Mixer */
  2446. SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
  2447. ARRAY_SIZE(rt5665_rec1_l_mix)),
  2448. SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
  2449. ARRAY_SIZE(rt5665_rec1_r_mix)),
  2450. SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
  2451. ARRAY_SIZE(rt5665_rec2_l_mix)),
  2452. SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
  2453. ARRAY_SIZE(rt5665_rec2_r_mix)),
  2454. SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
  2455. RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
  2456. SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
  2457. RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
  2458. SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
  2459. RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
  2460. SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
  2461. RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
  2462. /* ADCs */
  2463. SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
  2464. SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
  2465. SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
  2466. SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
  2467. SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
  2468. RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
  2469. SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
  2470. RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
  2471. SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
  2472. RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
  2473. SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
  2474. RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
  2475. SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
  2476. RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
  2477. SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
  2478. RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
  2479. /* ADC Mux */
  2480. SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
  2481. &rt5665_sto1_dmic_mux),
  2482. SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
  2483. &rt5665_sto1_dmic_mux),
  2484. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  2485. &rt5665_sto1_adc1l_mux),
  2486. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  2487. &rt5665_sto1_adc1r_mux),
  2488. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  2489. &rt5665_sto1_adc2l_mux),
  2490. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  2491. &rt5665_sto1_adc2r_mux),
  2492. SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
  2493. &rt5665_sto1_adcl_mux),
  2494. SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
  2495. &rt5665_sto1_adcr_mux),
  2496. SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
  2497. &rt5665_sto1_dd_l_mux),
  2498. SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
  2499. &rt5665_sto1_dd_r_mux),
  2500. SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  2501. &rt5665_mono_adc_l2_mux),
  2502. SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  2503. &rt5665_mono_adc_r2_mux),
  2504. SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  2505. &rt5665_mono_adc_l1_mux),
  2506. SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  2507. &rt5665_mono_adc_r1_mux),
  2508. SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
  2509. &rt5665_mono_dmic_l_mux),
  2510. SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
  2511. &rt5665_mono_dmic_r_mux),
  2512. SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
  2513. &rt5665_mono_adc_l_mux),
  2514. SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
  2515. &rt5665_mono_adc_r_mux),
  2516. SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
  2517. &rt5665_mono_dd_l_mux),
  2518. SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
  2519. &rt5665_mono_dd_r_mux),
  2520. SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
  2521. &rt5665_sto2_dmic_mux),
  2522. SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
  2523. &rt5665_sto2_dmic_mux),
  2524. SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  2525. &rt5665_sto2_adc1l_mux),
  2526. SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  2527. &rt5665_sto2_adc1r_mux),
  2528. SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  2529. &rt5665_sto2_adc2l_mux),
  2530. SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  2531. &rt5665_sto2_adc2r_mux),
  2532. SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
  2533. &rt5665_sto2_adcl_mux),
  2534. SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
  2535. &rt5665_sto2_adcr_mux),
  2536. SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
  2537. &rt5665_sto2_dd_l_mux),
  2538. SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
  2539. &rt5665_sto2_dd_r_mux),
  2540. /* ADC Mixer */
  2541. SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
  2542. RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
  2543. SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
  2544. RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
  2545. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
  2546. RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
  2547. ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
  2548. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
  2549. RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
  2550. ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
  2551. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
  2552. RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
  2553. ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
  2554. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
  2555. RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
  2556. ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
  2557. SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
  2558. RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
  2559. SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
  2560. RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
  2561. ARRAY_SIZE(rt5665_mono_adc_l_mix)),
  2562. SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
  2563. RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
  2564. SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
  2565. RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
  2566. ARRAY_SIZE(rt5665_mono_adc_r_mix)),
  2567. /* ADC PGA */
  2568. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2569. SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2570. SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2571. /* Digital Interface */
  2572. SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
  2573. 0, NULL, 0),
  2574. SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
  2575. 0, NULL, 0),
  2576. SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
  2577. 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
  2578. SND_SOC_DAPM_POST_PMD),
  2579. SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
  2580. 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
  2581. SND_SOC_DAPM_POST_PMD),
  2582. SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
  2583. 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
  2584. SND_SOC_DAPM_POST_PMD),
  2585. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  2586. SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  2587. SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  2588. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2589. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2590. SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2591. SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2592. SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2593. SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2594. SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2595. SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2596. SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2597. SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2598. SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2599. SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2600. SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2601. SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2602. SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2603. SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  2604. SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  2605. SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  2606. /* Digital Interface Select */
  2607. SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2608. &rt5665_if1_1_adc1_mux),
  2609. SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2610. &rt5665_if1_1_adc2_mux),
  2611. SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
  2612. &rt5665_if1_1_adc3_mux),
  2613. SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  2614. SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
  2615. &rt5665_if1_2_adc1_mux),
  2616. SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
  2617. &rt5665_if1_2_adc2_mux),
  2618. SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
  2619. &rt5665_if1_2_adc3_mux),
  2620. SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
  2621. &rt5665_if1_2_adc4_mux),
  2622. SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
  2623. &rt5665_tdm1_adc_mux),
  2624. SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
  2625. &rt5665_tdm1_adc_mux),
  2626. SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
  2627. &rt5665_tdm1_adc_mux),
  2628. SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
  2629. &rt5665_tdm1_adc_mux),
  2630. SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
  2631. &rt5665_tdm2_adc_mux),
  2632. SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
  2633. &rt5665_tdm2_adc_mux),
  2634. SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
  2635. &rt5665_tdm2_adc_mux),
  2636. SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
  2637. &rt5665_tdm2_adc_mux),
  2638. SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
  2639. &rt5665_if2_1_adc_in_mux),
  2640. SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
  2641. &rt5665_if2_2_adc_in_mux),
  2642. SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
  2643. &rt5665_if3_adc_in_mux),
  2644. SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2645. &rt5665_if1_1_01_adc_swap_mux),
  2646. SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2647. &rt5665_if1_1_01_adc_swap_mux),
  2648. SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2649. &rt5665_if1_1_23_adc_swap_mux),
  2650. SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2651. &rt5665_if1_1_23_adc_swap_mux),
  2652. SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2653. &rt5665_if1_1_45_adc_swap_mux),
  2654. SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2655. &rt5665_if1_1_45_adc_swap_mux),
  2656. SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2657. &rt5665_if1_1_67_adc_swap_mux),
  2658. SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2659. &rt5665_if1_1_67_adc_swap_mux),
  2660. SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2661. &rt5665_if1_2_01_adc_swap_mux),
  2662. SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2663. &rt5665_if1_2_01_adc_swap_mux),
  2664. SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2665. &rt5665_if1_2_23_adc_swap_mux),
  2666. SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2667. &rt5665_if1_2_23_adc_swap_mux),
  2668. SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2669. &rt5665_if1_2_45_adc_swap_mux),
  2670. SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2671. &rt5665_if1_2_45_adc_swap_mux),
  2672. SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2673. &rt5665_if1_2_67_adc_swap_mux),
  2674. SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2675. &rt5665_if1_2_67_adc_swap_mux),
  2676. SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
  2677. &rt5665_if2_1_dac_swap_mux),
  2678. SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2679. &rt5665_if2_1_adc_swap_mux),
  2680. SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
  2681. &rt5665_if2_2_dac_swap_mux),
  2682. SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2683. &rt5665_if2_2_adc_swap_mux),
  2684. SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
  2685. &rt5665_if3_dac_swap_mux),
  2686. SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  2687. &rt5665_if3_adc_swap_mux),
  2688. /* Audio Interface */
  2689. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
  2690. 0, SND_SOC_NOPM, 0, 0),
  2691. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
  2692. 1, SND_SOC_NOPM, 0, 0),
  2693. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
  2694. 2, SND_SOC_NOPM, 0, 0),
  2695. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
  2696. 3, SND_SOC_NOPM, 0, 0),
  2697. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
  2698. 4, SND_SOC_NOPM, 0, 0),
  2699. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
  2700. 5, SND_SOC_NOPM, 0, 0),
  2701. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
  2702. 6, SND_SOC_NOPM, 0, 0),
  2703. SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
  2704. 7, SND_SOC_NOPM, 0, 0),
  2705. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
  2706. 0, SND_SOC_NOPM, 0, 0),
  2707. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
  2708. 1, SND_SOC_NOPM, 0, 0),
  2709. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
  2710. 2, SND_SOC_NOPM, 0, 0),
  2711. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
  2712. 3, SND_SOC_NOPM, 0, 0),
  2713. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
  2714. 4, SND_SOC_NOPM, 0, 0),
  2715. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
  2716. 5, SND_SOC_NOPM, 0, 0),
  2717. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
  2718. 6, SND_SOC_NOPM, 0, 0),
  2719. SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
  2720. 7, SND_SOC_NOPM, 0, 0),
  2721. SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
  2722. 0, SND_SOC_NOPM, 0, 0),
  2723. SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
  2724. 0, SND_SOC_NOPM, 0, 0),
  2725. SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
  2726. 0, SND_SOC_NOPM, 0, 0),
  2727. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
  2728. 0, SND_SOC_NOPM, 0, 0),
  2729. SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
  2730. 0, SND_SOC_NOPM, 0, 0),
  2731. SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
  2732. 0, SND_SOC_NOPM, 0, 0),
  2733. SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
  2734. 0, SND_SOC_NOPM, 0, 0),
  2735. /* Output Side */
  2736. /* DAC mixer before sound effect */
  2737. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  2738. rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
  2739. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  2740. rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
  2741. /* DAC channel Mux */
  2742. SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
  2743. SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
  2744. SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
  2745. SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
  2746. SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
  2747. SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
  2748. SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
  2749. &rt5665_alg_dac_l1_mux),
  2750. SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
  2751. &rt5665_alg_dac_r1_mux),
  2752. SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
  2753. &rt5665_alg_dac_l2_mux),
  2754. SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
  2755. &rt5665_alg_dac_r2_mux),
  2756. /* DAC Mixer */
  2757. SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
  2758. RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
  2759. SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
  2760. RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
  2761. SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
  2762. RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
  2763. SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
  2764. RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
  2765. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
  2766. rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
  2767. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
  2768. rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
  2769. SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
  2770. rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
  2771. SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
  2772. rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
  2773. SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
  2774. rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
  2775. SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
  2776. rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
  2777. SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
  2778. &rt5665_dig_dac_mixl_mux),
  2779. SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
  2780. &rt5665_dig_dac_mixr_mux),
  2781. /* DACs */
  2782. SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
  2783. SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
  2784. SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
  2785. RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
  2786. SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
  2787. RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
  2788. SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
  2789. SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
  2790. SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  2791. SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
  2792. RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
  2793. SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
  2794. RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
  2795. /* OUT Mixer */
  2796. SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
  2797. 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
  2798. SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
  2799. 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
  2800. SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
  2801. 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
  2802. /* Output Volume */
  2803. SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
  2804. &monovol_switch),
  2805. SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
  2806. &outvol_l_switch),
  2807. SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
  2808. &outvol_r_switch),
  2809. /* MONO/HPO/LOUT */
  2810. SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
  2811. ARRAY_SIZE(rt5665_mono_mix)),
  2812. SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
  2813. ARRAY_SIZE(rt5665_lout_l_mix)),
  2814. SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
  2815. ARRAY_SIZE(rt5665_lout_r_mix)),
  2816. SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
  2817. 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
  2818. SND_SOC_DAPM_PRE_PMU),
  2819. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
  2820. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
  2821. SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
  2822. RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
  2823. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
  2824. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
  2825. SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
  2826. rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
  2827. SND_SOC_DAPM_POST_PMD),
  2828. SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
  2829. &mono_switch),
  2830. SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
  2831. &hpo_switch),
  2832. SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
  2833. &lout_l_switch),
  2834. SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
  2835. &lout_r_switch),
  2836. SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
  2837. &pdm_l_switch),
  2838. SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
  2839. &pdm_r_switch),
  2840. /* PDM */
  2841. SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
  2842. RT5665_PWR_PDM1_BIT, 0, NULL, 0),
  2843. SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
  2844. 0, 1, &rt5665_pdm_l_mux),
  2845. SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
  2846. 0, 1, &rt5665_pdm_r_mux),
  2847. /* CLK DET */
  2848. SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
  2849. 0, NULL, 0),
  2850. SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
  2851. 0, NULL, 0),
  2852. SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
  2853. 0, NULL, 0),
  2854. SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
  2855. 0, NULL, 0),
  2856. SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
  2857. 0, NULL, 0),
  2858. /* Output Lines */
  2859. SND_SOC_DAPM_OUTPUT("HPOL"),
  2860. SND_SOC_DAPM_OUTPUT("HPOR"),
  2861. SND_SOC_DAPM_OUTPUT("LOUTL"),
  2862. SND_SOC_DAPM_OUTPUT("LOUTR"),
  2863. SND_SOC_DAPM_OUTPUT("MONOOUT"),
  2864. SND_SOC_DAPM_OUTPUT("PDML"),
  2865. SND_SOC_DAPM_OUTPUT("PDMR"),
  2866. };
  2867. static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
  2868. /*PLL*/
  2869. {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
  2870. {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
  2871. {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
  2872. {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
  2873. {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
  2874. {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
  2875. {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
  2876. {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
  2877. /*ASRC*/
  2878. {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
  2879. {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
  2880. {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
  2881. {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
  2882. {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
  2883. {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
  2884. {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
  2885. {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
  2886. {"I2S1 ASRC", NULL, "CLKDET"},
  2887. {"I2S2 ASRC", NULL, "CLKDET"},
  2888. {"I2S3 ASRC", NULL, "CLKDET"},
  2889. /*Vref*/
  2890. {"Mic Det Power", NULL, "Vref2"},
  2891. {"MICBIAS1", NULL, "Vref1"},
  2892. {"MICBIAS1", NULL, "Vref2"},
  2893. {"MICBIAS2", NULL, "Vref1"},
  2894. {"MICBIAS2", NULL, "Vref2"},
  2895. {"MICBIAS3", NULL, "Vref1"},
  2896. {"MICBIAS3", NULL, "Vref2"},
  2897. {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
  2898. {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
  2899. {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
  2900. {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
  2901. {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
  2902. {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
  2903. {"I2S1_1", NULL, "I2S1 ASRC"},
  2904. {"I2S1_2", NULL, "I2S1 ASRC"},
  2905. {"I2S2_1", NULL, "I2S2 ASRC"},
  2906. {"I2S2_2", NULL, "I2S2 ASRC"},
  2907. {"I2S3", NULL, "I2S3 ASRC"},
  2908. {"CLKDET SYS", NULL, "CLKDET"},
  2909. {"CLKDET HP", NULL, "CLKDET"},
  2910. {"CLKDET MONO", NULL, "CLKDET"},
  2911. {"CLKDET LOUT", NULL, "CLKDET"},
  2912. {"IN1P", NULL, "LDO2"},
  2913. {"IN2P", NULL, "LDO2"},
  2914. {"IN3P", NULL, "LDO2"},
  2915. {"IN4P", NULL, "LDO2"},
  2916. {"DMIC1", NULL, "DMIC L1"},
  2917. {"DMIC1", NULL, "DMIC R1"},
  2918. {"DMIC2", NULL, "DMIC L2"},
  2919. {"DMIC2", NULL, "DMIC R2"},
  2920. {"BST1", NULL, "IN1P"},
  2921. {"BST1", NULL, "IN1N"},
  2922. {"BST1", NULL, "BST1 Power"},
  2923. {"BST1", NULL, "BST1P Power"},
  2924. {"BST2", NULL, "IN2P"},
  2925. {"BST2", NULL, "IN2N"},
  2926. {"BST2", NULL, "BST2 Power"},
  2927. {"BST2", NULL, "BST2P Power"},
  2928. {"BST3", NULL, "IN3P"},
  2929. {"BST3", NULL, "IN3N"},
  2930. {"BST3", NULL, "BST3 Power"},
  2931. {"BST3", NULL, "BST3P Power"},
  2932. {"BST4", NULL, "IN4P"},
  2933. {"BST4", NULL, "IN4N"},
  2934. {"BST4", NULL, "BST4 Power"},
  2935. {"BST4", NULL, "BST4P Power"},
  2936. {"BST1 CBJ", NULL, "IN1P"},
  2937. {"BST1 CBJ", NULL, "IN1N"},
  2938. {"BST1 CBJ", NULL, "CBJ Power"},
  2939. {"CBJ Power", NULL, "Vref2"},
  2940. {"INL VOL", NULL, "IN3P"},
  2941. {"INR VOL", NULL, "IN3N"},
  2942. {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
  2943. {"RECMIX1L", "INL Switch", "INL VOL"},
  2944. {"RECMIX1L", "INR Switch", "INR VOL"},
  2945. {"RECMIX1L", "BST4 Switch", "BST4"},
  2946. {"RECMIX1L", "BST3 Switch", "BST3"},
  2947. {"RECMIX1L", "BST2 Switch", "BST2"},
  2948. {"RECMIX1L", "BST1 Switch", "BST1"},
  2949. {"RECMIX1L", NULL, "RECMIX1L Power"},
  2950. {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
  2951. {"RECMIX1R", "INR Switch", "INR VOL"},
  2952. {"RECMIX1R", "BST4 Switch", "BST4"},
  2953. {"RECMIX1R", "BST3 Switch", "BST3"},
  2954. {"RECMIX1R", "BST2 Switch", "BST2"},
  2955. {"RECMIX1R", "BST1 Switch", "BST1"},
  2956. {"RECMIX1R", NULL, "RECMIX1R Power"},
  2957. {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
  2958. {"RECMIX2L", "INL Switch", "INL VOL"},
  2959. {"RECMIX2L", "INR Switch", "INR VOL"},
  2960. {"RECMIX2L", "BST4 Switch", "BST4"},
  2961. {"RECMIX2L", "BST3 Switch", "BST3"},
  2962. {"RECMIX2L", "BST2 Switch", "BST2"},
  2963. {"RECMIX2L", "BST1 Switch", "BST1"},
  2964. {"RECMIX2L", NULL, "RECMIX2L Power"},
  2965. {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
  2966. {"RECMIX2R", "INL Switch", "INL VOL"},
  2967. {"RECMIX2R", "INR Switch", "INR VOL"},
  2968. {"RECMIX2R", "BST4 Switch", "BST4"},
  2969. {"RECMIX2R", "BST3 Switch", "BST3"},
  2970. {"RECMIX2R", "BST2 Switch", "BST2"},
  2971. {"RECMIX2R", "BST1 Switch", "BST1"},
  2972. {"RECMIX2R", NULL, "RECMIX2R Power"},
  2973. {"ADC1 L", NULL, "RECMIX1L"},
  2974. {"ADC1 L", NULL, "ADC1 L Power"},
  2975. {"ADC1 L", NULL, "ADC1 clock"},
  2976. {"ADC1 R", NULL, "RECMIX1R"},
  2977. {"ADC1 R", NULL, "ADC1 R Power"},
  2978. {"ADC1 R", NULL, "ADC1 clock"},
  2979. {"ADC2 L", NULL, "RECMIX2L"},
  2980. {"ADC2 L", NULL, "ADC2 L Power"},
  2981. {"ADC2 L", NULL, "ADC2 clock"},
  2982. {"ADC2 R", NULL, "RECMIX2R"},
  2983. {"ADC2 R", NULL, "ADC2 R Power"},
  2984. {"ADC2 R", NULL, "ADC2 clock"},
  2985. {"DMIC L1", NULL, "DMIC CLK"},
  2986. {"DMIC L1", NULL, "DMIC1 Power"},
  2987. {"DMIC R1", NULL, "DMIC CLK"},
  2988. {"DMIC R1", NULL, "DMIC1 Power"},
  2989. {"DMIC L2", NULL, "DMIC CLK"},
  2990. {"DMIC L2", NULL, "DMIC2 Power"},
  2991. {"DMIC R2", NULL, "DMIC CLK"},
  2992. {"DMIC R2", NULL, "DMIC2 Power"},
  2993. {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
  2994. {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
  2995. {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
  2996. {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
  2997. {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
  2998. {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
  2999. {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
  3000. {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
  3001. {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
  3002. {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
  3003. {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
  3004. {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
  3005. {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
  3006. {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
  3007. {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
  3008. {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
  3009. {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
  3010. {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
  3011. {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
  3012. {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
  3013. {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
  3014. {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
  3015. {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
  3016. {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
  3017. {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
  3018. {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
  3019. {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
  3020. {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
  3021. {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
  3022. {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
  3023. {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
  3024. {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
  3025. {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
  3026. {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
  3027. {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
  3028. {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
  3029. {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
  3030. {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
  3031. {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
  3032. {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
  3033. {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
  3034. {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
  3035. {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
  3036. {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
  3037. {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
  3038. {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
  3039. {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
  3040. {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
  3041. {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
  3042. {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
  3043. {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
  3044. {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
  3045. {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
  3046. {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
  3047. {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
  3048. {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
  3049. {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
  3050. {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
  3051. {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
  3052. {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
  3053. {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
  3054. {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
  3055. {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
  3056. {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
  3057. {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
  3058. {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
  3059. {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
  3060. {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
  3061. {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
  3062. {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
  3063. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  3064. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  3065. {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
  3066. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  3067. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  3068. {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
  3069. {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
  3070. {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
  3071. {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
  3072. {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
  3073. {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
  3074. {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
  3075. {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
  3076. {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
  3077. {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
  3078. {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
  3079. {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
  3080. {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
  3081. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
  3082. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
  3083. {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
  3084. {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
  3085. {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
  3086. {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
  3087. {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
  3088. {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
  3089. {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
  3090. {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
  3091. {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
  3092. {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
  3093. {"IF1_1_ADC4", NULL, "DAC1 MIX"},
  3094. {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
  3095. {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
  3096. {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
  3097. {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
  3098. {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
  3099. {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
  3100. {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
  3101. {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
  3102. {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
  3103. {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
  3104. {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
  3105. {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
  3106. {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
  3107. {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
  3108. {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
  3109. {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
  3110. {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
  3111. {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
  3112. {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
  3113. {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
  3114. {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
  3115. {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
  3116. {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
  3117. {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
  3118. {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
  3119. {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
  3120. {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
  3121. {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
  3122. {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
  3123. {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
  3124. {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
  3125. {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
  3126. {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
  3127. {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
  3128. {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
  3129. {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
  3130. {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
  3131. {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
  3132. {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
  3133. {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
  3134. {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
  3135. {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
  3136. {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
  3137. {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
  3138. {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
  3139. {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
  3140. {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
  3141. {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
  3142. {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
  3143. {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
  3144. {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
  3145. {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
  3146. {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
  3147. {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
  3148. {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
  3149. {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
  3150. {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
  3151. {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
  3152. {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
  3153. {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
  3154. {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
  3155. {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
  3156. {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
  3157. {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
  3158. {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
  3159. {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
  3160. {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
  3161. {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
  3162. {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
  3163. {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
  3164. {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
  3165. {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
  3166. {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
  3167. {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
  3168. {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
  3169. {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
  3170. {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
  3171. {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
  3172. {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
  3173. {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
  3174. {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
  3175. {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
  3176. {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
  3177. {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
  3178. {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
  3179. {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
  3180. {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
  3181. {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
  3182. {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
  3183. {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
  3184. {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
  3185. {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
  3186. {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
  3187. {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
  3188. {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
  3189. {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
  3190. {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
  3191. {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
  3192. {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
  3193. {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
  3194. {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
  3195. {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
  3196. {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
  3197. {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
  3198. {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
  3199. {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
  3200. {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
  3201. {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
  3202. {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
  3203. {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
  3204. {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
  3205. {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
  3206. {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
  3207. {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
  3208. {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
  3209. {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
  3210. {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
  3211. {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
  3212. {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
  3213. {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
  3214. {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
  3215. {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
  3216. {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
  3217. {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
  3218. {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
  3219. {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
  3220. {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
  3221. {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
  3222. {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
  3223. {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
  3224. {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
  3225. {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
  3226. {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
  3227. {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
  3228. {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
  3229. {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
  3230. {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
  3231. {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
  3232. {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
  3233. {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
  3234. {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
  3235. {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
  3236. {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
  3237. {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
  3238. {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
  3239. {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
  3240. {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
  3241. {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
  3242. {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
  3243. {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
  3244. {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
  3245. {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
  3246. {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
  3247. {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
  3248. {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
  3249. {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
  3250. {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
  3251. {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
  3252. {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
  3253. {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
  3254. {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
  3255. {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
  3256. {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
  3257. {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
  3258. {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
  3259. {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
  3260. {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
  3261. {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
  3262. {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
  3263. {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
  3264. {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
  3265. {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
  3266. {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
  3267. {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
  3268. {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
  3269. {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
  3270. {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
  3271. {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
  3272. {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
  3273. {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
  3274. {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
  3275. {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
  3276. {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
  3277. {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
  3278. {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
  3279. {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
  3280. {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
  3281. {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
  3282. {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
  3283. {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
  3284. {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
  3285. {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
  3286. {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
  3287. {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
  3288. {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
  3289. {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
  3290. {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
  3291. {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
  3292. {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
  3293. {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
  3294. {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
  3295. {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
  3296. {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
  3297. {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
  3298. {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
  3299. {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
  3300. {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
  3301. {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
  3302. {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
  3303. {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
  3304. {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
  3305. {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
  3306. {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
  3307. {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
  3308. {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
  3309. {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
  3310. {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
  3311. {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
  3312. {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
  3313. {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
  3314. {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
  3315. {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
  3316. {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
  3317. {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
  3318. {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
  3319. {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
  3320. {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
  3321. {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
  3322. {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
  3323. {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
  3324. {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
  3325. {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
  3326. {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
  3327. {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
  3328. {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
  3329. {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
  3330. {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
  3331. {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
  3332. {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
  3333. {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
  3334. {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
  3335. {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
  3336. {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
  3337. {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
  3338. {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
  3339. {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
  3340. {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
  3341. {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
  3342. {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
  3343. {"IF2_1 ADC", NULL, "I2S2_1"},
  3344. {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
  3345. {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
  3346. {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
  3347. {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
  3348. {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
  3349. {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
  3350. {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
  3351. {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
  3352. {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
  3353. {"IF2_2 ADC", NULL, "I2S2_2"},
  3354. {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
  3355. {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
  3356. {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
  3357. {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
  3358. {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
  3359. {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
  3360. {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
  3361. {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
  3362. {"IF3 ADC", NULL, "IF3 ADC Mux"},
  3363. {"IF3 ADC", NULL, "I2S3"},
  3364. {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
  3365. {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
  3366. {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
  3367. {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
  3368. {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
  3369. {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
  3370. {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
  3371. {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
  3372. {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
  3373. {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
  3374. {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
  3375. {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
  3376. {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
  3377. {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
  3378. {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
  3379. {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
  3380. {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
  3381. {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
  3382. {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
  3383. {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
  3384. {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
  3385. {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
  3386. {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
  3387. {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
  3388. {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
  3389. {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
  3390. {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
  3391. {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
  3392. {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
  3393. {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
  3394. {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
  3395. {"IF1 DAC1", NULL, "AIF1RX"},
  3396. {"IF1 DAC2", NULL, "AIF1RX"},
  3397. {"IF1 DAC3", NULL, "AIF1RX"},
  3398. {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
  3399. {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
  3400. {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
  3401. {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
  3402. {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
  3403. {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
  3404. {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
  3405. {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
  3406. {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
  3407. {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
  3408. {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
  3409. {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
  3410. {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
  3411. {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
  3412. {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
  3413. {"IF1 DAC1", NULL, "I2S1_1"},
  3414. {"IF1 DAC2", NULL, "I2S1_1"},
  3415. {"IF1 DAC3", NULL, "I2S1_1"},
  3416. {"IF2_1 DAC", NULL, "I2S2_1"},
  3417. {"IF2_2 DAC", NULL, "I2S2_2"},
  3418. {"IF3 DAC", NULL, "I2S3"},
  3419. {"IF1 DAC1 L", NULL, "IF1 DAC1"},
  3420. {"IF1 DAC1 R", NULL, "IF1 DAC1"},
  3421. {"IF1 DAC2 L", NULL, "IF1 DAC2"},
  3422. {"IF1 DAC2 R", NULL, "IF1 DAC2"},
  3423. {"IF1 DAC3 L", NULL, "IF1 DAC3"},
  3424. {"IF1 DAC3 R", NULL, "IF1 DAC3"},
  3425. {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
  3426. {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
  3427. {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
  3428. {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
  3429. {"IF3 DAC L", NULL, "IF3 DAC"},
  3430. {"IF3 DAC R", NULL, "IF3 DAC"},
  3431. {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
  3432. {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
  3433. {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
  3434. {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
  3435. {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
  3436. {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
  3437. {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
  3438. {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
  3439. {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
  3440. {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
  3441. {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  3442. {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
  3443. {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  3444. {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
  3445. {"DAC1 MIX", NULL, "DAC1 MIXL"},
  3446. {"DAC1 MIX", NULL, "DAC1 MIXR"},
  3447. {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
  3448. {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
  3449. {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
  3450. {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
  3451. {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
  3452. {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
  3453. {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
  3454. {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
  3455. {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
  3456. {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
  3457. {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
  3458. {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
  3459. {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
  3460. {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
  3461. {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
  3462. {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
  3463. {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
  3464. {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
  3465. {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
  3466. {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
  3467. {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
  3468. {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
  3469. {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
  3470. {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
  3471. {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  3472. {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
  3473. {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
  3474. {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
  3475. {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  3476. {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
  3477. {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
  3478. {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
  3479. {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  3480. {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
  3481. {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
  3482. {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  3483. {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
  3484. {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
  3485. {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  3486. {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
  3487. {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
  3488. {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
  3489. {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
  3490. {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  3491. {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
  3492. {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
  3493. {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
  3494. {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
  3495. {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
  3496. {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
  3497. {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
  3498. {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
  3499. {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
  3500. {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
  3501. {"DAC L1 Source", "DMIC1", "DMIC L1"},
  3502. {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
  3503. {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
  3504. {"DAC R1 Source", "DMIC1", "DMIC R1"},
  3505. {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
  3506. {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
  3507. {"DAC L2 Source", NULL, "DAC L2 Power"},
  3508. {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
  3509. {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
  3510. {"DAC R2 Source", NULL, "DAC R2 Power"},
  3511. {"DAC L1", NULL, "DAC L1 Source"},
  3512. {"DAC R1", NULL, "DAC R1 Source"},
  3513. {"DAC L2", NULL, "DAC L2 Source"},
  3514. {"DAC R2", NULL, "DAC R2 Source"},
  3515. {"DAC L1", NULL, "DAC 1 Clock"},
  3516. {"DAC R1", NULL, "DAC 1 Clock"},
  3517. {"DAC L2", NULL, "DAC 2 Clock"},
  3518. {"DAC R2", NULL, "DAC 2 Clock"},
  3519. {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
  3520. {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
  3521. {"MONOVOL MIX", "BST1 Switch", "BST1"},
  3522. {"MONOVOL MIX", "BST2 Switch", "BST2"},
  3523. {"MONOVOL MIX", "BST3 Switch", "BST3"},
  3524. {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
  3525. {"OUT MIXL", "INL Switch", "INL VOL"},
  3526. {"OUT MIXL", "BST1 Switch", "BST1"},
  3527. {"OUT MIXL", "BST2 Switch", "BST2"},
  3528. {"OUT MIXL", "BST3 Switch", "BST3"},
  3529. {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
  3530. {"OUT MIXR", "INR Switch", "INR VOL"},
  3531. {"OUT MIXR", "BST2 Switch", "BST2"},
  3532. {"OUT MIXR", "BST3 Switch", "BST3"},
  3533. {"OUT MIXR", "BST4 Switch", "BST4"},
  3534. {"MONOVOL", "Switch", "MONOVOL MIX"},
  3535. {"Mono MIX", "DAC L2 Switch", "DAC L2"},
  3536. {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
  3537. {"Mono Amp", NULL, "Mono MIX"},
  3538. {"Mono Amp", NULL, "Vref2"},
  3539. {"Mono Amp", NULL, "Vref3"},
  3540. {"Mono Amp", NULL, "CLKDET SYS"},
  3541. {"Mono Amp", NULL, "CLKDET MONO"},
  3542. {"Mono Playback", "Switch", "Mono Amp"},
  3543. {"MONOOUT", NULL, "Mono Playback"},
  3544. {"HP Amp", NULL, "DAC L1"},
  3545. {"HP Amp", NULL, "DAC R1"},
  3546. {"HP Amp", NULL, "Charge Pump"},
  3547. {"HP Amp", NULL, "CLKDET SYS"},
  3548. {"HP Amp", NULL, "CLKDET HP"},
  3549. {"HP Amp", NULL, "CBJ Power"},
  3550. {"HP Amp", NULL, "Vref2"},
  3551. {"HPO Playback", "Switch", "HP Amp"},
  3552. {"HPOL", NULL, "HPO Playback"},
  3553. {"HPOR", NULL, "HPO Playback"},
  3554. {"OUTVOL L", "Switch", "OUT MIXL"},
  3555. {"OUTVOL R", "Switch", "OUT MIXR"},
  3556. {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
  3557. {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
  3558. {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
  3559. {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
  3560. {"LOUT Amp", NULL, "LOUT L MIX"},
  3561. {"LOUT Amp", NULL, "LOUT R MIX"},
  3562. {"LOUT Amp", NULL, "Vref1"},
  3563. {"LOUT Amp", NULL, "Vref2"},
  3564. {"LOUT Amp", NULL, "CLKDET SYS"},
  3565. {"LOUT Amp", NULL, "CLKDET LOUT"},
  3566. {"LOUT L Playback", "Switch", "LOUT Amp"},
  3567. {"LOUT R Playback", "Switch", "LOUT Amp"},
  3568. {"LOUTL", NULL, "LOUT L Playback"},
  3569. {"LOUTR", NULL, "LOUT R Playback"},
  3570. {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
  3571. {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
  3572. {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
  3573. {"PDM L Mux", NULL, "PDM Power"},
  3574. {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
  3575. {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
  3576. {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
  3577. {"PDM R Mux", NULL, "PDM Power"},
  3578. {"PDM L Playback", "Switch", "PDM L Mux"},
  3579. {"PDM R Playback", "Switch", "PDM R Mux"},
  3580. {"PDML", NULL, "PDM L Playback"},
  3581. {"PDMR", NULL, "PDM R Playback"},
  3582. };
  3583. static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  3584. unsigned int rx_mask, int slots, int slot_width)
  3585. {
  3586. struct snd_soc_component *component = dai->component;
  3587. unsigned int val = 0;
  3588. if (rx_mask || tx_mask)
  3589. val |= RT5665_I2S1_MODE_TDM;
  3590. switch (slots) {
  3591. case 4:
  3592. val |= RT5665_TDM_IN_CH_4;
  3593. val |= RT5665_TDM_OUT_CH_4;
  3594. break;
  3595. case 6:
  3596. val |= RT5665_TDM_IN_CH_6;
  3597. val |= RT5665_TDM_OUT_CH_6;
  3598. break;
  3599. case 8:
  3600. val |= RT5665_TDM_IN_CH_8;
  3601. val |= RT5665_TDM_OUT_CH_8;
  3602. break;
  3603. case 2:
  3604. break;
  3605. default:
  3606. return -EINVAL;
  3607. }
  3608. switch (slot_width) {
  3609. case 20:
  3610. val |= RT5665_TDM_IN_LEN_20;
  3611. val |= RT5665_TDM_OUT_LEN_20;
  3612. break;
  3613. case 24:
  3614. val |= RT5665_TDM_IN_LEN_24;
  3615. val |= RT5665_TDM_OUT_LEN_24;
  3616. break;
  3617. case 32:
  3618. val |= RT5665_TDM_IN_LEN_32;
  3619. val |= RT5665_TDM_OUT_LEN_32;
  3620. break;
  3621. case 16:
  3622. break;
  3623. default:
  3624. return -EINVAL;
  3625. }
  3626. snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1,
  3627. RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
  3628. RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
  3629. RT5665_TDM_OUT_LEN_MASK, val);
  3630. return 0;
  3631. }
  3632. static int rt5665_hw_params(struct snd_pcm_substream *substream,
  3633. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  3634. {
  3635. struct snd_soc_component *component = dai->component;
  3636. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3637. unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
  3638. int pre_div, frame_size;
  3639. rt5665->lrck[dai->id] = params_rate(params);
  3640. pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
  3641. if (pre_div < 0) {
  3642. dev_warn(component->dev, "Force using PLL");
  3643. snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK,
  3644. rt5665->sysclk, rt5665->lrck[dai->id] * 512);
  3645. snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0,
  3646. rt5665->lrck[dai->id] * 512, 0);
  3647. pre_div = 1;
  3648. }
  3649. frame_size = snd_soc_params_to_frame_size(params);
  3650. if (frame_size < 0) {
  3651. dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
  3652. return -EINVAL;
  3653. }
  3654. dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  3655. rt5665->lrck[dai->id], pre_div, dai->id);
  3656. switch (params_width(params)) {
  3657. case 16:
  3658. val_bits = 0x0100;
  3659. break;
  3660. case 20:
  3661. val_len |= RT5665_I2S_DL_20;
  3662. val_bits = 0x1300;
  3663. break;
  3664. case 24:
  3665. val_len |= RT5665_I2S_DL_24;
  3666. val_bits = 0x2500;
  3667. break;
  3668. case 8:
  3669. val_len |= RT5665_I2S_DL_8;
  3670. break;
  3671. default:
  3672. return -EINVAL;
  3673. }
  3674. switch (dai->id) {
  3675. case RT5665_AIF1_1:
  3676. case RT5665_AIF1_2:
  3677. if (params_channels(params) > 2)
  3678. rt5665_set_tdm_slot(dai, 0xf, 0xf,
  3679. params_channels(params), params_width(params));
  3680. reg_clk = RT5665_ADDA_CLK_1;
  3681. mask_clk = RT5665_I2S_PD1_MASK;
  3682. val_clk = pre_div << RT5665_I2S_PD1_SFT;
  3683. snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
  3684. RT5665_I2S_DL_MASK, val_len);
  3685. break;
  3686. case RT5665_AIF2_1:
  3687. case RT5665_AIF2_2:
  3688. reg_clk = RT5665_ADDA_CLK_2;
  3689. mask_clk = RT5665_I2S_PD2_MASK;
  3690. val_clk = pre_div << RT5665_I2S_PD2_SFT;
  3691. snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
  3692. RT5665_I2S_DL_MASK, val_len);
  3693. break;
  3694. case RT5665_AIF3:
  3695. reg_clk = RT5665_ADDA_CLK_2;
  3696. mask_clk = RT5665_I2S_PD3_MASK;
  3697. val_clk = pre_div << RT5665_I2S_PD3_SFT;
  3698. snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
  3699. RT5665_I2S_DL_MASK, val_len);
  3700. break;
  3701. default:
  3702. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  3703. return -EINVAL;
  3704. }
  3705. snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk);
  3706. snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
  3707. switch (rt5665->lrck[dai->id]) {
  3708. case 192000:
  3709. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
  3710. RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
  3711. RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
  3712. break;
  3713. case 96000:
  3714. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
  3715. RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
  3716. RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
  3717. break;
  3718. default:
  3719. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
  3720. RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
  3721. RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
  3722. break;
  3723. }
  3724. if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
  3725. snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
  3726. RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
  3727. }
  3728. if (rt5665->master[RT5665_AIF3]) {
  3729. snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
  3730. RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
  3731. }
  3732. return 0;
  3733. }
  3734. static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  3735. {
  3736. struct snd_soc_component *component = dai->component;
  3737. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3738. unsigned int reg_val = 0;
  3739. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  3740. case SND_SOC_DAIFMT_CBM_CFM:
  3741. rt5665->master[dai->id] = 1;
  3742. break;
  3743. case SND_SOC_DAIFMT_CBS_CFS:
  3744. reg_val |= RT5665_I2S_MS_S;
  3745. rt5665->master[dai->id] = 0;
  3746. break;
  3747. default:
  3748. return -EINVAL;
  3749. }
  3750. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  3751. case SND_SOC_DAIFMT_NB_NF:
  3752. break;
  3753. case SND_SOC_DAIFMT_IB_NF:
  3754. reg_val |= RT5665_I2S_BP_INV;
  3755. break;
  3756. default:
  3757. return -EINVAL;
  3758. }
  3759. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  3760. case SND_SOC_DAIFMT_I2S:
  3761. break;
  3762. case SND_SOC_DAIFMT_LEFT_J:
  3763. reg_val |= RT5665_I2S_DF_LEFT;
  3764. break;
  3765. case SND_SOC_DAIFMT_DSP_A:
  3766. reg_val |= RT5665_I2S_DF_PCM_A;
  3767. break;
  3768. case SND_SOC_DAIFMT_DSP_B:
  3769. reg_val |= RT5665_I2S_DF_PCM_B;
  3770. break;
  3771. default:
  3772. return -EINVAL;
  3773. }
  3774. switch (dai->id) {
  3775. case RT5665_AIF1_1:
  3776. case RT5665_AIF1_2:
  3777. snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
  3778. RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
  3779. RT5665_I2S_DF_MASK, reg_val);
  3780. break;
  3781. case RT5665_AIF2_1:
  3782. case RT5665_AIF2_2:
  3783. snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
  3784. RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
  3785. RT5665_I2S_DF_MASK, reg_val);
  3786. break;
  3787. case RT5665_AIF3:
  3788. snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
  3789. RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
  3790. RT5665_I2S_DF_MASK, reg_val);
  3791. break;
  3792. default:
  3793. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  3794. return -EINVAL;
  3795. }
  3796. return 0;
  3797. }
  3798. static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id,
  3799. int source, unsigned int freq, int dir)
  3800. {
  3801. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3802. unsigned int reg_val = 0, src = 0;
  3803. if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
  3804. return 0;
  3805. switch (clk_id) {
  3806. case RT5665_SCLK_S_MCLK:
  3807. reg_val |= RT5665_SCLK_SRC_MCLK;
  3808. src = RT5665_CLK_SRC_MCLK;
  3809. break;
  3810. case RT5665_SCLK_S_PLL1:
  3811. reg_val |= RT5665_SCLK_SRC_PLL1;
  3812. src = RT5665_CLK_SRC_PLL1;
  3813. break;
  3814. case RT5665_SCLK_S_RCCLK:
  3815. reg_val |= RT5665_SCLK_SRC_RCCLK;
  3816. src = RT5665_CLK_SRC_RCCLK;
  3817. break;
  3818. default:
  3819. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  3820. return -EINVAL;
  3821. }
  3822. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3823. RT5665_SCLK_SRC_MASK, reg_val);
  3824. if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
  3825. snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
  3826. RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
  3827. }
  3828. if (rt5665->master[RT5665_AIF3]) {
  3829. snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
  3830. RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
  3831. }
  3832. rt5665->sysclk = freq;
  3833. rt5665->sysclk_src = clk_id;
  3834. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  3835. return 0;
  3836. }
  3837. static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id,
  3838. int source, unsigned int freq_in,
  3839. unsigned int freq_out)
  3840. {
  3841. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3842. struct rl6231_pll_code pll_code;
  3843. int ret;
  3844. if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
  3845. freq_out == rt5665->pll_out)
  3846. return 0;
  3847. if (!freq_in || !freq_out) {
  3848. dev_dbg(component->dev, "PLL disabled\n");
  3849. rt5665->pll_in = 0;
  3850. rt5665->pll_out = 0;
  3851. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3852. RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
  3853. return 0;
  3854. }
  3855. switch (source) {
  3856. case RT5665_PLL1_S_MCLK:
  3857. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3858. RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
  3859. break;
  3860. case RT5665_PLL1_S_BCLK1:
  3861. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3862. RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
  3863. break;
  3864. case RT5665_PLL1_S_BCLK2:
  3865. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3866. RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
  3867. break;
  3868. case RT5665_PLL1_S_BCLK3:
  3869. snd_soc_component_update_bits(component, RT5665_GLB_CLK,
  3870. RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
  3871. break;
  3872. default:
  3873. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  3874. return -EINVAL;
  3875. }
  3876. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  3877. if (ret < 0) {
  3878. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  3879. return ret;
  3880. }
  3881. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  3882. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  3883. pll_code.n_code, pll_code.k_code);
  3884. snd_soc_component_write(component, RT5665_PLL_CTRL_1,
  3885. pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
  3886. snd_soc_component_write(component, RT5665_PLL_CTRL_2,
  3887. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
  3888. pll_code.m_bp << RT5665_PLL_M_BP_SFT);
  3889. rt5665->pll_in = freq_in;
  3890. rt5665->pll_out = freq_out;
  3891. rt5665->pll_src = source;
  3892. return 0;
  3893. }
  3894. static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  3895. {
  3896. struct snd_soc_component *component = dai->component;
  3897. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3898. dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
  3899. rt5665->bclk[dai->id] = ratio;
  3900. if (ratio == 64) {
  3901. switch (dai->id) {
  3902. case RT5665_AIF2_1:
  3903. case RT5665_AIF2_2:
  3904. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
  3905. RT5665_I2S_BCLK_MS2_MASK,
  3906. RT5665_I2S_BCLK_MS2_64);
  3907. break;
  3908. case RT5665_AIF3:
  3909. snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
  3910. RT5665_I2S_BCLK_MS3_MASK,
  3911. RT5665_I2S_BCLK_MS3_64);
  3912. break;
  3913. }
  3914. }
  3915. return 0;
  3916. }
  3917. static int rt5665_set_bias_level(struct snd_soc_component *component,
  3918. enum snd_soc_bias_level level)
  3919. {
  3920. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3921. switch (level) {
  3922. case SND_SOC_BIAS_PREPARE:
  3923. regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
  3924. RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
  3925. break;
  3926. case SND_SOC_BIAS_STANDBY:
  3927. regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
  3928. RT5665_PWR_LDO, RT5665_PWR_LDO);
  3929. regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
  3930. RT5665_PWR_MB, RT5665_PWR_MB);
  3931. regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
  3932. RT5665_DIG_GATE_CTRL, 0);
  3933. break;
  3934. case SND_SOC_BIAS_OFF:
  3935. regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
  3936. RT5665_PWR_LDO, 0);
  3937. regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
  3938. RT5665_PWR_MB, 0);
  3939. break;
  3940. default:
  3941. break;
  3942. }
  3943. return 0;
  3944. }
  3945. static int rt5665_probe(struct snd_soc_component *component)
  3946. {
  3947. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3948. rt5665->component = component;
  3949. schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
  3950. return 0;
  3951. }
  3952. static void rt5665_remove(struct snd_soc_component *component)
  3953. {
  3954. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3955. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  3956. }
  3957. #ifdef CONFIG_PM
  3958. static int rt5665_suspend(struct snd_soc_component *component)
  3959. {
  3960. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3961. regcache_cache_only(rt5665->regmap, true);
  3962. regcache_mark_dirty(rt5665->regmap);
  3963. return 0;
  3964. }
  3965. static int rt5665_resume(struct snd_soc_component *component)
  3966. {
  3967. struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
  3968. regcache_cache_only(rt5665->regmap, false);
  3969. regcache_sync(rt5665->regmap);
  3970. return 0;
  3971. }
  3972. #else
  3973. #define rt5665_suspend NULL
  3974. #define rt5665_resume NULL
  3975. #endif
  3976. #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
  3977. #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  3978. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  3979. static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
  3980. .hw_params = rt5665_hw_params,
  3981. .set_fmt = rt5665_set_dai_fmt,
  3982. .set_tdm_slot = rt5665_set_tdm_slot,
  3983. .set_bclk_ratio = rt5665_set_bclk_ratio,
  3984. };
  3985. static struct snd_soc_dai_driver rt5665_dai[] = {
  3986. {
  3987. .name = "rt5665-aif1_1",
  3988. .id = RT5665_AIF1_1,
  3989. .playback = {
  3990. .stream_name = "AIF1 Playback",
  3991. .channels_min = 1,
  3992. .channels_max = 8,
  3993. .rates = RT5665_STEREO_RATES,
  3994. .formats = RT5665_FORMATS,
  3995. },
  3996. .capture = {
  3997. .stream_name = "AIF1_1 Capture",
  3998. .channels_min = 1,
  3999. .channels_max = 8,
  4000. .rates = RT5665_STEREO_RATES,
  4001. .formats = RT5665_FORMATS,
  4002. },
  4003. .ops = &rt5665_aif_dai_ops,
  4004. },
  4005. {
  4006. .name = "rt5665-aif1_2",
  4007. .id = RT5665_AIF1_2,
  4008. .capture = {
  4009. .stream_name = "AIF1_2 Capture",
  4010. .channels_min = 1,
  4011. .channels_max = 8,
  4012. .rates = RT5665_STEREO_RATES,
  4013. .formats = RT5665_FORMATS,
  4014. },
  4015. .ops = &rt5665_aif_dai_ops,
  4016. },
  4017. {
  4018. .name = "rt5665-aif2_1",
  4019. .id = RT5665_AIF2_1,
  4020. .playback = {
  4021. .stream_name = "AIF2_1 Playback",
  4022. .channels_min = 1,
  4023. .channels_max = 2,
  4024. .rates = RT5665_STEREO_RATES,
  4025. .formats = RT5665_FORMATS,
  4026. },
  4027. .capture = {
  4028. .stream_name = "AIF2_1 Capture",
  4029. .channels_min = 1,
  4030. .channels_max = 2,
  4031. .rates = RT5665_STEREO_RATES,
  4032. .formats = RT5665_FORMATS,
  4033. },
  4034. .ops = &rt5665_aif_dai_ops,
  4035. },
  4036. {
  4037. .name = "rt5665-aif2_2",
  4038. .id = RT5665_AIF2_2,
  4039. .playback = {
  4040. .stream_name = "AIF2_2 Playback",
  4041. .channels_min = 1,
  4042. .channels_max = 2,
  4043. .rates = RT5665_STEREO_RATES,
  4044. .formats = RT5665_FORMATS,
  4045. },
  4046. .capture = {
  4047. .stream_name = "AIF2_2 Capture",
  4048. .channels_min = 1,
  4049. .channels_max = 2,
  4050. .rates = RT5665_STEREO_RATES,
  4051. .formats = RT5665_FORMATS,
  4052. },
  4053. .ops = &rt5665_aif_dai_ops,
  4054. },
  4055. {
  4056. .name = "rt5665-aif3",
  4057. .id = RT5665_AIF3,
  4058. .playback = {
  4059. .stream_name = "AIF3 Playback",
  4060. .channels_min = 1,
  4061. .channels_max = 2,
  4062. .rates = RT5665_STEREO_RATES,
  4063. .formats = RT5665_FORMATS,
  4064. },
  4065. .capture = {
  4066. .stream_name = "AIF3 Capture",
  4067. .channels_min = 1,
  4068. .channels_max = 2,
  4069. .rates = RT5665_STEREO_RATES,
  4070. .formats = RT5665_FORMATS,
  4071. },
  4072. .ops = &rt5665_aif_dai_ops,
  4073. },
  4074. };
  4075. static const struct snd_soc_component_driver soc_component_dev_rt5665 = {
  4076. .probe = rt5665_probe,
  4077. .remove = rt5665_remove,
  4078. .suspend = rt5665_suspend,
  4079. .resume = rt5665_resume,
  4080. .set_bias_level = rt5665_set_bias_level,
  4081. .controls = rt5665_snd_controls,
  4082. .num_controls = ARRAY_SIZE(rt5665_snd_controls),
  4083. .dapm_widgets = rt5665_dapm_widgets,
  4084. .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
  4085. .dapm_routes = rt5665_dapm_routes,
  4086. .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
  4087. .set_sysclk = rt5665_set_component_sysclk,
  4088. .set_pll = rt5665_set_component_pll,
  4089. .set_jack = rt5665_set_jack_detect,
  4090. .use_pmdown_time = 1,
  4091. .endianness = 1,
  4092. .non_legacy_dai_naming = 1,
  4093. };
  4094. static const struct regmap_config rt5665_regmap = {
  4095. .reg_bits = 16,
  4096. .val_bits = 16,
  4097. .max_register = 0x0400,
  4098. .volatile_reg = rt5665_volatile_register,
  4099. .readable_reg = rt5665_readable_register,
  4100. .cache_type = REGCACHE_RBTREE,
  4101. .reg_defaults = rt5665_reg,
  4102. .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
  4103. .use_single_read = true,
  4104. .use_single_write = true,
  4105. };
  4106. static const struct i2c_device_id rt5665_i2c_id[] = {
  4107. {"rt5665", 0},
  4108. {}
  4109. };
  4110. MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
  4111. static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
  4112. {
  4113. rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
  4114. "realtek,in1-differential");
  4115. rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
  4116. "realtek,in2-differential");
  4117. rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
  4118. "realtek,in3-differential");
  4119. rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
  4120. "realtek,in4-differential");
  4121. of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
  4122. &rt5665->pdata.dmic1_data_pin);
  4123. of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
  4124. &rt5665->pdata.dmic2_data_pin);
  4125. of_property_read_u32(dev->of_node, "realtek,jd-src",
  4126. &rt5665->pdata.jd_src);
  4127. rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
  4128. "realtek,ldo1-en-gpios", 0);
  4129. return 0;
  4130. }
  4131. static void rt5665_calibrate(struct rt5665_priv *rt5665)
  4132. {
  4133. int value, count;
  4134. mutex_lock(&rt5665->calibrate_mutex);
  4135. regcache_cache_bypass(rt5665->regmap, true);
  4136. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4137. regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
  4138. regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
  4139. regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
  4140. regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
  4141. regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
  4142. regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
  4143. regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
  4144. regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
  4145. regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
  4146. regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
  4147. regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
  4148. regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
  4149. regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
  4150. regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
  4151. regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
  4152. usleep_range(15000, 20000);
  4153. regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
  4154. regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
  4155. regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
  4156. count = 0;
  4157. while (true) {
  4158. regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
  4159. if (value & 0x8000)
  4160. usleep_range(10000, 10005);
  4161. else
  4162. break;
  4163. if (count > 60) {
  4164. pr_err("HP Calibration Failure\n");
  4165. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4166. regcache_cache_bypass(rt5665->regmap, false);
  4167. goto out_unlock;
  4168. }
  4169. count++;
  4170. }
  4171. regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
  4172. count = 0;
  4173. while (true) {
  4174. regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
  4175. if (value & 0x8000)
  4176. usleep_range(10000, 10005);
  4177. else
  4178. break;
  4179. if (count > 60) {
  4180. pr_err("MONO Calibration Failure\n");
  4181. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4182. regcache_cache_bypass(rt5665->regmap, false);
  4183. goto out_unlock;
  4184. }
  4185. count++;
  4186. }
  4187. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4188. regcache_cache_bypass(rt5665->regmap, false);
  4189. regcache_mark_dirty(rt5665->regmap);
  4190. regcache_sync(rt5665->regmap);
  4191. regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
  4192. regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
  4193. out_unlock:
  4194. rt5665->calibration_done = true;
  4195. mutex_unlock(&rt5665->calibrate_mutex);
  4196. }
  4197. static void rt5665_calibrate_handler(struct work_struct *work)
  4198. {
  4199. struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
  4200. calibrate_work.work);
  4201. while (!rt5665->component->card->instantiated) {
  4202. pr_debug("%s\n", __func__);
  4203. usleep_range(10000, 15000);
  4204. }
  4205. rt5665_calibrate(rt5665);
  4206. }
  4207. static int rt5665_i2c_probe(struct i2c_client *i2c,
  4208. const struct i2c_device_id *id)
  4209. {
  4210. struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
  4211. struct rt5665_priv *rt5665;
  4212. int i, ret;
  4213. unsigned int val;
  4214. rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
  4215. GFP_KERNEL);
  4216. if (rt5665 == NULL)
  4217. return -ENOMEM;
  4218. i2c_set_clientdata(i2c, rt5665);
  4219. if (pdata)
  4220. rt5665->pdata = *pdata;
  4221. else
  4222. rt5665_parse_dt(rt5665, &i2c->dev);
  4223. for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
  4224. rt5665->supplies[i].supply = rt5665_supply_names[i];
  4225. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
  4226. rt5665->supplies);
  4227. if (ret != 0) {
  4228. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  4229. return ret;
  4230. }
  4231. ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
  4232. rt5665->supplies);
  4233. if (ret != 0) {
  4234. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  4235. return ret;
  4236. }
  4237. if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
  4238. if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
  4239. GPIOF_OUT_INIT_HIGH, "rt5665"))
  4240. dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
  4241. }
  4242. /* Sleep for 300 ms miniumum */
  4243. usleep_range(300000, 350000);
  4244. rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
  4245. if (IS_ERR(rt5665->regmap)) {
  4246. ret = PTR_ERR(rt5665->regmap);
  4247. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  4248. ret);
  4249. return ret;
  4250. }
  4251. regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
  4252. if (val != DEVICE_ID) {
  4253. dev_err(&i2c->dev,
  4254. "Device with ID register %x is not rt5665\n", val);
  4255. return -ENODEV;
  4256. }
  4257. regmap_read(rt5665->regmap, RT5665_RESET, &val);
  4258. switch (val) {
  4259. case 0x0:
  4260. rt5665->id = CODEC_5666;
  4261. break;
  4262. case 0x3:
  4263. default:
  4264. rt5665->id = CODEC_5665;
  4265. break;
  4266. }
  4267. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4268. /* line in diff mode*/
  4269. if (rt5665->pdata.in1_diff)
  4270. regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
  4271. RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
  4272. if (rt5665->pdata.in2_diff)
  4273. regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
  4274. RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
  4275. if (rt5665->pdata.in3_diff)
  4276. regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
  4277. RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
  4278. if (rt5665->pdata.in4_diff)
  4279. regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
  4280. RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
  4281. /* DMIC pin*/
  4282. if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
  4283. rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
  4284. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
  4285. RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
  4286. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
  4287. RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
  4288. switch (rt5665->pdata.dmic1_data_pin) {
  4289. case RT5665_DMIC1_DATA_IN2N:
  4290. regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
  4291. RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
  4292. break;
  4293. case RT5665_DMIC1_DATA_GPIO4:
  4294. regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
  4295. RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
  4296. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
  4297. RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
  4298. break;
  4299. default:
  4300. dev_dbg(&i2c->dev, "no DMIC1\n");
  4301. break;
  4302. }
  4303. switch (rt5665->pdata.dmic2_data_pin) {
  4304. case RT5665_DMIC2_DATA_IN2P:
  4305. regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
  4306. RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
  4307. break;
  4308. case RT5665_DMIC2_DATA_GPIO5:
  4309. regmap_update_bits(rt5665->regmap,
  4310. RT5665_DMIC_CTRL_1,
  4311. RT5665_DMIC_2_DP_MASK,
  4312. RT5665_DMIC_2_DP_GPIO5);
  4313. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
  4314. RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
  4315. break;
  4316. default:
  4317. dev_dbg(&i2c->dev, "no DMIC2\n");
  4318. break;
  4319. }
  4320. }
  4321. regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
  4322. regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
  4323. 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
  4324. /* Work around for pow_pump */
  4325. regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
  4326. RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
  4327. regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
  4328. RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
  4329. /* Set GPIO4,8 as input for combo jack */
  4330. if (rt5665->id == CODEC_5666) {
  4331. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
  4332. RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
  4333. regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
  4334. RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
  4335. }
  4336. /* Enhance performance*/
  4337. regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
  4338. RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
  4339. RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
  4340. INIT_DELAYED_WORK(&rt5665->jack_detect_work,
  4341. rt5665_jack_detect_handler);
  4342. INIT_DELAYED_WORK(&rt5665->calibrate_work,
  4343. rt5665_calibrate_handler);
  4344. INIT_DELAYED_WORK(&rt5665->jd_check_work,
  4345. rt5665_jd_check_handler);
  4346. mutex_init(&rt5665->calibrate_mutex);
  4347. if (i2c->irq) {
  4348. ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
  4349. rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  4350. | IRQF_ONESHOT, "rt5665", rt5665);
  4351. if (ret)
  4352. dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
  4353. }
  4354. return devm_snd_soc_register_component(&i2c->dev,
  4355. &soc_component_dev_rt5665,
  4356. rt5665_dai, ARRAY_SIZE(rt5665_dai));
  4357. }
  4358. static void rt5665_i2c_shutdown(struct i2c_client *client)
  4359. {
  4360. struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
  4361. regmap_write(rt5665->regmap, RT5665_RESET, 0);
  4362. }
  4363. #ifdef CONFIG_OF
  4364. static const struct of_device_id rt5665_of_match[] = {
  4365. {.compatible = "realtek,rt5665"},
  4366. {.compatible = "realtek,rt5666"},
  4367. {},
  4368. };
  4369. MODULE_DEVICE_TABLE(of, rt5665_of_match);
  4370. #endif
  4371. #ifdef CONFIG_ACPI
  4372. static const struct acpi_device_id rt5665_acpi_match[] = {
  4373. {"10EC5665", 0,},
  4374. {"10EC5666", 0,},
  4375. {},
  4376. };
  4377. MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
  4378. #endif
  4379. static struct i2c_driver rt5665_i2c_driver = {
  4380. .driver = {
  4381. .name = "rt5665",
  4382. .of_match_table = of_match_ptr(rt5665_of_match),
  4383. .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
  4384. },
  4385. .probe = rt5665_i2c_probe,
  4386. .shutdown = rt5665_i2c_shutdown,
  4387. .id_table = rt5665_i2c_id,
  4388. };
  4389. module_i2c_driver(rt5665_i2c_driver);
  4390. MODULE_DESCRIPTION("ASoC RT5665 driver");
  4391. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  4392. MODULE_LICENSE("GPL v2");