rt5659.h 63 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
  4. *
  5. * Copyright 2015 Realtek Microelectronics
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #ifndef __RT5659_H__
  9. #define __RT5659_H__
  10. #include <sound/rt5659.h>
  11. #define DEVICE_ID 0x6311
  12. /* Info */
  13. #define RT5659_RESET 0x0000
  14. #define RT5659_VENDOR_ID 0x00fd
  15. #define RT5659_VENDOR_ID_1 0x00fe
  16. #define RT5659_DEVICE_ID 0x00ff
  17. /* I/O - Output */
  18. #define RT5659_SPO_VOL 0x0001
  19. #define RT5659_HP_VOL 0x0002
  20. #define RT5659_LOUT 0x0003
  21. #define RT5659_MONO_OUT 0x0004
  22. #define RT5659_HPL_GAIN 0x0005
  23. #define RT5659_HPR_GAIN 0x0006
  24. #define RT5659_MONO_GAIN 0x0007
  25. #define RT5659_SPDIF_CTRL_1 0x0008
  26. #define RT5659_SPDIF_CTRL_2 0x0009
  27. /* I/O - Input */
  28. #define RT5659_CAL_BST_CTRL 0x000a
  29. #define RT5659_IN1_IN2 0x000c
  30. #define RT5659_IN3_IN4 0x000d
  31. #define RT5659_INL1_INR1_VOL 0x000f
  32. /* I/O - Speaker */
  33. #define RT5659_EJD_CTRL_1 0x0010
  34. #define RT5659_EJD_CTRL_2 0x0011
  35. #define RT5659_EJD_CTRL_3 0x0012
  36. #define RT5659_SILENCE_CTRL 0x0015
  37. #define RT5659_PSV_CTRL 0x0016
  38. /* I/O - Sidetone */
  39. #define RT5659_SIDETONE_CTRL 0x0018
  40. /* I/O - ADC/DAC/DMIC */
  41. #define RT5659_DAC1_DIG_VOL 0x0019
  42. #define RT5659_DAC2_DIG_VOL 0x001a
  43. #define RT5659_DAC_CTRL 0x001b
  44. #define RT5659_STO1_ADC_DIG_VOL 0x001c
  45. #define RT5659_MONO_ADC_DIG_VOL 0x001d
  46. #define RT5659_STO2_ADC_DIG_VOL 0x001e
  47. #define RT5659_STO1_BOOST 0x001f
  48. #define RT5659_MONO_BOOST 0x0020
  49. #define RT5659_STO2_BOOST 0x0021
  50. #define RT5659_HP_IMP_GAIN_1 0x0022
  51. #define RT5659_HP_IMP_GAIN_2 0x0023
  52. /* Mixer - D-D */
  53. #define RT5659_STO1_ADC_MIXER 0x0026
  54. #define RT5659_MONO_ADC_MIXER 0x0027
  55. #define RT5659_AD_DA_MIXER 0x0029
  56. #define RT5659_STO_DAC_MIXER 0x002a
  57. #define RT5659_MONO_DAC_MIXER 0x002b
  58. #define RT5659_DIG_MIXER 0x002c
  59. #define RT5659_A_DAC_MUX 0x002d
  60. #define RT5659_DIG_INF23_DATA 0x002f
  61. /* Mixer - PDM */
  62. #define RT5659_PDM_OUT_CTRL 0x0031
  63. #define RT5659_PDM_DATA_CTRL_1 0x0032
  64. #define RT5659_PDM_DATA_CTRL_2 0x0033
  65. #define RT5659_PDM_DATA_CTRL_3 0x0034
  66. #define RT5659_PDM_DATA_CTRL_4 0x0035
  67. #define RT5659_SPDIF_CTRL 0x0036
  68. /* Mixer - ADC */
  69. #define RT5659_REC1_GAIN 0x003a
  70. #define RT5659_REC1_L1_MIXER 0x003b
  71. #define RT5659_REC1_L2_MIXER 0x003c
  72. #define RT5659_REC1_R1_MIXER 0x003d
  73. #define RT5659_REC1_R2_MIXER 0x003e
  74. #define RT5659_CAL_REC 0x0040
  75. #define RT5659_REC2_L1_MIXER 0x009b
  76. #define RT5659_REC2_L2_MIXER 0x009c
  77. #define RT5659_REC2_R1_MIXER 0x009d
  78. #define RT5659_REC2_R2_MIXER 0x009e
  79. #define RT5659_RC_CLK_CTRL 0x009f
  80. /* Mixer - DAC */
  81. #define RT5659_SPK_L_MIXER 0x0046
  82. #define RT5659_SPK_R_MIXER 0x0047
  83. #define RT5659_SPO_AMP_GAIN 0x0048
  84. #define RT5659_ALC_BACK_GAIN 0x0049
  85. #define RT5659_MONOMIX_GAIN 0x004a
  86. #define RT5659_MONOMIX_IN_GAIN 0x004b
  87. #define RT5659_OUT_L_GAIN 0x004d
  88. #define RT5659_OUT_L_MIXER 0x004e
  89. #define RT5659_OUT_R_GAIN 0x004f
  90. #define RT5659_OUT_R_MIXER 0x0050
  91. #define RT5659_LOUT_MIXER 0x0052
  92. #define RT5659_HAPTIC_GEN_CTRL_1 0x0053
  93. #define RT5659_HAPTIC_GEN_CTRL_2 0x0054
  94. #define RT5659_HAPTIC_GEN_CTRL_3 0x0055
  95. #define RT5659_HAPTIC_GEN_CTRL_4 0x0056
  96. #define RT5659_HAPTIC_GEN_CTRL_5 0x0057
  97. #define RT5659_HAPTIC_GEN_CTRL_6 0x0058
  98. #define RT5659_HAPTIC_GEN_CTRL_7 0x0059
  99. #define RT5659_HAPTIC_GEN_CTRL_8 0x005a
  100. #define RT5659_HAPTIC_GEN_CTRL_9 0x005b
  101. #define RT5659_HAPTIC_GEN_CTRL_10 0x005c
  102. #define RT5659_HAPTIC_GEN_CTRL_11 0x005d
  103. #define RT5659_HAPTIC_LPF_CTRL_1 0x005e
  104. #define RT5659_HAPTIC_LPF_CTRL_2 0x005f
  105. #define RT5659_HAPTIC_LPF_CTRL_3 0x0060
  106. /* Power */
  107. #define RT5659_PWR_DIG_1 0x0061
  108. #define RT5659_PWR_DIG_2 0x0062
  109. #define RT5659_PWR_ANLG_1 0x0063
  110. #define RT5659_PWR_ANLG_2 0x0064
  111. #define RT5659_PWR_ANLG_3 0x0065
  112. #define RT5659_PWR_MIXER 0x0066
  113. #define RT5659_PWR_VOL 0x0067
  114. /* Private Register Control */
  115. #define RT5659_PRIV_INDEX 0x006a
  116. #define RT5659_CLK_DET 0x006b
  117. #define RT5659_PRIV_DATA 0x006c
  118. /* System Clock Pre Divider Gating Control */
  119. #define RT5659_PRE_DIV_1 0x006e
  120. #define RT5659_PRE_DIV_2 0x006f
  121. /* Format - ADC/DAC */
  122. #define RT5659_I2S1_SDP 0x0070
  123. #define RT5659_I2S2_SDP 0x0071
  124. #define RT5659_I2S3_SDP 0x0072
  125. #define RT5659_ADDA_CLK_1 0x0073
  126. #define RT5659_ADDA_CLK_2 0x0074
  127. #define RT5659_DMIC_CTRL_1 0x0075
  128. #define RT5659_DMIC_CTRL_2 0x0076
  129. /* Format - TDM Control */
  130. #define RT5659_TDM_CTRL_1 0x0077
  131. #define RT5659_TDM_CTRL_2 0x0078
  132. #define RT5659_TDM_CTRL_3 0x0079
  133. #define RT5659_TDM_CTRL_4 0x007a
  134. #define RT5659_TDM_CTRL_5 0x007b
  135. /* Function - Analog */
  136. #define RT5659_GLB_CLK 0x0080
  137. #define RT5659_PLL_CTRL_1 0x0081
  138. #define RT5659_PLL_CTRL_2 0x0082
  139. #define RT5659_ASRC_1 0x0083
  140. #define RT5659_ASRC_2 0x0084
  141. #define RT5659_ASRC_3 0x0085
  142. #define RT5659_ASRC_4 0x0086
  143. #define RT5659_ASRC_5 0x0087
  144. #define RT5659_ASRC_6 0x0088
  145. #define RT5659_ASRC_7 0x0089
  146. #define RT5659_ASRC_8 0x008a
  147. #define RT5659_ASRC_9 0x008b
  148. #define RT5659_ASRC_10 0x008c
  149. #define RT5659_DEPOP_1 0x008e
  150. #define RT5659_DEPOP_2 0x008f
  151. #define RT5659_DEPOP_3 0x0090
  152. #define RT5659_HP_CHARGE_PUMP_1 0x0091
  153. #define RT5659_HP_CHARGE_PUMP_2 0x0092
  154. #define RT5659_MICBIAS_1 0x0093
  155. #define RT5659_MICBIAS_2 0x0094
  156. #define RT5659_ASRC_11 0x0097
  157. #define RT5659_ASRC_12 0x0098
  158. #define RT5659_ASRC_13 0x0099
  159. #define RT5659_REC_M1_M2_GAIN_CTRL 0x009a
  160. #define RT5659_CLASSD_CTRL_1 0x00a0
  161. #define RT5659_CLASSD_CTRL_2 0x00a1
  162. /* Function - Digital */
  163. #define RT5659_ADC_EQ_CTRL_1 0x00ae
  164. #define RT5659_ADC_EQ_CTRL_2 0x00af
  165. #define RT5659_DAC_EQ_CTRL_1 0x00b0
  166. #define RT5659_DAC_EQ_CTRL_2 0x00b1
  167. #define RT5659_DAC_EQ_CTRL_3 0x00b2
  168. #define RT5659_IRQ_CTRL_1 0x00b6
  169. #define RT5659_IRQ_CTRL_2 0x00b7
  170. #define RT5659_IRQ_CTRL_3 0x00b8
  171. #define RT5659_IRQ_CTRL_4 0x00ba
  172. #define RT5659_IRQ_CTRL_5 0x00bb
  173. #define RT5659_IRQ_CTRL_6 0x00bc
  174. #define RT5659_INT_ST_1 0x00be
  175. #define RT5659_INT_ST_2 0x00bf
  176. #define RT5659_GPIO_CTRL_1 0x00c0
  177. #define RT5659_GPIO_CTRL_2 0x00c1
  178. #define RT5659_GPIO_CTRL_3 0x00c2
  179. #define RT5659_GPIO_CTRL_4 0x00c3
  180. #define RT5659_GPIO_CTRL_5 0x00c4
  181. #define RT5659_GPIO_STA 0x00c5
  182. #define RT5659_SINE_GEN_CTRL_1 0x00cb
  183. #define RT5659_SINE_GEN_CTRL_2 0x00cc
  184. #define RT5659_SINE_GEN_CTRL_3 0x00cd
  185. #define RT5659_HP_AMP_DET_CTRL_1 0x00d6
  186. #define RT5659_HP_AMP_DET_CTRL_2 0x00d7
  187. #define RT5659_SV_ZCD_1 0x00d9
  188. #define RT5659_SV_ZCD_2 0x00da
  189. #define RT5659_IL_CMD_1 0x00db
  190. #define RT5659_IL_CMD_2 0x00dc
  191. #define RT5659_IL_CMD_3 0x00dd
  192. #define RT5659_IL_CMD_4 0x00de
  193. #define RT5659_4BTN_IL_CMD_1 0x00df
  194. #define RT5659_4BTN_IL_CMD_2 0x00e0
  195. #define RT5659_4BTN_IL_CMD_3 0x00e1
  196. #define RT5659_PSV_IL_CMD_1 0x00e4
  197. #define RT5659_PSV_IL_CMD_2 0x00e5
  198. #define RT5659_ADC_STO1_HP_CTRL_1 0x00ea
  199. #define RT5659_ADC_STO1_HP_CTRL_2 0x00eb
  200. #define RT5659_ADC_MONO_HP_CTRL_1 0x00ec
  201. #define RT5659_ADC_MONO_HP_CTRL_2 0x00ed
  202. #define RT5659_AJD1_CTRL 0x00f0
  203. #define RT5659_AJD2_AJD3_CTRL 0x00f1
  204. #define RT5659_JD1_THD 0x00f2
  205. #define RT5659_JD2_THD 0x00f3
  206. #define RT5659_JD3_THD 0x00f4
  207. #define RT5659_JD_CTRL_1 0x00f6
  208. #define RT5659_JD_CTRL_2 0x00f7
  209. #define RT5659_JD_CTRL_3 0x00f8
  210. #define RT5659_JD_CTRL_4 0x00f9
  211. /* General Control */
  212. #define RT5659_DIG_MISC 0x00fa
  213. #define RT5659_DUMMY_2 0x00fb
  214. #define RT5659_DUMMY_3 0x00fc
  215. #define RT5659_DAC_ADC_DIG_VOL 0x0100
  216. #define RT5659_BIAS_CUR_CTRL_1 0x010a
  217. #define RT5659_BIAS_CUR_CTRL_2 0x010b
  218. #define RT5659_BIAS_CUR_CTRL_3 0x010c
  219. #define RT5659_BIAS_CUR_CTRL_4 0x010d
  220. #define RT5659_BIAS_CUR_CTRL_5 0x010e
  221. #define RT5659_BIAS_CUR_CTRL_6 0x010f
  222. #define RT5659_BIAS_CUR_CTRL_7 0x0110
  223. #define RT5659_BIAS_CUR_CTRL_8 0x0111
  224. #define RT5659_BIAS_CUR_CTRL_9 0x0112
  225. #define RT5659_BIAS_CUR_CTRL_10 0x0113
  226. #define RT5659_MEMORY_TEST 0x0116
  227. #define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117
  228. #define RT5659_CLASSD_0 0x011a
  229. #define RT5659_CLASSD_1 0x011b
  230. #define RT5659_CLASSD_2 0x011c
  231. #define RT5659_CLASSD_3 0x011d
  232. #define RT5659_CLASSD_4 0x011e
  233. #define RT5659_CLASSD_5 0x011f
  234. #define RT5659_CLASSD_6 0x0120
  235. #define RT5659_CLASSD_7 0x0121
  236. #define RT5659_CLASSD_8 0x0122
  237. #define RT5659_CLASSD_9 0x0123
  238. #define RT5659_CLASSD_10 0x0124
  239. #define RT5659_CHARGE_PUMP_1 0x0125
  240. #define RT5659_CHARGE_PUMP_2 0x0126
  241. #define RT5659_DIG_IN_CTRL_1 0x0132
  242. #define RT5659_DIG_IN_CTRL_2 0x0133
  243. #define RT5659_PAD_DRIVING_CTRL 0x0137
  244. #define RT5659_SOFT_RAMP_DEPOP 0x0138
  245. #define RT5659_PLL 0x0139
  246. #define RT5659_CHOP_DAC 0x013a
  247. #define RT5659_CHOP_ADC 0x013b
  248. #define RT5659_CALIB_ADC_CTRL 0x013c
  249. #define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e
  250. #define RT5659_VOL_TEST 0x013f
  251. #define RT5659_TEST_MODE_CTRL_1 0x0145
  252. #define RT5659_TEST_MODE_CTRL_2 0x0146
  253. #define RT5659_TEST_MODE_CTRL_3 0x0147
  254. #define RT5659_TEST_MODE_CTRL_4 0x0148
  255. #define RT5659_BASSBACK_CTRL 0x0150
  256. #define RT5659_MP3_PLUS_CTRL_1 0x0151
  257. #define RT5659_MP3_PLUS_CTRL_2 0x0152
  258. #define RT5659_MP3_HPF_A1 0x0153
  259. #define RT5659_MP3_HPF_A2 0x0154
  260. #define RT5659_MP3_HPF_H0 0x0155
  261. #define RT5659_MP3_LPF_H0 0x0156
  262. #define RT5659_3D_SPK_CTRL 0x0157
  263. #define RT5659_3D_SPK_COEF_1 0x0158
  264. #define RT5659_3D_SPK_COEF_2 0x0159
  265. #define RT5659_3D_SPK_COEF_3 0x015a
  266. #define RT5659_3D_SPK_COEF_4 0x015b
  267. #define RT5659_3D_SPK_COEF_5 0x015c
  268. #define RT5659_3D_SPK_COEF_6 0x015d
  269. #define RT5659_3D_SPK_COEF_7 0x015e
  270. #define RT5659_STO_NG2_CTRL_1 0x0160
  271. #define RT5659_STO_NG2_CTRL_2 0x0161
  272. #define RT5659_STO_NG2_CTRL_3 0x0162
  273. #define RT5659_STO_NG2_CTRL_4 0x0163
  274. #define RT5659_STO_NG2_CTRL_5 0x0164
  275. #define RT5659_STO_NG2_CTRL_6 0x0165
  276. #define RT5659_STO_NG2_CTRL_7 0x0166
  277. #define RT5659_STO_NG2_CTRL_8 0x0167
  278. #define RT5659_MONO_NG2_CTRL_1 0x0170
  279. #define RT5659_MONO_NG2_CTRL_2 0x0171
  280. #define RT5659_MONO_NG2_CTRL_3 0x0172
  281. #define RT5659_MONO_NG2_CTRL_4 0x0173
  282. #define RT5659_MONO_NG2_CTRL_5 0x0174
  283. #define RT5659_MONO_NG2_CTRL_6 0x0175
  284. #define RT5659_MID_HP_AMP_DET 0x0190
  285. #define RT5659_LOW_HP_AMP_DET 0x0191
  286. #define RT5659_LDO_CTRL 0x0192
  287. #define RT5659_HP_DECROSS_CTRL_1 0x01b0
  288. #define RT5659_HP_DECROSS_CTRL_2 0x01b1
  289. #define RT5659_HP_DECROSS_CTRL_3 0x01b2
  290. #define RT5659_HP_DECROSS_CTRL_4 0x01b3
  291. #define RT5659_HP_IMP_SENS_CTRL_1 0x01c0
  292. #define RT5659_HP_IMP_SENS_CTRL_2 0x01c1
  293. #define RT5659_HP_IMP_SENS_CTRL_3 0x01c2
  294. #define RT5659_HP_IMP_SENS_CTRL_4 0x01c3
  295. #define RT5659_HP_IMP_SENS_MAP_1 0x01c7
  296. #define RT5659_HP_IMP_SENS_MAP_2 0x01c8
  297. #define RT5659_HP_IMP_SENS_MAP_3 0x01c9
  298. #define RT5659_HP_IMP_SENS_MAP_4 0x01ca
  299. #define RT5659_HP_IMP_SENS_MAP_5 0x01cb
  300. #define RT5659_HP_IMP_SENS_MAP_6 0x01cc
  301. #define RT5659_HP_IMP_SENS_MAP_7 0x01cd
  302. #define RT5659_HP_IMP_SENS_MAP_8 0x01ce
  303. #define RT5659_HP_LOGIC_CTRL_1 0x01da
  304. #define RT5659_HP_LOGIC_CTRL_2 0x01db
  305. #define RT5659_HP_CALIB_CTRL_1 0x01de
  306. #define RT5659_HP_CALIB_CTRL_2 0x01df
  307. #define RT5659_HP_CALIB_CTRL_3 0x01e0
  308. #define RT5659_HP_CALIB_CTRL_4 0x01e1
  309. #define RT5659_HP_CALIB_CTRL_5 0x01e2
  310. #define RT5659_HP_CALIB_CTRL_6 0x01e3
  311. #define RT5659_HP_CALIB_CTRL_7 0x01e4
  312. #define RT5659_HP_CALIB_CTRL_9 0x01e6
  313. #define RT5659_HP_CALIB_CTRL_10 0x01e7
  314. #define RT5659_HP_CALIB_CTRL_11 0x01e8
  315. #define RT5659_HP_CALIB_STA_1 0x01ea
  316. #define RT5659_HP_CALIB_STA_2 0x01eb
  317. #define RT5659_HP_CALIB_STA_3 0x01ec
  318. #define RT5659_HP_CALIB_STA_4 0x01ed
  319. #define RT5659_HP_CALIB_STA_5 0x01ee
  320. #define RT5659_HP_CALIB_STA_6 0x01ef
  321. #define RT5659_HP_CALIB_STA_7 0x01f0
  322. #define RT5659_HP_CALIB_STA_8 0x01f1
  323. #define RT5659_HP_CALIB_STA_9 0x01f2
  324. #define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6
  325. #define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7
  326. #define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8
  327. #define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9
  328. #define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa
  329. #define RT5659_MONO_AMP_CALIB_STA_1 0x01fb
  330. #define RT5659_MONO_AMP_CALIB_STA_2 0x01fc
  331. #define RT5659_MONO_AMP_CALIB_STA_3 0x01fd
  332. #define RT5659_MONO_AMP_CALIB_STA_4 0x01fe
  333. #define RT5659_SPK_PWR_LMT_CTRL_1 0x0200
  334. #define RT5659_SPK_PWR_LMT_CTRL_2 0x0201
  335. #define RT5659_SPK_PWR_LMT_CTRL_3 0x0202
  336. #define RT5659_SPK_PWR_LMT_STA_1 0x0203
  337. #define RT5659_SPK_PWR_LMT_STA_2 0x0204
  338. #define RT5659_SPK_PWR_LMT_STA_3 0x0205
  339. #define RT5659_SPK_PWR_LMT_STA_4 0x0206
  340. #define RT5659_SPK_PWR_LMT_STA_5 0x0207
  341. #define RT5659_SPK_PWR_LMT_STA_6 0x0208
  342. #define RT5659_FLEX_SPK_BST_CTRL_1 0x0256
  343. #define RT5659_FLEX_SPK_BST_CTRL_2 0x0257
  344. #define RT5659_FLEX_SPK_BST_CTRL_3 0x0258
  345. #define RT5659_FLEX_SPK_BST_CTRL_4 0x0259
  346. #define RT5659_SPK_EX_LMT_CTRL_1 0x025a
  347. #define RT5659_SPK_EX_LMT_CTRL_2 0x025b
  348. #define RT5659_SPK_EX_LMT_CTRL_3 0x025c
  349. #define RT5659_SPK_EX_LMT_CTRL_4 0x025d
  350. #define RT5659_SPK_EX_LMT_CTRL_5 0x025e
  351. #define RT5659_SPK_EX_LMT_CTRL_6 0x025f
  352. #define RT5659_SPK_EX_LMT_CTRL_7 0x0260
  353. #define RT5659_ADJ_HPF_CTRL_1 0x0261
  354. #define RT5659_ADJ_HPF_CTRL_2 0x0262
  355. #define RT5659_SPK_DC_CAILB_CTRL_1 0x0265
  356. #define RT5659_SPK_DC_CAILB_CTRL_2 0x0266
  357. #define RT5659_SPK_DC_CAILB_CTRL_3 0x0267
  358. #define RT5659_SPK_DC_CAILB_CTRL_4 0x0268
  359. #define RT5659_SPK_DC_CAILB_CTRL_5 0x0269
  360. #define RT5659_SPK_DC_CAILB_STA_1 0x026a
  361. #define RT5659_SPK_DC_CAILB_STA_2 0x026b
  362. #define RT5659_SPK_DC_CAILB_STA_3 0x026c
  363. #define RT5659_SPK_DC_CAILB_STA_4 0x026d
  364. #define RT5659_SPK_DC_CAILB_STA_5 0x026e
  365. #define RT5659_SPK_DC_CAILB_STA_6 0x026f
  366. #define RT5659_SPK_DC_CAILB_STA_7 0x0270
  367. #define RT5659_SPK_DC_CAILB_STA_8 0x0271
  368. #define RT5659_SPK_DC_CAILB_STA_9 0x0272
  369. #define RT5659_SPK_DC_CAILB_STA_10 0x0273
  370. #define RT5659_SPK_VDD_STA_1 0x0280
  371. #define RT5659_SPK_VDD_STA_2 0x0281
  372. #define RT5659_SPK_DC_DET_CTRL_1 0x0282
  373. #define RT5659_SPK_DC_DET_CTRL_2 0x0283
  374. #define RT5659_SPK_DC_DET_CTRL_3 0x0284
  375. #define RT5659_PURE_DC_DET_CTRL_1 0x0290
  376. #define RT5659_PURE_DC_DET_CTRL_2 0x0291
  377. #define RT5659_DUMMY_4 0x02fa
  378. #define RT5659_DUMMY_5 0x02fb
  379. #define RT5659_DUMMY_6 0x02fc
  380. #define RT5659_DRC1_CTRL_1 0x0300
  381. #define RT5659_DRC1_CTRL_2 0x0301
  382. #define RT5659_DRC1_CTRL_3 0x0302
  383. #define RT5659_DRC1_CTRL_4 0x0303
  384. #define RT5659_DRC1_CTRL_5 0x0304
  385. #define RT5659_DRC1_CTRL_6 0x0305
  386. #define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306
  387. #define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307
  388. #define RT5659_DRC2_CTRL_1 0x0308
  389. #define RT5659_DRC2_CTRL_2 0x0309
  390. #define RT5659_DRC2_CTRL_3 0x030a
  391. #define RT5659_DRC2_CTRL_4 0x030b
  392. #define RT5659_DRC2_CTRL_5 0x030c
  393. #define RT5659_DRC2_CTRL_6 0x030d
  394. #define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e
  395. #define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f
  396. #define RT5659_DRC1_PRIV_1 0x0310
  397. #define RT5659_DRC1_PRIV_2 0x0311
  398. #define RT5659_DRC1_PRIV_3 0x0312
  399. #define RT5659_DRC1_PRIV_4 0x0313
  400. #define RT5659_DRC1_PRIV_5 0x0314
  401. #define RT5659_DRC1_PRIV_6 0x0315
  402. #define RT5659_DRC1_PRIV_7 0x0316
  403. #define RT5659_DRC2_PRIV_1 0x0317
  404. #define RT5659_DRC2_PRIV_2 0x0318
  405. #define RT5659_DRC2_PRIV_3 0x0319
  406. #define RT5659_DRC2_PRIV_4 0x031a
  407. #define RT5659_DRC2_PRIV_5 0x031b
  408. #define RT5659_DRC2_PRIV_6 0x031c
  409. #define RT5659_DRC2_PRIV_7 0x031d
  410. #define RT5659_MULTI_DRC_CTRL 0x0320
  411. #define RT5659_CROSS_OVER_1 0x0321
  412. #define RT5659_CROSS_OVER_2 0x0322
  413. #define RT5659_CROSS_OVER_3 0x0323
  414. #define RT5659_CROSS_OVER_4 0x0324
  415. #define RT5659_CROSS_OVER_5 0x0325
  416. #define RT5659_CROSS_OVER_6 0x0326
  417. #define RT5659_CROSS_OVER_7 0x0327
  418. #define RT5659_CROSS_OVER_8 0x0328
  419. #define RT5659_CROSS_OVER_9 0x0329
  420. #define RT5659_CROSS_OVER_10 0x032a
  421. #define RT5659_ALC_PGA_CTRL_1 0x0330
  422. #define RT5659_ALC_PGA_CTRL_2 0x0331
  423. #define RT5659_ALC_PGA_CTRL_3 0x0332
  424. #define RT5659_ALC_PGA_CTRL_4 0x0333
  425. #define RT5659_ALC_PGA_CTRL_5 0x0334
  426. #define RT5659_ALC_PGA_CTRL_6 0x0335
  427. #define RT5659_ALC_PGA_CTRL_7 0x0336
  428. #define RT5659_ALC_PGA_CTRL_8 0x0337
  429. #define RT5659_ALC_PGA_STA_1 0x0338
  430. #define RT5659_ALC_PGA_STA_2 0x0339
  431. #define RT5659_ALC_PGA_STA_3 0x033a
  432. #define RT5659_DAC_L_EQ_PRE_VOL 0x0340
  433. #define RT5659_DAC_R_EQ_PRE_VOL 0x0341
  434. #define RT5659_DAC_L_EQ_POST_VOL 0x0342
  435. #define RT5659_DAC_R_EQ_POST_VOL 0x0343
  436. #define RT5659_DAC_L_EQ_LPF1_A1 0x0344
  437. #define RT5659_DAC_L_EQ_LPF1_H0 0x0345
  438. #define RT5659_DAC_R_EQ_LPF1_A1 0x0346
  439. #define RT5659_DAC_R_EQ_LPF1_H0 0x0347
  440. #define RT5659_DAC_L_EQ_BPF2_A1 0x0348
  441. #define RT5659_DAC_L_EQ_BPF2_A2 0x0349
  442. #define RT5659_DAC_L_EQ_BPF2_H0 0x034a
  443. #define RT5659_DAC_R_EQ_BPF2_A1 0x034b
  444. #define RT5659_DAC_R_EQ_BPF2_A2 0x034c
  445. #define RT5659_DAC_R_EQ_BPF2_H0 0x034d
  446. #define RT5659_DAC_L_EQ_BPF3_A1 0x034e
  447. #define RT5659_DAC_L_EQ_BPF3_A2 0x034f
  448. #define RT5659_DAC_L_EQ_BPF3_H0 0x0350
  449. #define RT5659_DAC_R_EQ_BPF3_A1 0x0351
  450. #define RT5659_DAC_R_EQ_BPF3_A2 0x0352
  451. #define RT5659_DAC_R_EQ_BPF3_H0 0x0353
  452. #define RT5659_DAC_L_EQ_BPF4_A1 0x0354
  453. #define RT5659_DAC_L_EQ_BPF4_A2 0x0355
  454. #define RT5659_DAC_L_EQ_BPF4_H0 0x0356
  455. #define RT5659_DAC_R_EQ_BPF4_A1 0x0357
  456. #define RT5659_DAC_R_EQ_BPF4_A2 0x0358
  457. #define RT5659_DAC_R_EQ_BPF4_H0 0x0359
  458. #define RT5659_DAC_L_EQ_HPF1_A1 0x035a
  459. #define RT5659_DAC_L_EQ_HPF1_H0 0x035b
  460. #define RT5659_DAC_R_EQ_HPF1_A1 0x035c
  461. #define RT5659_DAC_R_EQ_HPF1_H0 0x035d
  462. #define RT5659_DAC_L_EQ_HPF2_A1 0x035e
  463. #define RT5659_DAC_L_EQ_HPF2_A2 0x035f
  464. #define RT5659_DAC_L_EQ_HPF2_H0 0x0360
  465. #define RT5659_DAC_R_EQ_HPF2_A1 0x0361
  466. #define RT5659_DAC_R_EQ_HPF2_A2 0x0362
  467. #define RT5659_DAC_R_EQ_HPF2_H0 0x0363
  468. #define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364
  469. #define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365
  470. #define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366
  471. #define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367
  472. #define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368
  473. #define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369
  474. #define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a
  475. #define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b
  476. #define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c
  477. #define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d
  478. #define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e
  479. #define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f
  480. #define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370
  481. #define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371
  482. #define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372
  483. #define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373
  484. #define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374
  485. #define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375
  486. #define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376
  487. #define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377
  488. #define RT5659_ADC_L_EQ_LPF1_A1 0x03d0
  489. #define RT5659_ADC_R_EQ_LPF1_A1 0x03d1
  490. #define RT5659_ADC_L_EQ_LPF1_H0 0x03d2
  491. #define RT5659_ADC_R_EQ_LPF1_H0 0x03d3
  492. #define RT5659_ADC_L_EQ_BPF1_A1 0x03d4
  493. #define RT5659_ADC_R_EQ_BPF1_A1 0x03d5
  494. #define RT5659_ADC_L_EQ_BPF1_A2 0x03d6
  495. #define RT5659_ADC_R_EQ_BPF1_A2 0x03d7
  496. #define RT5659_ADC_L_EQ_BPF1_H0 0x03d8
  497. #define RT5659_ADC_R_EQ_BPF1_H0 0x03d9
  498. #define RT5659_ADC_L_EQ_BPF2_A1 0x03da
  499. #define RT5659_ADC_R_EQ_BPF2_A1 0x03db
  500. #define RT5659_ADC_L_EQ_BPF2_A2 0x03dc
  501. #define RT5659_ADC_R_EQ_BPF2_A2 0x03dd
  502. #define RT5659_ADC_L_EQ_BPF2_H0 0x03de
  503. #define RT5659_ADC_R_EQ_BPF2_H0 0x03df
  504. #define RT5659_ADC_L_EQ_BPF3_A1 0x03e0
  505. #define RT5659_ADC_R_EQ_BPF3_A1 0x03e1
  506. #define RT5659_ADC_L_EQ_BPF3_A2 0x03e2
  507. #define RT5659_ADC_R_EQ_BPF3_A2 0x03e3
  508. #define RT5659_ADC_L_EQ_BPF3_H0 0x03e4
  509. #define RT5659_ADC_R_EQ_BPF3_H0 0x03e5
  510. #define RT5659_ADC_L_EQ_BPF4_A1 0x03e6
  511. #define RT5659_ADC_R_EQ_BPF4_A1 0x03e7
  512. #define RT5659_ADC_L_EQ_BPF4_A2 0x03e8
  513. #define RT5659_ADC_R_EQ_BPF4_A2 0x03e9
  514. #define RT5659_ADC_L_EQ_BPF4_H0 0x03ea
  515. #define RT5659_ADC_R_EQ_BPF4_H0 0x03eb
  516. #define RT5659_ADC_L_EQ_HPF1_A1 0x03ec
  517. #define RT5659_ADC_R_EQ_HPF1_A1 0x03ed
  518. #define RT5659_ADC_L_EQ_HPF1_H0 0x03ee
  519. #define RT5659_ADC_R_EQ_HPF1_H0 0x03ef
  520. #define RT5659_ADC_L_EQ_PRE_VOL 0x03f0
  521. #define RT5659_ADC_R_EQ_PRE_VOL 0x03f1
  522. #define RT5659_ADC_L_EQ_POST_VOL 0x03f2
  523. #define RT5659_ADC_R_EQ_POST_VOL 0x03f3
  524. /* global definition */
  525. #define RT5659_L_MUTE (0x1 << 15)
  526. #define RT5659_L_MUTE_SFT 15
  527. #define RT5659_VOL_L_MUTE (0x1 << 14)
  528. #define RT5659_VOL_L_SFT 14
  529. #define RT5659_R_MUTE (0x1 << 7)
  530. #define RT5659_R_MUTE_SFT 7
  531. #define RT5659_VOL_R_MUTE (0x1 << 6)
  532. #define RT5659_VOL_R_SFT 6
  533. #define RT5659_L_VOL_MASK (0x3f << 8)
  534. #define RT5659_L_VOL_SFT 8
  535. #define RT5659_R_VOL_MASK (0x3f)
  536. #define RT5659_R_VOL_SFT 0
  537. /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
  538. #define RT5659_G_HP (0x1f << 8)
  539. #define RT5659_G_HP_SFT 8
  540. #define RT5659_G_STO_DA_DMIX (0x1f)
  541. #define RT5659_G_STO_DA_SFT 0
  542. /* IN1/IN2 Control (0x000c) */
  543. #define RT5659_IN1_DF_MASK (0x1 << 15)
  544. #define RT5659_IN1_DF 15
  545. #define RT5659_BST1_MASK (0x7f << 8)
  546. #define RT5659_BST1_SFT 8
  547. #define RT5659_BST2_MASK (0x7f)
  548. #define RT5659_BST2_SFT 0
  549. /* IN3/IN4 Control (0x000d) */
  550. #define RT5659_IN3_DF_MASK (0x1 << 15)
  551. #define RT5659_IN3_DF 15
  552. #define RT5659_BST3_MASK (0x7f << 8)
  553. #define RT5659_BST3_SFT 8
  554. #define RT5659_IN4_DF_MASK (0x1 << 7)
  555. #define RT5659_IN4_DF 7
  556. #define RT5659_BST4_MASK (0x7f)
  557. #define RT5659_BST4_SFT 0
  558. /* INL and INR Volume Control (0x000f) */
  559. #define RT5659_INL_VOL_MASK (0x1f << 8)
  560. #define RT5659_INL_VOL_SFT 8
  561. #define RT5659_INR_VOL_MASK (0x1f)
  562. #define RT5659_INR_VOL_SFT 0
  563. /* Embeeded Jack and Type Detection Control 1 (0x0010) */
  564. #define RT5659_EMB_JD_EN (0x1 << 15)
  565. #define RT5659_EMB_JD_EN_SFT 15
  566. #define RT5659_JD_MODE (0x1 << 13)
  567. #define RT5659_JD_MODE_SFT 13
  568. #define RT5659_EXT_JD_EN (0x1 << 11)
  569. #define RT5659_EXT_JD_EN_SFT 11
  570. #define RT5659_EXT_JD_DIG (0x1 << 9)
  571. /* Embeeded Jack and Type Detection Control 2 (0x0011) */
  572. #define RT5659_EXT_JD_SRC (0x7 << 4)
  573. #define RT5659_EXT_JD_SRC_SFT 4
  574. #define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
  575. #define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
  576. #define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4)
  577. #define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4)
  578. #define RT5659_EXT_JD_SRC_JD2 (0x4 << 4)
  579. #define RT5659_EXT_JD_SRC_JD3 (0x5 << 4)
  580. #define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4)
  581. /* Slience Detection Control (0x0015) */
  582. #define RT5659_SIL_DET_MASK (0x1 << 15)
  583. #define RT5659_SIL_DET_DIS (0x0 << 15)
  584. #define RT5659_SIL_DET_EN (0x1 << 15)
  585. /* Sidetone Control (0x0018) */
  586. #define RT5659_ST_SEL_MASK (0x7 << 9)
  587. #define RT5659_ST_SEL_SFT 9
  588. #define RT5659_ST_EN (0x1 << 6)
  589. #define RT5659_ST_EN_SFT 6
  590. /* DAC1 Digital Volume (0x0019) */
  591. #define RT5659_DAC_L1_VOL_MASK (0xff << 8)
  592. #define RT5659_DAC_L1_VOL_SFT 8
  593. #define RT5659_DAC_R1_VOL_MASK (0xff)
  594. #define RT5659_DAC_R1_VOL_SFT 0
  595. /* DAC2 Digital Volume (0x001a) */
  596. #define RT5659_DAC_L2_VOL_MASK (0xff << 8)
  597. #define RT5659_DAC_L2_VOL_SFT 8
  598. #define RT5659_DAC_R2_VOL_MASK (0xff)
  599. #define RT5659_DAC_R2_VOL_SFT 0
  600. /* DAC2 Control (0x001b) */
  601. #define RT5659_M_DAC2_L_VOL (0x1 << 13)
  602. #define RT5659_M_DAC2_L_VOL_SFT 13
  603. #define RT5659_M_DAC2_R_VOL (0x1 << 12)
  604. #define RT5659_M_DAC2_R_VOL_SFT 12
  605. #define RT5659_DAC_L2_SEL_MASK (0x7 << 4)
  606. #define RT5659_DAC_L2_SEL_SFT 4
  607. #define RT5659_DAC_R2_SEL_MASK (0x7 << 0)
  608. #define RT5659_DAC_R2_SEL_SFT 0
  609. /* ADC Digital Volume Control (0x001c) */
  610. #define RT5659_ADC_L_VOL_MASK (0x7f << 8)
  611. #define RT5659_ADC_L_VOL_SFT 8
  612. #define RT5659_ADC_R_VOL_MASK (0x7f)
  613. #define RT5659_ADC_R_VOL_SFT 0
  614. /* Mono ADC Digital Volume Control (0x001d) */
  615. #define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8)
  616. #define RT5659_MONO_ADC_L_VOL_SFT 8
  617. #define RT5659_MONO_ADC_R_VOL_MASK (0x7f)
  618. #define RT5659_MONO_ADC_R_VOL_SFT 0
  619. /* Stereo1 ADC Boost Gain Control (0x001f) */
  620. #define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14)
  621. #define RT5659_STO1_ADC_L_BST_SFT 14
  622. #define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12)
  623. #define RT5659_STO1_ADC_R_BST_SFT 12
  624. /* Mono ADC Boost Gain Control (0x0020) */
  625. #define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14)
  626. #define RT5659_MONO_ADC_L_BST_SFT 14
  627. #define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12)
  628. #define RT5659_MONO_ADC_R_BST_SFT 12
  629. /* Stereo1 ADC Boost Gain Control (0x001f) */
  630. #define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14)
  631. #define RT5659_STO2_ADC_L_BST_SFT 14
  632. #define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12)
  633. #define RT5659_STO2_ADC_R_BST_SFT 12
  634. /* Stereo ADC Mixer Control (0x0026) */
  635. #define RT5659_M_STO1_ADC_L1 (0x1 << 15)
  636. #define RT5659_M_STO1_ADC_L1_SFT 15
  637. #define RT5659_M_STO1_ADC_L2 (0x1 << 14)
  638. #define RT5659_M_STO1_ADC_L2_SFT 14
  639. #define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)
  640. #define RT5659_STO1_ADC1_SRC_SFT 13
  641. #define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)
  642. #define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13)
  643. #define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)
  644. #define RT5659_STO1_ADC_SRC_SFT 12
  645. #define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)
  646. #define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12)
  647. #define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)
  648. #define RT5659_STO1_ADC2_SRC_SFT 11
  649. #define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)
  650. #define RT5659_STO1_DMIC_SRC_SFT 8
  651. #define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
  652. #define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
  653. #define RT5659_M_STO1_ADC_R1 (0x1 << 6)
  654. #define RT5659_M_STO1_ADC_R1_SFT 6
  655. #define RT5659_M_STO1_ADC_R2 (0x1 << 5)
  656. #define RT5659_M_STO1_ADC_R2_SFT 5
  657. /* Mono1 ADC Mixer control (0x0027) */
  658. #define RT5659_M_MONO_ADC_L1 (0x1 << 15)
  659. #define RT5659_M_MONO_ADC_L1_SFT 15
  660. #define RT5659_M_MONO_ADC_L2 (0x1 << 14)
  661. #define RT5659_M_MONO_ADC_L2_SFT 14
  662. #define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)
  663. #define RT5659_MONO_ADC_L2_SRC_SFT 12
  664. #define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)
  665. #define RT5659_MONO_ADC_L1_SRC_SFT 11
  666. #define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9)
  667. #define RT5659_MONO_ADC_L_SRC_SFT 9
  668. #define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)
  669. #define RT5659_MONO_DMIC_L_SRC_SFT 8
  670. #define RT5659_M_MONO_ADC_R1 (0x1 << 7)
  671. #define RT5659_M_MONO_ADC_R1_SFT 7
  672. #define RT5659_M_MONO_ADC_R2 (0x1 << 6)
  673. #define RT5659_M_MONO_ADC_R2_SFT 6
  674. #define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)
  675. #define RT5659_STO2_ADC_SRC_SFT 5
  676. #define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)
  677. #define RT5659_MONO_ADC_R2_SRC_SFT 4
  678. #define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)
  679. #define RT5659_MONO_ADC_R1_SRC_SFT 3
  680. #define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1)
  681. #define RT5659_MONO_ADC_R_SRC_SFT 1
  682. #define RT5659_MONO_DMIC_R_SRC_MASK 0x1
  683. #define RT5659_MONO_DMIC_R_SRC_SFT 0
  684. /* ADC Mixer to DAC Mixer Control (0x0029) */
  685. #define RT5659_M_ADCMIX_L (0x1 << 15)
  686. #define RT5659_M_ADCMIX_L_SFT 15
  687. #define RT5659_M_DAC1_L (0x1 << 14)
  688. #define RT5659_M_DAC1_L_SFT 14
  689. #define RT5659_DAC1_R_SEL_MASK (0x3 << 10)
  690. #define RT5659_DAC1_R_SEL_SFT 10
  691. #define RT5659_DAC1_R_SEL_IF1 (0x0 << 10)
  692. #define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)
  693. #define RT5659_DAC1_R_SEL_IF3 (0x2 << 10)
  694. #define RT5659_DAC1_L_SEL_MASK (0x3 << 8)
  695. #define RT5659_DAC1_L_SEL_SFT 8
  696. #define RT5659_DAC1_L_SEL_IF1 (0x0 << 8)
  697. #define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)
  698. #define RT5659_DAC1_L_SEL_IF3 (0x2 << 8)
  699. #define RT5659_M_ADCMIX_R (0x1 << 7)
  700. #define RT5659_M_ADCMIX_R_SFT 7
  701. #define RT5659_M_DAC1_R (0x1 << 6)
  702. #define RT5659_M_DAC1_R_SFT 6
  703. /* Stereo DAC Mixer Control (0x002a) */
  704. #define RT5659_M_DAC_L1_STO_L (0x1 << 15)
  705. #define RT5659_M_DAC_L1_STO_L_SFT 15
  706. #define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)
  707. #define RT5659_G_DAC_L1_STO_L_SFT 14
  708. #define RT5659_M_DAC_R1_STO_L (0x1 << 13)
  709. #define RT5659_M_DAC_R1_STO_L_SFT 13
  710. #define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)
  711. #define RT5659_G_DAC_R1_STO_L_SFT 12
  712. #define RT5659_M_DAC_L2_STO_L (0x1 << 11)
  713. #define RT5659_M_DAC_L2_STO_L_SFT 11
  714. #define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)
  715. #define RT5659_G_DAC_L2_STO_L_SFT 10
  716. #define RT5659_M_DAC_R2_STO_L (0x1 << 9)
  717. #define RT5659_M_DAC_R2_STO_L_SFT 9
  718. #define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)
  719. #define RT5659_G_DAC_R2_STO_L_SFT 8
  720. #define RT5659_M_DAC_L1_STO_R (0x1 << 7)
  721. #define RT5659_M_DAC_L1_STO_R_SFT 7
  722. #define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)
  723. #define RT5659_G_DAC_L1_STO_R_SFT 6
  724. #define RT5659_M_DAC_R1_STO_R (0x1 << 5)
  725. #define RT5659_M_DAC_R1_STO_R_SFT 5
  726. #define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)
  727. #define RT5659_G_DAC_R1_STO_R_SFT 4
  728. #define RT5659_M_DAC_L2_STO_R (0x1 << 3)
  729. #define RT5659_M_DAC_L2_STO_R_SFT 3
  730. #define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)
  731. #define RT5659_G_DAC_L2_STO_R_SFT 2
  732. #define RT5659_M_DAC_R2_STO_R (0x1 << 1)
  733. #define RT5659_M_DAC_R2_STO_R_SFT 1
  734. #define RT5659_G_DAC_R2_STO_R_MASK (0x1)
  735. #define RT5659_G_DAC_R2_STO_R_SFT 0
  736. /* Mono DAC Mixer Control (0x002b) */
  737. #define RT5659_M_DAC_L1_MONO_L (0x1 << 15)
  738. #define RT5659_M_DAC_L1_MONO_L_SFT 15
  739. #define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)
  740. #define RT5659_G_DAC_L1_MONO_L_SFT 14
  741. #define RT5659_M_DAC_R1_MONO_L (0x1 << 13)
  742. #define RT5659_M_DAC_R1_MONO_L_SFT 13
  743. #define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)
  744. #define RT5659_G_DAC_R1_MONO_L_SFT 12
  745. #define RT5659_M_DAC_L2_MONO_L (0x1 << 11)
  746. #define RT5659_M_DAC_L2_MONO_L_SFT 11
  747. #define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)
  748. #define RT5659_G_DAC_L2_MONO_L_SFT 10
  749. #define RT5659_M_DAC_R2_MONO_L (0x1 << 9)
  750. #define RT5659_M_DAC_R2_MONO_L_SFT 9
  751. #define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)
  752. #define RT5659_G_DAC_R2_MONO_L_SFT 8
  753. #define RT5659_M_DAC_L1_MONO_R (0x1 << 7)
  754. #define RT5659_M_DAC_L1_MONO_R_SFT 7
  755. #define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)
  756. #define RT5659_G_DAC_L1_MONO_R_SFT 6
  757. #define RT5659_M_DAC_R1_MONO_R (0x1 << 5)
  758. #define RT5659_M_DAC_R1_MONO_R_SFT 5
  759. #define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)
  760. #define RT5659_G_DAC_R1_MONO_R_SFT 4
  761. #define RT5659_M_DAC_L2_MONO_R (0x1 << 3)
  762. #define RT5659_M_DAC_L2_MONO_R_SFT 3
  763. #define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)
  764. #define RT5659_G_DAC_L2_MONO_R_SFT 2
  765. #define RT5659_M_DAC_R2_MONO_R (0x1 << 1)
  766. #define RT5659_M_DAC_R2_MONO_R_SFT 1
  767. #define RT5659_G_DAC_R2_MONO_R_MASK (0x1)
  768. #define RT5659_G_DAC_R2_MONO_R_SFT 0
  769. /* Digital Mixer Control (0x002c) */
  770. #define RT5659_M_DAC_MIX_L (0x1 << 7)
  771. #define RT5659_M_DAC_MIX_L_SFT 7
  772. #define RT5659_DAC_MIX_L_MASK (0x1 << 6)
  773. #define RT5659_DAC_MIX_L_SFT 6
  774. #define RT5659_M_DAC_MIX_R (0x1 << 5)
  775. #define RT5659_M_DAC_MIX_R_SFT 5
  776. #define RT5659_DAC_MIX_R_MASK (0x1 << 4)
  777. #define RT5659_DAC_MIX_R_SFT 4
  778. /* Analog DAC Input Source Control (0x002d) */
  779. #define RT5659_A_DACL1_SEL (0x1 << 3)
  780. #define RT5659_A_DACL1_SFT 3
  781. #define RT5659_A_DACR1_SEL (0x1 << 2)
  782. #define RT5659_A_DACR1_SFT 2
  783. #define RT5659_A_DACL2_SEL (0x1 << 1)
  784. #define RT5659_A_DACL2_SFT 1
  785. #define RT5659_A_DACR2_SEL (0x1 << 0)
  786. #define RT5659_A_DACR2_SFT 0
  787. /* Digital Interface Data Control (0x002f) */
  788. #define RT5659_IF2_ADC3_IN_MASK (0x3 << 14)
  789. #define RT5659_IF2_ADC3_IN_SFT 14
  790. #define RT5659_IF2_ADC_IN_MASK (0x3 << 12)
  791. #define RT5659_IF2_ADC_IN_SFT 12
  792. #define RT5659_IF2_DAC_SEL_MASK (0x3 << 10)
  793. #define RT5659_IF2_DAC_SEL_SFT 10
  794. #define RT5659_IF2_ADC_SEL_MASK (0x3 << 8)
  795. #define RT5659_IF2_ADC_SEL_SFT 8
  796. #define RT5659_IF3_DAC_SEL_MASK (0x3 << 6)
  797. #define RT5659_IF3_DAC_SEL_SFT 6
  798. #define RT5659_IF3_ADC_SEL_MASK (0x3 << 4)
  799. #define RT5659_IF3_ADC_SEL_SFT 4
  800. #define RT5659_IF3_ADC_IN_MASK (0x3 << 0)
  801. #define RT5659_IF3_ADC_IN_SFT 0
  802. /* PDM Output Control (0x0031) */
  803. #define RT5659_PDM1_L_MASK (0x1 << 15)
  804. #define RT5659_PDM1_L_SFT 15
  805. #define RT5659_M_PDM1_L (0x1 << 14)
  806. #define RT5659_M_PDM1_L_SFT 14
  807. #define RT5659_PDM1_R_MASK (0x1 << 13)
  808. #define RT5659_PDM1_R_SFT 13
  809. #define RT5659_M_PDM1_R (0x1 << 12)
  810. #define RT5659_M_PDM1_R_SFT 12
  811. #define RT5659_PDM2_BUSY (0x1 << 7)
  812. #define RT5659_PDM1_BUSY (0x1 << 6)
  813. #define RT5659_PDM_PATTERN (0x1 << 5)
  814. #define RT5659_PDM_GAIN (0x1 << 4)
  815. #define RT5659_PDM_DIV_MASK (0x3)
  816. /*S/PDIF Output Control (0x0036) */
  817. #define RT5659_SPDIF_SEL_MASK (0x3 << 0)
  818. #define RT5659_SPDIF_SEL_SFT 0
  819. /* REC Left Mixer Control 2 (0x003c) */
  820. #define RT5659_M_BST1_RM1_L (0x1 << 5)
  821. #define RT5659_M_BST1_RM1_L_SFT 5
  822. #define RT5659_M_BST2_RM1_L (0x1 << 4)
  823. #define RT5659_M_BST2_RM1_L_SFT 4
  824. #define RT5659_M_BST3_RM1_L (0x1 << 3)
  825. #define RT5659_M_BST3_RM1_L_SFT 3
  826. #define RT5659_M_BST4_RM1_L (0x1 << 2)
  827. #define RT5659_M_BST4_RM1_L_SFT 2
  828. #define RT5659_M_INL_RM1_L (0x1 << 1)
  829. #define RT5659_M_INL_RM1_L_SFT 1
  830. #define RT5659_M_SPKVOLL_RM1_L (0x1)
  831. #define RT5659_M_SPKVOLL_RM1_L_SFT 0
  832. /* REC Right Mixer Control 2 (0x003e) */
  833. #define RT5659_M_BST1_RM1_R (0x1 << 5)
  834. #define RT5659_M_BST1_RM1_R_SFT 5
  835. #define RT5659_M_BST2_RM1_R (0x1 << 4)
  836. #define RT5659_M_BST2_RM1_R_SFT 4
  837. #define RT5659_M_BST3_RM1_R (0x1 << 3)
  838. #define RT5659_M_BST3_RM1_R_SFT 3
  839. #define RT5659_M_BST4_RM1_R (0x1 << 2)
  840. #define RT5659_M_BST4_RM1_R_SFT 2
  841. #define RT5659_M_INR_RM1_R (0x1 << 1)
  842. #define RT5659_M_INR_RM1_R_SFT 1
  843. #define RT5659_M_HPOVOLR_RM1_R (0x1)
  844. #define RT5659_M_HPOVOLR_RM1_R_SFT 0
  845. /* SPK Left Mixer Control (0x0046) */
  846. #define RT5659_M_BST3_SM_L (0x1 << 4)
  847. #define RT5659_M_BST3_SM_L_SFT 4
  848. #define RT5659_M_IN_R_SM_L (0x1 << 3)
  849. #define RT5659_M_IN_R_SM_L_SFT 3
  850. #define RT5659_M_IN_L_SM_L (0x1 << 2)
  851. #define RT5659_M_IN_L_SM_L_SFT 2
  852. #define RT5659_M_BST1_SM_L (0x1 << 1)
  853. #define RT5659_M_BST1_SM_L_SFT 1
  854. #define RT5659_M_DAC_L2_SM_L (0x1)
  855. #define RT5659_M_DAC_L2_SM_L_SFT 0
  856. /* SPK Right Mixer Control (0x0047) */
  857. #define RT5659_M_BST3_SM_R (0x1 << 4)
  858. #define RT5659_M_BST3_SM_R_SFT 4
  859. #define RT5659_M_IN_R_SM_R (0x1 << 3)
  860. #define RT5659_M_IN_R_SM_R_SFT 3
  861. #define RT5659_M_IN_L_SM_R (0x1 << 2)
  862. #define RT5659_M_IN_L_SM_R_SFT 2
  863. #define RT5659_M_BST4_SM_R (0x1 << 1)
  864. #define RT5659_M_BST4_SM_R_SFT 1
  865. #define RT5659_M_DAC_R2_SM_R (0x1)
  866. #define RT5659_M_DAC_R2_SM_R_SFT 0
  867. /* SPO Amp Input and Gain Control (0x0048) */
  868. #define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)
  869. #define RT5659_M_DAC_L2_SPKOMIX_SFT 13
  870. #define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)
  871. #define RT5659_M_SPKVOLL_SPKOMIX_SFT 12
  872. #define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)
  873. #define RT5659_M_DAC_R2_SPKOMIX_SFT 9
  874. #define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)
  875. #define RT5659_M_SPKVOLR_SPKOMIX_SFT 8
  876. /* MONOMIX Input and Gain Control (0x004b) */
  877. #define RT5659_M_MONOVOL_MA (0x1 << 9)
  878. #define RT5659_M_MONOVOL_MA_SFT 9
  879. #define RT5659_M_DAC_L2_MA (0x1 << 8)
  880. #define RT5659_M_DAC_L2_MA_SFT 8
  881. #define RT5659_M_BST3_MM (0x1 << 4)
  882. #define RT5659_M_BST3_MM_SFT 4
  883. #define RT5659_M_BST2_MM (0x1 << 3)
  884. #define RT5659_M_BST2_MM_SFT 3
  885. #define RT5659_M_BST1_MM (0x1 << 2)
  886. #define RT5659_M_BST1_MM_SFT 2
  887. #define RT5659_M_DAC_R2_MM (0x1 << 1)
  888. #define RT5659_M_DAC_R2_MM_SFT 1
  889. #define RT5659_M_DAC_L2_MM (0x1)
  890. #define RT5659_M_DAC_L2_MM_SFT 0
  891. /* Output Left Mixer Control 1 (0x004d) */
  892. #define RT5659_G_BST3_OM_L_MASK (0x7 << 12)
  893. #define RT5659_G_BST3_OM_L_SFT 12
  894. #define RT5659_G_BST2_OM_L_MASK (0x7 << 9)
  895. #define RT5659_G_BST2_OM_L_SFT 9
  896. #define RT5659_G_BST1_OM_L_MASK (0x7 << 6)
  897. #define RT5659_G_BST1_OM_L_SFT 6
  898. #define RT5659_G_IN_L_OM_L_MASK (0x7 << 3)
  899. #define RT5659_G_IN_L_OM_L_SFT 3
  900. #define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0)
  901. #define RT5659_G_DAC_L2_OM_L_SFT 0
  902. /* Output Left Mixer Input Control (0x004e) */
  903. #define RT5659_M_BST3_OM_L (0x1 << 4)
  904. #define RT5659_M_BST3_OM_L_SFT 4
  905. #define RT5659_M_BST2_OM_L (0x1 << 3)
  906. #define RT5659_M_BST2_OM_L_SFT 3
  907. #define RT5659_M_BST1_OM_L (0x1 << 2)
  908. #define RT5659_M_BST1_OM_L_SFT 2
  909. #define RT5659_M_IN_L_OM_L (0x1 << 1)
  910. #define RT5659_M_IN_L_OM_L_SFT 1
  911. #define RT5659_M_DAC_L2_OM_L (0x1)
  912. #define RT5659_M_DAC_L2_OM_L_SFT 0
  913. /* Output Right Mixer Input Control (0x0050) */
  914. #define RT5659_M_BST4_OM_R (0x1 << 4)
  915. #define RT5659_M_BST4_OM_R_SFT 4
  916. #define RT5659_M_BST3_OM_R (0x1 << 3)
  917. #define RT5659_M_BST3_OM_R_SFT 3
  918. #define RT5659_M_BST2_OM_R (0x1 << 2)
  919. #define RT5659_M_BST2_OM_R_SFT 2
  920. #define RT5659_M_IN_R_OM_R (0x1 << 1)
  921. #define RT5659_M_IN_R_OM_R_SFT 1
  922. #define RT5659_M_DAC_R2_OM_R (0x1)
  923. #define RT5659_M_DAC_R2_OM_R_SFT 0
  924. /* LOUT Mixer Control (0x0052) */
  925. #define RT5659_M_DAC_L2_LM (0x1 << 15)
  926. #define RT5659_M_DAC_L2_LM_SFT 15
  927. #define RT5659_M_DAC_R2_LM (0x1 << 14)
  928. #define RT5659_M_DAC_R2_LM_SFT 14
  929. #define RT5659_M_OV_L_LM (0x1 << 13)
  930. #define RT5659_M_OV_L_LM_SFT 13
  931. #define RT5659_M_OV_R_LM (0x1 << 12)
  932. #define RT5659_M_OV_R_LM_SFT 12
  933. /* Power Management for Digital 1 (0x0061) */
  934. #define RT5659_PWR_I2S1 (0x1 << 15)
  935. #define RT5659_PWR_I2S1_BIT 15
  936. #define RT5659_PWR_I2S2 (0x1 << 14)
  937. #define RT5659_PWR_I2S2_BIT 14
  938. #define RT5659_PWR_I2S3 (0x1 << 13)
  939. #define RT5659_PWR_I2S3_BIT 13
  940. #define RT5659_PWR_SPDIF (0x1 << 12)
  941. #define RT5659_PWR_SPDIF_BIT 12
  942. #define RT5659_PWR_DAC_L1 (0x1 << 11)
  943. #define RT5659_PWR_DAC_L1_BIT 11
  944. #define RT5659_PWR_DAC_R1 (0x1 << 10)
  945. #define RT5659_PWR_DAC_R1_BIT 10
  946. #define RT5659_PWR_DAC_L2 (0x1 << 9)
  947. #define RT5659_PWR_DAC_L2_BIT 9
  948. #define RT5659_PWR_DAC_R2 (0x1 << 8)
  949. #define RT5659_PWR_DAC_R2_BIT 8
  950. #define RT5659_PWR_LDO (0x1 << 7)
  951. #define RT5659_PWR_LDO_BIT 7
  952. #define RT5659_PWR_ADC_L1 (0x1 << 4)
  953. #define RT5659_PWR_ADC_L1_BIT 4
  954. #define RT5659_PWR_ADC_R1 (0x1 << 3)
  955. #define RT5659_PWR_ADC_R1_BIT 3
  956. #define RT5659_PWR_ADC_L2 (0x1 << 2)
  957. #define RT5659_PWR_ADC_L2_BIT 2
  958. #define RT5659_PWR_ADC_R2 (0x1 << 1)
  959. #define RT5659_PWR_ADC_R2_BIT 1
  960. #define RT5659_PWR_CLS_D (0x1)
  961. #define RT5659_PWR_CLS_D_BIT 0
  962. /* Power Management for Digital 2 (0x0062) */
  963. #define RT5659_PWR_ADC_S1F (0x1 << 15)
  964. #define RT5659_PWR_ADC_S1F_BIT 15
  965. #define RT5659_PWR_ADC_S2F (0x1 << 14)
  966. #define RT5659_PWR_ADC_S2F_BIT 14
  967. #define RT5659_PWR_ADC_MF_L (0x1 << 13)
  968. #define RT5659_PWR_ADC_MF_L_BIT 13
  969. #define RT5659_PWR_ADC_MF_R (0x1 << 12)
  970. #define RT5659_PWR_ADC_MF_R_BIT 12
  971. #define RT5659_PWR_DAC_S1F (0x1 << 10)
  972. #define RT5659_PWR_DAC_S1F_BIT 10
  973. #define RT5659_PWR_DAC_MF_L (0x1 << 9)
  974. #define RT5659_PWR_DAC_MF_L_BIT 9
  975. #define RT5659_PWR_DAC_MF_R (0x1 << 8)
  976. #define RT5659_PWR_DAC_MF_R_BIT 8
  977. #define RT5659_PWR_PDM1 (0x1 << 7)
  978. #define RT5659_PWR_PDM1_BIT 7
  979. /* Power Management for Analog 1 (0x0063) */
  980. #define RT5659_PWR_VREF1 (0x1 << 15)
  981. #define RT5659_PWR_VREF1_BIT 15
  982. #define RT5659_PWR_FV1 (0x1 << 14)
  983. #define RT5659_PWR_FV1_BIT 14
  984. #define RT5659_PWR_VREF2 (0x1 << 13)
  985. #define RT5659_PWR_VREF2_BIT 13
  986. #define RT5659_PWR_FV2 (0x1 << 12)
  987. #define RT5659_PWR_FV2_BIT 12
  988. #define RT5659_PWR_VREF3 (0x1 << 11)
  989. #define RT5659_PWR_VREF3_BIT 11
  990. #define RT5659_PWR_FV3 (0x1 << 10)
  991. #define RT5659_PWR_FV3_BIT 10
  992. #define RT5659_PWR_MB (0x1 << 9)
  993. #define RT5659_PWR_MB_BIT 9
  994. #define RT5659_PWR_LM (0x1 << 8)
  995. #define RT5659_PWR_LM_BIT 8
  996. #define RT5659_PWR_BG (0x1 << 7)
  997. #define RT5659_PWR_BG_BIT 7
  998. #define RT5659_PWR_MA (0x1 << 6)
  999. #define RT5659_PWR_MA_BIT 6
  1000. #define RT5659_PWR_HA_L (0x1 << 5)
  1001. #define RT5659_PWR_HA_L_BIT 5
  1002. #define RT5659_PWR_HA_R (0x1 << 4)
  1003. #define RT5659_PWR_HA_R_BIT 4
  1004. /* Power Management for Analog 2 (0x0064) */
  1005. #define RT5659_PWR_BST1 (0x1 << 15)
  1006. #define RT5659_PWR_BST1_BIT 15
  1007. #define RT5659_PWR_BST2 (0x1 << 14)
  1008. #define RT5659_PWR_BST2_BIT 14
  1009. #define RT5659_PWR_BST3 (0x1 << 13)
  1010. #define RT5659_PWR_BST3_BIT 13
  1011. #define RT5659_PWR_BST4 (0x1 << 12)
  1012. #define RT5659_PWR_BST4_BIT 12
  1013. #define RT5659_PWR_MB1 (0x1 << 11)
  1014. #define RT5659_PWR_MB1_BIT 11
  1015. #define RT5659_PWR_MB2 (0x1 << 10)
  1016. #define RT5659_PWR_MB2_BIT 10
  1017. #define RT5659_PWR_MB3 (0x1 << 9)
  1018. #define RT5659_PWR_MB3_BIT 9
  1019. #define RT5659_PWR_BST1_P (0x1 << 6)
  1020. #define RT5659_PWR_BST1_P_BIT 6
  1021. #define RT5659_PWR_BST2_P (0x1 << 5)
  1022. #define RT5659_PWR_BST2_P_BIT 5
  1023. #define RT5659_PWR_BST3_P (0x1 << 4)
  1024. #define RT5659_PWR_BST3_P_BIT 4
  1025. #define RT5659_PWR_BST4_P (0x1 << 3)
  1026. #define RT5659_PWR_BST4_P_BIT 3
  1027. #define RT5659_PWR_JD1 (0x1 << 2)
  1028. #define RT5659_PWR_JD1_BIT 2
  1029. #define RT5659_PWR_JD2 (0x1 << 1)
  1030. #define RT5659_PWR_JD2_BIT 1
  1031. #define RT5659_PWR_JD3 (0x1)
  1032. #define RT5659_PWR_JD3_BIT 0
  1033. /* Power Management for Analog 3 (0x0065) */
  1034. #define RT5659_PWR_BST_L (0x1 << 8)
  1035. #define RT5659_PWR_BST_L_BIT 8
  1036. #define RT5659_PWR_BST_R (0x1 << 7)
  1037. #define RT5659_PWR_BST_R_BIT 7
  1038. #define RT5659_PWR_PLL (0x1 << 6)
  1039. #define RT5659_PWR_PLL_BIT 6
  1040. #define RT5659_PWR_LDO5 (0x1 << 5)
  1041. #define RT5659_PWR_LDO5_BIT 5
  1042. #define RT5659_PWR_LDO4 (0x1 << 4)
  1043. #define RT5659_PWR_LDO4_BIT 4
  1044. #define RT5659_PWR_LDO3 (0x1 << 3)
  1045. #define RT5659_PWR_LDO3_BIT 3
  1046. #define RT5659_PWR_LDO2 (0x1 << 2)
  1047. #define RT5659_PWR_LDO2_BIT 2
  1048. #define RT5659_PWR_SVD (0x1 << 1)
  1049. #define RT5659_PWR_SVD_BIT 1
  1050. /* Power Management for Mixer (0x0066) */
  1051. #define RT5659_PWR_OM_L (0x1 << 15)
  1052. #define RT5659_PWR_OM_L_BIT 15
  1053. #define RT5659_PWR_OM_R (0x1 << 14)
  1054. #define RT5659_PWR_OM_R_BIT 14
  1055. #define RT5659_PWR_SM_L (0x1 << 13)
  1056. #define RT5659_PWR_SM_L_BIT 13
  1057. #define RT5659_PWR_SM_R (0x1 << 12)
  1058. #define RT5659_PWR_SM_R_BIT 12
  1059. #define RT5659_PWR_RM1_L (0x1 << 11)
  1060. #define RT5659_PWR_RM1_L_BIT 11
  1061. #define RT5659_PWR_RM1_R (0x1 << 10)
  1062. #define RT5659_PWR_RM1_R_BIT 10
  1063. #define RT5659_PWR_MM (0x1 << 8)
  1064. #define RT5659_PWR_MM_BIT 8
  1065. #define RT5659_PWR_RM2_L (0x1 << 3)
  1066. #define RT5659_PWR_RM2_L_BIT 3
  1067. #define RT5659_PWR_RM2_R (0x1 << 2)
  1068. #define RT5659_PWR_RM2_R_BIT 2
  1069. /* Power Management for Volume (0x0067) */
  1070. #define RT5659_PWR_SV_L (0x1 << 15)
  1071. #define RT5659_PWR_SV_L_BIT 15
  1072. #define RT5659_PWR_SV_R (0x1 << 14)
  1073. #define RT5659_PWR_SV_R_BIT 14
  1074. #define RT5659_PWR_OV_L (0x1 << 13)
  1075. #define RT5659_PWR_OV_L_BIT 13
  1076. #define RT5659_PWR_OV_R (0x1 << 12)
  1077. #define RT5659_PWR_OV_R_BIT 12
  1078. #define RT5659_PWR_IN_L (0x1 << 9)
  1079. #define RT5659_PWR_IN_L_BIT 9
  1080. #define RT5659_PWR_IN_R (0x1 << 8)
  1081. #define RT5659_PWR_IN_R_BIT 8
  1082. #define RT5659_PWR_MV (0x1 << 7)
  1083. #define RT5659_PWR_MV_BIT 7
  1084. #define RT5659_PWR_MIC_DET (0x1 << 5)
  1085. #define RT5659_PWR_MIC_DET_BIT 5
  1086. /* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
  1087. #define RT5659_I2S_MS_MASK (0x1 << 15)
  1088. #define RT5659_I2S_MS_SFT 15
  1089. #define RT5659_I2S_MS_M (0x0 << 15)
  1090. #define RT5659_I2S_MS_S (0x1 << 15)
  1091. #define RT5659_I2S_O_CP_MASK (0x3 << 12)
  1092. #define RT5659_I2S_O_CP_SFT 12
  1093. #define RT5659_I2S_O_CP_OFF (0x0 << 12)
  1094. #define RT5659_I2S_O_CP_U_LAW (0x1 << 12)
  1095. #define RT5659_I2S_O_CP_A_LAW (0x2 << 12)
  1096. #define RT5659_I2S_I_CP_MASK (0x3 << 10)
  1097. #define RT5659_I2S_I_CP_SFT 10
  1098. #define RT5659_I2S_I_CP_OFF (0x0 << 10)
  1099. #define RT5659_I2S_I_CP_U_LAW (0x1 << 10)
  1100. #define RT5659_I2S_I_CP_A_LAW (0x2 << 10)
  1101. #define RT5659_I2S_BP_MASK (0x1 << 8)
  1102. #define RT5659_I2S_BP_SFT 8
  1103. #define RT5659_I2S_BP_NOR (0x0 << 8)
  1104. #define RT5659_I2S_BP_INV (0x1 << 8)
  1105. #define RT5659_I2S_DL_MASK (0x3 << 4)
  1106. #define RT5659_I2S_DL_SFT 4
  1107. #define RT5659_I2S_DL_16 (0x0 << 4)
  1108. #define RT5659_I2S_DL_20 (0x1 << 4)
  1109. #define RT5659_I2S_DL_24 (0x2 << 4)
  1110. #define RT5659_I2S_DL_8 (0x3 << 4)
  1111. #define RT5659_I2S_DF_MASK (0x7)
  1112. #define RT5659_I2S_DF_SFT 0
  1113. #define RT5659_I2S_DF_I2S (0x0)
  1114. #define RT5659_I2S_DF_LEFT (0x1)
  1115. #define RT5659_I2S_DF_PCM_A (0x2)
  1116. #define RT5659_I2S_DF_PCM_B (0x3)
  1117. #define RT5659_I2S_DF_PCM_A_N (0x6)
  1118. #define RT5659_I2S_DF_PCM_B_N (0x7)
  1119. /* ADC/DAC Clock Control 1 (0x0073) */
  1120. #define RT5659_I2S_PD1_MASK (0x7 << 12)
  1121. #define RT5659_I2S_PD1_SFT 12
  1122. #define RT5659_I2S_PD1_1 (0x0 << 12)
  1123. #define RT5659_I2S_PD1_2 (0x1 << 12)
  1124. #define RT5659_I2S_PD1_3 (0x2 << 12)
  1125. #define RT5659_I2S_PD1_4 (0x3 << 12)
  1126. #define RT5659_I2S_PD1_6 (0x4 << 12)
  1127. #define RT5659_I2S_PD1_8 (0x5 << 12)
  1128. #define RT5659_I2S_PD1_12 (0x6 << 12)
  1129. #define RT5659_I2S_PD1_16 (0x7 << 12)
  1130. #define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)
  1131. #define RT5659_I2S_BCLK_MS2_SFT 11
  1132. #define RT5659_I2S_BCLK_MS2_32 (0x0 << 11)
  1133. #define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)
  1134. #define RT5659_I2S_PD2_MASK (0x7 << 8)
  1135. #define RT5659_I2S_PD2_SFT 8
  1136. #define RT5659_I2S_PD2_1 (0x0 << 8)
  1137. #define RT5659_I2S_PD2_2 (0x1 << 8)
  1138. #define RT5659_I2S_PD2_3 (0x2 << 8)
  1139. #define RT5659_I2S_PD2_4 (0x3 << 8)
  1140. #define RT5659_I2S_PD2_6 (0x4 << 8)
  1141. #define RT5659_I2S_PD2_8 (0x5 << 8)
  1142. #define RT5659_I2S_PD2_12 (0x6 << 8)
  1143. #define RT5659_I2S_PD2_16 (0x7 << 8)
  1144. #define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)
  1145. #define RT5659_I2S_BCLK_MS3_SFT 7
  1146. #define RT5659_I2S_BCLK_MS3_32 (0x0 << 7)
  1147. #define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)
  1148. #define RT5659_I2S_PD3_MASK (0x7 << 4)
  1149. #define RT5659_I2S_PD3_SFT 4
  1150. #define RT5659_I2S_PD3_1 (0x0 << 4)
  1151. #define RT5659_I2S_PD3_2 (0x1 << 4)
  1152. #define RT5659_I2S_PD3_3 (0x2 << 4)
  1153. #define RT5659_I2S_PD3_4 (0x3 << 4)
  1154. #define RT5659_I2S_PD3_6 (0x4 << 4)
  1155. #define RT5659_I2S_PD3_8 (0x5 << 4)
  1156. #define RT5659_I2S_PD3_12 (0x6 << 4)
  1157. #define RT5659_I2S_PD3_16 (0x7 << 4)
  1158. #define RT5659_DAC_OSR_MASK (0x3 << 2)
  1159. #define RT5659_DAC_OSR_SFT 2
  1160. #define RT5659_DAC_OSR_128 (0x0 << 2)
  1161. #define RT5659_DAC_OSR_64 (0x1 << 2)
  1162. #define RT5659_DAC_OSR_32 (0x2 << 2)
  1163. #define RT5659_DAC_OSR_16 (0x3 << 2)
  1164. #define RT5659_ADC_OSR_MASK (0x3)
  1165. #define RT5659_ADC_OSR_SFT 0
  1166. #define RT5659_ADC_OSR_128 (0x0)
  1167. #define RT5659_ADC_OSR_64 (0x1)
  1168. #define RT5659_ADC_OSR_32 (0x2)
  1169. #define RT5659_ADC_OSR_16 (0x3)
  1170. /* Digital Microphone Control (0x0075) */
  1171. #define RT5659_DMIC_1_EN_MASK (0x1 << 15)
  1172. #define RT5659_DMIC_1_EN_SFT 15
  1173. #define RT5659_DMIC_1_DIS (0x0 << 15)
  1174. #define RT5659_DMIC_1_EN (0x1 << 15)
  1175. #define RT5659_DMIC_2_EN_MASK (0x1 << 14)
  1176. #define RT5659_DMIC_2_EN_SFT 14
  1177. #define RT5659_DMIC_2_DIS (0x0 << 14)
  1178. #define RT5659_DMIC_2_EN (0x1 << 14)
  1179. #define RT5659_DMIC_1L_LH_MASK (0x1 << 13)
  1180. #define RT5659_DMIC_1L_LH_SFT 13
  1181. #define RT5659_DMIC_1L_LH_RISING (0x0 << 13)
  1182. #define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)
  1183. #define RT5659_DMIC_1R_LH_MASK (0x1 << 12)
  1184. #define RT5659_DMIC_1R_LH_SFT 12
  1185. #define RT5659_DMIC_1R_LH_RISING (0x0 << 12)
  1186. #define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)
  1187. #define RT5659_DMIC_2_DP_MASK (0x3 << 10)
  1188. #define RT5659_DMIC_2_DP_SFT 10
  1189. #define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10)
  1190. #define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)
  1191. #define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10)
  1192. #define RT5659_DMIC_2_DP_IN2P (0x3 << 10)
  1193. #define RT5659_DMIC_CLK_MASK (0x7 << 5)
  1194. #define RT5659_DMIC_CLK_SFT 5
  1195. #define RT5659_DMIC_1_DP_MASK (0x3 << 0)
  1196. #define RT5659_DMIC_1_DP_SFT 0
  1197. #define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0)
  1198. #define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)
  1199. #define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0)
  1200. #define RT5659_DMIC_1_DP_IN2N (0x3 << 0)
  1201. /* TDM control 1 (0x0078)*/
  1202. #define RT5659_DS_ADC_SLOT01_SFT 14
  1203. #define RT5659_DS_ADC_SLOT23_SFT 12
  1204. #define RT5659_DS_ADC_SLOT45_SFT 10
  1205. #define RT5659_DS_ADC_SLOT67_SFT 8
  1206. #define RT5659_ADCDAT_SRC_MASK 0x1f
  1207. #define RT5659_ADCDAT_SRC_SFT 0
  1208. /* Global Clock Control (0x0080) */
  1209. #define RT5659_SCLK_SRC_MASK (0x3 << 14)
  1210. #define RT5659_SCLK_SRC_SFT 14
  1211. #define RT5659_SCLK_SRC_MCLK (0x0 << 14)
  1212. #define RT5659_SCLK_SRC_PLL1 (0x1 << 14)
  1213. #define RT5659_SCLK_SRC_RCCLK (0x2 << 14)
  1214. #define RT5659_PLL1_SRC_MASK (0x7 << 11)
  1215. #define RT5659_PLL1_SRC_SFT 11
  1216. #define RT5659_PLL1_SRC_MCLK (0x0 << 11)
  1217. #define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)
  1218. #define RT5659_PLL1_SRC_BCLK2 (0x2 << 11)
  1219. #define RT5659_PLL1_SRC_BCLK3 (0x3 << 11)
  1220. #define RT5659_PLL1_PD_MASK (0x1 << 3)
  1221. #define RT5659_PLL1_PD_SFT 3
  1222. #define RT5659_PLL1_PD_1 (0x0 << 3)
  1223. #define RT5659_PLL1_PD_2 (0x1 << 3)
  1224. #define RT5659_PLL_INP_MAX 40000000
  1225. #define RT5659_PLL_INP_MIN 256000
  1226. /* PLL M/N/K Code Control 1 (0x0081) */
  1227. #define RT5659_PLL_N_MAX 0x001ff
  1228. #define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7)
  1229. #define RT5659_PLL_N_SFT 7
  1230. #define RT5659_PLL_K_MAX 0x001f
  1231. #define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX)
  1232. #define RT5659_PLL_K_SFT 0
  1233. /* PLL M/N/K Code Control 2 (0x0082) */
  1234. #define RT5659_PLL_M_MAX 0x00f
  1235. #define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12)
  1236. #define RT5659_PLL_M_SFT 12
  1237. #define RT5659_PLL_M_BP (0x1 << 11)
  1238. #define RT5659_PLL_M_BP_SFT 11
  1239. /* PLL tracking mode 1 (0x0083) */
  1240. #define RT5659_I2S3_ASRC_MASK (0x1 << 13)
  1241. #define RT5659_I2S3_ASRC_SFT 13
  1242. #define RT5659_I2S2_ASRC_MASK (0x1 << 12)
  1243. #define RT5659_I2S2_ASRC_SFT 12
  1244. #define RT5659_I2S1_ASRC_MASK (0x1 << 11)
  1245. #define RT5659_I2S1_ASRC_SFT 11
  1246. #define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)
  1247. #define RT5659_DAC_STO_ASRC_SFT 10
  1248. #define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)
  1249. #define RT5659_DAC_MONO_L_ASRC_SFT 9
  1250. #define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)
  1251. #define RT5659_DAC_MONO_R_ASRC_SFT 8
  1252. #define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)
  1253. #define RT5659_DMIC_STO1_ASRC_SFT 7
  1254. #define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)
  1255. #define RT5659_DMIC_MONO_L_ASRC_SFT 5
  1256. #define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)
  1257. #define RT5659_DMIC_MONO_R_ASRC_SFT 4
  1258. #define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)
  1259. #define RT5659_ADC_STO1_ASRC_SFT 3
  1260. #define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)
  1261. #define RT5659_ADC_MONO_L_ASRC_SFT 1
  1262. #define RT5659_ADC_MONO_R_ASRC_MASK (0x1)
  1263. #define RT5659_ADC_MONO_R_ASRC_SFT 0
  1264. /* PLL tracking mode 2 (0x0084)*/
  1265. #define RT5659_DA_STO_T_MASK (0x7 << 12)
  1266. #define RT5659_DA_STO_T_SFT 12
  1267. #define RT5659_DA_MONO_L_T_MASK (0x7 << 8)
  1268. #define RT5659_DA_MONO_L_T_SFT 8
  1269. #define RT5659_DA_MONO_R_T_MASK (0x7 << 4)
  1270. #define RT5659_DA_MONO_R_T_SFT 4
  1271. #define RT5659_AD_STO1_T_MASK (0x7)
  1272. #define RT5659_AD_STO1_T_SFT 0
  1273. /* PLL tracking mode 3 (0x0085)*/
  1274. #define RT5659_AD_STO2_T_MASK (0x7 << 8)
  1275. #define RT5659_AD_STO2_T_SFT 8
  1276. #define RT5659_AD_MONO_L_T_MASK (0x7 << 4)
  1277. #define RT5659_AD_MONO_L_T_SFT 4
  1278. #define RT5659_AD_MONO_R_T_MASK (0x7)
  1279. #define RT5659_AD_MONO_R_T_SFT 0
  1280. /* ASRC Control 4 (0x0086) */
  1281. #define RT5659_I2S1_RATE_MASK (0xf << 12)
  1282. #define RT5659_I2S1_RATE_SFT 12
  1283. #define RT5659_I2S2_RATE_MASK (0xf << 8)
  1284. #define RT5659_I2S2_RATE_SFT 8
  1285. #define RT5659_I2S3_RATE_MASK (0xf << 4)
  1286. #define RT5659_I2S3_RATE_SFT 4
  1287. /* Depop Mode Control 1 (0x8e) */
  1288. #define RT5659_SMT_TRIG_MASK (0x1 << 15)
  1289. #define RT5659_SMT_TRIG_SFT 15
  1290. #define RT5659_SMT_TRIG_DIS (0x0 << 15)
  1291. #define RT5659_SMT_TRIG_EN (0x1 << 15)
  1292. #define RT5659_HP_L_SMT_MASK (0x1 << 9)
  1293. #define RT5659_HP_L_SMT_SFT 9
  1294. #define RT5659_HP_L_SMT_DIS (0x0 << 9)
  1295. #define RT5659_HP_L_SMT_EN (0x1 << 9)
  1296. #define RT5659_HP_R_SMT_MASK (0x1 << 8)
  1297. #define RT5659_HP_R_SMT_SFT 8
  1298. #define RT5659_HP_R_SMT_DIS (0x0 << 8)
  1299. #define RT5659_HP_R_SMT_EN (0x1 << 8)
  1300. #define RT5659_HP_CD_PD_MASK (0x1 << 7)
  1301. #define RT5659_HP_CD_PD_SFT 7
  1302. #define RT5659_HP_CD_PD_DIS (0x0 << 7)
  1303. #define RT5659_HP_CD_PD_EN (0x1 << 7)
  1304. #define RT5659_RSTN_MASK (0x1 << 6)
  1305. #define RT5659_RSTN_SFT 6
  1306. #define RT5659_RSTN_DIS (0x0 << 6)
  1307. #define RT5659_RSTN_EN (0x1 << 6)
  1308. #define RT5659_RSTP_MASK (0x1 << 5)
  1309. #define RT5659_RSTP_SFT 5
  1310. #define RT5659_RSTP_DIS (0x0 << 5)
  1311. #define RT5659_RSTP_EN (0x1 << 5)
  1312. #define RT5659_HP_CO_MASK (0x1 << 4)
  1313. #define RT5659_HP_CO_SFT 4
  1314. #define RT5659_HP_CO_DIS (0x0 << 4)
  1315. #define RT5659_HP_CO_EN (0x1 << 4)
  1316. #define RT5659_HP_CP_MASK (0x1 << 3)
  1317. #define RT5659_HP_CP_SFT 3
  1318. #define RT5659_HP_CP_PD (0x0 << 3)
  1319. #define RT5659_HP_CP_PU (0x1 << 3)
  1320. #define RT5659_HP_SG_MASK (0x1 << 2)
  1321. #define RT5659_HP_SG_SFT 2
  1322. #define RT5659_HP_SG_DIS (0x0 << 2)
  1323. #define RT5659_HP_SG_EN (0x1 << 2)
  1324. #define RT5659_HP_DP_MASK (0x1 << 1)
  1325. #define RT5659_HP_DP_SFT 1
  1326. #define RT5659_HP_DP_PD (0x0 << 1)
  1327. #define RT5659_HP_DP_PU (0x1 << 1)
  1328. #define RT5659_HP_CB_MASK (0x1)
  1329. #define RT5659_HP_CB_SFT 0
  1330. #define RT5659_HP_CB_PD (0x0)
  1331. #define RT5659_HP_CB_PU (0x1)
  1332. /* Depop Mode Control 2 (0x8f) */
  1333. #define RT5659_DEPOP_MASK (0x1 << 13)
  1334. #define RT5659_DEPOP_SFT 13
  1335. #define RT5659_DEPOP_AUTO (0x0 << 13)
  1336. #define RT5659_DEPOP_MAN (0x1 << 13)
  1337. #define RT5659_RAMP_MASK (0x1 << 12)
  1338. #define RT5659_RAMP_SFT 12
  1339. #define RT5659_RAMP_DIS (0x0 << 12)
  1340. #define RT5659_RAMP_EN (0x1 << 12)
  1341. #define RT5659_BPS_MASK (0x1 << 11)
  1342. #define RT5659_BPS_SFT 11
  1343. #define RT5659_BPS_DIS (0x0 << 11)
  1344. #define RT5659_BPS_EN (0x1 << 11)
  1345. #define RT5659_FAST_UPDN_MASK (0x1 << 10)
  1346. #define RT5659_FAST_UPDN_SFT 10
  1347. #define RT5659_FAST_UPDN_DIS (0x0 << 10)
  1348. #define RT5659_FAST_UPDN_EN (0x1 << 10)
  1349. #define RT5659_MRES_MASK (0x3 << 8)
  1350. #define RT5659_MRES_SFT 8
  1351. #define RT5659_MRES_15MO (0x0 << 8)
  1352. #define RT5659_MRES_25MO (0x1 << 8)
  1353. #define RT5659_MRES_35MO (0x2 << 8)
  1354. #define RT5659_MRES_45MO (0x3 << 8)
  1355. #define RT5659_VLO_MASK (0x1 << 7)
  1356. #define RT5659_VLO_SFT 7
  1357. #define RT5659_VLO_3V (0x0 << 7)
  1358. #define RT5659_VLO_32V (0x1 << 7)
  1359. #define RT5659_DIG_DP_MASK (0x1 << 6)
  1360. #define RT5659_DIG_DP_SFT 6
  1361. #define RT5659_DIG_DP_DIS (0x0 << 6)
  1362. #define RT5659_DIG_DP_EN (0x1 << 6)
  1363. #define RT5659_DP_TH_MASK (0x3 << 4)
  1364. #define RT5659_DP_TH_SFT 4
  1365. /* Depop Mode Control 3 (0x90) */
  1366. #define RT5659_CP_SYS_MASK (0x7 << 12)
  1367. #define RT5659_CP_SYS_SFT 12
  1368. #define RT5659_CP_FQ1_MASK (0x7 << 8)
  1369. #define RT5659_CP_FQ1_SFT 8
  1370. #define RT5659_CP_FQ2_MASK (0x7 << 4)
  1371. #define RT5659_CP_FQ2_SFT 4
  1372. #define RT5659_CP_FQ3_MASK (0x7)
  1373. #define RT5659_CP_FQ3_SFT 0
  1374. #define RT5659_CP_FQ_1_5_KHZ 0
  1375. #define RT5659_CP_FQ_3_KHZ 1
  1376. #define RT5659_CP_FQ_6_KHZ 2
  1377. #define RT5659_CP_FQ_12_KHZ 3
  1378. #define RT5659_CP_FQ_24_KHZ 4
  1379. #define RT5659_CP_FQ_48_KHZ 5
  1380. #define RT5659_CP_FQ_96_KHZ 6
  1381. #define RT5659_CP_FQ_192_KHZ 7
  1382. /* HPOUT charge pump 1 (0x0091) */
  1383. #define RT5659_OSW_L_MASK (0x1 << 11)
  1384. #define RT5659_OSW_L_SFT 11
  1385. #define RT5659_OSW_L_DIS (0x0 << 11)
  1386. #define RT5659_OSW_L_EN (0x1 << 11)
  1387. #define RT5659_OSW_R_MASK (0x1 << 10)
  1388. #define RT5659_OSW_R_SFT 10
  1389. #define RT5659_OSW_R_DIS (0x0 << 10)
  1390. #define RT5659_OSW_R_EN (0x1 << 10)
  1391. #define RT5659_PM_HP_MASK (0x3 << 8)
  1392. #define RT5659_PM_HP_SFT 8
  1393. #define RT5659_PM_HP_LV (0x0 << 8)
  1394. #define RT5659_PM_HP_MV (0x1 << 8)
  1395. #define RT5659_PM_HP_HV (0x2 << 8)
  1396. #define RT5659_IB_HP_MASK (0x3 << 6)
  1397. #define RT5659_IB_HP_SFT 6
  1398. #define RT5659_IB_HP_125IL (0x0 << 6)
  1399. #define RT5659_IB_HP_25IL (0x1 << 6)
  1400. #define RT5659_IB_HP_5IL (0x2 << 6)
  1401. #define RT5659_IB_HP_1IL (0x3 << 6)
  1402. /* PV detection and SPK gain control (0x92) */
  1403. #define RT5659_PVDD_DET_MASK (0x1 << 15)
  1404. #define RT5659_PVDD_DET_SFT 15
  1405. #define RT5659_PVDD_DET_DIS (0x0 << 15)
  1406. #define RT5659_PVDD_DET_EN (0x1 << 15)
  1407. #define RT5659_SPK_AG_MASK (0x1 << 14)
  1408. #define RT5659_SPK_AG_SFT 14
  1409. #define RT5659_SPK_AG_DIS (0x0 << 14)
  1410. #define RT5659_SPK_AG_EN (0x1 << 14)
  1411. /* Micbias Control (0x93) */
  1412. #define RT5659_MIC1_BS_MASK (0x1 << 15)
  1413. #define RT5659_MIC1_BS_SFT 15
  1414. #define RT5659_MIC1_BS_9AV (0x0 << 15)
  1415. #define RT5659_MIC1_BS_75AV (0x1 << 15)
  1416. #define RT5659_MIC2_BS_MASK (0x1 << 14)
  1417. #define RT5659_MIC2_BS_SFT 14
  1418. #define RT5659_MIC2_BS_9AV (0x0 << 14)
  1419. #define RT5659_MIC2_BS_75AV (0x1 << 14)
  1420. #define RT5659_MIC1_CLK_MASK (0x1 << 13)
  1421. #define RT5659_MIC1_CLK_SFT 13
  1422. #define RT5659_MIC1_CLK_DIS (0x0 << 13)
  1423. #define RT5659_MIC1_CLK_EN (0x1 << 13)
  1424. #define RT5659_MIC2_CLK_MASK (0x1 << 12)
  1425. #define RT5659_MIC2_CLK_SFT 12
  1426. #define RT5659_MIC2_CLK_DIS (0x0 << 12)
  1427. #define RT5659_MIC2_CLK_EN (0x1 << 12)
  1428. #define RT5659_MIC1_OVCD_MASK (0x1 << 11)
  1429. #define RT5659_MIC1_OVCD_SFT 11
  1430. #define RT5659_MIC1_OVCD_DIS (0x0 << 11)
  1431. #define RT5659_MIC1_OVCD_EN (0x1 << 11)
  1432. #define RT5659_MIC1_OVTH_MASK (0x3 << 9)
  1433. #define RT5659_MIC1_OVTH_SFT 9
  1434. #define RT5659_MIC1_OVTH_600UA (0x0 << 9)
  1435. #define RT5659_MIC1_OVTH_1500UA (0x1 << 9)
  1436. #define RT5659_MIC1_OVTH_2000UA (0x2 << 9)
  1437. #define RT5659_MIC2_OVCD_MASK (0x1 << 8)
  1438. #define RT5659_MIC2_OVCD_SFT 8
  1439. #define RT5659_MIC2_OVCD_DIS (0x0 << 8)
  1440. #define RT5659_MIC2_OVCD_EN (0x1 << 8)
  1441. #define RT5659_MIC2_OVTH_MASK (0x3 << 6)
  1442. #define RT5659_MIC2_OVTH_SFT 6
  1443. #define RT5659_MIC2_OVTH_600UA (0x0 << 6)
  1444. #define RT5659_MIC2_OVTH_1500UA (0x1 << 6)
  1445. #define RT5659_MIC2_OVTH_2000UA (0x2 << 6)
  1446. #define RT5659_PWR_MB_MASK (0x1 << 5)
  1447. #define RT5659_PWR_MB_SFT 5
  1448. #define RT5659_PWR_MB_PD (0x0 << 5)
  1449. #define RT5659_PWR_MB_PU (0x1 << 5)
  1450. #define RT5659_PWR_CLK25M_MASK (0x1 << 4)
  1451. #define RT5659_PWR_CLK25M_SFT 4
  1452. #define RT5659_PWR_CLK25M_PD (0x0 << 4)
  1453. #define RT5659_PWR_CLK25M_PU (0x1 << 4)
  1454. /* REC Mixer 2 Left Control 2 (0x009c) */
  1455. #define RT5659_M_BST1_RM2_L (0x1 << 5)
  1456. #define RT5659_M_BST1_RM2_L_SFT 5
  1457. #define RT5659_M_BST2_RM2_L (0x1 << 4)
  1458. #define RT5659_M_BST2_RM2_L_SFT 4
  1459. #define RT5659_M_BST3_RM2_L (0x1 << 3)
  1460. #define RT5659_M_BST3_RM2_L_SFT 3
  1461. #define RT5659_M_BST4_RM2_L (0x1 << 2)
  1462. #define RT5659_M_BST4_RM2_L_SFT 2
  1463. #define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)
  1464. #define RT5659_M_OUTVOLL_RM2_L_SFT 1
  1465. #define RT5659_M_SPKVOL_RM2_L (0x1)
  1466. #define RT5659_M_SPKVOL_RM2_L_SFT 0
  1467. /* REC Mixer 2 Right Control 2 (0x009e) */
  1468. #define RT5659_M_BST1_RM2_R (0x1 << 5)
  1469. #define RT5659_M_BST1_RM2_R_SFT 5
  1470. #define RT5659_M_BST2_RM2_R (0x1 << 4)
  1471. #define RT5659_M_BST2_RM2_R_SFT 4
  1472. #define RT5659_M_BST3_RM2_R (0x1 << 3)
  1473. #define RT5659_M_BST3_RM2_R_SFT 3
  1474. #define RT5659_M_BST4_RM2_R (0x1 << 2)
  1475. #define RT5659_M_BST4_RM2_R_SFT 2
  1476. #define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)
  1477. #define RT5659_M_OUTVOLR_RM2_R_SFT 1
  1478. #define RT5659_M_MONOVOL_RM2_R (0x1)
  1479. #define RT5659_M_MONOVOL_RM2_R_SFT 0
  1480. /* Class D Output Control (0x00a0) */
  1481. #define RT5659_POW_CLSD_DB_MASK (0x1 << 9)
  1482. #define RT5659_POW_CLSD_DB_EN (0x1 << 9)
  1483. #define RT5659_POW_CLSD_DB_DIS (0x0 << 9)
  1484. /* EQ Control 1 (0x00b0) */
  1485. #define RT5659_EQ_SRC_DAC (0x0 << 15)
  1486. #define RT5659_EQ_SRC_ADC (0x1 << 15)
  1487. #define RT5659_EQ_UPD (0x1 << 14)
  1488. #define RT5659_EQ_UPD_BIT 14
  1489. #define RT5659_EQ_CD_MASK (0x1 << 13)
  1490. #define RT5659_EQ_CD_SFT 13
  1491. #define RT5659_EQ_CD_DIS (0x0 << 13)
  1492. #define RT5659_EQ_CD_EN (0x1 << 13)
  1493. #define RT5659_EQ_DITH_MASK (0x3 << 8)
  1494. #define RT5659_EQ_DITH_SFT 8
  1495. #define RT5659_EQ_DITH_NOR (0x0 << 8)
  1496. #define RT5659_EQ_DITH_LSB (0x1 << 8)
  1497. #define RT5659_EQ_DITH_LSB_1 (0x2 << 8)
  1498. #define RT5659_EQ_DITH_LSB_2 (0x3 << 8)
  1499. /* IRQ Control 1 (0x00b7) */
  1500. #define RT5659_JD1_1_EN_MASK (0x1 << 15)
  1501. #define RT5659_JD1_1_EN_SFT 15
  1502. #define RT5659_JD1_1_DIS (0x0 << 15)
  1503. #define RT5659_JD1_1_EN (0x1 << 15)
  1504. #define RT5659_JD1_2_EN_MASK (0x1 << 12)
  1505. #define RT5659_JD1_2_EN_SFT 12
  1506. #define RT5659_JD1_2_DIS (0x0 << 12)
  1507. #define RT5659_JD1_2_EN (0x1 << 12)
  1508. #define RT5659_IL_IRQ_MASK (0x1 << 3)
  1509. #define RT5659_IL_IRQ_DIS (0x0 << 3)
  1510. #define RT5659_IL_IRQ_EN (0x1 << 3)
  1511. /* IRQ Control 5 (0x00ba) */
  1512. #define RT5659_IRQ_JD_EN (0x1 << 3)
  1513. #define RT5659_IRQ_JD_EN_SFT 3
  1514. /* GPIO Control 1 (0x00c0) */
  1515. #define RT5659_GP1_PIN_MASK (0x1 << 15)
  1516. #define RT5659_GP1_PIN_SFT 15
  1517. #define RT5659_GP1_PIN_GPIO1 (0x0 << 15)
  1518. #define RT5659_GP1_PIN_IRQ (0x1 << 15)
  1519. #define RT5659_GP2_PIN_MASK (0x1 << 14)
  1520. #define RT5659_GP2_PIN_SFT 14
  1521. #define RT5659_GP2_PIN_GPIO2 (0x0 << 14)
  1522. #define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)
  1523. #define RT5659_GP3_PIN_MASK (0x1 << 13)
  1524. #define RT5659_GP3_PIN_SFT 13
  1525. #define RT5659_GP3_PIN_GPIO3 (0x0 << 13)
  1526. #define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)
  1527. #define RT5659_GP4_PIN_MASK (0x1 << 12)
  1528. #define RT5659_GP4_PIN_SFT 12
  1529. #define RT5659_GP4_PIN_GPIO4 (0x0 << 12)
  1530. #define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)
  1531. #define RT5659_GP5_PIN_MASK (0x1 << 11)
  1532. #define RT5659_GP5_PIN_SFT 11
  1533. #define RT5659_GP5_PIN_GPIO5 (0x0 << 11)
  1534. #define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)
  1535. #define RT5659_GP6_PIN_MASK (0x1 << 10)
  1536. #define RT5659_GP6_PIN_SFT 10
  1537. #define RT5659_GP6_PIN_GPIO6 (0x0 << 10)
  1538. #define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)
  1539. #define RT5659_GP7_PIN_MASK (0x1 << 9)
  1540. #define RT5659_GP7_PIN_SFT 9
  1541. #define RT5659_GP7_PIN_GPIO7 (0x0 << 9)
  1542. #define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)
  1543. #define RT5659_GP8_PIN_MASK (0x1 << 8)
  1544. #define RT5659_GP8_PIN_SFT 8
  1545. #define RT5659_GP8_PIN_GPIO8 (0x0 << 8)
  1546. #define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)
  1547. #define RT5659_GP9_PIN_MASK (0x1 << 7)
  1548. #define RT5659_GP9_PIN_SFT 7
  1549. #define RT5659_GP9_PIN_GPIO9 (0x0 << 7)
  1550. #define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)
  1551. #define RT5659_GP10_PIN_MASK (0x1 << 6)
  1552. #define RT5659_GP10_PIN_SFT 6
  1553. #define RT5659_GP10_PIN_GPIO10 (0x0 << 6)
  1554. #define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)
  1555. #define RT5659_GP11_PIN_MASK (0x1 << 5)
  1556. #define RT5659_GP11_PIN_SFT 5
  1557. #define RT5659_GP11_PIN_GPIO11 (0x0 << 5)
  1558. #define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)
  1559. #define RT5659_GP12_PIN_MASK (0x1 << 4)
  1560. #define RT5659_GP12_PIN_SFT 4
  1561. #define RT5659_GP12_PIN_GPIO12 (0x0 << 4)
  1562. #define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)
  1563. #define RT5659_GP13_PIN_MASK (0x3 << 2)
  1564. #define RT5659_GP13_PIN_SFT 2
  1565. #define RT5659_GP13_PIN_GPIO13 (0x0 << 2)
  1566. #define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)
  1567. #define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2)
  1568. #define RT5659_GP13_PIN_PDM_SCL (0x3 << 2)
  1569. #define RT5659_GP15_PIN_MASK (0x3)
  1570. #define RT5659_GP15_PIN_SFT 0
  1571. #define RT5659_GP15_PIN_GPIO15 (0x0)
  1572. #define RT5659_GP15_PIN_DMIC3_SCL (0x1)
  1573. #define RT5659_GP15_PIN_PDM_SDA (0x2)
  1574. /* GPIO Control 2 (0x00c1)*/
  1575. #define RT5659_GP1_PF_IN (0x0 << 2)
  1576. #define RT5659_GP1_PF_OUT (0x1 << 2)
  1577. #define RT5659_GP1_PF_MASK (0x1 << 2)
  1578. #define RT5659_GP1_PF_SFT 2
  1579. /* GPIO Control 3 (0x00c2) */
  1580. #define RT5659_I2S2_PIN_MASK (0x1 << 15)
  1581. #define RT5659_I2S2_PIN_SFT 15
  1582. #define RT5659_I2S2_PIN_I2S (0x0 << 15)
  1583. #define RT5659_I2S2_PIN_GPIO (0x1 << 15)
  1584. /* Soft volume and zero cross control 1 (0x00d9) */
  1585. #define RT5659_SV_MASK (0x1 << 15)
  1586. #define RT5659_SV_SFT 15
  1587. #define RT5659_SV_DIS (0x0 << 15)
  1588. #define RT5659_SV_EN (0x1 << 15)
  1589. #define RT5659_OUT_SV_MASK (0x1 << 13)
  1590. #define RT5659_OUT_SV_SFT 13
  1591. #define RT5659_OUT_SV_DIS (0x0 << 13)
  1592. #define RT5659_OUT_SV_EN (0x1 << 13)
  1593. #define RT5659_HP_SV_MASK (0x1 << 12)
  1594. #define RT5659_HP_SV_SFT 12
  1595. #define RT5659_HP_SV_DIS (0x0 << 12)
  1596. #define RT5659_HP_SV_EN (0x1 << 12)
  1597. #define RT5659_ZCD_DIG_MASK (0x1 << 11)
  1598. #define RT5659_ZCD_DIG_SFT 11
  1599. #define RT5659_ZCD_DIG_DIS (0x0 << 11)
  1600. #define RT5659_ZCD_DIG_EN (0x1 << 11)
  1601. #define RT5659_ZCD_MASK (0x1 << 10)
  1602. #define RT5659_ZCD_SFT 10
  1603. #define RT5659_ZCD_PD (0x0 << 10)
  1604. #define RT5659_ZCD_PU (0x1 << 10)
  1605. #define RT5659_SV_DLY_MASK (0xf)
  1606. #define RT5659_SV_DLY_SFT 0
  1607. /* Soft volume and zero cross control 2 (0x00da) */
  1608. #define RT5659_ZCD_HP_MASK (0x1 << 15)
  1609. #define RT5659_ZCD_HP_SFT 15
  1610. #define RT5659_ZCD_HP_DIS (0x0 << 15)
  1611. #define RT5659_ZCD_HP_EN (0x1 << 15)
  1612. /* 4 Button Inline Command Control 2 (0x00e0) */
  1613. #define RT5659_4BTN_IL_MASK (0x1 << 15)
  1614. #define RT5659_4BTN_IL_EN (0x1 << 15)
  1615. #define RT5659_4BTN_IL_DIS (0x0 << 15)
  1616. /* Analog JD Control 1 (0x00f0) */
  1617. #define RT5659_JD1_MODE_MASK (0x3 << 0)
  1618. #define RT5659_JD1_MODE_0 (0x0 << 0)
  1619. #define RT5659_JD1_MODE_1 (0x1 << 0)
  1620. #define RT5659_JD1_MODE_2 (0x2 << 0)
  1621. /* Jack Detect Control 3 (0x00f8) */
  1622. #define RT5659_JD_TRI_HPO_SEL_MASK (0x7)
  1623. #define RT5659_JD_TRI_HPO_SEL_SFT (0)
  1624. #define RT5659_JD_HPO_GPIO_JD1 (0x0)
  1625. #define RT5659_JD_HPO_JD1_1 (0x1)
  1626. #define RT5659_JD_HPO_JD1_2 (0x2)
  1627. #define RT5659_JD_HPO_JD2 (0x3)
  1628. #define RT5659_JD_HPO_GPIO_JD2 (0x4)
  1629. #define RT5659_JD_HPO_JD3 (0x5)
  1630. #define RT5659_JD_HPO_JD_D (0x6)
  1631. /* Digital Misc Control (0x00fa) */
  1632. #define RT5659_AM_MASK (0x1 << 7)
  1633. #define RT5659_AM_EN (0x1 << 7)
  1634. #define RT5659_AM_DIS (0x1 << 7)
  1635. #define RT5659_DIG_GATE_CTRL 0x1
  1636. #define RT5659_DIG_GATE_CTRL_SFT (0)
  1637. /* Chopper and Clock control for ADC (0x011c)*/
  1638. #define RT5659_M_RF_DIG_MASK (0x1 << 12)
  1639. #define RT5659_M_RF_DIG_SFT 12
  1640. #define RT5659_M_RI_DIG (0x1 << 11)
  1641. /* Chopper and Clock control for DAC (0x013a)*/
  1642. #define RT5659_CKXEN_DAC1_MASK (0x1 << 13)
  1643. #define RT5659_CKXEN_DAC1_SFT 13
  1644. #define RT5659_CKGEN_DAC1_MASK (0x1 << 12)
  1645. #define RT5659_CKGEN_DAC1_SFT 12
  1646. #define RT5659_CKXEN_DAC2_MASK (0x1 << 5)
  1647. #define RT5659_CKXEN_DAC2_SFT 5
  1648. #define RT5659_CKGEN_DAC2_MASK (0x1 << 4)
  1649. #define RT5659_CKGEN_DAC2_SFT 4
  1650. /* Chopper and Clock control for ADC (0x013b)*/
  1651. #define RT5659_CKXEN_ADC1_MASK (0x1 << 13)
  1652. #define RT5659_CKXEN_ADC1_SFT 13
  1653. #define RT5659_CKGEN_ADC1_MASK (0x1 << 12)
  1654. #define RT5659_CKGEN_ADC1_SFT 12
  1655. #define RT5659_CKXEN_ADC2_MASK (0x1 << 5)
  1656. #define RT5659_CKXEN_ADC2_SFT 5
  1657. #define RT5659_CKGEN_ADC2_MASK (0x1 << 4)
  1658. #define RT5659_CKGEN_ADC2_SFT 4
  1659. /* Test Mode Control 1 (0x0145) */
  1660. #define RT5659_AD2DA_LB_MASK (0x1 << 9)
  1661. #define RT5659_AD2DA_LB_SFT 9
  1662. /* Stereo Noise Gate Control 1 (0x0160) */
  1663. #define RT5659_NG2_EN_MASK (0x1 << 15)
  1664. #define RT5659_NG2_EN (0x1 << 15)
  1665. #define RT5659_NG2_DIS (0x0 << 15)
  1666. /* System Clock Source */
  1667. enum {
  1668. RT5659_SCLK_S_MCLK,
  1669. RT5659_SCLK_S_PLL1,
  1670. RT5659_SCLK_S_RCCLK,
  1671. };
  1672. /* PLL1 Source */
  1673. enum {
  1674. RT5659_PLL1_S_MCLK,
  1675. RT5659_PLL1_S_BCLK1,
  1676. RT5659_PLL1_S_BCLK2,
  1677. RT5659_PLL1_S_BCLK3,
  1678. RT5659_PLL1_S_BCLK4,
  1679. };
  1680. enum {
  1681. RT5659_AIF1,
  1682. RT5659_AIF2,
  1683. RT5659_AIF3,
  1684. RT5659_AIF4,
  1685. RT5659_AIFS,
  1686. };
  1687. struct rt5659_pll_code {
  1688. bool m_bp;
  1689. int m_code;
  1690. int n_code;
  1691. int k_code;
  1692. };
  1693. struct rt5659_priv {
  1694. struct snd_soc_component *component;
  1695. struct rt5659_platform_data pdata;
  1696. struct regmap *regmap;
  1697. struct gpio_desc *gpiod_ldo1_en;
  1698. struct gpio_desc *gpiod_reset;
  1699. struct snd_soc_jack *hs_jack;
  1700. struct delayed_work jack_detect_work;
  1701. struct clk *mclk;
  1702. int sysclk;
  1703. int sysclk_src;
  1704. int lrck[RT5659_AIFS];
  1705. int bclk[RT5659_AIFS];
  1706. int master[RT5659_AIFS];
  1707. int v_id;
  1708. int pll_src;
  1709. int pll_in;
  1710. int pll_out;
  1711. int jack_type;
  1712. bool hda_hp_plugged;
  1713. bool hda_mic_plugged;
  1714. };
  1715. int rt5659_set_jack_detect(struct snd_soc_component *component,
  1716. struct snd_soc_jack *hs_jack);
  1717. #endif /* __RT5659_H__ */