rt5651.h 72 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5651.h -- RT5651 ALSA SoC audio driver
  4. *
  5. * Copyright 2011 Realtek Microelectronics
  6. * Author: Johnny Hsu <johnnyhsu@realtek.com>
  7. */
  8. #ifndef __RT5651_H__
  9. #define __RT5651_H__
  10. #include <dt-bindings/sound/rt5651.h>
  11. /* Info */
  12. #define RT5651_RESET 0x00
  13. #define RT5651_VERSION_ID 0xfd
  14. #define RT5651_VENDOR_ID 0xfe
  15. #define RT5651_DEVICE_ID 0xff
  16. /* I/O - Output */
  17. #define RT5651_HP_VOL 0x02
  18. #define RT5651_LOUT_CTRL1 0x03
  19. #define RT5651_LOUT_CTRL2 0x05
  20. /* I/O - Input */
  21. #define RT5651_IN1_IN2 0x0d
  22. #define RT5651_IN3 0x0e
  23. #define RT5651_INL1_INR1_VOL 0x0f
  24. #define RT5651_INL2_INR2_VOL 0x10
  25. /* I/O - ADC/DAC/DMIC */
  26. #define RT5651_DAC1_DIG_VOL 0x19
  27. #define RT5651_DAC2_DIG_VOL 0x1a
  28. #define RT5651_DAC2_CTRL 0x1b
  29. #define RT5651_ADC_DIG_VOL 0x1c
  30. #define RT5651_ADC_DATA 0x1d
  31. #define RT5651_ADC_BST_VOL 0x1e
  32. /* Mixer - D-D */
  33. #define RT5651_STO1_ADC_MIXER 0x27
  34. #define RT5651_STO2_ADC_MIXER 0x28
  35. #define RT5651_AD_DA_MIXER 0x29
  36. #define RT5651_STO_DAC_MIXER 0x2a
  37. #define RT5651_DD_MIXER 0x2b
  38. #define RT5651_DIG_INF_DATA 0x2f
  39. /* PDM */
  40. #define RT5651_PDM_CTL 0x30
  41. #define RT5651_PDM_I2C_CTL1 0x31
  42. #define RT5651_PDM_I2C_CTL2 0x32
  43. #define RT5651_PDM_I2C_DATA_W 0x33
  44. #define RT5651_PDM_I2C_DATA_R 0x34
  45. /* Mixer - ADC */
  46. #define RT5651_REC_L1_MIXER 0x3b
  47. #define RT5651_REC_L2_MIXER 0x3c
  48. #define RT5651_REC_R1_MIXER 0x3d
  49. #define RT5651_REC_R2_MIXER 0x3e
  50. /* Mixer - DAC */
  51. #define RT5651_HPO_MIXER 0x45
  52. #define RT5651_OUT_L1_MIXER 0x4d
  53. #define RT5651_OUT_L2_MIXER 0x4e
  54. #define RT5651_OUT_L3_MIXER 0x4f
  55. #define RT5651_OUT_R1_MIXER 0x50
  56. #define RT5651_OUT_R2_MIXER 0x51
  57. #define RT5651_OUT_R3_MIXER 0x52
  58. #define RT5651_LOUT_MIXER 0x53
  59. /* Power */
  60. #define RT5651_PWR_DIG1 0x61
  61. #define RT5651_PWR_DIG2 0x62
  62. #define RT5651_PWR_ANLG1 0x63
  63. #define RT5651_PWR_ANLG2 0x64
  64. #define RT5651_PWR_MIXER 0x65
  65. #define RT5651_PWR_VOL 0x66
  66. /* Private Register Control */
  67. #define RT5651_PRIV_INDEX 0x6a
  68. #define RT5651_PRIV_DATA 0x6c
  69. /* Format - ADC/DAC */
  70. #define RT5651_I2S1_SDP 0x70
  71. #define RT5651_I2S2_SDP 0x71
  72. #define RT5651_ADDA_CLK1 0x73
  73. #define RT5651_ADDA_CLK2 0x74
  74. #define RT5651_DMIC 0x75
  75. /* TDM Control */
  76. #define RT5651_TDM_CTL_1 0x77
  77. #define RT5651_TDM_CTL_2 0x78
  78. #define RT5651_TDM_CTL_3 0x79
  79. /* Function - Analog */
  80. #define RT5651_GLB_CLK 0x80
  81. #define RT5651_PLL_CTRL1 0x81
  82. #define RT5651_PLL_CTRL2 0x82
  83. #define RT5651_PLL_MODE_1 0x83
  84. #define RT5651_PLL_MODE_2 0x84
  85. #define RT5651_PLL_MODE_3 0x85
  86. #define RT5651_PLL_MODE_4 0x86
  87. #define RT5651_PLL_MODE_5 0x87
  88. #define RT5651_PLL_MODE_6 0x89
  89. #define RT5651_PLL_MODE_7 0x8a
  90. #define RT5651_DEPOP_M1 0x8e
  91. #define RT5651_DEPOP_M2 0x8f
  92. #define RT5651_DEPOP_M3 0x90
  93. #define RT5651_CHARGE_PUMP 0x91
  94. #define RT5651_MICBIAS 0x93
  95. #define RT5651_A_JD_CTL1 0x94
  96. /* Function - Digital */
  97. #define RT5651_EQ_CTRL1 0xb0
  98. #define RT5651_EQ_CTRL2 0xb1
  99. #define RT5651_ALC_1 0xb4
  100. #define RT5651_ALC_2 0xb5
  101. #define RT5651_ALC_3 0xb6
  102. #define RT5651_JD_CTRL1 0xbb
  103. #define RT5651_JD_CTRL2 0xbc
  104. #define RT5651_IRQ_CTRL1 0xbd
  105. #define RT5651_IRQ_CTRL2 0xbe
  106. #define RT5651_INT_IRQ_ST 0xbf
  107. #define RT5651_GPIO_CTRL1 0xc0
  108. #define RT5651_GPIO_CTRL2 0xc1
  109. #define RT5651_GPIO_CTRL3 0xc2
  110. #define RT5651_PGM_REG_ARR1 0xc8
  111. #define RT5651_PGM_REG_ARR2 0xc9
  112. #define RT5651_PGM_REG_ARR3 0xca
  113. #define RT5651_PGM_REG_ARR4 0xcb
  114. #define RT5651_PGM_REG_ARR5 0xcc
  115. #define RT5651_SCB_FUNC 0xcd
  116. #define RT5651_SCB_CTRL 0xce
  117. #define RT5651_BASE_BACK 0xcf
  118. #define RT5651_MP3_PLUS1 0xd0
  119. #define RT5651_MP3_PLUS2 0xd1
  120. #define RT5651_ADJ_HPF_CTRL1 0xd3
  121. #define RT5651_ADJ_HPF_CTRL2 0xd4
  122. #define RT5651_HP_CALIB_AMP_DET 0xd6
  123. #define RT5651_HP_CALIB2 0xd7
  124. #define RT5651_SV_ZCD1 0xd9
  125. #define RT5651_SV_ZCD2 0xda
  126. #define RT5651_D_MISC 0xfa
  127. /* Dummy Register */
  128. #define RT5651_DUMMY2 0xfb
  129. #define RT5651_DUMMY3 0xfc
  130. /* Index of Codec Private Register definition */
  131. #define RT5651_BIAS_CUR1 0x12
  132. #define RT5651_BIAS_CUR3 0x14
  133. #define RT5651_BIAS_CUR4 0x15
  134. #define RT5651_CLSD_INT_REG1 0x1c
  135. #define RT5651_CHPUMP_INT_REG1 0x24
  136. #define RT5651_MAMP_INT_REG2 0x37
  137. #define RT5651_CHOP_DAC_ADC 0x3d
  138. #define RT5651_3D_SPK 0x63
  139. #define RT5651_WND_1 0x6c
  140. #define RT5651_WND_2 0x6d
  141. #define RT5651_WND_3 0x6e
  142. #define RT5651_WND_4 0x6f
  143. #define RT5651_WND_5 0x70
  144. #define RT5651_WND_8 0x73
  145. #define RT5651_DIP_SPK_INF 0x75
  146. #define RT5651_HP_DCC_INT1 0x77
  147. #define RT5651_EQ_BW_LOP 0xa0
  148. #define RT5651_EQ_GN_LOP 0xa1
  149. #define RT5651_EQ_FC_BP1 0xa2
  150. #define RT5651_EQ_BW_BP1 0xa3
  151. #define RT5651_EQ_GN_BP1 0xa4
  152. #define RT5651_EQ_FC_BP2 0xa5
  153. #define RT5651_EQ_BW_BP2 0xa6
  154. #define RT5651_EQ_GN_BP2 0xa7
  155. #define RT5651_EQ_FC_BP3 0xa8
  156. #define RT5651_EQ_BW_BP3 0xa9
  157. #define RT5651_EQ_GN_BP3 0xaa
  158. #define RT5651_EQ_FC_BP4 0xab
  159. #define RT5651_EQ_BW_BP4 0xac
  160. #define RT5651_EQ_GN_BP4 0xad
  161. #define RT5651_EQ_FC_HIP1 0xae
  162. #define RT5651_EQ_GN_HIP1 0xaf
  163. #define RT5651_EQ_FC_HIP2 0xb0
  164. #define RT5651_EQ_BW_HIP2 0xb1
  165. #define RT5651_EQ_GN_HIP2 0xb2
  166. #define RT5651_EQ_PRE_VOL 0xb3
  167. #define RT5651_EQ_PST_VOL 0xb4
  168. /* global definition */
  169. #define RT5651_L_MUTE (0x1 << 15)
  170. #define RT5651_L_MUTE_SFT 15
  171. #define RT5651_VOL_L_MUTE (0x1 << 14)
  172. #define RT5651_VOL_L_SFT 14
  173. #define RT5651_R_MUTE (0x1 << 7)
  174. #define RT5651_R_MUTE_SFT 7
  175. #define RT5651_VOL_R_MUTE (0x1 << 6)
  176. #define RT5651_VOL_R_SFT 6
  177. #define RT5651_L_VOL_MASK (0x3f << 8)
  178. #define RT5651_L_VOL_SFT 8
  179. #define RT5651_R_VOL_MASK (0x3f)
  180. #define RT5651_R_VOL_SFT 0
  181. /* LOUT Control 2(0x05) */
  182. #define RT5651_EN_DFO (0x1 << 15)
  183. /* IN1 and IN2 Control (0x0d) */
  184. /* IN3 and IN4 Control (0x0e) */
  185. #define RT5651_BST_MASK1 (0xf<<12)
  186. #define RT5651_BST_SFT1 12
  187. #define RT5651_BST_MASK2 (0xf<<8)
  188. #define RT5651_BST_SFT2 8
  189. #define RT5651_IN_DF1 (0x1 << 7)
  190. #define RT5651_IN_SFT1 7
  191. #define RT5651_IN_DF2 (0x1 << 6)
  192. #define RT5651_IN_SFT2 6
  193. /* INL1 and INR1 Volume Control (0x0f) */
  194. /* INL2 and INR2 Volume Control (0x10) */
  195. #define RT5651_INL_SEL_MASK (0x1 << 15)
  196. #define RT5651_INL_SEL_SFT 15
  197. #define RT5651_INL_SEL_IN4P (0x0 << 15)
  198. #define RT5651_INL_SEL_MONOP (0x1 << 15)
  199. #define RT5651_INL_VOL_MASK (0x1f << 8)
  200. #define RT5651_INL_VOL_SFT 8
  201. #define RT5651_INR_SEL_MASK (0x1 << 7)
  202. #define RT5651_INR_SEL_SFT 7
  203. #define RT5651_INR_SEL_IN4N (0x0 << 7)
  204. #define RT5651_INR_SEL_MONON (0x1 << 7)
  205. #define RT5651_INR_VOL_MASK (0x1f)
  206. #define RT5651_INR_VOL_SFT 0
  207. /* DAC1 Digital Volume (0x19) */
  208. #define RT5651_DAC_L1_VOL_MASK (0xff << 8)
  209. #define RT5651_DAC_L1_VOL_SFT 8
  210. #define RT5651_DAC_R1_VOL_MASK (0xff)
  211. #define RT5651_DAC_R1_VOL_SFT 0
  212. /* DAC2 Digital Volume (0x1a) */
  213. #define RT5651_DAC_L2_VOL_MASK (0xff << 8)
  214. #define RT5651_DAC_L2_VOL_SFT 8
  215. #define RT5651_DAC_R2_VOL_MASK (0xff)
  216. #define RT5651_DAC_R2_VOL_SFT 0
  217. /* DAC2 Control (0x1b) */
  218. #define RT5651_M_DAC_L2_VOL (0x1 << 13)
  219. #define RT5651_M_DAC_L2_VOL_SFT 13
  220. #define RT5651_M_DAC_R2_VOL (0x1 << 12)
  221. #define RT5651_M_DAC_R2_VOL_SFT 12
  222. #define RT5651_SEL_DAC_L2 (0x1 << 11)
  223. #define RT5651_IF2_DAC_L2 (0x1 << 11)
  224. #define RT5651_IF1_DAC_L2 (0x0 << 11)
  225. #define RT5651_SEL_DAC_L2_SFT 11
  226. #define RT5651_SEL_DAC_R2 (0x1 << 10)
  227. #define RT5651_IF2_DAC_R2 (0x1 << 11)
  228. #define RT5651_IF1_DAC_R2 (0x0 << 11)
  229. #define RT5651_SEL_DAC_R2_SFT 10
  230. /* ADC Digital Volume Control (0x1c) */
  231. #define RT5651_ADC_L_VOL_MASK (0x7f << 8)
  232. #define RT5651_ADC_L_VOL_SFT 8
  233. #define RT5651_ADC_R_VOL_MASK (0x7f)
  234. #define RT5651_ADC_R_VOL_SFT 0
  235. /* Mono ADC Digital Volume Control (0x1d) */
  236. #define RT5651_M_MONO_ADC_L (0x1 << 15)
  237. #define RT5651_M_MONO_ADC_L_SFT 15
  238. #define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
  239. #define RT5651_MONO_ADC_L_VOL_SFT 8
  240. #define RT5651_M_MONO_ADC_R (0x1 << 7)
  241. #define RT5651_M_MONO_ADC_R_SFT 7
  242. #define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
  243. #define RT5651_MONO_ADC_R_VOL_SFT 0
  244. /* ADC Boost Volume Control (0x1e) */
  245. #define RT5651_ADC_L_BST_MASK (0x3 << 14)
  246. #define RT5651_ADC_L_BST_SFT 14
  247. #define RT5651_ADC_R_BST_MASK (0x3 << 12)
  248. #define RT5651_ADC_R_BST_SFT 12
  249. #define RT5651_ADC_COMP_MASK (0x3 << 10)
  250. #define RT5651_ADC_COMP_SFT 10
  251. /* Stereo ADC1 Mixer Control (0x27) */
  252. #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
  253. #define RT5651_M_STO1_ADC_L1_SFT 14
  254. #define RT5651_M_STO1_ADC_L2 (0x1 << 13)
  255. #define RT5651_M_STO1_ADC_L2_SFT 13
  256. #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
  257. #define RT5651_STO1_ADC_1_SRC_SFT 12
  258. #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
  259. #define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
  260. #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
  261. #define RT5651_STO1_ADC_2_SRC_SFT 11
  262. #define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
  263. #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
  264. #define RT5651_M_STO1_ADC_R1 (0x1 << 6)
  265. #define RT5651_M_STO1_ADC_R1_SFT 6
  266. #define RT5651_M_STO1_ADC_R2 (0x1 << 5)
  267. #define RT5651_M_STO1_ADC_R2_SFT 5
  268. /* Stereo ADC2 Mixer Control (0x28) */
  269. #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
  270. #define RT5651_M_STO2_ADC_L1_SFT 14
  271. #define RT5651_M_STO2_ADC_L2 (0x1 << 13)
  272. #define RT5651_M_STO2_ADC_L2_SFT 13
  273. #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
  274. #define RT5651_STO2_ADC_L1_SRC_SFT 12
  275. #define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
  276. #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
  277. #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
  278. #define RT5651_STO2_ADC_L2_SRC_SFT 11
  279. #define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
  280. #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
  281. #define RT5651_M_STO2_ADC_R1 (0x1 << 6)
  282. #define RT5651_M_STO2_ADC_R1_SFT 6
  283. #define RT5651_M_STO2_ADC_R2 (0x1 << 5)
  284. #define RT5651_M_STO2_ADC_R2_SFT 5
  285. #define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
  286. #define RT5651_STO2_ADC_R1_SRC_SFT 4
  287. #define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
  288. #define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
  289. #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
  290. #define RT5651_STO2_ADC_R2_SRC_SFT 3
  291. #define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
  292. #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
  293. /* ADC Mixer to DAC Mixer Control (0x29) */
  294. #define RT5651_M_ADCMIX_L (0x1 << 15)
  295. #define RT5651_M_ADCMIX_L_SFT 15
  296. #define RT5651_M_IF1_DAC_L (0x1 << 14)
  297. #define RT5651_M_IF1_DAC_L_SFT 14
  298. #define RT5651_M_ADCMIX_R (0x1 << 7)
  299. #define RT5651_M_ADCMIX_R_SFT 7
  300. #define RT5651_M_IF1_DAC_R (0x1 << 6)
  301. #define RT5651_M_IF1_DAC_R_SFT 6
  302. /* Stereo DAC Mixer Control (0x2a) */
  303. #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
  304. #define RT5651_M_DAC_L1_MIXL_SFT 14
  305. #define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
  306. #define RT5651_DAC_L1_STO_L_VOL_SFT 13
  307. #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
  308. #define RT5651_M_DAC_L2_MIXL_SFT 12
  309. #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
  310. #define RT5651_DAC_L2_STO_L_VOL_SFT 11
  311. #define RT5651_M_DAC_R1_MIXL (0x1 << 9)
  312. #define RT5651_M_DAC_R1_MIXL_SFT 9
  313. #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
  314. #define RT5651_DAC_R1_STO_L_VOL_SFT 8
  315. #define RT5651_M_DAC_R1_MIXR (0x1 << 6)
  316. #define RT5651_M_DAC_R1_MIXR_SFT 6
  317. #define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
  318. #define RT5651_DAC_R1_STO_R_VOL_SFT 5
  319. #define RT5651_M_DAC_R2_MIXR (0x1 << 4)
  320. #define RT5651_M_DAC_R2_MIXR_SFT 4
  321. #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
  322. #define RT5651_DAC_R2_STO_R_VOL_SFT 3
  323. #define RT5651_M_DAC_L1_MIXR (0x1 << 1)
  324. #define RT5651_M_DAC_L1_MIXR_SFT 1
  325. #define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
  326. #define RT5651_DAC_L1_STO_R_VOL_SFT 0
  327. /* DD Mixer Control (0x2b) */
  328. #define RT5651_M_STO_DD_L1 (0x1 << 14)
  329. #define RT5651_M_STO_DD_L1_SFT 14
  330. #define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
  331. #define RT5651_DAC_DD_L1_VOL_SFT 13
  332. #define RT5651_M_STO_DD_L2 (0x1 << 12)
  333. #define RT5651_M_STO_DD_L2_SFT 12
  334. #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
  335. #define RT5651_STO_DD_L2_VOL_SFT 11
  336. #define RT5651_M_STO_DD_R2_L (0x1 << 10)
  337. #define RT5651_M_STO_DD_R2_L_SFT 10
  338. #define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
  339. #define RT5651_STO_DD_R2_L_VOL_SFT 9
  340. #define RT5651_M_STO_DD_R1 (0x1 << 6)
  341. #define RT5651_M_STO_DD_R1_SFT 6
  342. #define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
  343. #define RT5651_STO_DD_R1_VOL_SFT 5
  344. #define RT5651_M_STO_DD_R2 (0x1 << 4)
  345. #define RT5651_M_STO_DD_R2_SFT 4
  346. #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
  347. #define RT5651_STO_DD_R2_VOL_SFT 3
  348. #define RT5651_M_STO_DD_L2_R (0x1 << 2)
  349. #define RT5651_M_STO_DD_L2_R_SFT 2
  350. #define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
  351. #define RT5651_STO_DD_L2_R_VOL_SFT 1
  352. /* Digital Mixer Control (0x2c) */
  353. #define RT5651_M_STO_L_DAC_L (0x1 << 15)
  354. #define RT5651_M_STO_L_DAC_L_SFT 15
  355. #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
  356. #define RT5651_STO_L_DAC_L_VOL_SFT 14
  357. #define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
  358. #define RT5651_M_DAC_L2_DAC_L_SFT 13
  359. #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
  360. #define RT5651_DAC_L2_DAC_L_VOL_SFT 12
  361. #define RT5651_M_STO_R_DAC_R (0x1 << 11)
  362. #define RT5651_M_STO_R_DAC_R_SFT 11
  363. #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
  364. #define RT5651_STO_R_DAC_R_VOL_SFT 10
  365. #define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
  366. #define RT5651_M_DAC_R2_DAC_R_SFT 9
  367. #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
  368. #define RT5651_DAC_R2_DAC_R_VOL_SFT 8
  369. /* DSP Path Control 1 (0x2d) */
  370. #define RT5651_RXDP_SRC_MASK (0x1 << 15)
  371. #define RT5651_RXDP_SRC_SFT 15
  372. #define RT5651_RXDP_SRC_NOR (0x0 << 15)
  373. #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
  374. #define RT5651_TXDP_SRC_MASK (0x1 << 14)
  375. #define RT5651_TXDP_SRC_SFT 14
  376. #define RT5651_TXDP_SRC_NOR (0x0 << 14)
  377. #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
  378. /* DSP Path Control 2 (0x2e) */
  379. #define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
  380. #define RT5651_DAC_L2_SEL_SFT 14
  381. #define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
  382. #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
  383. #define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
  384. #define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
  385. #define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
  386. #define RT5651_DAC_R2_SEL_SFT 12
  387. #define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
  388. #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
  389. #define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
  390. #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
  391. #define RT5651_IF2_ADC_L_SEL_SFT 11
  392. #define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
  393. #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
  394. #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
  395. #define RT5651_IF2_ADC_R_SEL_SFT 10
  396. #define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
  397. #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
  398. #define RT5651_RXDC_SEL_MASK (0x3 << 8)
  399. #define RT5651_RXDC_SEL_SFT 8
  400. #define RT5651_RXDC_SEL_NOR (0x0 << 8)
  401. #define RT5651_RXDC_SEL_L2R (0x1 << 8)
  402. #define RT5651_RXDC_SEL_R2L (0x2 << 8)
  403. #define RT5651_RXDC_SEL_SWAP (0x3 << 8)
  404. #define RT5651_RXDP_SEL_MASK (0x3 << 6)
  405. #define RT5651_RXDP_SEL_SFT 6
  406. #define RT5651_RXDP_SEL_NOR (0x0 << 6)
  407. #define RT5651_RXDP_SEL_L2R (0x1 << 6)
  408. #define RT5651_RXDP_SEL_R2L (0x2 << 6)
  409. #define RT5651_RXDP_SEL_SWAP (0x3 << 6)
  410. #define RT5651_TXDC_SEL_MASK (0x3 << 4)
  411. #define RT5651_TXDC_SEL_SFT 4
  412. #define RT5651_TXDC_SEL_NOR (0x0 << 4)
  413. #define RT5651_TXDC_SEL_L2R (0x1 << 4)
  414. #define RT5651_TXDC_SEL_R2L (0x2 << 4)
  415. #define RT5651_TXDC_SEL_SWAP (0x3 << 4)
  416. #define RT5651_TXDP_SEL_MASK (0x3 << 2)
  417. #define RT5651_TXDP_SEL_SFT 2
  418. #define RT5651_TXDP_SEL_NOR (0x0 << 2)
  419. #define RT5651_TXDP_SEL_L2R (0x1 << 2)
  420. #define RT5651_TXDP_SEL_R2L (0x2 << 2)
  421. #define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
  422. /* Digital Interface Data Control (0x2f) */
  423. #define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
  424. #define RT5651_IF2_DAC_SEL_SFT 10
  425. #define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
  426. #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
  427. #define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
  428. #define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
  429. #define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
  430. #define RT5651_IF2_ADC_SEL_SFT 8
  431. #define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
  432. #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
  433. #define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
  434. #define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
  435. #define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
  436. #define RT5651_IF2_ADC_SRC_SFT 7
  437. #define RT5651_IF1_ADC1 (0x0 << 7)
  438. #define RT5651_IF1_ADC2 (0x1 << 7)
  439. /* PDM Output Control (0x30) */
  440. #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
  441. #define RT5651_PDM_L_SEL_SFT 15
  442. #define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
  443. #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
  444. #define RT5651_M_PDM_L (0x1 << 14)
  445. #define RT5651_M_PDM_L_SFT 14
  446. #define RT5651_PDM_R_SEL_MASK (0x1 << 13)
  447. #define RT5651_PDM_R_SEL_SFT 13
  448. #define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
  449. #define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
  450. #define RT5651_M_PDM_R (0x1 << 12)
  451. #define RT5651_M_PDM_R_SFT 12
  452. #define RT5651_PDM_BUSY (0x1 << 6)
  453. #define RT5651_PDM_BUSY_SFT 6
  454. #define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
  455. #define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
  456. #define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
  457. #define RT5651_PDM_VOL_MASK (0x1 << 4)
  458. #define RT5651_PDM_VOL_SFT 4
  459. #define RT5651_PDM_DIV_MASK (0x3)
  460. #define RT5651_PDM_DIV_SFT 0
  461. #define RT5651_PDM_DIV_1 0
  462. #define RT5651_PDM_DIV_2 1
  463. #define RT5651_PDM_DIV_3 2
  464. #define RT5651_PDM_DIV_4 3
  465. /* PDM I2C/Data Control 1 (0x31) */
  466. #define RT5651_PDM_I2C_ID_MASK (0xf << 12)
  467. #define PT5631_PDM_CMD_EXE (0x1 << 11)
  468. #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
  469. #define RT5651_PDM_I2C_CMD_R (0x0 << 10)
  470. #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
  471. #define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
  472. #define RT5651_PDM_I2C_NORMAL (0x0 << 8)
  473. #define RT5651_PDM_I2C_BUSY (0x1 << 8)
  474. /* PDM I2C/Data Control 2 (0x32) */
  475. #define RT5651_PDM_I2C_ADDR (0xff << 8)
  476. #define RT5651_PDM_I2C_CMD_PATTERN (0xff)
  477. /* REC Left Mixer Control 1 (0x3b) */
  478. #define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
  479. #define RT5651_G_IN_L2_RM_L_SFT 13
  480. #define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
  481. #define RT5651_G_IN_L1_RM_L_SFT 10
  482. #define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
  483. #define RT5651_G_BST3_RM_L_SFT 4
  484. #define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
  485. #define RT5651_G_BST2_RM_L_SFT 1
  486. /* REC Left Mixer Control 2 (0x3c) */
  487. #define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
  488. #define RT5651_G_BST1_RM_L_SFT 13
  489. #define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
  490. #define RT5651_G_OM_L_RM_L_SFT 10
  491. #define RT5651_M_IN2_L_RM_L (0x1 << 6)
  492. #define RT5651_M_IN2_L_RM_L_SFT 6
  493. #define RT5651_M_IN1_L_RM_L (0x1 << 5)
  494. #define RT5651_M_IN1_L_RM_L_SFT 5
  495. #define RT5651_M_BST3_RM_L (0x1 << 3)
  496. #define RT5651_M_BST3_RM_L_SFT 3
  497. #define RT5651_M_BST2_RM_L (0x1 << 2)
  498. #define RT5651_M_BST2_RM_L_SFT 2
  499. #define RT5651_M_BST1_RM_L (0x1 << 1)
  500. #define RT5651_M_BST1_RM_L_SFT 1
  501. #define RT5651_M_OM_L_RM_L (0x1)
  502. #define RT5651_M_OM_L_RM_L_SFT 0
  503. /* REC Right Mixer Control 1 (0x3d) */
  504. #define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
  505. #define RT5651_G_IN2_R_RM_R_SFT 13
  506. #define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
  507. #define RT5651_G_IN1_R_RM_R_SFT 10
  508. #define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
  509. #define RT5651_G_BST3_RM_R_SFT 4
  510. #define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
  511. #define RT5651_G_BST2_RM_R_SFT 1
  512. /* REC Right Mixer Control 2 (0x3e) */
  513. #define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
  514. #define RT5651_G_BST1_RM_R_SFT 13
  515. #define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
  516. #define RT5651_G_OM_R_RM_R_SFT 10
  517. #define RT5651_M_IN2_R_RM_R (0x1 << 6)
  518. #define RT5651_M_IN2_R_RM_R_SFT 6
  519. #define RT5651_M_IN1_R_RM_R (0x1 << 5)
  520. #define RT5651_M_IN1_R_RM_R_SFT 5
  521. #define RT5651_M_BST3_RM_R (0x1 << 3)
  522. #define RT5651_M_BST3_RM_R_SFT 3
  523. #define RT5651_M_BST2_RM_R (0x1 << 2)
  524. #define RT5651_M_BST2_RM_R_SFT 2
  525. #define RT5651_M_BST1_RM_R (0x1 << 1)
  526. #define RT5651_M_BST1_RM_R_SFT 1
  527. #define RT5651_M_OM_R_RM_R (0x1)
  528. #define RT5651_M_OM_R_RM_R_SFT 0
  529. /* HPMIX Control (0x45) */
  530. #define RT5651_M_DAC1_HM (0x1 << 14)
  531. #define RT5651_M_DAC1_HM_SFT 14
  532. #define RT5651_M_HPVOL_HM (0x1 << 13)
  533. #define RT5651_M_HPVOL_HM_SFT 13
  534. #define RT5651_G_HPOMIX_MASK (0x1 << 12)
  535. #define RT5651_G_HPOMIX_SFT 12
  536. /* SPK Left Mixer Control (0x46) */
  537. #define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
  538. #define RT5651_G_RM_L_SM_L_SFT 14
  539. #define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
  540. #define RT5651_G_IN_L_SM_L_SFT 12
  541. #define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
  542. #define RT5651_G_DAC_L1_SM_L_SFT 10
  543. #define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
  544. #define RT5651_G_DAC_L2_SM_L_SFT 8
  545. #define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
  546. #define RT5651_G_OM_L_SM_L_SFT 6
  547. #define RT5651_M_RM_L_SM_L (0x1 << 5)
  548. #define RT5651_M_RM_L_SM_L_SFT 5
  549. #define RT5651_M_IN_L_SM_L (0x1 << 4)
  550. #define RT5651_M_IN_L_SM_L_SFT 4
  551. #define RT5651_M_DAC_L1_SM_L (0x1 << 3)
  552. #define RT5651_M_DAC_L1_SM_L_SFT 3
  553. #define RT5651_M_DAC_L2_SM_L (0x1 << 2)
  554. #define RT5651_M_DAC_L2_SM_L_SFT 2
  555. #define RT5651_M_OM_L_SM_L (0x1 << 1)
  556. #define RT5651_M_OM_L_SM_L_SFT 1
  557. /* SPK Right Mixer Control (0x47) */
  558. #define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
  559. #define RT5651_G_RM_R_SM_R_SFT 14
  560. #define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
  561. #define RT5651_G_IN_R_SM_R_SFT 12
  562. #define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
  563. #define RT5651_G_DAC_R1_SM_R_SFT 10
  564. #define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
  565. #define RT5651_G_DAC_R2_SM_R_SFT 8
  566. #define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
  567. #define RT5651_G_OM_R_SM_R_SFT 6
  568. #define RT5651_M_RM_R_SM_R (0x1 << 5)
  569. #define RT5651_M_RM_R_SM_R_SFT 5
  570. #define RT5651_M_IN_R_SM_R (0x1 << 4)
  571. #define RT5651_M_IN_R_SM_R_SFT 4
  572. #define RT5651_M_DAC_R1_SM_R (0x1 << 3)
  573. #define RT5651_M_DAC_R1_SM_R_SFT 3
  574. #define RT5651_M_DAC_R2_SM_R (0x1 << 2)
  575. #define RT5651_M_DAC_R2_SM_R_SFT 2
  576. #define RT5651_M_OM_R_SM_R (0x1 << 1)
  577. #define RT5651_M_OM_R_SM_R_SFT 1
  578. /* SPOLMIX Control (0x48) */
  579. #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
  580. #define RT5651_M_DAC_R1_SPM_L_SFT 15
  581. #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
  582. #define RT5651_M_DAC_L1_SPM_L_SFT 14
  583. #define RT5651_M_SV_R_SPM_L (0x1 << 13)
  584. #define RT5651_M_SV_R_SPM_L_SFT 13
  585. #define RT5651_M_SV_L_SPM_L (0x1 << 12)
  586. #define RT5651_M_SV_L_SPM_L_SFT 12
  587. #define RT5651_M_BST1_SPM_L (0x1 << 11)
  588. #define RT5651_M_BST1_SPM_L_SFT 11
  589. /* SPORMIX Control (0x49) */
  590. #define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
  591. #define RT5651_M_DAC_R1_SPM_R_SFT 13
  592. #define RT5651_M_SV_R_SPM_R (0x1 << 12)
  593. #define RT5651_M_SV_R_SPM_R_SFT 12
  594. #define RT5651_M_BST1_SPM_R (0x1 << 11)
  595. #define RT5651_M_BST1_SPM_R_SFT 11
  596. /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
  597. #define RT5651_SPO_CLSD_RATIO_MASK (0x7)
  598. #define RT5651_SPO_CLSD_RATIO_SFT 0
  599. /* Mono Output Mixer Control (0x4c) */
  600. #define RT5651_M_DAC_R2_MM (0x1 << 15)
  601. #define RT5651_M_DAC_R2_MM_SFT 15
  602. #define RT5651_M_DAC_L2_MM (0x1 << 14)
  603. #define RT5651_M_DAC_L2_MM_SFT 14
  604. #define RT5651_M_OV_R_MM (0x1 << 13)
  605. #define RT5651_M_OV_R_MM_SFT 13
  606. #define RT5651_M_OV_L_MM (0x1 << 12)
  607. #define RT5651_M_OV_L_MM_SFT 12
  608. #define RT5651_M_BST1_MM (0x1 << 11)
  609. #define RT5651_M_BST1_MM_SFT 11
  610. #define RT5651_G_MONOMIX_MASK (0x1 << 10)
  611. #define RT5651_G_MONOMIX_SFT 10
  612. /* Output Left Mixer Control 1 (0x4d) */
  613. #define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
  614. #define RT5651_G_BST2_OM_L_SFT 10
  615. #define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
  616. #define RT5651_G_BST1_OM_L_SFT 7
  617. #define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
  618. #define RT5651_G_IN1_L_OM_L_SFT 4
  619. #define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
  620. #define RT5651_G_RM_L_OM_L_SFT 1
  621. /* Output Left Mixer Control 2 (0x4e) */
  622. #define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
  623. #define RT5651_G_DAC_L1_OM_L_SFT 7
  624. #define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
  625. #define RT5651_G_IN2_L_OM_L_SFT 4
  626. /* Output Left Mixer Control 3 (0x4f) */
  627. #define RT5651_M_IN2_L_OM_L (0x1 << 9)
  628. #define RT5651_M_IN2_L_OM_L_SFT 9
  629. #define RT5651_M_BST2_OM_L (0x1 << 6)
  630. #define RT5651_M_BST2_OM_L_SFT 6
  631. #define RT5651_M_BST1_OM_L (0x1 << 5)
  632. #define RT5651_M_BST1_OM_L_SFT 5
  633. #define RT5651_M_IN1_L_OM_L (0x1 << 4)
  634. #define RT5651_M_IN1_L_OM_L_SFT 4
  635. #define RT5651_M_RM_L_OM_L (0x1 << 3)
  636. #define RT5651_M_RM_L_OM_L_SFT 3
  637. #define RT5651_M_DAC_L1_OM_L (0x1)
  638. #define RT5651_M_DAC_L1_OM_L_SFT 0
  639. /* Output Right Mixer Control 1 (0x50) */
  640. #define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
  641. #define RT5651_G_BST2_OM_R_SFT 10
  642. #define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
  643. #define RT5651_G_BST1_OM_R_SFT 7
  644. #define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
  645. #define RT5651_G_IN1_R_OM_R_SFT 4
  646. #define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
  647. #define RT5651_G_RM_R_OM_R_SFT 1
  648. /* Output Right Mixer Control 2 (0x51) */
  649. #define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
  650. #define RT5651_G_DAC_R1_OM_R_SFT 7
  651. #define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
  652. #define RT5651_G_IN2_R_OM_R_SFT 4
  653. /* Output Right Mixer Control 3 (0x52) */
  654. #define RT5651_M_IN2_R_OM_R (0x1 << 9)
  655. #define RT5651_M_IN2_R_OM_R_SFT 9
  656. #define RT5651_M_BST2_OM_R (0x1 << 6)
  657. #define RT5651_M_BST2_OM_R_SFT 6
  658. #define RT5651_M_BST1_OM_R (0x1 << 5)
  659. #define RT5651_M_BST1_OM_R_SFT 5
  660. #define RT5651_M_IN1_R_OM_R (0x1 << 4)
  661. #define RT5651_M_IN1_R_OM_R_SFT 4
  662. #define RT5651_M_RM_R_OM_R (0x1 << 3)
  663. #define RT5651_M_RM_R_OM_R_SFT 3
  664. #define RT5651_M_DAC_R1_OM_R (0x1)
  665. #define RT5651_M_DAC_R1_OM_R_SFT 0
  666. /* LOUT Mixer Control (0x53) */
  667. #define RT5651_M_DAC_L1_LM (0x1 << 15)
  668. #define RT5651_M_DAC_L1_LM_SFT 15
  669. #define RT5651_M_DAC_R1_LM (0x1 << 14)
  670. #define RT5651_M_DAC_R1_LM_SFT 14
  671. #define RT5651_M_OV_L_LM (0x1 << 13)
  672. #define RT5651_M_OV_L_LM_SFT 13
  673. #define RT5651_M_OV_R_LM (0x1 << 12)
  674. #define RT5651_M_OV_R_LM_SFT 12
  675. #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
  676. #define RT5651_G_LOUTMIX_SFT 11
  677. /* Power Management for Digital 1 (0x61) */
  678. #define RT5651_PWR_I2S1 (0x1 << 15)
  679. #define RT5651_PWR_I2S1_BIT 15
  680. #define RT5651_PWR_I2S2 (0x1 << 14)
  681. #define RT5651_PWR_I2S2_BIT 14
  682. #define RT5651_PWR_DAC_L1 (0x1 << 12)
  683. #define RT5651_PWR_DAC_L1_BIT 12
  684. #define RT5651_PWR_DAC_R1 (0x1 << 11)
  685. #define RT5651_PWR_DAC_R1_BIT 11
  686. #define RT5651_PWR_ADC_L (0x1 << 2)
  687. #define RT5651_PWR_ADC_L_BIT 2
  688. #define RT5651_PWR_ADC_R (0x1 << 1)
  689. #define RT5651_PWR_ADC_R_BIT 1
  690. /* Power Management for Digital 2 (0x62) */
  691. #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
  692. #define RT5651_PWR_ADC_STO1_F_BIT 15
  693. #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
  694. #define RT5651_PWR_ADC_STO2_F_BIT 14
  695. #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
  696. #define RT5651_PWR_DAC_STO1_F_BIT 11
  697. #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
  698. #define RT5651_PWR_DAC_STO2_F_BIT 10
  699. #define RT5651_PWR_PDM (0x1 << 9)
  700. #define RT5651_PWR_PDM_BIT 9
  701. /* Power Management for Analog 1 (0x63) */
  702. #define RT5651_PWR_VREF1 (0x1 << 15)
  703. #define RT5651_PWR_VREF1_BIT 15
  704. #define RT5651_PWR_FV1 (0x1 << 14)
  705. #define RT5651_PWR_FV1_BIT 14
  706. #define RT5651_PWR_MB (0x1 << 13)
  707. #define RT5651_PWR_MB_BIT 13
  708. #define RT5651_PWR_LM (0x1 << 12)
  709. #define RT5651_PWR_LM_BIT 12
  710. #define RT5651_PWR_BG (0x1 << 11)
  711. #define RT5651_PWR_BG_BIT 11
  712. #define RT5651_PWR_HP_L (0x1 << 7)
  713. #define RT5651_PWR_HP_L_BIT 7
  714. #define RT5651_PWR_HP_R (0x1 << 6)
  715. #define RT5651_PWR_HP_R_BIT 6
  716. #define RT5651_PWR_HA (0x1 << 5)
  717. #define RT5651_PWR_HA_BIT 5
  718. #define RT5651_PWR_VREF2 (0x1 << 4)
  719. #define RT5651_PWR_VREF2_BIT 4
  720. #define RT5651_PWR_FV2 (0x1 << 3)
  721. #define RT5651_PWR_FV2_BIT 3
  722. #define RT5651_PWR_LDO (0x1 << 2)
  723. #define RT5651_PWR_LDO_BIT 2
  724. #define RT5651_PWR_LDO_DVO_MASK (0x3)
  725. #define RT5651_PWR_LDO_DVO_1_0V 0
  726. #define RT5651_PWR_LDO_DVO_1_1V 1
  727. #define RT5651_PWR_LDO_DVO_1_2V 2
  728. #define RT5651_PWR_LDO_DVO_1_3V 3
  729. /* Power Management for Analog 2 (0x64) */
  730. #define RT5651_PWR_BST1 (0x1 << 15)
  731. #define RT5651_PWR_BST1_BIT 15
  732. #define RT5651_PWR_BST2 (0x1 << 14)
  733. #define RT5651_PWR_BST2_BIT 14
  734. #define RT5651_PWR_BST3 (0x1 << 13)
  735. #define RT5651_PWR_BST3_BIT 13
  736. #define RT5651_PWR_MB1 (0x1 << 11)
  737. #define RT5651_PWR_MB1_BIT 11
  738. #define RT5651_PWR_PLL (0x1 << 9)
  739. #define RT5651_PWR_PLL_BIT 9
  740. #define RT5651_PWR_BST1_OP2 (0x1 << 5)
  741. #define RT5651_PWR_BST1_OP2_BIT 5
  742. #define RT5651_PWR_BST2_OP2 (0x1 << 4)
  743. #define RT5651_PWR_BST2_OP2_BIT 4
  744. #define RT5651_PWR_BST3_OP2 (0x1 << 3)
  745. #define RT5651_PWR_BST3_OP2_BIT 3
  746. #define RT5651_PWR_JD_M (0x1 << 2)
  747. #define RT5651_PWM_JD_M_BIT 2
  748. #define RT5651_PWR_JD2 (0x1 << 1)
  749. #define RT5651_PWM_JD2_BIT 1
  750. #define RT5651_PWR_JD3 (0x1)
  751. #define RT5651_PWM_JD3_BIT 0
  752. /* Power Management for Mixer (0x65) */
  753. #define RT5651_PWR_OM_L (0x1 << 15)
  754. #define RT5651_PWR_OM_L_BIT 15
  755. #define RT5651_PWR_OM_R (0x1 << 14)
  756. #define RT5651_PWR_OM_R_BIT 14
  757. #define RT5651_PWR_RM_L (0x1 << 11)
  758. #define RT5651_PWR_RM_L_BIT 11
  759. #define RT5651_PWR_RM_R (0x1 << 10)
  760. #define RT5651_PWR_RM_R_BIT 10
  761. /* Power Management for Volume (0x66) */
  762. #define RT5651_PWR_OV_L (0x1 << 13)
  763. #define RT5651_PWR_OV_L_BIT 13
  764. #define RT5651_PWR_OV_R (0x1 << 12)
  765. #define RT5651_PWR_OV_R_BIT 12
  766. #define RT5651_PWR_HV_L (0x1 << 11)
  767. #define RT5651_PWR_HV_L_BIT 11
  768. #define RT5651_PWR_HV_R (0x1 << 10)
  769. #define RT5651_PWR_HV_R_BIT 10
  770. #define RT5651_PWR_IN1_L (0x1 << 9)
  771. #define RT5651_PWR_IN1_L_BIT 9
  772. #define RT5651_PWR_IN1_R (0x1 << 8)
  773. #define RT5651_PWR_IN1_R_BIT 8
  774. #define RT5651_PWR_IN2_L (0x1 << 7)
  775. #define RT5651_PWR_IN2_L_BIT 7
  776. #define RT5651_PWR_IN2_R (0x1 << 6)
  777. #define RT5651_PWR_IN2_R_BIT 6
  778. /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
  779. #define RT5651_I2S_MS_MASK (0x1 << 15)
  780. #define RT5651_I2S_MS_SFT 15
  781. #define RT5651_I2S_MS_M (0x0 << 15)
  782. #define RT5651_I2S_MS_S (0x1 << 15)
  783. #define RT5651_I2S_O_CP_MASK (0x3 << 10)
  784. #define RT5651_I2S_O_CP_SFT 10
  785. #define RT5651_I2S_O_CP_OFF (0x0 << 10)
  786. #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
  787. #define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
  788. #define RT5651_I2S_I_CP_MASK (0x3 << 8)
  789. #define RT5651_I2S_I_CP_SFT 8
  790. #define RT5651_I2S_I_CP_OFF (0x0 << 8)
  791. #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
  792. #define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
  793. #define RT5651_I2S_BP_MASK (0x1 << 7)
  794. #define RT5651_I2S_BP_SFT 7
  795. #define RT5651_I2S_BP_NOR (0x0 << 7)
  796. #define RT5651_I2S_BP_INV (0x1 << 7)
  797. #define RT5651_I2S_DL_MASK (0x3 << 2)
  798. #define RT5651_I2S_DL_SFT 2
  799. #define RT5651_I2S_DL_16 (0x0 << 2)
  800. #define RT5651_I2S_DL_20 (0x1 << 2)
  801. #define RT5651_I2S_DL_24 (0x2 << 2)
  802. #define RT5651_I2S_DL_8 (0x3 << 2)
  803. #define RT5651_I2S_DF_MASK (0x3)
  804. #define RT5651_I2S_DF_SFT 0
  805. #define RT5651_I2S_DF_I2S (0x0)
  806. #define RT5651_I2S_DF_LEFT (0x1)
  807. #define RT5651_I2S_DF_PCM_A (0x2)
  808. #define RT5651_I2S_DF_PCM_B (0x3)
  809. /* ADC/DAC Clock Control 1 (0x73) */
  810. #define RT5651_I2S_PD1_MASK (0x7 << 12)
  811. #define RT5651_I2S_PD1_SFT 12
  812. #define RT5651_I2S_PD1_1 (0x0 << 12)
  813. #define RT5651_I2S_PD1_2 (0x1 << 12)
  814. #define RT5651_I2S_PD1_3 (0x2 << 12)
  815. #define RT5651_I2S_PD1_4 (0x3 << 12)
  816. #define RT5651_I2S_PD1_6 (0x4 << 12)
  817. #define RT5651_I2S_PD1_8 (0x5 << 12)
  818. #define RT5651_I2S_PD1_12 (0x6 << 12)
  819. #define RT5651_I2S_PD1_16 (0x7 << 12)
  820. #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
  821. #define RT5651_I2S_BCLK_MS2_SFT 11
  822. #define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
  823. #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
  824. #define RT5651_I2S_PD2_MASK (0x7 << 8)
  825. #define RT5651_I2S_PD2_SFT 8
  826. #define RT5651_I2S_PD2_1 (0x0 << 8)
  827. #define RT5651_I2S_PD2_2 (0x1 << 8)
  828. #define RT5651_I2S_PD2_3 (0x2 << 8)
  829. #define RT5651_I2S_PD2_4 (0x3 << 8)
  830. #define RT5651_I2S_PD2_6 (0x4 << 8)
  831. #define RT5651_I2S_PD2_8 (0x5 << 8)
  832. #define RT5651_I2S_PD2_12 (0x6 << 8)
  833. #define RT5651_I2S_PD2_16 (0x7 << 8)
  834. #define RT5651_DAC_OSR_MASK (0x3 << 2)
  835. #define RT5651_DAC_OSR_SFT 2
  836. #define RT5651_DAC_OSR_128 (0x0 << 2)
  837. #define RT5651_DAC_OSR_64 (0x1 << 2)
  838. #define RT5651_DAC_OSR_32 (0x2 << 2)
  839. #define RT5651_DAC_OSR_128_3 (0x3 << 2)
  840. #define RT5651_ADC_OSR_MASK (0x3)
  841. #define RT5651_ADC_OSR_SFT 0
  842. #define RT5651_ADC_OSR_128 (0x0)
  843. #define RT5651_ADC_OSR_64 (0x1)
  844. #define RT5651_ADC_OSR_32 (0x2)
  845. #define RT5651_ADC_OSR_128_3 (0x3)
  846. /* ADC/DAC Clock Control 2 (0x74) */
  847. #define RT5651_DAHPF_EN (0x1 << 11)
  848. #define RT5651_DAHPF_EN_SFT 11
  849. #define RT5651_ADHPF_EN (0x1 << 10)
  850. #define RT5651_ADHPF_EN_SFT 10
  851. /* Digital Microphone Control (0x75) */
  852. #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
  853. #define RT5651_DMIC_1_EN_SFT 15
  854. #define RT5651_DMIC_1_DIS (0x0 << 15)
  855. #define RT5651_DMIC_1_EN (0x1 << 15)
  856. #define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
  857. #define RT5651_DMIC_1L_LH_SFT 13
  858. #define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
  859. #define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
  860. #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
  861. #define RT5651_DMIC_1R_LH_SFT 12
  862. #define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
  863. #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
  864. #define RT5651_DMIC_1_DP_MASK (0x3 << 10)
  865. #define RT5651_DMIC_1_DP_SFT 10
  866. #define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
  867. #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
  868. #define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
  869. #define RT5651_DMIC_CLK_MASK (0x7 << 5)
  870. #define RT5651_DMIC_CLK_SFT 5
  871. /* TDM Control 1 (0x77) */
  872. #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
  873. #define RT5651_TDM_INTEL_SEL_SFT 15
  874. #define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
  875. #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
  876. #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
  877. #define RT5651_TDM_MODE_SEL_SFT 14
  878. #define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
  879. #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
  880. #define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
  881. #define RT5651_TDM_CH_NUM_SEL_SFT 12
  882. #define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
  883. #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
  884. #define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
  885. #define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
  886. #define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
  887. #define RT5651_TDM_CH_LEN_SEL_SFT 10
  888. #define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
  889. #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
  890. #define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
  891. #define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
  892. #define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
  893. #define RT5651_TDM_ADC_SEL_SFT 9
  894. #define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
  895. #define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
  896. #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
  897. #define RT5651_TDM_ADC_START_SEL_SFT 8
  898. #define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
  899. #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
  900. #define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
  901. #define RT5651_TDM_I2S_CH2_SEL_SFT 6
  902. #define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
  903. #define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
  904. #define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
  905. #define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
  906. #define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
  907. #define RT5651_TDM_I2S_CH4_SEL_SFT 4
  908. #define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
  909. #define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
  910. #define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
  911. #define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
  912. #define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
  913. #define RT5651_TDM_I2S_CH6_SEL_SFT 2
  914. #define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
  915. #define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
  916. #define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
  917. #define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
  918. #define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
  919. #define RT5651_TDM_I2S_CH8_SEL_SFT 0
  920. #define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
  921. #define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
  922. #define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
  923. #define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
  924. /* TDM Control 2 (0x78) */
  925. #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
  926. #define RT5651_TDM_LRCK_POL_SEL_SFT 15
  927. #define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
  928. #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
  929. #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
  930. #define RT5651_TDM_CH_VAL_SEL_SFT 14
  931. #define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
  932. #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
  933. #define RT5651_TDM_CH_VAL_EN (0x1 << 13)
  934. #define RT5651_TDM_CH_VAL_SFT 13
  935. #define RT5651_TDM_LPBK_EN (0x1 << 12)
  936. #define RT5651_TDM_LPBK_SFT 12
  937. #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
  938. #define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
  939. #define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
  940. #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
  941. #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
  942. #define RT5651_TDM_END_EDGE_SEL_SFT 10
  943. #define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
  944. #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
  945. #define RT5651_TDM_END_EDGE_EN (0x1 << 9)
  946. #define RT5651_TDM_END_EDGE_EN_SFT 9
  947. #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
  948. #define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
  949. #define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
  950. #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
  951. #define RT5651_M_TDM2_L (0x1 << 7)
  952. #define RT5651_M_TDM2_L_SFT 7
  953. #define RT5651_M_TDM2_R (0x1 << 6)
  954. #define RT5651_M_TDM2_R_SFT 6
  955. #define RT5651_M_TDM4_L (0x1 << 5)
  956. #define RT5651_M_TDM4_L_SFT 5
  957. #define RT5651_M_TDM4_R (0x1 << 4)
  958. #define RT5651_M_TDM4_R_SFT 4
  959. /* TDM Control 3 (0x79) */
  960. #define RT5651_CH2_L_SEL_MASK (0x7 << 12)
  961. #define RT5651_CH2_L_SEL_SFT 12
  962. #define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
  963. #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
  964. #define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
  965. #define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
  966. #define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
  967. #define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
  968. #define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
  969. #define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
  970. #define RT5651_CH2_R_SEL_MASK (0x7 << 8)
  971. #define RT5651_CH2_R_SEL_SFT 8
  972. #define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
  973. #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
  974. #define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
  975. #define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
  976. #define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
  977. #define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
  978. #define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
  979. #define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
  980. #define RT5651_CH4_L_SEL_MASK (0x7 << 4)
  981. #define RT5651_CH4_L_SEL_SFT 4
  982. #define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
  983. #define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
  984. #define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
  985. #define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
  986. #define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
  987. #define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
  988. #define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
  989. #define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
  990. #define RT5651_CH4_R_SEL_MASK (0x7)
  991. #define RT5651_CH4_R_SEL_SFT 0
  992. #define RT5651_CH4_R_SEL_SL0 (0x0)
  993. #define RT5651_CH4_R_SEL_SL1 (0x1)
  994. #define RT5651_CH4_R_SEL_SL2 (0x2)
  995. #define RT5651_CH4_R_SEL_SL3 (0x3)
  996. #define RT5651_CH4_R_SEL_SL4 (0x4)
  997. #define RT5651_CH4_R_SEL_SL5 (0x5)
  998. #define RT5651_CH4_R_SEL_SL6 (0x6)
  999. #define RT5651_CH4_R_SEL_SL7 (0x7)
  1000. /* Global Clock Control (0x80) */
  1001. #define RT5651_SCLK_SRC_MASK (0x3 << 14)
  1002. #define RT5651_SCLK_SRC_SFT 14
  1003. #define RT5651_SCLK_SRC_MCLK (0x0 << 14)
  1004. #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
  1005. #define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
  1006. #define RT5651_PLL1_SRC_MASK (0x3 << 12)
  1007. #define RT5651_PLL1_SRC_SFT 12
  1008. #define RT5651_PLL1_SRC_MCLK (0x0 << 12)
  1009. #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
  1010. #define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
  1011. #define RT5651_PLL1_PD_MASK (0x1 << 3)
  1012. #define RT5651_PLL1_PD_SFT 3
  1013. #define RT5651_PLL1_PD_1 (0x0 << 3)
  1014. #define RT5651_PLL1_PD_2 (0x1 << 3)
  1015. #define RT5651_PLL_INP_MAX 40000000
  1016. #define RT5651_PLL_INP_MIN 256000
  1017. /* PLL M/N/K Code Control 1 (0x81) */
  1018. #define RT5651_PLL_N_MAX 0x1ff
  1019. #define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
  1020. #define RT5651_PLL_N_SFT 7
  1021. #define RT5651_PLL_K_MAX 0x1f
  1022. #define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
  1023. #define RT5651_PLL_K_SFT 0
  1024. /* PLL M/N/K Code Control 2 (0x82) */
  1025. #define RT5651_PLL_M_MAX 0xf
  1026. #define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
  1027. #define RT5651_PLL_M_SFT 12
  1028. #define RT5651_PLL_M_BP (0x1 << 11)
  1029. #define RT5651_PLL_M_BP_SFT 11
  1030. /* PLL tracking mode 1 (0x83) */
  1031. #define RT5651_STO1_T_MASK (0x1 << 15)
  1032. #define RT5651_STO1_T_SFT 15
  1033. #define RT5651_STO1_T_SCLK (0x0 << 15)
  1034. #define RT5651_STO1_T_LRCK1 (0x1 << 15)
  1035. #define RT5651_STO2_T_MASK (0x1 << 12)
  1036. #define RT5651_STO2_T_SFT 12
  1037. #define RT5651_STO2_T_I2S2 (0x0 << 12)
  1038. #define RT5651_STO2_T_LRCK2 (0x1 << 12)
  1039. #define RT5651_ASRC2_REF_MASK (0x1 << 11)
  1040. #define RT5651_ASRC2_REF_SFT 11
  1041. #define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
  1042. #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
  1043. #define RT5651_DMIC_1_M_MASK (0x1 << 9)
  1044. #define RT5651_DMIC_1_M_SFT 9
  1045. #define RT5651_DMIC_1_M_NOR (0x0 << 9)
  1046. #define RT5651_DMIC_1_M_ASYN (0x1 << 9)
  1047. /* PLL tracking mode 2 (0x84) */
  1048. #define RT5651_STO1_ASRC_EN (0x1 << 15)
  1049. #define RT5651_STO1_ASRC_EN_SFT 15
  1050. #define RT5651_STO2_ASRC_EN (0x1 << 14)
  1051. #define RT5651_STO2_ASRC_EN_SFT 14
  1052. #define RT5651_STO1_DAC_M_MASK (0x1 << 13)
  1053. #define RT5651_STO1_DAC_M_SFT 13
  1054. #define RT5651_STO1_DAC_M_NOR (0x0 << 13)
  1055. #define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
  1056. #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
  1057. #define RT5651_STO2_DAC_M_SFT 12
  1058. #define RT5651_STO2_DAC_M_NOR (0x0 << 12)
  1059. #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
  1060. #define RT5651_ADC_M_MASK (0x1 << 11)
  1061. #define RT5651_ADC_M_SFT 11
  1062. #define RT5651_ADC_M_NOR (0x0 << 11)
  1063. #define RT5651_ADC_M_ASRC (0x1 << 11)
  1064. #define RT5651_I2S1_R_D_MASK (0x1 << 4)
  1065. #define RT5651_I2S1_R_D_SFT 4
  1066. #define RT5651_I2S1_R_D_DIS (0x0 << 4)
  1067. #define RT5651_I2S1_R_D_EN (0x1 << 4)
  1068. #define RT5651_I2S2_R_D_MASK (0x1 << 3)
  1069. #define RT5651_I2S2_R_D_SFT 3
  1070. #define RT5651_I2S2_R_D_DIS (0x0 << 3)
  1071. #define RT5651_I2S2_R_D_EN (0x1 << 3)
  1072. #define RT5651_PRE_SCLK_MASK (0x3)
  1073. #define RT5651_PRE_SCLK_SFT 0
  1074. #define RT5651_PRE_SCLK_512 (0x0)
  1075. #define RT5651_PRE_SCLK_1024 (0x1)
  1076. #define RT5651_PRE_SCLK_2048 (0x2)
  1077. /* PLL tracking mode 3 (0x85) */
  1078. #define RT5651_I2S1_RATE_MASK (0xf << 12)
  1079. #define RT5651_I2S1_RATE_SFT 12
  1080. #define RT5651_I2S2_RATE_MASK (0xf << 8)
  1081. #define RT5651_I2S2_RATE_SFT 8
  1082. #define RT5651_G_ASRC_LP_MASK (0x1 << 3)
  1083. #define RT5651_G_ASRC_LP_SFT 3
  1084. #define RT5651_ASRC_LP_F_M (0x1 << 2)
  1085. #define RT5651_ASRC_LP_F_SFT 2
  1086. #define RT5651_ASRC_LP_F_NOR (0x0 << 2)
  1087. #define RT5651_ASRC_LP_F_SB (0x1 << 2)
  1088. #define RT5651_FTK_PH_DET_MASK (0x3)
  1089. #define RT5651_FTK_PH_DET_SFT 0
  1090. #define RT5651_FTK_PH_DET_DIV1 (0x0)
  1091. #define RT5651_FTK_PH_DET_DIV2 (0x1)
  1092. #define RT5651_FTK_PH_DET_DIV4 (0x2)
  1093. #define RT5651_FTK_PH_DET_DIV8 (0x3)
  1094. /*PLL tracking mode 6 (0x89) */
  1095. #define RT5651_I2S1_PD_MASK (0x7 << 12)
  1096. #define RT5651_I2S1_PD_SFT 12
  1097. #define RT5651_I2S2_PD_MASK (0x7 << 8)
  1098. #define RT5651_I2S2_PD_SFT 8
  1099. /*PLL tracking mode 7 (0x8a) */
  1100. #define RT5651_FSI1_RATE_MASK (0xf << 12)
  1101. #define RT5651_FSI1_RATE_SFT 12
  1102. #define RT5651_FSI2_RATE_MASK (0xf << 8)
  1103. #define RT5651_FSI2_RATE_SFT 8
  1104. /* HPOUT Over Current Detection (0x8b) */
  1105. #define RT5651_HP_OVCD_MASK (0x1 << 10)
  1106. #define RT5651_HP_OVCD_SFT 10
  1107. #define RT5651_HP_OVCD_DIS (0x0 << 10)
  1108. #define RT5651_HP_OVCD_EN (0x1 << 10)
  1109. #define RT5651_HP_OC_TH_MASK (0x3 << 8)
  1110. #define RT5651_HP_OC_TH_SFT 8
  1111. #define RT5651_HP_OC_TH_90 (0x0 << 8)
  1112. #define RT5651_HP_OC_TH_105 (0x1 << 8)
  1113. #define RT5651_HP_OC_TH_120 (0x2 << 8)
  1114. #define RT5651_HP_OC_TH_135 (0x3 << 8)
  1115. /* Depop Mode Control 1 (0x8e) */
  1116. #define RT5651_SMT_TRIG_MASK (0x1 << 15)
  1117. #define RT5651_SMT_TRIG_SFT 15
  1118. #define RT5651_SMT_TRIG_DIS (0x0 << 15)
  1119. #define RT5651_SMT_TRIG_EN (0x1 << 15)
  1120. #define RT5651_HP_L_SMT_MASK (0x1 << 9)
  1121. #define RT5651_HP_L_SMT_SFT 9
  1122. #define RT5651_HP_L_SMT_DIS (0x0 << 9)
  1123. #define RT5651_HP_L_SMT_EN (0x1 << 9)
  1124. #define RT5651_HP_R_SMT_MASK (0x1 << 8)
  1125. #define RT5651_HP_R_SMT_SFT 8
  1126. #define RT5651_HP_R_SMT_DIS (0x0 << 8)
  1127. #define RT5651_HP_R_SMT_EN (0x1 << 8)
  1128. #define RT5651_HP_CD_PD_MASK (0x1 << 7)
  1129. #define RT5651_HP_CD_PD_SFT 7
  1130. #define RT5651_HP_CD_PD_DIS (0x0 << 7)
  1131. #define RT5651_HP_CD_PD_EN (0x1 << 7)
  1132. #define RT5651_RSTN_MASK (0x1 << 6)
  1133. #define RT5651_RSTN_SFT 6
  1134. #define RT5651_RSTN_DIS (0x0 << 6)
  1135. #define RT5651_RSTN_EN (0x1 << 6)
  1136. #define RT5651_RSTP_MASK (0x1 << 5)
  1137. #define RT5651_RSTP_SFT 5
  1138. #define RT5651_RSTP_DIS (0x0 << 5)
  1139. #define RT5651_RSTP_EN (0x1 << 5)
  1140. #define RT5651_HP_CO_MASK (0x1 << 4)
  1141. #define RT5651_HP_CO_SFT 4
  1142. #define RT5651_HP_CO_DIS (0x0 << 4)
  1143. #define RT5651_HP_CO_EN (0x1 << 4)
  1144. #define RT5651_HP_CP_MASK (0x1 << 3)
  1145. #define RT5651_HP_CP_SFT 3
  1146. #define RT5651_HP_CP_PD (0x0 << 3)
  1147. #define RT5651_HP_CP_PU (0x1 << 3)
  1148. #define RT5651_HP_SG_MASK (0x1 << 2)
  1149. #define RT5651_HP_SG_SFT 2
  1150. #define RT5651_HP_SG_DIS (0x0 << 2)
  1151. #define RT5651_HP_SG_EN (0x1 << 2)
  1152. #define RT5651_HP_DP_MASK (0x1 << 1)
  1153. #define RT5651_HP_DP_SFT 1
  1154. #define RT5651_HP_DP_PD (0x0 << 1)
  1155. #define RT5651_HP_DP_PU (0x1 << 1)
  1156. #define RT5651_HP_CB_MASK (0x1)
  1157. #define RT5651_HP_CB_SFT 0
  1158. #define RT5651_HP_CB_PD (0x0)
  1159. #define RT5651_HP_CB_PU (0x1)
  1160. /* Depop Mode Control 2 (0x8f) */
  1161. #define RT5651_DEPOP_MASK (0x1 << 13)
  1162. #define RT5651_DEPOP_SFT 13
  1163. #define RT5651_DEPOP_AUTO (0x0 << 13)
  1164. #define RT5651_DEPOP_MAN (0x1 << 13)
  1165. #define RT5651_RAMP_MASK (0x1 << 12)
  1166. #define RT5651_RAMP_SFT 12
  1167. #define RT5651_RAMP_DIS (0x0 << 12)
  1168. #define RT5651_RAMP_EN (0x1 << 12)
  1169. #define RT5651_BPS_MASK (0x1 << 11)
  1170. #define RT5651_BPS_SFT 11
  1171. #define RT5651_BPS_DIS (0x0 << 11)
  1172. #define RT5651_BPS_EN (0x1 << 11)
  1173. #define RT5651_FAST_UPDN_MASK (0x1 << 10)
  1174. #define RT5651_FAST_UPDN_SFT 10
  1175. #define RT5651_FAST_UPDN_DIS (0x0 << 10)
  1176. #define RT5651_FAST_UPDN_EN (0x1 << 10)
  1177. #define RT5651_MRES_MASK (0x3 << 8)
  1178. #define RT5651_MRES_SFT 8
  1179. #define RT5651_MRES_15MO (0x0 << 8)
  1180. #define RT5651_MRES_25MO (0x1 << 8)
  1181. #define RT5651_MRES_35MO (0x2 << 8)
  1182. #define RT5651_MRES_45MO (0x3 << 8)
  1183. #define RT5651_VLO_MASK (0x1 << 7)
  1184. #define RT5651_VLO_SFT 7
  1185. #define RT5651_VLO_3V (0x0 << 7)
  1186. #define RT5651_VLO_32V (0x1 << 7)
  1187. #define RT5651_DIG_DP_MASK (0x1 << 6)
  1188. #define RT5651_DIG_DP_SFT 6
  1189. #define RT5651_DIG_DP_DIS (0x0 << 6)
  1190. #define RT5651_DIG_DP_EN (0x1 << 6)
  1191. #define RT5651_DP_TH_MASK (0x3 << 4)
  1192. #define RT5651_DP_TH_SFT 4
  1193. /* Depop Mode Control 3 (0x90) */
  1194. #define RT5651_CP_SYS_MASK (0x7 << 12)
  1195. #define RT5651_CP_SYS_SFT 12
  1196. #define RT5651_CP_FQ1_MASK (0x7 << 8)
  1197. #define RT5651_CP_FQ1_SFT 8
  1198. #define RT5651_CP_FQ2_MASK (0x7 << 4)
  1199. #define RT5651_CP_FQ2_SFT 4
  1200. #define RT5651_CP_FQ3_MASK (0x7)
  1201. #define RT5651_CP_FQ3_SFT 0
  1202. #define RT5651_CP_FQ_1_5_KHZ 0
  1203. #define RT5651_CP_FQ_3_KHZ 1
  1204. #define RT5651_CP_FQ_6_KHZ 2
  1205. #define RT5651_CP_FQ_12_KHZ 3
  1206. #define RT5651_CP_FQ_24_KHZ 4
  1207. #define RT5651_CP_FQ_48_KHZ 5
  1208. #define RT5651_CP_FQ_96_KHZ 6
  1209. #define RT5651_CP_FQ_192_KHZ 7
  1210. /* HPOUT charge pump (0x91) */
  1211. #define RT5651_OSW_L_MASK (0x1 << 11)
  1212. #define RT5651_OSW_L_SFT 11
  1213. #define RT5651_OSW_L_DIS (0x0 << 11)
  1214. #define RT5651_OSW_L_EN (0x1 << 11)
  1215. #define RT5651_OSW_R_MASK (0x1 << 10)
  1216. #define RT5651_OSW_R_SFT 10
  1217. #define RT5651_OSW_R_DIS (0x0 << 10)
  1218. #define RT5651_OSW_R_EN (0x1 << 10)
  1219. #define RT5651_PM_HP_MASK (0x3 << 8)
  1220. #define RT5651_PM_HP_SFT 8
  1221. #define RT5651_PM_HP_LV (0x0 << 8)
  1222. #define RT5651_PM_HP_MV (0x1 << 8)
  1223. #define RT5651_PM_HP_HV (0x2 << 8)
  1224. #define RT5651_IB_HP_MASK (0x3 << 6)
  1225. #define RT5651_IB_HP_SFT 6
  1226. #define RT5651_IB_HP_125IL (0x0 << 6)
  1227. #define RT5651_IB_HP_25IL (0x1 << 6)
  1228. #define RT5651_IB_HP_5IL (0x2 << 6)
  1229. #define RT5651_IB_HP_1IL (0x3 << 6)
  1230. /* Micbias Control (0x93) */
  1231. #define RT5651_MIC1_BS_MASK (0x1 << 15)
  1232. #define RT5651_MIC1_BS_SFT 15
  1233. #define RT5651_MIC1_BS_9AV (0x0 << 15)
  1234. #define RT5651_MIC1_BS_75AV (0x1 << 15)
  1235. #define RT5651_MIC1_CLK_MASK (0x1 << 13)
  1236. #define RT5651_MIC1_CLK_SFT 13
  1237. #define RT5651_MIC1_CLK_DIS (0x0 << 13)
  1238. #define RT5651_MIC1_CLK_EN (0x1 << 13)
  1239. #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
  1240. #define RT5651_MIC1_OVCD_SFT 11
  1241. #define RT5651_MIC1_OVCD_DIS (0x0 << 11)
  1242. #define RT5651_MIC1_OVCD_EN (0x1 << 11)
  1243. #define RT5651_MIC1_OVTH_MASK (0x3 << 9)
  1244. #define RT5651_MIC1_OVTH_SFT 9
  1245. #define RT5651_MIC1_OVTH_600UA (0x0 << 9)
  1246. #define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
  1247. #define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
  1248. #define RT5651_PWR_MB_MASK (0x1 << 5)
  1249. #define RT5651_PWR_MB_SFT 5
  1250. #define RT5651_PWR_MB_PD (0x0 << 5)
  1251. #define RT5651_PWR_MB_PU (0x1 << 5)
  1252. #define RT5651_PWR_CLK12M_MASK (0x1 << 4)
  1253. #define RT5651_PWR_CLK12M_SFT 4
  1254. #define RT5651_PWR_CLK12M_PD (0x0 << 4)
  1255. #define RT5651_PWR_CLK12M_PU (0x1 << 4)
  1256. /* Analog JD Control 1 (0x94) */
  1257. #define RT5651_JD2_CMP_MASK (0x7 << 12)
  1258. #define RT5651_JD2_CMP_SFT 12
  1259. #define RT5651_JD_PU (0x1 << 11)
  1260. #define RT5651_JD_PU_SFT 11
  1261. #define RT5651_JD_PD (0x1 << 10)
  1262. #define RT5651_JD_PD_SFT 10
  1263. #define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
  1264. #define RT5651_JD_MODE_SEL_SFT 8
  1265. #define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
  1266. #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
  1267. #define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
  1268. #define RT5651_JD_M_CMP (0x7 << 4)
  1269. #define RT5651_JD_M_CMP_SFT 4
  1270. #define RT5651_JD_M_PU (0x1 << 3)
  1271. #define RT5651_JD_M_PU_SFT 3
  1272. #define RT5651_JD_M_PD (0x1 << 2)
  1273. #define RT5651_JD_M_PD_SFT 2
  1274. #define RT5651_JD_M_MODE_SEL_MASK (0x3)
  1275. #define RT5651_JD_M_MODE_SEL_SFT 0
  1276. #define RT5651_JD_M_MODE_SEL_M0 (0x0)
  1277. #define RT5651_JD_M_MODE_SEL_M1 (0x1)
  1278. #define RT5651_JD_M_MODE_SEL_M2 (0x2)
  1279. /* Analog JD Control 2 (0x95) */
  1280. #define RT5651_JD3_CMP_MASK (0x7 << 12)
  1281. #define RT5651_JD3_CMP_SFT 12
  1282. /* EQ Control 1 (0xb0) */
  1283. #define RT5651_EQ_SRC_MASK (0x1 << 15)
  1284. #define RT5651_EQ_SRC_SFT 15
  1285. #define RT5651_EQ_SRC_DAC (0x0 << 15)
  1286. #define RT5651_EQ_SRC_ADC (0x1 << 15)
  1287. #define RT5651_EQ_UPD (0x1 << 14)
  1288. #define RT5651_EQ_UPD_BIT 14
  1289. #define RT5651_EQ_CD_MASK (0x1 << 13)
  1290. #define RT5651_EQ_CD_SFT 13
  1291. #define RT5651_EQ_CD_DIS (0x0 << 13)
  1292. #define RT5651_EQ_CD_EN (0x1 << 13)
  1293. #define RT5651_EQ_DITH_MASK (0x3 << 8)
  1294. #define RT5651_EQ_DITH_SFT 8
  1295. #define RT5651_EQ_DITH_NOR (0x0 << 8)
  1296. #define RT5651_EQ_DITH_LSB (0x1 << 8)
  1297. #define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
  1298. #define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
  1299. #define RT5651_EQ_CD_F (0x1 << 7)
  1300. #define RT5651_EQ_CD_F_BIT 7
  1301. #define RT5651_EQ_STA_HP2 (0x1 << 6)
  1302. #define RT5651_EQ_STA_HP2_BIT 6
  1303. #define RT5651_EQ_STA_HP1 (0x1 << 5)
  1304. #define RT5651_EQ_STA_HP1_BIT 5
  1305. #define RT5651_EQ_STA_BP4 (0x1 << 4)
  1306. #define RT5651_EQ_STA_BP4_BIT 4
  1307. #define RT5651_EQ_STA_BP3 (0x1 << 3)
  1308. #define RT5651_EQ_STA_BP3_BIT 3
  1309. #define RT5651_EQ_STA_BP2 (0x1 << 2)
  1310. #define RT5651_EQ_STA_BP2_BIT 2
  1311. #define RT5651_EQ_STA_BP1 (0x1 << 1)
  1312. #define RT5651_EQ_STA_BP1_BIT 1
  1313. #define RT5651_EQ_STA_LP (0x1)
  1314. #define RT5651_EQ_STA_LP_BIT 0
  1315. /* EQ Control 2 (0xb1) */
  1316. #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
  1317. #define RT5651_EQ_HPF1_M_SFT 8
  1318. #define RT5651_EQ_HPF1_M_HI (0x0 << 8)
  1319. #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
  1320. #define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
  1321. #define RT5651_EQ_LPF1_M_SFT 7
  1322. #define RT5651_EQ_LPF1_M_LO (0x0 << 7)
  1323. #define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
  1324. #define RT5651_EQ_HPF2_MASK (0x1 << 6)
  1325. #define RT5651_EQ_HPF2_SFT 6
  1326. #define RT5651_EQ_HPF2_DIS (0x0 << 6)
  1327. #define RT5651_EQ_HPF2_EN (0x1 << 6)
  1328. #define RT5651_EQ_HPF1_MASK (0x1 << 5)
  1329. #define RT5651_EQ_HPF1_SFT 5
  1330. #define RT5651_EQ_HPF1_DIS (0x0 << 5)
  1331. #define RT5651_EQ_HPF1_EN (0x1 << 5)
  1332. #define RT5651_EQ_BPF4_MASK (0x1 << 4)
  1333. #define RT5651_EQ_BPF4_SFT 4
  1334. #define RT5651_EQ_BPF4_DIS (0x0 << 4)
  1335. #define RT5651_EQ_BPF4_EN (0x1 << 4)
  1336. #define RT5651_EQ_BPF3_MASK (0x1 << 3)
  1337. #define RT5651_EQ_BPF3_SFT 3
  1338. #define RT5651_EQ_BPF3_DIS (0x0 << 3)
  1339. #define RT5651_EQ_BPF3_EN (0x1 << 3)
  1340. #define RT5651_EQ_BPF2_MASK (0x1 << 2)
  1341. #define RT5651_EQ_BPF2_SFT 2
  1342. #define RT5651_EQ_BPF2_DIS (0x0 << 2)
  1343. #define RT5651_EQ_BPF2_EN (0x1 << 2)
  1344. #define RT5651_EQ_BPF1_MASK (0x1 << 1)
  1345. #define RT5651_EQ_BPF1_SFT 1
  1346. #define RT5651_EQ_BPF1_DIS (0x0 << 1)
  1347. #define RT5651_EQ_BPF1_EN (0x1 << 1)
  1348. #define RT5651_EQ_LPF_MASK (0x1)
  1349. #define RT5651_EQ_LPF_SFT 0
  1350. #define RT5651_EQ_LPF_DIS (0x0)
  1351. #define RT5651_EQ_LPF_EN (0x1)
  1352. #define RT5651_EQ_CTRL_MASK (0x7f)
  1353. /* Memory Test (0xb2) */
  1354. #define RT5651_MT_MASK (0x1 << 15)
  1355. #define RT5651_MT_SFT 15
  1356. #define RT5651_MT_DIS (0x0 << 15)
  1357. #define RT5651_MT_EN (0x1 << 15)
  1358. /* ALC Control 1 (0xb4) */
  1359. #define RT5651_ALC_P_MASK (0x1 << 15)
  1360. #define RT5651_ALC_P_SFT 15
  1361. #define RT5651_ALC_P_DAC (0x0 << 15)
  1362. #define RT5651_ALC_P_ADC (0x1 << 15)
  1363. #define RT5651_ALC_MASK (0x1 << 14)
  1364. #define RT5651_ALC_SFT 14
  1365. #define RT5651_ALC_DIS (0x0 << 14)
  1366. #define RT5651_ALC_EN (0x1 << 14)
  1367. #define RT5651_ALC_UPD (0x1 << 13)
  1368. #define RT5651_ALC_UPD_BIT 13
  1369. #define RT5651_ALC_AR_MASK (0x1f << 8)
  1370. #define RT5651_ALC_AR_SFT 8
  1371. #define RT5651_ALC_R_MASK (0x7 << 5)
  1372. #define RT5651_ALC_R_SFT 5
  1373. #define RT5651_ALC_R_48K (0x1 << 5)
  1374. #define RT5651_ALC_R_96K (0x2 << 5)
  1375. #define RT5651_ALC_R_192K (0x3 << 5)
  1376. #define RT5651_ALC_R_441K (0x5 << 5)
  1377. #define RT5651_ALC_R_882K (0x6 << 5)
  1378. #define RT5651_ALC_R_1764K (0x7 << 5)
  1379. #define RT5651_ALC_RC_MASK (0x1f)
  1380. #define RT5651_ALC_RC_SFT 0
  1381. /* ALC Control 2 (0xb5) */
  1382. #define RT5651_ALC_POB_MASK (0x3f << 8)
  1383. #define RT5651_ALC_POB_SFT 8
  1384. #define RT5651_ALC_DRC_MASK (0x1 << 7)
  1385. #define RT5651_ALC_DRC_SFT 7
  1386. #define RT5651_ALC_DRC_DIS (0x0 << 7)
  1387. #define RT5651_ALC_DRC_EN (0x1 << 7)
  1388. #define RT5651_ALC_CPR_MASK (0x3 << 5)
  1389. #define RT5651_ALC_CPR_SFT 5
  1390. #define RT5651_ALC_CPR_1_1 (0x0 << 5)
  1391. #define RT5651_ALC_CPR_1_2 (0x1 << 5)
  1392. #define RT5651_ALC_CPR_1_4 (0x2 << 5)
  1393. #define RT5651_ALC_CPR_1_8 (0x3 << 5)
  1394. #define RT5651_ALC_PRB_MASK (0x1f)
  1395. #define RT5651_ALC_PRB_SFT 0
  1396. /* ALC Control 3 (0xb6) */
  1397. #define RT5651_ALC_NGB_MASK (0xf << 12)
  1398. #define RT5651_ALC_NGB_SFT 12
  1399. #define RT5651_ALC_TAR_MASK (0x1f << 7)
  1400. #define RT5651_ALC_TAR_SFT 7
  1401. #define RT5651_ALC_NG_MASK (0x1 << 6)
  1402. #define RT5651_ALC_NG_SFT 6
  1403. #define RT5651_ALC_NG_DIS (0x0 << 6)
  1404. #define RT5651_ALC_NG_EN (0x1 << 6)
  1405. #define RT5651_ALC_NGH_MASK (0x1 << 5)
  1406. #define RT5651_ALC_NGH_SFT 5
  1407. #define RT5651_ALC_NGH_DIS (0x0 << 5)
  1408. #define RT5651_ALC_NGH_EN (0x1 << 5)
  1409. #define RT5651_ALC_NGT_MASK (0x1f)
  1410. #define RT5651_ALC_NGT_SFT 0
  1411. /* Jack Detect Control 1 (0xbb) */
  1412. #define RT5651_JD_MASK (0x7 << 13)
  1413. #define RT5651_JD_SFT 13
  1414. #define RT5651_JD_DIS (0x0 << 13)
  1415. #define RT5651_JD_GPIO1 (0x1 << 13)
  1416. #define RT5651_JD_GPIO2 (0x2 << 13)
  1417. #define RT5651_JD_GPIO3 (0x3 << 13)
  1418. #define RT5651_JD_GPIO4 (0x4 << 13)
  1419. #define RT5651_JD_GPIO5 (0x5 << 13)
  1420. #define RT5651_JD_GPIO6 (0x6 << 13)
  1421. #define RT5651_JD_HP_MASK (0x1 << 11)
  1422. #define RT5651_JD_HP_SFT 11
  1423. #define RT5651_JD_HP_DIS (0x0 << 11)
  1424. #define RT5651_JD_HP_EN (0x1 << 11)
  1425. #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
  1426. #define RT5651_JD_HP_TRG_SFT 10
  1427. #define RT5651_JD_HP_TRG_LO (0x0 << 10)
  1428. #define RT5651_JD_HP_TRG_HI (0x1 << 10)
  1429. #define RT5651_JD_SPL_MASK (0x1 << 9)
  1430. #define RT5651_JD_SPL_SFT 9
  1431. #define RT5651_JD_SPL_DIS (0x0 << 9)
  1432. #define RT5651_JD_SPL_EN (0x1 << 9)
  1433. #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
  1434. #define RT5651_JD_SPL_TRG_SFT 8
  1435. #define RT5651_JD_SPL_TRG_LO (0x0 << 8)
  1436. #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
  1437. #define RT5651_JD_SPR_MASK (0x1 << 7)
  1438. #define RT5651_JD_SPR_SFT 7
  1439. #define RT5651_JD_SPR_DIS (0x0 << 7)
  1440. #define RT5651_JD_SPR_EN (0x1 << 7)
  1441. #define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
  1442. #define RT5651_JD_SPR_TRG_SFT 6
  1443. #define RT5651_JD_SPR_TRG_LO (0x0 << 6)
  1444. #define RT5651_JD_SPR_TRG_HI (0x1 << 6)
  1445. #define RT5651_JD_LO_MASK (0x1 << 3)
  1446. #define RT5651_JD_LO_SFT 3
  1447. #define RT5651_JD_LO_DIS (0x0 << 3)
  1448. #define RT5651_JD_LO_EN (0x1 << 3)
  1449. #define RT5651_JD_LO_TRG_MASK (0x1 << 2)
  1450. #define RT5651_JD_LO_TRG_SFT 2
  1451. #define RT5651_JD_LO_TRG_LO (0x0 << 2)
  1452. #define RT5651_JD_LO_TRG_HI (0x1 << 2)
  1453. /* Jack Detect Control 2 (0xbc) */
  1454. #define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
  1455. #define RT5651_JD_TRG_SEL_SFT 9
  1456. #define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
  1457. #define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
  1458. #define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
  1459. #define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
  1460. #define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
  1461. #define RT5651_JD3_IRQ_EN (0x1 << 8)
  1462. #define RT5651_JD3_IRQ_EN_SFT 8
  1463. #define RT5651_JD3_EN_STKY (0x1 << 7)
  1464. #define RT5651_JD3_EN_STKY_SFT 7
  1465. #define RT5651_JD3_INV (0x1 << 6)
  1466. #define RT5651_JD3_INV_SFT 6
  1467. /* IRQ Control 1 (0xbd) */
  1468. #define RT5651_IRQ_JD_MASK (0x1 << 15)
  1469. #define RT5651_IRQ_JD_SFT 15
  1470. #define RT5651_IRQ_JD_BP (0x0 << 15)
  1471. #define RT5651_IRQ_JD_NOR (0x1 << 15)
  1472. #define RT5651_JD_STKY_MASK (0x1 << 13)
  1473. #define RT5651_JD_STKY_SFT 13
  1474. #define RT5651_JD_STKY_DIS (0x0 << 13)
  1475. #define RT5651_JD_STKY_EN (0x1 << 13)
  1476. #define RT5651_JD_P_MASK (0x1 << 11)
  1477. #define RT5651_JD_P_SFT 11
  1478. #define RT5651_JD_P_NOR (0x0 << 11)
  1479. #define RT5651_JD_P_INV (0x1 << 11)
  1480. #define RT5651_JD1_1_IRQ_EN (0x1 << 9)
  1481. #define RT5651_JD1_1_IRQ_EN_SFT 9
  1482. #define RT5651_JD1_1_EN_STKY (0x1 << 8)
  1483. #define RT5651_JD1_1_EN_STKY_SFT 8
  1484. #define RT5651_JD1_1_INV (0x1 << 7)
  1485. #define RT5651_JD1_1_INV_SFT 7
  1486. #define RT5651_JD1_2_IRQ_EN (0x1 << 6)
  1487. #define RT5651_JD1_2_IRQ_EN_SFT 6
  1488. #define RT5651_JD1_2_EN_STKY (0x1 << 5)
  1489. #define RT5651_JD1_2_EN_STKY_SFT 5
  1490. #define RT5651_JD1_2_INV (0x1 << 4)
  1491. #define RT5651_JD1_2_INV_SFT 4
  1492. #define RT5651_JD2_IRQ_EN (0x1 << 3)
  1493. #define RT5651_JD2_IRQ_EN_SFT 3
  1494. #define RT5651_JD2_EN_STKY (0x1 << 2)
  1495. #define RT5651_JD2_EN_STKY_SFT 2
  1496. #define RT5651_JD2_INV (0x1 << 1)
  1497. #define RT5651_JD2_INV_SFT 1
  1498. /* IRQ Control 2 (0xbe) */
  1499. #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
  1500. #define RT5651_IRQ_MB1_OC_SFT 15
  1501. #define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
  1502. #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
  1503. #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
  1504. #define RT5651_MB1_OC_STKY_SFT 11
  1505. #define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
  1506. #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
  1507. #define RT5651_MB1_OC_P_MASK (0x1 << 7)
  1508. #define RT5651_MB1_OC_P_SFT 7
  1509. #define RT5651_MB1_OC_P_NOR (0x0 << 7)
  1510. #define RT5651_MB1_OC_P_INV (0x1 << 7)
  1511. #define RT5651_MB2_OC_P_MASK (0x1 << 6)
  1512. #define RT5651_MB1_OC_CLR (0x1 << 3)
  1513. #define RT5651_MB1_OC_CLR_SFT 3
  1514. #define RT5651_STA_GPIO8 (0x1)
  1515. #define RT5651_STA_GPIO8_BIT 0
  1516. /* Internal Status and GPIO status (0xbf) */
  1517. #define RT5651_STA_JD3 (0x1 << 15)
  1518. #define RT5651_STA_JD3_BIT 15
  1519. #define RT5651_STA_JD2 (0x1 << 14)
  1520. #define RT5651_STA_JD2_BIT 14
  1521. #define RT5651_STA_JD1_2 (0x1 << 13)
  1522. #define RT5651_STA_JD1_2_BIT 13
  1523. #define RT5651_STA_JD1_1 (0x1 << 12)
  1524. #define RT5651_STA_JD1_1_BIT 12
  1525. #define RT5651_STA_GP7 (0x1 << 11)
  1526. #define RT5651_STA_GP7_BIT 11
  1527. #define RT5651_STA_GP6 (0x1 << 10)
  1528. #define RT5651_STA_GP6_BIT 10
  1529. #define RT5651_STA_GP5 (0x1 << 9)
  1530. #define RT5651_STA_GP5_BIT 9
  1531. #define RT5651_STA_GP1 (0x1 << 8)
  1532. #define RT5651_STA_GP1_BIT 8
  1533. #define RT5651_STA_GP2 (0x1 << 7)
  1534. #define RT5651_STA_GP2_BIT 7
  1535. #define RT5651_STA_GP3 (0x1 << 6)
  1536. #define RT5651_STA_GP3_BIT 6
  1537. #define RT5651_STA_GP4 (0x1 << 5)
  1538. #define RT5651_STA_GP4_BIT 5
  1539. #define RT5651_STA_GP_JD (0x1 << 4)
  1540. #define RT5651_STA_GP_JD_BIT 4
  1541. /* GPIO Control 1 (0xc0) */
  1542. #define RT5651_GP1_PIN_MASK (0x1 << 15)
  1543. #define RT5651_GP1_PIN_SFT 15
  1544. #define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
  1545. #define RT5651_GP1_PIN_IRQ (0x1 << 15)
  1546. #define RT5651_GP2_PIN_MASK (0x1 << 14)
  1547. #define RT5651_GP2_PIN_SFT 14
  1548. #define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
  1549. #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
  1550. #define RT5651_GPIO_M_MASK (0x1 << 9)
  1551. #define RT5651_GPIO_M_SFT 9
  1552. #define RT5651_GPIO_M_FLT (0x0 << 9)
  1553. #define RT5651_GPIO_M_PH (0x1 << 9)
  1554. #define RT5651_I2S2_SEL_MASK (0x1 << 8)
  1555. #define RT5651_I2S2_SEL_SFT 8
  1556. #define RT5651_I2S2_SEL_I2S (0x0 << 8)
  1557. #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
  1558. #define RT5651_GP5_PIN_MASK (0x1 << 7)
  1559. #define RT5651_GP5_PIN_SFT 7
  1560. #define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
  1561. #define RT5651_GP5_PIN_IRQ (0x1 << 7)
  1562. #define RT5651_GP6_PIN_MASK (0x1 << 6)
  1563. #define RT5651_GP6_PIN_SFT 6
  1564. #define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
  1565. #define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
  1566. #define RT5651_GP7_PIN_MASK (0x1 << 5)
  1567. #define RT5651_GP7_PIN_SFT 5
  1568. #define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
  1569. #define RT5651_GP7_PIN_IRQ (0x1 << 5)
  1570. #define RT5651_GP8_PIN_MASK (0x1 << 4)
  1571. #define RT5651_GP8_PIN_SFT 4
  1572. #define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
  1573. #define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
  1574. #define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
  1575. #define RT5651_GPIO_PDM_SEL_SFT 3
  1576. #define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
  1577. #define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
  1578. /* GPIO Control 2 (0xc1) */
  1579. #define RT5651_GP5_DR_MASK (0x1 << 14)
  1580. #define RT5651_GP5_DR_SFT 14
  1581. #define RT5651_GP5_DR_IN (0x0 << 14)
  1582. #define RT5651_GP5_DR_OUT (0x1 << 14)
  1583. #define RT5651_GP5_OUT_MASK (0x1 << 13)
  1584. #define RT5651_GP5_OUT_SFT 13
  1585. #define RT5651_GP5_OUT_LO (0x0 << 13)
  1586. #define RT5651_GP5_OUT_HI (0x1 << 13)
  1587. #define RT5651_GP5_P_MASK (0x1 << 12)
  1588. #define RT5651_GP5_P_SFT 12
  1589. #define RT5651_GP5_P_NOR (0x0 << 12)
  1590. #define RT5651_GP5_P_INV (0x1 << 12)
  1591. #define RT5651_GP4_DR_MASK (0x1 << 11)
  1592. #define RT5651_GP4_DR_SFT 11
  1593. #define RT5651_GP4_DR_IN (0x0 << 11)
  1594. #define RT5651_GP4_DR_OUT (0x1 << 11)
  1595. #define RT5651_GP4_OUT_MASK (0x1 << 10)
  1596. #define RT5651_GP4_OUT_SFT 10
  1597. #define RT5651_GP4_OUT_LO (0x0 << 10)
  1598. #define RT5651_GP4_OUT_HI (0x1 << 10)
  1599. #define RT5651_GP4_P_MASK (0x1 << 9)
  1600. #define RT5651_GP4_P_SFT 9
  1601. #define RT5651_GP4_P_NOR (0x0 << 9)
  1602. #define RT5651_GP4_P_INV (0x1 << 9)
  1603. #define RT5651_GP3_DR_MASK (0x1 << 8)
  1604. #define RT5651_GP3_DR_SFT 8
  1605. #define RT5651_GP3_DR_IN (0x0 << 8)
  1606. #define RT5651_GP3_DR_OUT (0x1 << 8)
  1607. #define RT5651_GP3_OUT_MASK (0x1 << 7)
  1608. #define RT5651_GP3_OUT_SFT 7
  1609. #define RT5651_GP3_OUT_LO (0x0 << 7)
  1610. #define RT5651_GP3_OUT_HI (0x1 << 7)
  1611. #define RT5651_GP3_P_MASK (0x1 << 6)
  1612. #define RT5651_GP3_P_SFT 6
  1613. #define RT5651_GP3_P_NOR (0x0 << 6)
  1614. #define RT5651_GP3_P_INV (0x1 << 6)
  1615. #define RT5651_GP2_DR_MASK (0x1 << 5)
  1616. #define RT5651_GP2_DR_SFT 5
  1617. #define RT5651_GP2_DR_IN (0x0 << 5)
  1618. #define RT5651_GP2_DR_OUT (0x1 << 5)
  1619. #define RT5651_GP2_OUT_MASK (0x1 << 4)
  1620. #define RT5651_GP2_OUT_SFT 4
  1621. #define RT5651_GP2_OUT_LO (0x0 << 4)
  1622. #define RT5651_GP2_OUT_HI (0x1 << 4)
  1623. #define RT5651_GP2_P_MASK (0x1 << 3)
  1624. #define RT5651_GP2_P_SFT 3
  1625. #define RT5651_GP2_P_NOR (0x0 << 3)
  1626. #define RT5651_GP2_P_INV (0x1 << 3)
  1627. #define RT5651_GP1_DR_MASK (0x1 << 2)
  1628. #define RT5651_GP1_DR_SFT 2
  1629. #define RT5651_GP1_DR_IN (0x0 << 2)
  1630. #define RT5651_GP1_DR_OUT (0x1 << 2)
  1631. #define RT5651_GP1_OUT_MASK (0x1 << 1)
  1632. #define RT5651_GP1_OUT_SFT 1
  1633. #define RT5651_GP1_OUT_LO (0x0 << 1)
  1634. #define RT5651_GP1_OUT_HI (0x1 << 1)
  1635. #define RT5651_GP1_P_MASK (0x1)
  1636. #define RT5651_GP1_P_SFT 0
  1637. #define RT5651_GP1_P_NOR (0x0)
  1638. #define RT5651_GP1_P_INV (0x1)
  1639. /* GPIO Control 3 (0xc2) */
  1640. #define RT5651_GP8_DR_MASK (0x1 << 8)
  1641. #define RT5651_GP8_DR_SFT 8
  1642. #define RT5651_GP8_DR_IN (0x0 << 8)
  1643. #define RT5651_GP8_DR_OUT (0x1 << 8)
  1644. #define RT5651_GP8_OUT_MASK (0x1 << 7)
  1645. #define RT5651_GP8_OUT_SFT 7
  1646. #define RT5651_GP8_OUT_LO (0x0 << 7)
  1647. #define RT5651_GP8_OUT_HI (0x1 << 7)
  1648. #define RT5651_GP8_P_MASK (0x1 << 6)
  1649. #define RT5651_GP8_P_SFT 6
  1650. #define RT5651_GP8_P_NOR (0x0 << 6)
  1651. #define RT5651_GP8_P_INV (0x1 << 6)
  1652. #define RT5651_GP7_DR_MASK (0x1 << 5)
  1653. #define RT5651_GP7_DR_SFT 5
  1654. #define RT5651_GP7_DR_IN (0x0 << 5)
  1655. #define RT5651_GP7_DR_OUT (0x1 << 5)
  1656. #define RT5651_GP7_OUT_MASK (0x1 << 4)
  1657. #define RT5651_GP7_OUT_SFT 4
  1658. #define RT5651_GP7_OUT_LO (0x0 << 4)
  1659. #define RT5651_GP7_OUT_HI (0x1 << 4)
  1660. #define RT5651_GP7_P_MASK (0x1 << 3)
  1661. #define RT5651_GP7_P_SFT 3
  1662. #define RT5651_GP7_P_NOR (0x0 << 3)
  1663. #define RT5651_GP7_P_INV (0x1 << 3)
  1664. #define RT5651_GP6_DR_MASK (0x1 << 2)
  1665. #define RT5651_GP6_DR_SFT 2
  1666. #define RT5651_GP6_DR_IN (0x0 << 2)
  1667. #define RT5651_GP6_DR_OUT (0x1 << 2)
  1668. #define RT5651_GP6_OUT_MASK (0x1 << 1)
  1669. #define RT5651_GP6_OUT_SFT 1
  1670. #define RT5651_GP6_OUT_LO (0x0 << 1)
  1671. #define RT5651_GP6_OUT_HI (0x1 << 1)
  1672. #define RT5651_GP6_P_MASK (0x1)
  1673. #define RT5651_GP6_P_SFT 0
  1674. #define RT5651_GP6_P_NOR (0x0)
  1675. #define RT5651_GP6_P_INV (0x1)
  1676. /* Scramble Control (0xce) */
  1677. #define RT5651_SCB_SWAP_MASK (0x1 << 15)
  1678. #define RT5651_SCB_SWAP_SFT 15
  1679. #define RT5651_SCB_SWAP_DIS (0x0 << 15)
  1680. #define RT5651_SCB_SWAP_EN (0x1 << 15)
  1681. #define RT5651_SCB_MASK (0x1 << 14)
  1682. #define RT5651_SCB_SFT 14
  1683. #define RT5651_SCB_DIS (0x0 << 14)
  1684. #define RT5651_SCB_EN (0x1 << 14)
  1685. /* Baseback Control (0xcf) */
  1686. #define RT5651_BB_MASK (0x1 << 15)
  1687. #define RT5651_BB_SFT 15
  1688. #define RT5651_BB_DIS (0x0 << 15)
  1689. #define RT5651_BB_EN (0x1 << 15)
  1690. #define RT5651_BB_CT_MASK (0x7 << 12)
  1691. #define RT5651_BB_CT_SFT 12
  1692. #define RT5651_BB_CT_A (0x0 << 12)
  1693. #define RT5651_BB_CT_B (0x1 << 12)
  1694. #define RT5651_BB_CT_C (0x2 << 12)
  1695. #define RT5651_BB_CT_D (0x3 << 12)
  1696. #define RT5651_M_BB_L_MASK (0x1 << 9)
  1697. #define RT5651_M_BB_L_SFT 9
  1698. #define RT5651_M_BB_R_MASK (0x1 << 8)
  1699. #define RT5651_M_BB_R_SFT 8
  1700. #define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
  1701. #define RT5651_M_BB_HPF_L_SFT 7
  1702. #define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
  1703. #define RT5651_M_BB_HPF_R_SFT 6
  1704. #define RT5651_G_BB_BST_MASK (0x3f)
  1705. #define RT5651_G_BB_BST_SFT 0
  1706. /* MP3 Plus Control 1 (0xd0) */
  1707. #define RT5651_M_MP3_L_MASK (0x1 << 15)
  1708. #define RT5651_M_MP3_L_SFT 15
  1709. #define RT5651_M_MP3_R_MASK (0x1 << 14)
  1710. #define RT5651_M_MP3_R_SFT 14
  1711. #define RT5651_M_MP3_MASK (0x1 << 13)
  1712. #define RT5651_M_MP3_SFT 13
  1713. #define RT5651_M_MP3_DIS (0x0 << 13)
  1714. #define RT5651_M_MP3_EN (0x1 << 13)
  1715. #define RT5651_EG_MP3_MASK (0x1f << 8)
  1716. #define RT5651_EG_MP3_SFT 8
  1717. #define RT5651_MP3_HLP_MASK (0x1 << 7)
  1718. #define RT5651_MP3_HLP_SFT 7
  1719. #define RT5651_MP3_HLP_DIS (0x0 << 7)
  1720. #define RT5651_MP3_HLP_EN (0x1 << 7)
  1721. #define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
  1722. #define RT5651_M_MP3_ORG_L_SFT 6
  1723. #define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
  1724. #define RT5651_M_MP3_ORG_R_SFT 5
  1725. /* MP3 Plus Control 2 (0xd1) */
  1726. #define RT5651_MP3_WT_MASK (0x1 << 13)
  1727. #define RT5651_MP3_WT_SFT 13
  1728. #define RT5651_MP3_WT_1_4 (0x0 << 13)
  1729. #define RT5651_MP3_WT_1_2 (0x1 << 13)
  1730. #define RT5651_OG_MP3_MASK (0x1f << 8)
  1731. #define RT5651_OG_MP3_SFT 8
  1732. #define RT5651_HG_MP3_MASK (0x3f)
  1733. #define RT5651_HG_MP3_SFT 0
  1734. /* 3D HP Control 1 (0xd2) */
  1735. #define RT5651_3D_CF_MASK (0x1 << 15)
  1736. #define RT5651_3D_CF_SFT 15
  1737. #define RT5651_3D_CF_DIS (0x0 << 15)
  1738. #define RT5651_3D_CF_EN (0x1 << 15)
  1739. #define RT5651_3D_HP_MASK (0x1 << 14)
  1740. #define RT5651_3D_HP_SFT 14
  1741. #define RT5651_3D_HP_DIS (0x0 << 14)
  1742. #define RT5651_3D_HP_EN (0x1 << 14)
  1743. #define RT5651_3D_BT_MASK (0x1 << 13)
  1744. #define RT5651_3D_BT_SFT 13
  1745. #define RT5651_3D_BT_DIS (0x0 << 13)
  1746. #define RT5651_3D_BT_EN (0x1 << 13)
  1747. #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
  1748. #define RT5651_3D_1F_MIX_SFT 11
  1749. #define RT5651_3D_HP_M_MASK (0x1 << 10)
  1750. #define RT5651_3D_HP_M_SFT 10
  1751. #define RT5651_3D_HP_M_SUR (0x0 << 10)
  1752. #define RT5651_3D_HP_M_FRO (0x1 << 10)
  1753. #define RT5651_M_3D_HRTF_MASK (0x1 << 9)
  1754. #define RT5651_M_3D_HRTF_SFT 9
  1755. #define RT5651_M_3D_D2H_MASK (0x1 << 8)
  1756. #define RT5651_M_3D_D2H_SFT 8
  1757. #define RT5651_M_3D_D2R_MASK (0x1 << 7)
  1758. #define RT5651_M_3D_D2R_SFT 7
  1759. #define RT5651_M_3D_REVB_MASK (0x1 << 6)
  1760. #define RT5651_M_3D_REVB_SFT 6
  1761. /* Adjustable high pass filter control 1 (0xd3) */
  1762. #define RT5651_2ND_HPF_MASK (0x1 << 15)
  1763. #define RT5651_2ND_HPF_SFT 15
  1764. #define RT5651_2ND_HPF_DIS (0x0 << 15)
  1765. #define RT5651_2ND_HPF_EN (0x1 << 15)
  1766. #define RT5651_HPF_CF_L_MASK (0x7 << 12)
  1767. #define RT5651_HPF_CF_L_SFT 12
  1768. #define RT5651_HPF_CF_R_MASK (0x7 << 8)
  1769. #define RT5651_HPF_CF_R_SFT 8
  1770. #define RT5651_ZD_T_MASK (0x3 << 6)
  1771. #define RT5651_ZD_T_SFT 6
  1772. #define RT5651_ZD_F_MASK (0x3 << 4)
  1773. #define RT5651_ZD_F_SFT 4
  1774. #define RT5651_ZD_F_IM (0x0 << 4)
  1775. #define RT5651_ZD_F_ZC_IM (0x1 << 4)
  1776. #define RT5651_ZD_F_ZC_IOD (0x2 << 4)
  1777. #define RT5651_ZD_F_UN (0x3 << 4)
  1778. /* Adjustable high pass filter control 2 (0xd4) */
  1779. #define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
  1780. #define RT5651_HPF_CF_L_NUM_SFT 8
  1781. #define RT5651_HPF_CF_R_NUM_MASK (0x3f)
  1782. #define RT5651_HPF_CF_R_NUM_SFT 0
  1783. /* HP calibration control and Amp detection (0xd6) */
  1784. #define RT5651_SI_DAC_MASK (0x1 << 11)
  1785. #define RT5651_SI_DAC_SFT 11
  1786. #define RT5651_SI_DAC_AUTO (0x0 << 11)
  1787. #define RT5651_SI_DAC_TEST (0x1 << 11)
  1788. #define RT5651_DC_CAL_M_MASK (0x1 << 10)
  1789. #define RT5651_DC_CAL_M_SFT 10
  1790. #define RT5651_DC_CAL_M_NOR (0x0 << 10)
  1791. #define RT5651_DC_CAL_M_CAL (0x1 << 10)
  1792. #define RT5651_DC_CAL_MASK (0x1 << 9)
  1793. #define RT5651_DC_CAL_SFT 9
  1794. #define RT5651_DC_CAL_DIS (0x0 << 9)
  1795. #define RT5651_DC_CAL_EN (0x1 << 9)
  1796. #define RT5651_HPD_RCV_MASK (0x7 << 6)
  1797. #define RT5651_HPD_RCV_SFT 6
  1798. #define RT5651_HPD_PS_MASK (0x1 << 5)
  1799. #define RT5651_HPD_PS_SFT 5
  1800. #define RT5651_HPD_PS_DIS (0x0 << 5)
  1801. #define RT5651_HPD_PS_EN (0x1 << 5)
  1802. #define RT5651_CAL_M_MASK (0x1 << 4)
  1803. #define RT5651_CAL_M_SFT 4
  1804. #define RT5651_CAL_M_DEP (0x0 << 4)
  1805. #define RT5651_CAL_M_CAL (0x1 << 4)
  1806. #define RT5651_CAL_MASK (0x1 << 3)
  1807. #define RT5651_CAL_SFT 3
  1808. #define RT5651_CAL_DIS (0x0 << 3)
  1809. #define RT5651_CAL_EN (0x1 << 3)
  1810. #define RT5651_CAL_TEST_MASK (0x1 << 2)
  1811. #define RT5651_CAL_TEST_SFT 2
  1812. #define RT5651_CAL_TEST_DIS (0x0 << 2)
  1813. #define RT5651_CAL_TEST_EN (0x1 << 2)
  1814. #define RT5651_CAL_P_MASK (0x3)
  1815. #define RT5651_CAL_P_SFT 0
  1816. #define RT5651_CAL_P_NONE (0x0)
  1817. #define RT5651_CAL_P_CAL (0x1)
  1818. #define RT5651_CAL_P_DAC_CAL (0x2)
  1819. /* Soft volume and zero cross control 1 (0xd9) */
  1820. #define RT5651_SV_MASK (0x1 << 15)
  1821. #define RT5651_SV_SFT 15
  1822. #define RT5651_SV_DIS (0x0 << 15)
  1823. #define RT5651_SV_EN (0x1 << 15)
  1824. #define RT5651_OUT_SV_MASK (0x1 << 13)
  1825. #define RT5651_OUT_SV_SFT 13
  1826. #define RT5651_OUT_SV_DIS (0x0 << 13)
  1827. #define RT5651_OUT_SV_EN (0x1 << 13)
  1828. #define RT5651_HP_SV_MASK (0x1 << 12)
  1829. #define RT5651_HP_SV_SFT 12
  1830. #define RT5651_HP_SV_DIS (0x0 << 12)
  1831. #define RT5651_HP_SV_EN (0x1 << 12)
  1832. #define RT5651_ZCD_DIG_MASK (0x1 << 11)
  1833. #define RT5651_ZCD_DIG_SFT 11
  1834. #define RT5651_ZCD_DIG_DIS (0x0 << 11)
  1835. #define RT5651_ZCD_DIG_EN (0x1 << 11)
  1836. #define RT5651_ZCD_MASK (0x1 << 10)
  1837. #define RT5651_ZCD_SFT 10
  1838. #define RT5651_ZCD_PD (0x0 << 10)
  1839. #define RT5651_ZCD_PU (0x1 << 10)
  1840. #define RT5651_M_ZCD_MASK (0x3f << 4)
  1841. #define RT5651_M_ZCD_SFT 4
  1842. #define RT5651_M_ZCD_OM_L (0x1 << 7)
  1843. #define RT5651_M_ZCD_OM_R (0x1 << 6)
  1844. #define RT5651_M_ZCD_RM_L (0x1 << 5)
  1845. #define RT5651_M_ZCD_RM_R (0x1 << 4)
  1846. #define RT5651_SV_DLY_MASK (0xf)
  1847. #define RT5651_SV_DLY_SFT 0
  1848. /* Soft volume and zero cross control 2 (0xda) */
  1849. #define RT5651_ZCD_HP_MASK (0x1 << 15)
  1850. #define RT5651_ZCD_HP_SFT 15
  1851. #define RT5651_ZCD_HP_DIS (0x0 << 15)
  1852. #define RT5651_ZCD_HP_EN (0x1 << 15)
  1853. /* Digital Misc Control (0xfa) */
  1854. #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
  1855. #define RT5651_I2S2_MS_SP_SEL 8
  1856. #define RT5651_I2S2_MS_SP_64 (0x0 << 8)
  1857. #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
  1858. #define RT5651_CLK_DET_EN (0x1 << 3)
  1859. #define RT5651_CLK_DET_EN_SFT 3
  1860. #define RT5651_AMP_DET_EN (0x1 << 1)
  1861. #define RT5651_AMP_DET_EN_SFT 1
  1862. #define RT5651_D_GATE_EN (0x1)
  1863. #define RT5651_D_GATE_EN_SFT 0
  1864. /* Codec Private Register definition */
  1865. /* MIC Over current threshold scale factor (0x15) */
  1866. #define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
  1867. #define RT5651_MIC_OVCD_SF_SFT 8
  1868. #define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
  1869. #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
  1870. #define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
  1871. #define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
  1872. /* 3D Speaker Control (0x63) */
  1873. #define RT5651_3D_SPK_MASK (0x1 << 15)
  1874. #define RT5651_3D_SPK_SFT 15
  1875. #define RT5651_3D_SPK_DIS (0x0 << 15)
  1876. #define RT5651_3D_SPK_EN (0x1 << 15)
  1877. #define RT5651_3D_SPK_M_MASK (0x3 << 13)
  1878. #define RT5651_3D_SPK_M_SFT 13
  1879. #define RT5651_3D_SPK_CG_MASK (0x1f << 8)
  1880. #define RT5651_3D_SPK_CG_SFT 8
  1881. #define RT5651_3D_SPK_SG_MASK (0x1f)
  1882. #define RT5651_3D_SPK_SG_SFT 0
  1883. /* Wind Noise Detection Control 1 (0x6c) */
  1884. #define RT5651_WND_MASK (0x1 << 15)
  1885. #define RT5651_WND_SFT 15
  1886. #define RT5651_WND_DIS (0x0 << 15)
  1887. #define RT5651_WND_EN (0x1 << 15)
  1888. /* Wind Noise Detection Control 2 (0x6d) */
  1889. #define RT5651_WND_FC_NW_MASK (0x3f << 10)
  1890. #define RT5651_WND_FC_NW_SFT 10
  1891. #define RT5651_WND_FC_WK_MASK (0x3f << 4)
  1892. #define RT5651_WND_FC_WK_SFT 4
  1893. /* Wind Noise Detection Control 3 (0x6e) */
  1894. #define RT5651_HPF_FC_MASK (0x3f << 6)
  1895. #define RT5651_HPF_FC_SFT 6
  1896. #define RT5651_WND_FC_ST_MASK (0x3f)
  1897. #define RT5651_WND_FC_ST_SFT 0
  1898. /* Wind Noise Detection Control 4 (0x6f) */
  1899. #define RT5651_WND_TH_LO_MASK (0x3ff)
  1900. #define RT5651_WND_TH_LO_SFT 0
  1901. /* Wind Noise Detection Control 5 (0x70) */
  1902. #define RT5651_WND_TH_HI_MASK (0x3ff)
  1903. #define RT5651_WND_TH_HI_SFT 0
  1904. /* Wind Noise Detection Control 8 (0x73) */
  1905. #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
  1906. #define RT5651_WND_WIND_SFT 13
  1907. #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
  1908. #define RT5651_WND_STRONG_SFT 12
  1909. enum {
  1910. RT5651_NO_WIND,
  1911. RT5651_BREEZE,
  1912. RT5651_STORM,
  1913. };
  1914. /* Dipole Speaker Interface (0x75) */
  1915. #define RT5651_DP_ATT_MASK (0x3 << 14)
  1916. #define RT5651_DP_ATT_SFT 14
  1917. #define RT5651_DP_SPK_MASK (0x1 << 10)
  1918. #define RT5651_DP_SPK_SFT 10
  1919. #define RT5651_DP_SPK_DIS (0x0 << 10)
  1920. #define RT5651_DP_SPK_EN (0x1 << 10)
  1921. /* EQ Pre Volume Control (0xb3) */
  1922. #define RT5651_EQ_PRE_VOL_MASK (0xffff)
  1923. #define RT5651_EQ_PRE_VOL_SFT 0
  1924. /* EQ Post Volume Control (0xb4) */
  1925. #define RT5651_EQ_PST_VOL_MASK (0xffff)
  1926. #define RT5651_EQ_PST_VOL_SFT 0
  1927. /* System Clock Source */
  1928. enum {
  1929. RT5651_SCLK_S_MCLK,
  1930. RT5651_SCLK_S_PLL1,
  1931. RT5651_SCLK_S_RCCLK,
  1932. };
  1933. /* PLL1 Source */
  1934. enum {
  1935. RT5651_PLL1_S_MCLK,
  1936. RT5651_PLL1_S_BCLK1,
  1937. RT5651_PLL1_S_BCLK2,
  1938. };
  1939. enum {
  1940. RT5651_AIF1,
  1941. RT5651_AIF2,
  1942. RT5651_AIFS,
  1943. };
  1944. struct rt5651_pll_code {
  1945. bool m_bp; /* Indicates bypass m code or not. */
  1946. int m_code;
  1947. int n_code;
  1948. int k_code;
  1949. };
  1950. struct rt5651_priv {
  1951. struct snd_soc_component *component;
  1952. struct regmap *regmap;
  1953. /* Jack and button detect data */
  1954. struct snd_soc_jack *hp_jack;
  1955. struct gpio_desc *gpiod_hp_det;
  1956. struct work_struct jack_detect_work;
  1957. struct delayed_work bp_work;
  1958. bool ovcd_irq_enabled;
  1959. bool pressed;
  1960. bool press_reported;
  1961. int press_count;
  1962. int release_count;
  1963. int poll_count;
  1964. unsigned int jd_src;
  1965. bool jd_active_high;
  1966. unsigned int ovcd_th;
  1967. unsigned int ovcd_sf;
  1968. int irq;
  1969. int sysclk;
  1970. int sysclk_src;
  1971. int lrck[RT5651_AIFS];
  1972. int bclk[RT5651_AIFS];
  1973. int master[RT5651_AIFS];
  1974. int pll_src;
  1975. int pll_in;
  1976. int pll_out;
  1977. int dmic_en;
  1978. bool hp_mute;
  1979. };
  1980. #endif /* __RT5651_H__ */