rt5651.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5651.c -- RT5651 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2014 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/delay.h>
  11. #include <linux/pm.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/i2c.h>
  14. #include <linux/regmap.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/acpi.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <sound/jack.h>
  26. #include "rl6231.h"
  27. #include "rt5651.h"
  28. #define RT5651_DEVICE_ID_VALUE 0x6281
  29. #define RT5651_PR_RANGE_BASE (0xff + 1)
  30. #define RT5651_PR_SPACING 0x100
  31. #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
  32. static const struct regmap_range_cfg rt5651_ranges[] = {
  33. { .name = "PR", .range_min = RT5651_PR_BASE,
  34. .range_max = RT5651_PR_BASE + 0xb4,
  35. .selector_reg = RT5651_PRIV_INDEX,
  36. .selector_mask = 0xff,
  37. .selector_shift = 0x0,
  38. .window_start = RT5651_PRIV_DATA,
  39. .window_len = 0x1, },
  40. };
  41. static const struct reg_sequence init_list[] = {
  42. {RT5651_PR_BASE + 0x3d, 0x3e00},
  43. };
  44. static const struct reg_default rt5651_reg[] = {
  45. { 0x00, 0x0000 },
  46. { 0x02, 0xc8c8 },
  47. { 0x03, 0xc8c8 },
  48. { 0x05, 0x0000 },
  49. { 0x0d, 0x0000 },
  50. { 0x0e, 0x0000 },
  51. { 0x0f, 0x0808 },
  52. { 0x10, 0x0808 },
  53. { 0x19, 0xafaf },
  54. { 0x1a, 0xafaf },
  55. { 0x1b, 0x0c00 },
  56. { 0x1c, 0x2f2f },
  57. { 0x1d, 0x2f2f },
  58. { 0x1e, 0x0000 },
  59. { 0x27, 0x7860 },
  60. { 0x28, 0x7070 },
  61. { 0x29, 0x8080 },
  62. { 0x2a, 0x5252 },
  63. { 0x2b, 0x5454 },
  64. { 0x2f, 0x0000 },
  65. { 0x30, 0x5000 },
  66. { 0x3b, 0x0000 },
  67. { 0x3c, 0x006f },
  68. { 0x3d, 0x0000 },
  69. { 0x3e, 0x006f },
  70. { 0x45, 0x6000 },
  71. { 0x4d, 0x0000 },
  72. { 0x4e, 0x0000 },
  73. { 0x4f, 0x0279 },
  74. { 0x50, 0x0000 },
  75. { 0x51, 0x0000 },
  76. { 0x52, 0x0279 },
  77. { 0x53, 0xf000 },
  78. { 0x61, 0x0000 },
  79. { 0x62, 0x0000 },
  80. { 0x63, 0x00c0 },
  81. { 0x64, 0x0000 },
  82. { 0x65, 0x0000 },
  83. { 0x66, 0x0000 },
  84. { 0x70, 0x8000 },
  85. { 0x71, 0x8000 },
  86. { 0x73, 0x1104 },
  87. { 0x74, 0x0c00 },
  88. { 0x75, 0x1400 },
  89. { 0x77, 0x0c00 },
  90. { 0x78, 0x4000 },
  91. { 0x79, 0x0123 },
  92. { 0x80, 0x0000 },
  93. { 0x81, 0x0000 },
  94. { 0x82, 0x0000 },
  95. { 0x83, 0x0800 },
  96. { 0x84, 0x0000 },
  97. { 0x85, 0x0008 },
  98. { 0x89, 0x0000 },
  99. { 0x8e, 0x0004 },
  100. { 0x8f, 0x1100 },
  101. { 0x90, 0x0000 },
  102. { 0x93, 0x2000 },
  103. { 0x94, 0x0200 },
  104. { 0xb0, 0x2080 },
  105. { 0xb1, 0x0000 },
  106. { 0xb4, 0x2206 },
  107. { 0xb5, 0x1f00 },
  108. { 0xb6, 0x0000 },
  109. { 0xbb, 0x0000 },
  110. { 0xbc, 0x0000 },
  111. { 0xbd, 0x0000 },
  112. { 0xbe, 0x0000 },
  113. { 0xbf, 0x0000 },
  114. { 0xc0, 0x0400 },
  115. { 0xc1, 0x0000 },
  116. { 0xc2, 0x0000 },
  117. { 0xcf, 0x0013 },
  118. { 0xd0, 0x0680 },
  119. { 0xd1, 0x1c17 },
  120. { 0xd3, 0xb320 },
  121. { 0xd9, 0x0809 },
  122. { 0xfa, 0x0010 },
  123. { 0xfe, 0x10ec },
  124. { 0xff, 0x6281 },
  125. };
  126. static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
  127. {
  128. int i;
  129. for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
  130. if ((reg >= rt5651_ranges[i].window_start &&
  131. reg <= rt5651_ranges[i].window_start +
  132. rt5651_ranges[i].window_len) ||
  133. (reg >= rt5651_ranges[i].range_min &&
  134. reg <= rt5651_ranges[i].range_max)) {
  135. return true;
  136. }
  137. }
  138. switch (reg) {
  139. case RT5651_RESET:
  140. case RT5651_PRIV_DATA:
  141. case RT5651_EQ_CTRL1:
  142. case RT5651_ALC_1:
  143. case RT5651_IRQ_CTRL2:
  144. case RT5651_INT_IRQ_ST:
  145. case RT5651_PGM_REG_ARR1:
  146. case RT5651_PGM_REG_ARR3:
  147. case RT5651_VENDOR_ID:
  148. case RT5651_DEVICE_ID:
  149. return true;
  150. default:
  151. return false;
  152. }
  153. }
  154. static bool rt5651_readable_register(struct device *dev, unsigned int reg)
  155. {
  156. int i;
  157. for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
  158. if ((reg >= rt5651_ranges[i].window_start &&
  159. reg <= rt5651_ranges[i].window_start +
  160. rt5651_ranges[i].window_len) ||
  161. (reg >= rt5651_ranges[i].range_min &&
  162. reg <= rt5651_ranges[i].range_max)) {
  163. return true;
  164. }
  165. }
  166. switch (reg) {
  167. case RT5651_RESET:
  168. case RT5651_VERSION_ID:
  169. case RT5651_VENDOR_ID:
  170. case RT5651_DEVICE_ID:
  171. case RT5651_HP_VOL:
  172. case RT5651_LOUT_CTRL1:
  173. case RT5651_LOUT_CTRL2:
  174. case RT5651_IN1_IN2:
  175. case RT5651_IN3:
  176. case RT5651_INL1_INR1_VOL:
  177. case RT5651_INL2_INR2_VOL:
  178. case RT5651_DAC1_DIG_VOL:
  179. case RT5651_DAC2_DIG_VOL:
  180. case RT5651_DAC2_CTRL:
  181. case RT5651_ADC_DIG_VOL:
  182. case RT5651_ADC_DATA:
  183. case RT5651_ADC_BST_VOL:
  184. case RT5651_STO1_ADC_MIXER:
  185. case RT5651_STO2_ADC_MIXER:
  186. case RT5651_AD_DA_MIXER:
  187. case RT5651_STO_DAC_MIXER:
  188. case RT5651_DD_MIXER:
  189. case RT5651_DIG_INF_DATA:
  190. case RT5651_PDM_CTL:
  191. case RT5651_REC_L1_MIXER:
  192. case RT5651_REC_L2_MIXER:
  193. case RT5651_REC_R1_MIXER:
  194. case RT5651_REC_R2_MIXER:
  195. case RT5651_HPO_MIXER:
  196. case RT5651_OUT_L1_MIXER:
  197. case RT5651_OUT_L2_MIXER:
  198. case RT5651_OUT_L3_MIXER:
  199. case RT5651_OUT_R1_MIXER:
  200. case RT5651_OUT_R2_MIXER:
  201. case RT5651_OUT_R3_MIXER:
  202. case RT5651_LOUT_MIXER:
  203. case RT5651_PWR_DIG1:
  204. case RT5651_PWR_DIG2:
  205. case RT5651_PWR_ANLG1:
  206. case RT5651_PWR_ANLG2:
  207. case RT5651_PWR_MIXER:
  208. case RT5651_PWR_VOL:
  209. case RT5651_PRIV_INDEX:
  210. case RT5651_PRIV_DATA:
  211. case RT5651_I2S1_SDP:
  212. case RT5651_I2S2_SDP:
  213. case RT5651_ADDA_CLK1:
  214. case RT5651_ADDA_CLK2:
  215. case RT5651_DMIC:
  216. case RT5651_TDM_CTL_1:
  217. case RT5651_TDM_CTL_2:
  218. case RT5651_TDM_CTL_3:
  219. case RT5651_GLB_CLK:
  220. case RT5651_PLL_CTRL1:
  221. case RT5651_PLL_CTRL2:
  222. case RT5651_PLL_MODE_1:
  223. case RT5651_PLL_MODE_2:
  224. case RT5651_PLL_MODE_3:
  225. case RT5651_PLL_MODE_4:
  226. case RT5651_PLL_MODE_5:
  227. case RT5651_PLL_MODE_6:
  228. case RT5651_PLL_MODE_7:
  229. case RT5651_DEPOP_M1:
  230. case RT5651_DEPOP_M2:
  231. case RT5651_DEPOP_M3:
  232. case RT5651_CHARGE_PUMP:
  233. case RT5651_MICBIAS:
  234. case RT5651_A_JD_CTL1:
  235. case RT5651_EQ_CTRL1:
  236. case RT5651_EQ_CTRL2:
  237. case RT5651_ALC_1:
  238. case RT5651_ALC_2:
  239. case RT5651_ALC_3:
  240. case RT5651_JD_CTRL1:
  241. case RT5651_JD_CTRL2:
  242. case RT5651_IRQ_CTRL1:
  243. case RT5651_IRQ_CTRL2:
  244. case RT5651_INT_IRQ_ST:
  245. case RT5651_GPIO_CTRL1:
  246. case RT5651_GPIO_CTRL2:
  247. case RT5651_GPIO_CTRL3:
  248. case RT5651_PGM_REG_ARR1:
  249. case RT5651_PGM_REG_ARR2:
  250. case RT5651_PGM_REG_ARR3:
  251. case RT5651_PGM_REG_ARR4:
  252. case RT5651_PGM_REG_ARR5:
  253. case RT5651_SCB_FUNC:
  254. case RT5651_SCB_CTRL:
  255. case RT5651_BASE_BACK:
  256. case RT5651_MP3_PLUS1:
  257. case RT5651_MP3_PLUS2:
  258. case RT5651_ADJ_HPF_CTRL1:
  259. case RT5651_ADJ_HPF_CTRL2:
  260. case RT5651_HP_CALIB_AMP_DET:
  261. case RT5651_HP_CALIB2:
  262. case RT5651_SV_ZCD1:
  263. case RT5651_SV_ZCD2:
  264. case RT5651_D_MISC:
  265. case RT5651_DUMMY2:
  266. case RT5651_DUMMY3:
  267. return true;
  268. default:
  269. return false;
  270. }
  271. }
  272. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
  273. static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
  274. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
  275. static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
  276. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  277. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  278. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  279. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  280. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  281. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  282. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  283. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  284. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  285. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  286. );
  287. /* Interface data select */
  288. static const char * const rt5651_data_select[] = {
  289. "Normal", "Swap", "left copy to right", "right copy to left"};
  290. static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
  291. RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
  292. static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
  293. RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
  294. static const struct snd_kcontrol_new rt5651_snd_controls[] = {
  295. /* Headphone Output Volume */
  296. SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
  297. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
  298. /* OUTPUT Control */
  299. SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
  300. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
  301. /* DAC Digital Volume */
  302. SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
  303. RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
  304. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
  305. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  306. 175, 0, dac_vol_tlv),
  307. SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
  308. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  309. 175, 0, dac_vol_tlv),
  310. /* IN1/IN2/IN3 Control */
  311. SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
  312. RT5651_BST_SFT1, 8, 0, bst_tlv),
  313. SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
  314. RT5651_BST_SFT2, 8, 0, bst_tlv),
  315. SOC_SINGLE_TLV("IN3 Boost", RT5651_IN3,
  316. RT5651_BST_SFT1, 8, 0, bst_tlv),
  317. /* INL/INR Volume Control */
  318. SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
  319. RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
  320. 31, 1, in_vol_tlv),
  321. /* ADC Digital Volume Control */
  322. SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
  323. RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
  324. SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
  325. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  326. 127, 0, adc_vol_tlv),
  327. SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
  328. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  329. 127, 0, adc_vol_tlv),
  330. /* ADC Boost Volume Control */
  331. SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
  332. RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
  333. 3, 0, adc_bst_tlv),
  334. /* ASRC */
  335. SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
  336. RT5651_STO1_T_SFT, 1, 0),
  337. SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
  338. RT5651_STO2_T_SFT, 1, 0),
  339. SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
  340. RT5651_DMIC_1_M_SFT, 1, 0),
  341. SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
  342. SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
  343. };
  344. /**
  345. * set_dmic_clk - Set parameter of dmic.
  346. *
  347. * @w: DAPM widget.
  348. * @kcontrol: The kcontrol of this widget.
  349. * @event: Event id.
  350. *
  351. */
  352. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  353. struct snd_kcontrol *kcontrol, int event)
  354. {
  355. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  356. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  357. int idx, rate;
  358. rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
  359. RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
  360. idx = rl6231_calc_dmic_clk(rate);
  361. if (idx < 0)
  362. dev_err(component->dev, "Failed to set DMIC clock\n");
  363. else
  364. snd_soc_component_update_bits(component, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
  365. idx << RT5651_DMIC_CLK_SFT);
  366. return idx;
  367. }
  368. /* Digital Mixer */
  369. static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
  370. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
  371. RT5651_M_STO1_ADC_L1_SFT, 1, 1),
  372. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
  373. RT5651_M_STO1_ADC_L2_SFT, 1, 1),
  374. };
  375. static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
  376. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
  377. RT5651_M_STO1_ADC_R1_SFT, 1, 1),
  378. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
  379. RT5651_M_STO1_ADC_R2_SFT, 1, 1),
  380. };
  381. static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
  382. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
  383. RT5651_M_STO2_ADC_L1_SFT, 1, 1),
  384. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
  385. RT5651_M_STO2_ADC_L2_SFT, 1, 1),
  386. };
  387. static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
  388. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
  389. RT5651_M_STO2_ADC_R1_SFT, 1, 1),
  390. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
  391. RT5651_M_STO2_ADC_R2_SFT, 1, 1),
  392. };
  393. static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
  394. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
  395. RT5651_M_ADCMIX_L_SFT, 1, 1),
  396. SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
  397. RT5651_M_IF1_DAC_L_SFT, 1, 1),
  398. };
  399. static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
  400. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
  401. RT5651_M_ADCMIX_R_SFT, 1, 1),
  402. SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
  403. RT5651_M_IF1_DAC_R_SFT, 1, 1),
  404. };
  405. static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
  406. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
  407. RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
  408. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
  409. RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
  410. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
  411. RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
  412. };
  413. static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
  414. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
  415. RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
  416. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
  417. RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
  418. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
  419. RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
  420. };
  421. static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
  422. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
  423. RT5651_M_STO_DD_L1_SFT, 1, 1),
  424. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
  425. RT5651_M_STO_DD_L2_SFT, 1, 1),
  426. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
  427. RT5651_M_STO_DD_R2_L_SFT, 1, 1),
  428. };
  429. static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
  430. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
  431. RT5651_M_STO_DD_R1_SFT, 1, 1),
  432. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
  433. RT5651_M_STO_DD_R2_SFT, 1, 1),
  434. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
  435. RT5651_M_STO_DD_L2_R_SFT, 1, 1),
  436. };
  437. /* Analog Input Mixer */
  438. static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
  439. SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
  440. RT5651_M_IN1_L_RM_L_SFT, 1, 1),
  441. SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
  442. RT5651_M_BST3_RM_L_SFT, 1, 1),
  443. SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
  444. RT5651_M_BST2_RM_L_SFT, 1, 1),
  445. SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
  446. RT5651_M_BST1_RM_L_SFT, 1, 1),
  447. };
  448. static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
  449. SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
  450. RT5651_M_IN1_R_RM_R_SFT, 1, 1),
  451. SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
  452. RT5651_M_BST3_RM_R_SFT, 1, 1),
  453. SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
  454. RT5651_M_BST2_RM_R_SFT, 1, 1),
  455. SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
  456. RT5651_M_BST1_RM_R_SFT, 1, 1),
  457. };
  458. /* Analog Output Mixer */
  459. static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
  460. SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
  461. RT5651_M_BST1_OM_L_SFT, 1, 1),
  462. SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
  463. RT5651_M_BST2_OM_L_SFT, 1, 1),
  464. SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
  465. RT5651_M_IN1_L_OM_L_SFT, 1, 1),
  466. SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
  467. RT5651_M_RM_L_OM_L_SFT, 1, 1),
  468. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
  469. RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
  470. };
  471. static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
  472. SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
  473. RT5651_M_BST2_OM_R_SFT, 1, 1),
  474. SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
  475. RT5651_M_BST1_OM_R_SFT, 1, 1),
  476. SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
  477. RT5651_M_IN1_R_OM_R_SFT, 1, 1),
  478. SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
  479. RT5651_M_RM_R_OM_R_SFT, 1, 1),
  480. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
  481. RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
  482. };
  483. static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
  484. SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
  485. RT5651_M_DAC1_HM_SFT, 1, 1),
  486. SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
  487. RT5651_M_HPVOL_HM_SFT, 1, 1),
  488. };
  489. static const struct snd_kcontrol_new rt5651_lout_mix[] = {
  490. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
  491. RT5651_M_DAC_L1_LM_SFT, 1, 1),
  492. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
  493. RT5651_M_DAC_R1_LM_SFT, 1, 1),
  494. SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
  495. RT5651_M_OV_L_LM_SFT, 1, 1),
  496. SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
  497. RT5651_M_OV_R_LM_SFT, 1, 1),
  498. };
  499. static const struct snd_kcontrol_new outvol_l_control =
  500. SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
  501. RT5651_VOL_L_SFT, 1, 1);
  502. static const struct snd_kcontrol_new outvol_r_control =
  503. SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
  504. RT5651_VOL_R_SFT, 1, 1);
  505. static const struct snd_kcontrol_new lout_l_mute_control =
  506. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
  507. RT5651_L_MUTE_SFT, 1, 1);
  508. static const struct snd_kcontrol_new lout_r_mute_control =
  509. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
  510. RT5651_R_MUTE_SFT, 1, 1);
  511. static const struct snd_kcontrol_new hpovol_l_control =
  512. SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
  513. RT5651_VOL_L_SFT, 1, 1);
  514. static const struct snd_kcontrol_new hpovol_r_control =
  515. SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
  516. RT5651_VOL_R_SFT, 1, 1);
  517. static const struct snd_kcontrol_new hpo_l_mute_control =
  518. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
  519. RT5651_L_MUTE_SFT, 1, 1);
  520. static const struct snd_kcontrol_new hpo_r_mute_control =
  521. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
  522. RT5651_R_MUTE_SFT, 1, 1);
  523. /* Stereo ADC source */
  524. static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
  525. static SOC_ENUM_SINGLE_DECL(
  526. rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
  527. RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
  528. static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
  529. SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
  530. static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
  531. SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
  532. static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
  533. static SOC_ENUM_SINGLE_DECL(
  534. rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
  535. RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
  536. static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
  537. SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
  538. static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
  539. SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
  540. /* Mono ADC source */
  541. static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
  542. static SOC_ENUM_SINGLE_DECL(
  543. rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
  544. RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
  545. static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
  546. SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
  547. static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
  548. static SOC_ENUM_SINGLE_DECL(
  549. rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
  550. RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
  551. static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
  552. SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
  553. static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
  554. static SOC_ENUM_SINGLE_DECL(
  555. rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
  556. RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
  557. static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
  558. SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
  559. static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
  560. static SOC_ENUM_SINGLE_DECL(
  561. rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
  562. RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
  563. static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
  564. SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
  565. /* DAC2 channel source */
  566. static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
  567. static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
  568. RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
  569. static const struct snd_kcontrol_new rt5651_dac_l2_mux =
  570. SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
  571. static SOC_ENUM_SINGLE_DECL(
  572. rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
  573. RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
  574. static const struct snd_kcontrol_new rt5651_dac_r2_mux =
  575. SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
  576. /* IF2_ADC channel source */
  577. static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
  578. static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
  579. RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
  580. static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
  581. SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
  582. /* PDM select */
  583. static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
  584. static SOC_ENUM_SINGLE_DECL(
  585. rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
  586. RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
  587. static SOC_ENUM_SINGLE_DECL(
  588. rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
  589. RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
  590. static const struct snd_kcontrol_new rt5651_pdm_l_mux =
  591. SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
  592. static const struct snd_kcontrol_new rt5651_pdm_r_mux =
  593. SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
  594. static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
  595. struct snd_kcontrol *kcontrol, int event)
  596. {
  597. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  598. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  599. switch (event) {
  600. case SND_SOC_DAPM_POST_PMU:
  601. /* depop parameters */
  602. regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
  603. RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
  604. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
  605. RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
  606. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
  607. RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
  608. RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
  609. RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
  610. regmap_write(rt5651->regmap, RT5651_PR_BASE +
  611. RT5651_HP_DCC_INT1, 0x9f00);
  612. /* headphone amp power on */
  613. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  614. RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
  615. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  616. RT5651_PWR_HA,
  617. RT5651_PWR_HA);
  618. usleep_range(10000, 15000);
  619. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  620. RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
  621. RT5651_PWR_FV1 | RT5651_PWR_FV2);
  622. break;
  623. default:
  624. return 0;
  625. }
  626. return 0;
  627. }
  628. static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
  629. struct snd_kcontrol *kcontrol, int event)
  630. {
  631. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  632. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  633. switch (event) {
  634. case SND_SOC_DAPM_POST_PMU:
  635. /* headphone unmute sequence */
  636. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
  637. RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
  638. RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
  639. regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
  640. RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
  641. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
  642. RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
  643. RT5651_CP_FQ3_MASK,
  644. (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
  645. (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
  646. (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
  647. regmap_write(rt5651->regmap, RT5651_PR_BASE +
  648. RT5651_MAMP_INT_REG2, 0x1c00);
  649. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
  650. RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
  651. RT5651_HP_CP_PD | RT5651_HP_SG_EN);
  652. regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
  653. RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
  654. rt5651->hp_mute = false;
  655. break;
  656. case SND_SOC_DAPM_PRE_PMD:
  657. rt5651->hp_mute = true;
  658. usleep_range(70000, 75000);
  659. break;
  660. default:
  661. return 0;
  662. }
  663. return 0;
  664. }
  665. static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
  666. struct snd_kcontrol *kcontrol, int event)
  667. {
  668. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  669. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  670. switch (event) {
  671. case SND_SOC_DAPM_POST_PMU:
  672. if (!rt5651->hp_mute)
  673. usleep_range(80000, 85000);
  674. break;
  675. default:
  676. return 0;
  677. }
  678. return 0;
  679. }
  680. static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
  681. struct snd_kcontrol *kcontrol, int event)
  682. {
  683. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  684. switch (event) {
  685. case SND_SOC_DAPM_POST_PMU:
  686. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  687. RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
  688. break;
  689. case SND_SOC_DAPM_PRE_PMD:
  690. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  691. RT5651_PWR_BST1_OP2, 0);
  692. break;
  693. default:
  694. return 0;
  695. }
  696. return 0;
  697. }
  698. static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
  699. struct snd_kcontrol *kcontrol, int event)
  700. {
  701. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  702. switch (event) {
  703. case SND_SOC_DAPM_POST_PMU:
  704. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  705. RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
  706. break;
  707. case SND_SOC_DAPM_PRE_PMD:
  708. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  709. RT5651_PWR_BST2_OP2, 0);
  710. break;
  711. default:
  712. return 0;
  713. }
  714. return 0;
  715. }
  716. static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
  717. struct snd_kcontrol *kcontrol, int event)
  718. {
  719. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  720. switch (event) {
  721. case SND_SOC_DAPM_POST_PMU:
  722. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  723. RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
  724. break;
  725. case SND_SOC_DAPM_PRE_PMD:
  726. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  727. RT5651_PWR_BST3_OP2, 0);
  728. break;
  729. default:
  730. return 0;
  731. }
  732. return 0;
  733. }
  734. static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
  735. /* ASRC */
  736. SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
  737. 15, 0, NULL, 0),
  738. SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
  739. 14, 0, NULL, 0),
  740. SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
  741. 13, 0, NULL, 0),
  742. SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
  743. 12, 0, NULL, 0),
  744. SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
  745. 11, 0, NULL, 0),
  746. /* micbias */
  747. SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
  748. RT5651_PWR_LDO_BIT, 0, NULL, 0),
  749. SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2,
  750. RT5651_PWR_MB1_BIT, 0, NULL, 0),
  751. /* Input Lines */
  752. SND_SOC_DAPM_INPUT("MIC1"),
  753. SND_SOC_DAPM_INPUT("MIC2"),
  754. SND_SOC_DAPM_INPUT("MIC3"),
  755. SND_SOC_DAPM_INPUT("IN1P"),
  756. SND_SOC_DAPM_INPUT("IN2P"),
  757. SND_SOC_DAPM_INPUT("IN2N"),
  758. SND_SOC_DAPM_INPUT("IN3P"),
  759. SND_SOC_DAPM_INPUT("DMIC L1"),
  760. SND_SOC_DAPM_INPUT("DMIC R1"),
  761. SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
  762. 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  763. /* Boost */
  764. SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
  765. RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
  766. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  767. SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
  768. RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
  769. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  770. SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
  771. RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
  772. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  773. /* Input Volume */
  774. SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
  775. RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
  776. SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
  777. RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
  778. SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
  779. RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
  780. SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
  781. RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
  782. /* REC Mixer */
  783. SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
  784. rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
  785. SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
  786. rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
  787. /* ADCs */
  788. SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
  789. SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
  790. SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
  791. RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
  792. SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
  793. RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
  794. /* ADC Mux */
  795. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  796. &rt5651_sto1_adc_l2_mux),
  797. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  798. &rt5651_sto1_adc_r2_mux),
  799. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  800. &rt5651_sto1_adc_l1_mux),
  801. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  802. &rt5651_sto1_adc_r1_mux),
  803. SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  804. &rt5651_sto2_adc_l2_mux),
  805. SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  806. &rt5651_sto2_adc_l1_mux),
  807. SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  808. &rt5651_sto2_adc_r1_mux),
  809. SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  810. &rt5651_sto2_adc_r2_mux),
  811. /* ADC Mixer */
  812. SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
  813. RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
  814. SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
  815. RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
  816. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  817. rt5651_sto1_adc_l_mix,
  818. ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
  819. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  820. rt5651_sto1_adc_r_mix,
  821. ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
  822. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
  823. rt5651_sto2_adc_l_mix,
  824. ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
  825. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
  826. rt5651_sto2_adc_r_mix,
  827. ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
  828. /* Digital Interface */
  829. SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
  830. RT5651_PWR_I2S1_BIT, 0, NULL, 0),
  831. SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  832. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  833. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  834. SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  835. SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  836. SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  837. SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  838. SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
  839. RT5651_PWR_I2S2_BIT, 0, NULL, 0),
  840. SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  841. SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  842. SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  843. SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
  844. &rt5651_if2_adc_src_mux),
  845. /* Digital Interface Select */
  846. SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
  847. RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
  848. SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
  849. RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
  850. /* Audio Interface */
  851. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  852. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  853. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  854. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  855. /* Audio DSP */
  856. SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
  857. /* Output Side */
  858. /* DAC mixer before sound effect */
  859. SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
  860. rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
  861. SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
  862. rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
  863. /* DAC2 channel Mux */
  864. SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
  865. SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
  866. SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
  867. SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
  868. SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
  869. RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
  870. SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
  871. RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
  872. /* DAC Mixer */
  873. SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
  874. rt5651_sto_dac_l_mix,
  875. ARRAY_SIZE(rt5651_sto_dac_l_mix)),
  876. SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
  877. rt5651_sto_dac_r_mix,
  878. ARRAY_SIZE(rt5651_sto_dac_r_mix)),
  879. SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
  880. rt5651_dd_dac_l_mix,
  881. ARRAY_SIZE(rt5651_dd_dac_l_mix)),
  882. SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
  883. rt5651_dd_dac_r_mix,
  884. ARRAY_SIZE(rt5651_dd_dac_r_mix)),
  885. /* DACs */
  886. SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
  887. SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
  888. SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
  889. RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
  890. SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
  891. RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
  892. /* OUT Mixer */
  893. SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
  894. 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
  895. SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
  896. 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
  897. /* Ouput Volume */
  898. SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
  899. RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
  900. SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
  901. RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
  902. SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
  903. RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
  904. SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
  905. RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
  906. SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
  907. RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
  908. SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
  909. RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
  910. SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
  911. RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
  912. SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
  913. RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
  914. /* HPO/LOUT/Mono Mixer */
  915. SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
  916. rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
  917. SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
  918. rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
  919. SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
  920. RT5651_PWR_HP_L_BIT, 0, NULL, 0),
  921. SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
  922. RT5651_PWR_HP_R_BIT, 0, NULL, 0),
  923. SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
  924. rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
  925. SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
  926. RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
  927. SND_SOC_DAPM_POST_PMU),
  928. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
  929. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  930. SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
  931. &hpo_l_mute_control),
  932. SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
  933. &hpo_r_mute_control),
  934. SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
  935. &lout_l_mute_control),
  936. SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
  937. &lout_r_mute_control),
  938. SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
  939. /* Output Lines */
  940. SND_SOC_DAPM_OUTPUT("HPOL"),
  941. SND_SOC_DAPM_OUTPUT("HPOR"),
  942. SND_SOC_DAPM_OUTPUT("LOUTL"),
  943. SND_SOC_DAPM_OUTPUT("LOUTR"),
  944. SND_SOC_DAPM_OUTPUT("PDML"),
  945. SND_SOC_DAPM_OUTPUT("PDMR"),
  946. };
  947. static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
  948. {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
  949. {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
  950. {"I2S1", NULL, "I2S1 ASRC"},
  951. {"I2S2", NULL, "I2S2 ASRC"},
  952. {"IN1P", NULL, "LDO"},
  953. {"IN2P", NULL, "LDO"},
  954. {"IN3P", NULL, "LDO"},
  955. {"IN1P", NULL, "MIC1"},
  956. {"IN2P", NULL, "MIC2"},
  957. {"IN2N", NULL, "MIC2"},
  958. {"IN3P", NULL, "MIC3"},
  959. {"BST1", NULL, "IN1P"},
  960. {"BST2", NULL, "IN2P"},
  961. {"BST2", NULL, "IN2N"},
  962. {"BST3", NULL, "IN3P"},
  963. {"INL1 VOL", NULL, "IN2P"},
  964. {"INR1 VOL", NULL, "IN2N"},
  965. {"RECMIXL", "INL1 Switch", "INL1 VOL"},
  966. {"RECMIXL", "BST3 Switch", "BST3"},
  967. {"RECMIXL", "BST2 Switch", "BST2"},
  968. {"RECMIXL", "BST1 Switch", "BST1"},
  969. {"RECMIXR", "INR1 Switch", "INR1 VOL"},
  970. {"RECMIXR", "BST3 Switch", "BST3"},
  971. {"RECMIXR", "BST2 Switch", "BST2"},
  972. {"RECMIXR", "BST1 Switch", "BST1"},
  973. {"ADC L", NULL, "RECMIXL"},
  974. {"ADC L", NULL, "ADC L Power"},
  975. {"ADC R", NULL, "RECMIXR"},
  976. {"ADC R", NULL, "ADC R Power"},
  977. {"DMIC L1", NULL, "DMIC CLK"},
  978. {"DMIC R1", NULL, "DMIC CLK"},
  979. {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
  980. {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
  981. {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
  982. {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
  983. {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
  984. {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
  985. {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
  986. {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
  987. {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
  988. {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
  989. {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
  990. {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
  991. {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
  992. {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
  993. {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
  994. {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
  995. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  996. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  997. {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
  998. {"Stereo1 Filter", NULL, "ADC ASRC"},
  999. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  1000. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  1001. {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
  1002. {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
  1003. {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
  1004. {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
  1005. {"Stereo2 Filter", NULL, "ADC ASRC"},
  1006. {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
  1007. {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
  1008. {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
  1009. {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
  1010. {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
  1011. {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
  1012. {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
  1013. {"IF1 ADC1", NULL, "I2S1"},
  1014. {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
  1015. {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
  1016. {"IF2 ADC", NULL, "I2S2"},
  1017. {"AIF1TX", NULL, "IF1 ADC1"},
  1018. {"AIF1TX", NULL, "IF1 ADC2"},
  1019. {"AIF2TX", NULL, "IF2 ADC"},
  1020. {"IF1 DAC", NULL, "AIF1RX"},
  1021. {"IF1 DAC", NULL, "I2S1"},
  1022. {"IF2 DAC", NULL, "AIF2RX"},
  1023. {"IF2 DAC", NULL, "I2S2"},
  1024. {"IF1 DAC1 L", NULL, "IF1 DAC"},
  1025. {"IF1 DAC1 R", NULL, "IF1 DAC"},
  1026. {"IF1 DAC2 L", NULL, "IF1 DAC"},
  1027. {"IF1 DAC2 R", NULL, "IF1 DAC"},
  1028. {"IF2 DAC L", NULL, "IF2 DAC"},
  1029. {"IF2 DAC R", NULL, "IF2 DAC"},
  1030. {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  1031. {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
  1032. {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  1033. {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
  1034. {"Audio DSP", NULL, "DAC MIXL"},
  1035. {"Audio DSP", NULL, "DAC MIXR"},
  1036. {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
  1037. {"DAC L2 Mux", "IF2", "IF2 DAC L"},
  1038. {"DAC L2 Volume", NULL, "DAC L2 Mux"},
  1039. {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
  1040. {"DAC R2 Mux", "IF2", "IF2 DAC R"},
  1041. {"DAC R2 Volume", NULL, "DAC R2 Mux"},
  1042. {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
  1043. {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
  1044. {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
  1045. {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
  1046. {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
  1047. {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
  1048. {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
  1049. {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
  1050. {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
  1051. {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
  1052. {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
  1053. {"PDM L Mux", "DD MIX", "DAC MIXL"},
  1054. {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
  1055. {"PDM R Mux", "DD MIX", "DAC MIXR"},
  1056. {"DAC L1", NULL, "Stereo DAC MIXL"},
  1057. {"DAC L1", NULL, "DAC L1 Power"},
  1058. {"DAC R1", NULL, "Stereo DAC MIXR"},
  1059. {"DAC R1", NULL, "DAC R1 Power"},
  1060. {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
  1061. {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
  1062. {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
  1063. {"DD MIXL", NULL, "Stero2 DAC Power"},
  1064. {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
  1065. {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
  1066. {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
  1067. {"DD MIXR", NULL, "Stero2 DAC Power"},
  1068. {"OUT MIXL", "BST1 Switch", "BST1"},
  1069. {"OUT MIXL", "BST2 Switch", "BST2"},
  1070. {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
  1071. {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
  1072. {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
  1073. {"OUT MIXR", "BST2 Switch", "BST2"},
  1074. {"OUT MIXR", "BST1 Switch", "BST1"},
  1075. {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
  1076. {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
  1077. {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
  1078. {"HPOVOL L", "Switch", "OUT MIXL"},
  1079. {"HPOVOL R", "Switch", "OUT MIXR"},
  1080. {"OUTVOL L", "Switch", "OUT MIXL"},
  1081. {"OUTVOL R", "Switch", "OUT MIXR"},
  1082. {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
  1083. {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
  1084. {"HPOL MIX", NULL, "HP L Amp"},
  1085. {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
  1086. {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
  1087. {"HPOR MIX", NULL, "HP R Amp"},
  1088. {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
  1089. {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
  1090. {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
  1091. {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
  1092. {"HP Amp", NULL, "HPOL MIX"},
  1093. {"HP Amp", NULL, "HPOR MIX"},
  1094. {"HP Amp", NULL, "Amp Power"},
  1095. {"HPO L Playback", "Switch", "HP Amp"},
  1096. {"HPO R Playback", "Switch", "HP Amp"},
  1097. {"HPOL", NULL, "HPO L Playback"},
  1098. {"HPOR", NULL, "HPO R Playback"},
  1099. {"LOUT L Playback", "Switch", "LOUT MIX"},
  1100. {"LOUT R Playback", "Switch", "LOUT MIX"},
  1101. {"LOUTL", NULL, "LOUT L Playback"},
  1102. {"LOUTL", NULL, "Amp Power"},
  1103. {"LOUTR", NULL, "LOUT R Playback"},
  1104. {"LOUTR", NULL, "Amp Power"},
  1105. {"PDML", NULL, "PDM L Mux"},
  1106. {"PDMR", NULL, "PDM R Mux"},
  1107. };
  1108. static int rt5651_hw_params(struct snd_pcm_substream *substream,
  1109. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1110. {
  1111. struct snd_soc_component *component = dai->component;
  1112. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1113. unsigned int val_len = 0, val_clk, mask_clk;
  1114. int pre_div, bclk_ms, frame_size;
  1115. rt5651->lrck[dai->id] = params_rate(params);
  1116. pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
  1117. if (pre_div < 0) {
  1118. dev_err(component->dev, "Unsupported clock setting\n");
  1119. return -EINVAL;
  1120. }
  1121. frame_size = snd_soc_params_to_frame_size(params);
  1122. if (frame_size < 0) {
  1123. dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
  1124. return -EINVAL;
  1125. }
  1126. bclk_ms = frame_size > 32 ? 1 : 0;
  1127. rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
  1128. dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  1129. rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
  1130. dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  1131. bclk_ms, pre_div, dai->id);
  1132. switch (params_width(params)) {
  1133. case 16:
  1134. break;
  1135. case 20:
  1136. val_len |= RT5651_I2S_DL_20;
  1137. break;
  1138. case 24:
  1139. val_len |= RT5651_I2S_DL_24;
  1140. break;
  1141. case 8:
  1142. val_len |= RT5651_I2S_DL_8;
  1143. break;
  1144. default:
  1145. return -EINVAL;
  1146. }
  1147. switch (dai->id) {
  1148. case RT5651_AIF1:
  1149. mask_clk = RT5651_I2S_PD1_MASK;
  1150. val_clk = pre_div << RT5651_I2S_PD1_SFT;
  1151. snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
  1152. RT5651_I2S_DL_MASK, val_len);
  1153. snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
  1154. break;
  1155. case RT5651_AIF2:
  1156. mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
  1157. val_clk = pre_div << RT5651_I2S_PD2_SFT;
  1158. snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
  1159. RT5651_I2S_DL_MASK, val_len);
  1160. snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
  1161. break;
  1162. default:
  1163. dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
  1164. return -EINVAL;
  1165. }
  1166. return 0;
  1167. }
  1168. static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1169. {
  1170. struct snd_soc_component *component = dai->component;
  1171. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1172. unsigned int reg_val = 0;
  1173. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1174. case SND_SOC_DAIFMT_CBM_CFM:
  1175. rt5651->master[dai->id] = 1;
  1176. break;
  1177. case SND_SOC_DAIFMT_CBS_CFS:
  1178. reg_val |= RT5651_I2S_MS_S;
  1179. rt5651->master[dai->id] = 0;
  1180. break;
  1181. default:
  1182. return -EINVAL;
  1183. }
  1184. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1185. case SND_SOC_DAIFMT_NB_NF:
  1186. break;
  1187. case SND_SOC_DAIFMT_IB_NF:
  1188. reg_val |= RT5651_I2S_BP_INV;
  1189. break;
  1190. default:
  1191. return -EINVAL;
  1192. }
  1193. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1194. case SND_SOC_DAIFMT_I2S:
  1195. break;
  1196. case SND_SOC_DAIFMT_LEFT_J:
  1197. reg_val |= RT5651_I2S_DF_LEFT;
  1198. break;
  1199. case SND_SOC_DAIFMT_DSP_A:
  1200. reg_val |= RT5651_I2S_DF_PCM_A;
  1201. break;
  1202. case SND_SOC_DAIFMT_DSP_B:
  1203. reg_val |= RT5651_I2S_DF_PCM_B;
  1204. break;
  1205. default:
  1206. return -EINVAL;
  1207. }
  1208. switch (dai->id) {
  1209. case RT5651_AIF1:
  1210. snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
  1211. RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
  1212. RT5651_I2S_DF_MASK, reg_val);
  1213. break;
  1214. case RT5651_AIF2:
  1215. snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
  1216. RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
  1217. RT5651_I2S_DF_MASK, reg_val);
  1218. break;
  1219. default:
  1220. dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
  1221. return -EINVAL;
  1222. }
  1223. return 0;
  1224. }
  1225. static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
  1226. int clk_id, unsigned int freq, int dir)
  1227. {
  1228. struct snd_soc_component *component = dai->component;
  1229. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1230. unsigned int reg_val = 0;
  1231. unsigned int pll_bit = 0;
  1232. if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
  1233. return 0;
  1234. switch (clk_id) {
  1235. case RT5651_SCLK_S_MCLK:
  1236. reg_val |= RT5651_SCLK_SRC_MCLK;
  1237. break;
  1238. case RT5651_SCLK_S_PLL1:
  1239. reg_val |= RT5651_SCLK_SRC_PLL1;
  1240. pll_bit |= RT5651_PWR_PLL;
  1241. break;
  1242. case RT5651_SCLK_S_RCCLK:
  1243. reg_val |= RT5651_SCLK_SRC_RCCLK;
  1244. break;
  1245. default:
  1246. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  1247. return -EINVAL;
  1248. }
  1249. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  1250. RT5651_PWR_PLL, pll_bit);
  1251. snd_soc_component_update_bits(component, RT5651_GLB_CLK,
  1252. RT5651_SCLK_SRC_MASK, reg_val);
  1253. rt5651->sysclk = freq;
  1254. rt5651->sysclk_src = clk_id;
  1255. dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  1256. return 0;
  1257. }
  1258. static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  1259. unsigned int freq_in, unsigned int freq_out)
  1260. {
  1261. struct snd_soc_component *component = dai->component;
  1262. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1263. struct rl6231_pll_code pll_code;
  1264. int ret;
  1265. if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
  1266. freq_out == rt5651->pll_out)
  1267. return 0;
  1268. if (!freq_in || !freq_out) {
  1269. dev_dbg(component->dev, "PLL disabled\n");
  1270. rt5651->pll_in = 0;
  1271. rt5651->pll_out = 0;
  1272. snd_soc_component_update_bits(component, RT5651_GLB_CLK,
  1273. RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
  1274. return 0;
  1275. }
  1276. switch (source) {
  1277. case RT5651_PLL1_S_MCLK:
  1278. snd_soc_component_update_bits(component, RT5651_GLB_CLK,
  1279. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
  1280. break;
  1281. case RT5651_PLL1_S_BCLK1:
  1282. snd_soc_component_update_bits(component, RT5651_GLB_CLK,
  1283. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
  1284. break;
  1285. case RT5651_PLL1_S_BCLK2:
  1286. snd_soc_component_update_bits(component, RT5651_GLB_CLK,
  1287. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
  1288. break;
  1289. default:
  1290. dev_err(component->dev, "Unknown PLL source %d\n", source);
  1291. return -EINVAL;
  1292. }
  1293. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  1294. if (ret < 0) {
  1295. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  1296. return ret;
  1297. }
  1298. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  1299. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  1300. pll_code.n_code, pll_code.k_code);
  1301. snd_soc_component_write(component, RT5651_PLL_CTRL1,
  1302. pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
  1303. snd_soc_component_write(component, RT5651_PLL_CTRL2,
  1304. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
  1305. pll_code.m_bp << RT5651_PLL_M_BP_SFT);
  1306. rt5651->pll_in = freq_in;
  1307. rt5651->pll_out = freq_out;
  1308. rt5651->pll_src = source;
  1309. return 0;
  1310. }
  1311. static int rt5651_set_bias_level(struct snd_soc_component *component,
  1312. enum snd_soc_bias_level level)
  1313. {
  1314. switch (level) {
  1315. case SND_SOC_BIAS_PREPARE:
  1316. if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
  1317. if (snd_soc_component_read(component, RT5651_PLL_MODE_1) & 0x9200)
  1318. snd_soc_component_update_bits(component, RT5651_D_MISC,
  1319. 0xc00, 0xc00);
  1320. }
  1321. break;
  1322. case SND_SOC_BIAS_STANDBY:
  1323. if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
  1324. snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
  1325. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1326. RT5651_PWR_BG | RT5651_PWR_VREF2,
  1327. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1328. RT5651_PWR_BG | RT5651_PWR_VREF2);
  1329. usleep_range(10000, 15000);
  1330. snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
  1331. RT5651_PWR_FV1 | RT5651_PWR_FV2,
  1332. RT5651_PWR_FV1 | RT5651_PWR_FV2);
  1333. snd_soc_component_update_bits(component, RT5651_D_MISC, 0x1, 0x1);
  1334. }
  1335. break;
  1336. case SND_SOC_BIAS_OFF:
  1337. snd_soc_component_write(component, RT5651_D_MISC, 0x0010);
  1338. snd_soc_component_write(component, RT5651_PWR_DIG1, 0x0000);
  1339. snd_soc_component_write(component, RT5651_PWR_DIG2, 0x0000);
  1340. snd_soc_component_write(component, RT5651_PWR_VOL, 0x0000);
  1341. snd_soc_component_write(component, RT5651_PWR_MIXER, 0x0000);
  1342. /* Do not touch the LDO voltage select bits on bias-off */
  1343. snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
  1344. ~RT5651_PWR_LDO_DVO_MASK, 0);
  1345. /* Leave PLL1 and jack-detect power as is, all others off */
  1346. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  1347. ~(RT5651_PWR_PLL | RT5651_PWR_JD_M), 0);
  1348. break;
  1349. default:
  1350. break;
  1351. }
  1352. return 0;
  1353. }
  1354. static void rt5651_enable_micbias1_for_ovcd(struct snd_soc_component *component)
  1355. {
  1356. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1357. snd_soc_dapm_mutex_lock(dapm);
  1358. snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO");
  1359. snd_soc_dapm_force_enable_pin_unlocked(dapm, "micbias1");
  1360. /* OVCD is unreliable when used with RCCLK as sysclk-source */
  1361. snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
  1362. snd_soc_dapm_sync_unlocked(dapm);
  1363. snd_soc_dapm_mutex_unlock(dapm);
  1364. }
  1365. static void rt5651_disable_micbias1_for_ovcd(struct snd_soc_component *component)
  1366. {
  1367. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1368. snd_soc_dapm_mutex_lock(dapm);
  1369. snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
  1370. snd_soc_dapm_disable_pin_unlocked(dapm, "micbias1");
  1371. snd_soc_dapm_disable_pin_unlocked(dapm, "LDO");
  1372. snd_soc_dapm_sync_unlocked(dapm);
  1373. snd_soc_dapm_mutex_unlock(dapm);
  1374. }
  1375. static void rt5651_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
  1376. {
  1377. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1378. snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
  1379. RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_NOR);
  1380. rt5651->ovcd_irq_enabled = true;
  1381. }
  1382. static void rt5651_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
  1383. {
  1384. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1385. snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
  1386. RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_BP);
  1387. rt5651->ovcd_irq_enabled = false;
  1388. }
  1389. static void rt5651_clear_micbias1_ovcd(struct snd_soc_component *component)
  1390. {
  1391. snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
  1392. RT5651_MB1_OC_CLR, 0);
  1393. }
  1394. static bool rt5651_micbias1_ovcd(struct snd_soc_component *component)
  1395. {
  1396. int val;
  1397. val = snd_soc_component_read(component, RT5651_IRQ_CTRL2);
  1398. dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
  1399. return (val & RT5651_MB1_OC_CLR);
  1400. }
  1401. static bool rt5651_jack_inserted(struct snd_soc_component *component)
  1402. {
  1403. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1404. int val;
  1405. if (rt5651->gpiod_hp_det) {
  1406. val = gpiod_get_value_cansleep(rt5651->gpiod_hp_det);
  1407. dev_dbg(component->dev, "jack-detect gpio %d\n", val);
  1408. return val;
  1409. }
  1410. val = snd_soc_component_read(component, RT5651_INT_IRQ_ST);
  1411. dev_dbg(component->dev, "irq status %#04x\n", val);
  1412. switch (rt5651->jd_src) {
  1413. case RT5651_JD1_1:
  1414. val &= 0x1000;
  1415. break;
  1416. case RT5651_JD1_2:
  1417. val &= 0x2000;
  1418. break;
  1419. case RT5651_JD2:
  1420. val &= 0x4000;
  1421. break;
  1422. default:
  1423. break;
  1424. }
  1425. if (rt5651->jd_active_high)
  1426. return val != 0;
  1427. else
  1428. return val == 0;
  1429. }
  1430. /* Jack detect and button-press timings */
  1431. #define JACK_SETTLE_TIME 100 /* milli seconds */
  1432. #define JACK_DETECT_COUNT 5
  1433. #define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
  1434. #define JACK_UNPLUG_TIME 80 /* milli seconds */
  1435. #define BP_POLL_TIME 10 /* milli seconds */
  1436. #define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
  1437. #define BP_THRESHOLD 3
  1438. static void rt5651_start_button_press_work(struct snd_soc_component *component)
  1439. {
  1440. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1441. rt5651->poll_count = 0;
  1442. rt5651->press_count = 0;
  1443. rt5651->release_count = 0;
  1444. rt5651->pressed = false;
  1445. rt5651->press_reported = false;
  1446. rt5651_clear_micbias1_ovcd(component);
  1447. schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
  1448. }
  1449. static void rt5651_button_press_work(struct work_struct *work)
  1450. {
  1451. struct rt5651_priv *rt5651 =
  1452. container_of(work, struct rt5651_priv, bp_work.work);
  1453. struct snd_soc_component *component = rt5651->component;
  1454. /* Check the jack was not removed underneath us */
  1455. if (!rt5651_jack_inserted(component))
  1456. return;
  1457. if (rt5651_micbias1_ovcd(component)) {
  1458. rt5651->release_count = 0;
  1459. rt5651->press_count++;
  1460. /* Remember till after JACK_UNPLUG_TIME wait */
  1461. if (rt5651->press_count >= BP_THRESHOLD)
  1462. rt5651->pressed = true;
  1463. rt5651_clear_micbias1_ovcd(component);
  1464. } else {
  1465. rt5651->press_count = 0;
  1466. rt5651->release_count++;
  1467. }
  1468. /*
  1469. * The pins get temporarily shorted on jack unplug, so we poll for
  1470. * at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
  1471. */
  1472. rt5651->poll_count++;
  1473. if (rt5651->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
  1474. schedule_delayed_work(&rt5651->bp_work,
  1475. msecs_to_jiffies(BP_POLL_TIME));
  1476. return;
  1477. }
  1478. if (rt5651->pressed && !rt5651->press_reported) {
  1479. dev_dbg(component->dev, "headset button press\n");
  1480. snd_soc_jack_report(rt5651->hp_jack, SND_JACK_BTN_0,
  1481. SND_JACK_BTN_0);
  1482. rt5651->press_reported = true;
  1483. }
  1484. if (rt5651->release_count >= BP_THRESHOLD) {
  1485. if (rt5651->press_reported) {
  1486. dev_dbg(component->dev, "headset button release\n");
  1487. snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
  1488. }
  1489. /* Re-enable OVCD IRQ to detect next press */
  1490. rt5651_enable_micbias1_ovcd_irq(component);
  1491. return; /* Stop polling */
  1492. }
  1493. schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
  1494. }
  1495. static int rt5651_detect_headset(struct snd_soc_component *component)
  1496. {
  1497. int i, headset_count = 0, headphone_count = 0;
  1498. /*
  1499. * We get the insertion event before the jack is fully inserted at which
  1500. * point the second ring on a TRRS connector may short the 2nd ring and
  1501. * sleeve contacts, also the overcurrent detection is not entirely
  1502. * reliable. So we try several times with a wait in between until we
  1503. * detect the same type JACK_DETECT_COUNT times in a row.
  1504. */
  1505. for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
  1506. /* Clear any previous over-current status flag */
  1507. rt5651_clear_micbias1_ovcd(component);
  1508. msleep(JACK_SETTLE_TIME);
  1509. /* Check the jack is still connected before checking ovcd */
  1510. if (!rt5651_jack_inserted(component))
  1511. return 0;
  1512. if (rt5651_micbias1_ovcd(component)) {
  1513. /*
  1514. * Over current detected, there is a short between the
  1515. * 2nd ring contact and the ground, so a TRS connector
  1516. * without a mic contact and thus plain headphones.
  1517. */
  1518. dev_dbg(component->dev, "mic-gnd shorted\n");
  1519. headset_count = 0;
  1520. headphone_count++;
  1521. if (headphone_count == JACK_DETECT_COUNT)
  1522. return SND_JACK_HEADPHONE;
  1523. } else {
  1524. dev_dbg(component->dev, "mic-gnd open\n");
  1525. headphone_count = 0;
  1526. headset_count++;
  1527. if (headset_count == JACK_DETECT_COUNT)
  1528. return SND_JACK_HEADSET;
  1529. }
  1530. }
  1531. dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
  1532. return SND_JACK_HEADPHONE;
  1533. }
  1534. static bool rt5651_support_button_press(struct rt5651_priv *rt5651)
  1535. {
  1536. if (!rt5651->hp_jack)
  1537. return false;
  1538. /* Button press support only works with internal jack-detection */
  1539. return (rt5651->hp_jack->status & SND_JACK_MICROPHONE) &&
  1540. rt5651->gpiod_hp_det == NULL;
  1541. }
  1542. static void rt5651_jack_detect_work(struct work_struct *work)
  1543. {
  1544. struct rt5651_priv *rt5651 =
  1545. container_of(work, struct rt5651_priv, jack_detect_work);
  1546. struct snd_soc_component *component = rt5651->component;
  1547. int report = 0;
  1548. if (!rt5651_jack_inserted(component)) {
  1549. /* Jack removed, or spurious IRQ? */
  1550. if (rt5651->hp_jack->status & SND_JACK_HEADPHONE) {
  1551. if (rt5651->hp_jack->status & SND_JACK_MICROPHONE) {
  1552. cancel_delayed_work_sync(&rt5651->bp_work);
  1553. rt5651_disable_micbias1_ovcd_irq(component);
  1554. rt5651_disable_micbias1_for_ovcd(component);
  1555. }
  1556. snd_soc_jack_report(rt5651->hp_jack, 0,
  1557. SND_JACK_HEADSET | SND_JACK_BTN_0);
  1558. dev_dbg(component->dev, "jack unplugged\n");
  1559. }
  1560. } else if (!(rt5651->hp_jack->status & SND_JACK_HEADPHONE)) {
  1561. /* Jack inserted */
  1562. WARN_ON(rt5651->ovcd_irq_enabled);
  1563. rt5651_enable_micbias1_for_ovcd(component);
  1564. report = rt5651_detect_headset(component);
  1565. dev_dbg(component->dev, "detect report %#02x\n", report);
  1566. snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET);
  1567. if (rt5651_support_button_press(rt5651)) {
  1568. /* Enable ovcd IRQ for button press detect. */
  1569. rt5651_enable_micbias1_ovcd_irq(component);
  1570. } else {
  1571. /* No more need for overcurrent detect. */
  1572. rt5651_disable_micbias1_for_ovcd(component);
  1573. }
  1574. } else if (rt5651->ovcd_irq_enabled && rt5651_micbias1_ovcd(component)) {
  1575. dev_dbg(component->dev, "OVCD IRQ\n");
  1576. /*
  1577. * The ovcd IRQ keeps firing while the button is pressed, so
  1578. * we disable it and start polling the button until released.
  1579. *
  1580. * The disable will make the IRQ pin 0 again and since we get
  1581. * IRQs on both edges (so as to detect both jack plugin and
  1582. * unplug) this means we will immediately get another IRQ.
  1583. * The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
  1584. */
  1585. rt5651_disable_micbias1_ovcd_irq(component);
  1586. rt5651_start_button_press_work(component);
  1587. /*
  1588. * If the jack-detect IRQ flag goes high (unplug) after our
  1589. * above rt5651_jack_inserted() check and before we have
  1590. * disabled the OVCD IRQ, the IRQ pin will stay high and as
  1591. * we react to edges, we miss the unplug event -> recheck.
  1592. */
  1593. queue_work(system_long_wq, &rt5651->jack_detect_work);
  1594. }
  1595. }
  1596. static irqreturn_t rt5651_irq(int irq, void *data)
  1597. {
  1598. struct rt5651_priv *rt5651 = data;
  1599. queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
  1600. return IRQ_HANDLED;
  1601. }
  1602. static void rt5651_cancel_work(void *data)
  1603. {
  1604. struct rt5651_priv *rt5651 = data;
  1605. cancel_work_sync(&rt5651->jack_detect_work);
  1606. cancel_delayed_work_sync(&rt5651->bp_work);
  1607. }
  1608. static void rt5651_enable_jack_detect(struct snd_soc_component *component,
  1609. struct snd_soc_jack *hp_jack,
  1610. struct gpio_desc *gpiod_hp_det)
  1611. {
  1612. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1613. bool using_internal_jack_detect = true;
  1614. /* Select jack detect source */
  1615. switch (rt5651->jd_src) {
  1616. case RT5651_JD_NULL:
  1617. rt5651->gpiod_hp_det = gpiod_hp_det;
  1618. if (!rt5651->gpiod_hp_det)
  1619. return; /* No jack detect */
  1620. using_internal_jack_detect = false;
  1621. break;
  1622. case RT5651_JD1_1:
  1623. snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
  1624. RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_1);
  1625. /* active-low is normal, set inv flag for active-high */
  1626. if (rt5651->jd_active_high)
  1627. snd_soc_component_update_bits(component,
  1628. RT5651_IRQ_CTRL1,
  1629. RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
  1630. RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV);
  1631. else
  1632. snd_soc_component_update_bits(component,
  1633. RT5651_IRQ_CTRL1,
  1634. RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
  1635. RT5651_JD1_1_IRQ_EN);
  1636. break;
  1637. case RT5651_JD1_2:
  1638. snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
  1639. RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_2);
  1640. /* active-low is normal, set inv flag for active-high */
  1641. if (rt5651->jd_active_high)
  1642. snd_soc_component_update_bits(component,
  1643. RT5651_IRQ_CTRL1,
  1644. RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
  1645. RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV);
  1646. else
  1647. snd_soc_component_update_bits(component,
  1648. RT5651_IRQ_CTRL1,
  1649. RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
  1650. RT5651_JD1_2_IRQ_EN);
  1651. break;
  1652. case RT5651_JD2:
  1653. snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
  1654. RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD2);
  1655. /* active-low is normal, set inv flag for active-high */
  1656. if (rt5651->jd_active_high)
  1657. snd_soc_component_update_bits(component,
  1658. RT5651_IRQ_CTRL1,
  1659. RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
  1660. RT5651_JD2_IRQ_EN | RT5651_JD2_INV);
  1661. else
  1662. snd_soc_component_update_bits(component,
  1663. RT5651_IRQ_CTRL1,
  1664. RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
  1665. RT5651_JD2_IRQ_EN);
  1666. break;
  1667. default:
  1668. dev_err(component->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n");
  1669. return;
  1670. }
  1671. if (using_internal_jack_detect) {
  1672. /* IRQ output on GPIO1 */
  1673. snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
  1674. RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ);
  1675. /* Enable jack detect power */
  1676. snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
  1677. RT5651_PWR_JD_M, RT5651_PWR_JD_M);
  1678. }
  1679. /* Set OVCD threshold current and scale-factor */
  1680. snd_soc_component_write(component, RT5651_PR_BASE + RT5651_BIAS_CUR4,
  1681. 0xa800 | rt5651->ovcd_sf);
  1682. snd_soc_component_update_bits(component, RT5651_MICBIAS,
  1683. RT5651_MIC1_OVCD_MASK |
  1684. RT5651_MIC1_OVTH_MASK |
  1685. RT5651_PWR_CLK12M_MASK |
  1686. RT5651_PWR_MB_MASK,
  1687. RT5651_MIC1_OVCD_EN |
  1688. rt5651->ovcd_th |
  1689. RT5651_PWR_MB_PU |
  1690. RT5651_PWR_CLK12M_PU);
  1691. /*
  1692. * The over-current-detect is only reliable in detecting the absence
  1693. * of over-current, when the mic-contact in the jack is short-circuited,
  1694. * the hardware periodically retries if it can apply the bias-current
  1695. * leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
  1696. * 10% of the time, as we poll the ovcd status bit we might hit that
  1697. * 10%, so we enable sticky mode and when checking OVCD we clear the
  1698. * status, msleep() a bit and then check to get a reliable reading.
  1699. */
  1700. snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
  1701. RT5651_MB1_OC_STKY_MASK, RT5651_MB1_OC_STKY_EN);
  1702. rt5651->hp_jack = hp_jack;
  1703. if (rt5651_support_button_press(rt5651)) {
  1704. rt5651_enable_micbias1_for_ovcd(component);
  1705. rt5651_enable_micbias1_ovcd_irq(component);
  1706. }
  1707. enable_irq(rt5651->irq);
  1708. /* sync initial jack state */
  1709. queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
  1710. }
  1711. static void rt5651_disable_jack_detect(struct snd_soc_component *component)
  1712. {
  1713. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1714. disable_irq(rt5651->irq);
  1715. rt5651_cancel_work(rt5651);
  1716. if (rt5651_support_button_press(rt5651)) {
  1717. rt5651_disable_micbias1_ovcd_irq(component);
  1718. rt5651_disable_micbias1_for_ovcd(component);
  1719. snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
  1720. }
  1721. rt5651->hp_jack = NULL;
  1722. }
  1723. static int rt5651_set_jack(struct snd_soc_component *component,
  1724. struct snd_soc_jack *jack, void *data)
  1725. {
  1726. if (jack)
  1727. rt5651_enable_jack_detect(component, jack, data);
  1728. else
  1729. rt5651_disable_jack_detect(component);
  1730. return 0;
  1731. }
  1732. /*
  1733. * Note on some platforms the platform code may need to add device-properties,
  1734. * rather then relying only on properties set by the firmware. Therefor the
  1735. * property parsing MUST be done from the component driver's probe function,
  1736. * rather then from the i2c driver's probe function, so that the platform-code
  1737. * can attach extra properties before calling snd_soc_register_card().
  1738. */
  1739. static void rt5651_apply_properties(struct snd_soc_component *component)
  1740. {
  1741. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1742. u32 val;
  1743. if (device_property_read_bool(component->dev, "realtek,in2-differential"))
  1744. snd_soc_component_update_bits(component, RT5651_IN1_IN2,
  1745. RT5651_IN_DF2, RT5651_IN_DF2);
  1746. if (device_property_read_bool(component->dev, "realtek,dmic-en"))
  1747. snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
  1748. RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
  1749. if (device_property_read_u32(component->dev,
  1750. "realtek,jack-detect-source", &val) == 0)
  1751. rt5651->jd_src = val;
  1752. if (device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
  1753. rt5651->jd_active_high = true;
  1754. /*
  1755. * Testing on various boards has shown that good defaults for the OVCD
  1756. * threshold and scale-factor are 2000µA and 0.75. For an effective
  1757. * limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
  1758. */
  1759. rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
  1760. rt5651->ovcd_sf = RT5651_MIC_OVCD_SF_0P75;
  1761. if (device_property_read_u32(component->dev,
  1762. "realtek,over-current-threshold-microamp", &val) == 0) {
  1763. switch (val) {
  1764. case 600:
  1765. rt5651->ovcd_th = RT5651_MIC1_OVTH_600UA;
  1766. break;
  1767. case 1500:
  1768. rt5651->ovcd_th = RT5651_MIC1_OVTH_1500UA;
  1769. break;
  1770. case 2000:
  1771. rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
  1772. break;
  1773. default:
  1774. dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
  1775. val);
  1776. }
  1777. }
  1778. if (device_property_read_u32(component->dev,
  1779. "realtek,over-current-scale-factor", &val) == 0) {
  1780. if (val <= RT5651_OVCD_SF_1P5)
  1781. rt5651->ovcd_sf = val << RT5651_MIC_OVCD_SF_SFT;
  1782. else
  1783. dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
  1784. val);
  1785. }
  1786. }
  1787. static int rt5651_probe(struct snd_soc_component *component)
  1788. {
  1789. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1790. rt5651->component = component;
  1791. snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
  1792. RT5651_PWR_LDO_DVO_MASK, RT5651_PWR_LDO_DVO_1_2V);
  1793. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  1794. rt5651_apply_properties(component);
  1795. return 0;
  1796. }
  1797. #ifdef CONFIG_PM
  1798. static int rt5651_suspend(struct snd_soc_component *component)
  1799. {
  1800. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1801. regcache_cache_only(rt5651->regmap, true);
  1802. regcache_mark_dirty(rt5651->regmap);
  1803. return 0;
  1804. }
  1805. static int rt5651_resume(struct snd_soc_component *component)
  1806. {
  1807. struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
  1808. regcache_cache_only(rt5651->regmap, false);
  1809. snd_soc_component_cache_sync(component);
  1810. return 0;
  1811. }
  1812. #else
  1813. #define rt5651_suspend NULL
  1814. #define rt5651_resume NULL
  1815. #endif
  1816. #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
  1817. #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1818. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  1819. static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
  1820. .hw_params = rt5651_hw_params,
  1821. .set_fmt = rt5651_set_dai_fmt,
  1822. .set_sysclk = rt5651_set_dai_sysclk,
  1823. .set_pll = rt5651_set_dai_pll,
  1824. };
  1825. static struct snd_soc_dai_driver rt5651_dai[] = {
  1826. {
  1827. .name = "rt5651-aif1",
  1828. .id = RT5651_AIF1,
  1829. .playback = {
  1830. .stream_name = "AIF1 Playback",
  1831. .channels_min = 1,
  1832. .channels_max = 2,
  1833. .rates = RT5651_STEREO_RATES,
  1834. .formats = RT5651_FORMATS,
  1835. },
  1836. .capture = {
  1837. .stream_name = "AIF1 Capture",
  1838. .channels_min = 1,
  1839. .channels_max = 2,
  1840. .rates = RT5651_STEREO_RATES,
  1841. .formats = RT5651_FORMATS,
  1842. },
  1843. .ops = &rt5651_aif_dai_ops,
  1844. },
  1845. {
  1846. .name = "rt5651-aif2",
  1847. .id = RT5651_AIF2,
  1848. .playback = {
  1849. .stream_name = "AIF2 Playback",
  1850. .channels_min = 1,
  1851. .channels_max = 2,
  1852. .rates = RT5651_STEREO_RATES,
  1853. .formats = RT5651_FORMATS,
  1854. },
  1855. .capture = {
  1856. .stream_name = "AIF2 Capture",
  1857. .channels_min = 1,
  1858. .channels_max = 2,
  1859. .rates = RT5651_STEREO_RATES,
  1860. .formats = RT5651_FORMATS,
  1861. },
  1862. .ops = &rt5651_aif_dai_ops,
  1863. },
  1864. };
  1865. static const struct snd_soc_component_driver soc_component_dev_rt5651 = {
  1866. .probe = rt5651_probe,
  1867. .suspend = rt5651_suspend,
  1868. .resume = rt5651_resume,
  1869. .set_bias_level = rt5651_set_bias_level,
  1870. .set_jack = rt5651_set_jack,
  1871. .controls = rt5651_snd_controls,
  1872. .num_controls = ARRAY_SIZE(rt5651_snd_controls),
  1873. .dapm_widgets = rt5651_dapm_widgets,
  1874. .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
  1875. .dapm_routes = rt5651_dapm_routes,
  1876. .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
  1877. .use_pmdown_time = 1,
  1878. .endianness = 1,
  1879. .non_legacy_dai_naming = 1,
  1880. };
  1881. static const struct regmap_config rt5651_regmap = {
  1882. .reg_bits = 8,
  1883. .val_bits = 16,
  1884. .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
  1885. RT5651_PR_SPACING),
  1886. .volatile_reg = rt5651_volatile_register,
  1887. .readable_reg = rt5651_readable_register,
  1888. .cache_type = REGCACHE_RBTREE,
  1889. .reg_defaults = rt5651_reg,
  1890. .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
  1891. .ranges = rt5651_ranges,
  1892. .num_ranges = ARRAY_SIZE(rt5651_ranges),
  1893. .use_single_read = true,
  1894. .use_single_write = true,
  1895. };
  1896. #if defined(CONFIG_OF)
  1897. static const struct of_device_id rt5651_of_match[] = {
  1898. { .compatible = "realtek,rt5651", },
  1899. {},
  1900. };
  1901. MODULE_DEVICE_TABLE(of, rt5651_of_match);
  1902. #endif
  1903. #ifdef CONFIG_ACPI
  1904. static const struct acpi_device_id rt5651_acpi_match[] = {
  1905. { "10EC5651", 0 },
  1906. { "10EC5640", 0 },
  1907. { },
  1908. };
  1909. MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
  1910. #endif
  1911. static const struct i2c_device_id rt5651_i2c_id[] = {
  1912. { "rt5651", 0 },
  1913. { }
  1914. };
  1915. MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
  1916. /*
  1917. * Note this function MUST not look at device-properties, see the comment
  1918. * above rt5651_apply_properties().
  1919. */
  1920. static int rt5651_i2c_probe(struct i2c_client *i2c,
  1921. const struct i2c_device_id *id)
  1922. {
  1923. struct rt5651_priv *rt5651;
  1924. int ret;
  1925. int err;
  1926. rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
  1927. GFP_KERNEL);
  1928. if (NULL == rt5651)
  1929. return -ENOMEM;
  1930. i2c_set_clientdata(i2c, rt5651);
  1931. rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
  1932. if (IS_ERR(rt5651->regmap)) {
  1933. ret = PTR_ERR(rt5651->regmap);
  1934. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1935. ret);
  1936. return ret;
  1937. }
  1938. err = regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
  1939. if (err)
  1940. return err;
  1941. if (ret != RT5651_DEVICE_ID_VALUE) {
  1942. dev_err(&i2c->dev,
  1943. "Device with ID register %#x is not rt5651\n", ret);
  1944. return -ENODEV;
  1945. }
  1946. regmap_write(rt5651->regmap, RT5651_RESET, 0);
  1947. ret = regmap_register_patch(rt5651->regmap, init_list,
  1948. ARRAY_SIZE(init_list));
  1949. if (ret != 0)
  1950. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  1951. rt5651->irq = i2c->irq;
  1952. rt5651->hp_mute = true;
  1953. INIT_DELAYED_WORK(&rt5651->bp_work, rt5651_button_press_work);
  1954. INIT_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work);
  1955. /* Make sure work is stopped on probe-error / remove */
  1956. ret = devm_add_action_or_reset(&i2c->dev, rt5651_cancel_work, rt5651);
  1957. if (ret)
  1958. return ret;
  1959. ret = devm_request_irq(&i2c->dev, rt5651->irq, rt5651_irq,
  1960. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  1961. | IRQF_ONESHOT, "rt5651", rt5651);
  1962. if (ret == 0) {
  1963. /* Gets re-enabled by rt5651_set_jack() */
  1964. disable_irq(rt5651->irq);
  1965. } else {
  1966. dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n",
  1967. rt5651->irq, ret);
  1968. rt5651->irq = -ENXIO;
  1969. }
  1970. ret = devm_snd_soc_register_component(&i2c->dev,
  1971. &soc_component_dev_rt5651,
  1972. rt5651_dai, ARRAY_SIZE(rt5651_dai));
  1973. return ret;
  1974. }
  1975. static struct i2c_driver rt5651_i2c_driver = {
  1976. .driver = {
  1977. .name = "rt5651",
  1978. .acpi_match_table = ACPI_PTR(rt5651_acpi_match),
  1979. .of_match_table = of_match_ptr(rt5651_of_match),
  1980. },
  1981. .probe = rt5651_i2c_probe,
  1982. .id_table = rt5651_i2c_id,
  1983. };
  1984. module_i2c_driver(rt5651_i2c_driver);
  1985. MODULE_DESCRIPTION("ASoC RT5651 driver");
  1986. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1987. MODULE_LICENSE("GPL v2");