rt5645.h 75 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt5645.h -- RT5645 ALSA SoC audio driver
  4. *
  5. * Copyright 2013 Realtek Microelectronics
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #ifndef __RT5645_H__
  9. #define __RT5645_H__
  10. #include <sound/rt5645.h>
  11. /* Info */
  12. #define RT5645_RESET 0x00
  13. #define RT5645_VENDOR_ID 0xfd
  14. #define RT5645_VENDOR_ID1 0xfe
  15. #define RT5645_VENDOR_ID2 0xff
  16. /* I/O - Output */
  17. #define RT5645_SPK_VOL 0x01
  18. #define RT5645_HP_VOL 0x02
  19. #define RT5645_LOUT1 0x03
  20. #define RT5645_LOUT_CTRL 0x05
  21. /* I/O - Input */
  22. #define RT5645_IN1_CTRL1 0x0a
  23. #define RT5645_IN1_CTRL2 0x0b
  24. #define RT5645_IN1_CTRL3 0x0c
  25. #define RT5645_IN2_CTRL 0x0d
  26. #define RT5645_INL1_INR1_VOL 0x0f
  27. #define RT5645_SPK_FUNC_LIM 0x14
  28. #define RT5645_ADJ_HPF_CTRL 0x16
  29. /* I/O - ADC/DAC/DMIC */
  30. #define RT5645_DAC1_DIG_VOL 0x19
  31. #define RT5645_DAC2_DIG_VOL 0x1a
  32. #define RT5645_DAC_CTRL 0x1b
  33. #define RT5645_STO1_ADC_DIG_VOL 0x1c
  34. #define RT5645_MONO_ADC_DIG_VOL 0x1d
  35. #define RT5645_ADC_BST_VOL1 0x1e
  36. #define RT5645_ADC_BST_VOL2 0x20
  37. /* Mixer - D-D */
  38. #define RT5645_STO1_ADC_MIXER 0x27
  39. #define RT5645_MONO_ADC_MIXER 0x28
  40. #define RT5645_AD_DA_MIXER 0x29
  41. #define RT5645_STO_DAC_MIXER 0x2a
  42. #define RT5645_MONO_DAC_MIXER 0x2b
  43. #define RT5645_DIG_MIXER 0x2c
  44. #define RT5650_A_DAC_SOUR 0x2d
  45. #define RT5645_DIG_INF1_DATA 0x2f
  46. /* Mixer - PDM */
  47. #define RT5645_PDM_OUT_CTRL 0x31
  48. /* Mixer - ADC */
  49. #define RT5645_REC_L1_MIXER 0x3b
  50. #define RT5645_REC_L2_MIXER 0x3c
  51. #define RT5645_REC_R1_MIXER 0x3d
  52. #define RT5645_REC_R2_MIXER 0x3e
  53. /* Mixer - DAC */
  54. #define RT5645_HPMIXL_CTRL 0x3f
  55. #define RT5645_HPOMIXL_CTRL 0x40
  56. #define RT5645_HPMIXR_CTRL 0x41
  57. #define RT5645_HPOMIXR_CTRL 0x42
  58. #define RT5645_HPO_MIXER 0x45
  59. #define RT5645_SPK_L_MIXER 0x46
  60. #define RT5645_SPK_R_MIXER 0x47
  61. #define RT5645_SPO_MIXER 0x48
  62. #define RT5645_SPO_CLSD_RATIO 0x4a
  63. #define RT5645_OUT_L_GAIN1 0x4d
  64. #define RT5645_OUT_L_GAIN2 0x4e
  65. #define RT5645_OUT_L1_MIXER 0x4f
  66. #define RT5645_OUT_R_GAIN1 0x50
  67. #define RT5645_OUT_R_GAIN2 0x51
  68. #define RT5645_OUT_R1_MIXER 0x52
  69. #define RT5645_LOUT_MIXER 0x53
  70. /* Haptic */
  71. #define RT5645_HAPTIC_CTRL1 0x56
  72. #define RT5645_HAPTIC_CTRL2 0x57
  73. #define RT5645_HAPTIC_CTRL3 0x58
  74. #define RT5645_HAPTIC_CTRL4 0x59
  75. #define RT5645_HAPTIC_CTRL5 0x5a
  76. #define RT5645_HAPTIC_CTRL6 0x5b
  77. #define RT5645_HAPTIC_CTRL7 0x5c
  78. #define RT5645_HAPTIC_CTRL8 0x5d
  79. #define RT5645_HAPTIC_CTRL9 0x5e
  80. #define RT5645_HAPTIC_CTRL10 0x5f
  81. /* Power */
  82. #define RT5645_PWR_DIG1 0x61
  83. #define RT5645_PWR_DIG2 0x62
  84. #define RT5645_PWR_ANLG1 0x63
  85. #define RT5645_PWR_ANLG2 0x64
  86. #define RT5645_PWR_MIXER 0x65
  87. #define RT5645_PWR_VOL 0x66
  88. /* Private Register Control */
  89. #define RT5645_PRIV_INDEX 0x6a
  90. #define RT5645_PRIV_DATA 0x6c
  91. /* Format - ADC/DAC */
  92. #define RT5645_I2S1_SDP 0x70
  93. #define RT5645_I2S2_SDP 0x71
  94. #define RT5645_ADDA_CLK1 0x73
  95. #define RT5645_ADDA_CLK2 0x74
  96. #define RT5645_DMIC_CTRL1 0x75
  97. #define RT5645_DMIC_CTRL2 0x76
  98. /* Format - TDM Control */
  99. #define RT5645_TDM_CTRL_1 0x77
  100. #define RT5645_TDM_CTRL_2 0x78
  101. #define RT5645_TDM_CTRL_3 0x79
  102. #define RT5650_TDM_CTRL_4 0x7a
  103. /* Function - Analog */
  104. #define RT5645_GLB_CLK 0x80
  105. #define RT5645_PLL_CTRL1 0x81
  106. #define RT5645_PLL_CTRL2 0x82
  107. #define RT5645_ASRC_1 0x83
  108. #define RT5645_ASRC_2 0x84
  109. #define RT5645_ASRC_3 0x85
  110. #define RT5645_ASRC_4 0x8a
  111. #define RT5645_DEPOP_M1 0x8e
  112. #define RT5645_DEPOP_M2 0x8f
  113. #define RT5645_DEPOP_M3 0x90
  114. #define RT5645_CHARGE_PUMP 0x91
  115. #define RT5645_MICBIAS 0x93
  116. #define RT5645_A_JD_CTRL1 0x94
  117. #define RT5645_VAD_CTRL4 0x9d
  118. #define RT5645_CLSD_OUT_CTRL 0xa0
  119. /* Function - Digital */
  120. #define RT5645_ADC_EQ_CTRL1 0xae
  121. #define RT5645_ADC_EQ_CTRL2 0xaf
  122. #define RT5645_EQ_CTRL1 0xb0
  123. #define RT5645_EQ_CTRL2 0xb1
  124. #define RT5645_ALC_CTRL_1 0xb3
  125. #define RT5645_ALC_CTRL_2 0xb4
  126. #define RT5645_ALC_CTRL_3 0xb5
  127. #define RT5645_ALC_CTRL_4 0xb6
  128. #define RT5645_ALC_CTRL_5 0xb7
  129. #define RT5645_JD_CTRL 0xbb
  130. #define RT5645_IRQ_CTRL1 0xbc
  131. #define RT5645_IRQ_CTRL2 0xbd
  132. #define RT5645_IRQ_CTRL3 0xbe
  133. #define RT5645_INT_IRQ_ST 0xbf
  134. #define RT5645_GPIO_CTRL1 0xc0
  135. #define RT5645_GPIO_CTRL2 0xc1
  136. #define RT5645_GPIO_CTRL3 0xc2
  137. #define RT5645_BASS_BACK 0xcf
  138. #define RT5645_MP3_PLUS1 0xd0
  139. #define RT5645_MP3_PLUS2 0xd1
  140. #define RT5645_ADJ_HPF1 0xd3
  141. #define RT5645_ADJ_HPF2 0xd4
  142. #define RT5645_HP_CALIB_AMP_DET 0xd6
  143. #define RT5645_SV_ZCD1 0xd9
  144. #define RT5645_SV_ZCD2 0xda
  145. #define RT5645_IL_CMD 0xdb
  146. #define RT5645_IL_CMD2 0xdc
  147. #define RT5645_IL_CMD3 0xdd
  148. #define RT5650_4BTN_IL_CMD1 0xdf
  149. #define RT5650_4BTN_IL_CMD2 0xe0
  150. #define RT5645_DRC1_HL_CTRL1 0xe7
  151. #define RT5645_DRC2_HL_CTRL1 0xe9
  152. #define RT5645_MUTI_DRC_CTRL1 0xea
  153. #define RT5645_ADC_MONO_HP_CTRL1 0xec
  154. #define RT5645_ADC_MONO_HP_CTRL2 0xed
  155. #define RT5645_DRC2_CTRL1 0xf0
  156. #define RT5645_DRC2_CTRL2 0xf1
  157. #define RT5645_DRC2_CTRL3 0xf2
  158. #define RT5645_DRC2_CTRL4 0xf3
  159. #define RT5645_DRC2_CTRL5 0xf4
  160. #define RT5645_JD_CTRL3 0xf8
  161. #define RT5645_JD_CTRL4 0xf9
  162. /* General Control */
  163. #define RT5645_GEN_CTRL1 0xfa
  164. #define RT5645_GEN_CTRL2 0xfb
  165. #define RT5645_GEN_CTRL3 0xfc
  166. /* Index of Codec Private Register definition */
  167. #define RT5645_DIG_VOL 0x00
  168. #define RT5645_PR_ALC_CTRL_1 0x01
  169. #define RT5645_PR_ALC_CTRL_2 0x02
  170. #define RT5645_PR_ALC_CTRL_3 0x03
  171. #define RT5645_PR_ALC_CTRL_4 0x04
  172. #define RT5645_PR_ALC_CTRL_5 0x05
  173. #define RT5645_PR_ALC_CTRL_6 0x06
  174. #define RT5645_BIAS_CUR1 0x12
  175. #define RT5645_BIAS_CUR3 0x14
  176. #define RT5645_CLSD_INT_REG1 0x1c
  177. #define RT5645_MAMP_INT_REG2 0x37
  178. #define RT5645_CHOP_DAC_ADC 0x3d
  179. #define RT5645_MIXER_INT_REG 0x3f
  180. #define RT5645_3D_SPK 0x63
  181. #define RT5645_WND_1 0x6c
  182. #define RT5645_WND_2 0x6d
  183. #define RT5645_WND_3 0x6e
  184. #define RT5645_WND_4 0x6f
  185. #define RT5645_WND_5 0x70
  186. #define RT5645_WND_8 0x73
  187. #define RT5645_DIP_SPK_INF 0x75
  188. #define RT5645_HP_DCC_INT1 0x77
  189. #define RT5645_EQ_BW_LOP 0xa0
  190. #define RT5645_EQ_GN_LOP 0xa1
  191. #define RT5645_EQ_FC_BP1 0xa2
  192. #define RT5645_EQ_BW_BP1 0xa3
  193. #define RT5645_EQ_GN_BP1 0xa4
  194. #define RT5645_EQ_FC_BP2 0xa5
  195. #define RT5645_EQ_BW_BP2 0xa6
  196. #define RT5645_EQ_GN_BP2 0xa7
  197. #define RT5645_EQ_FC_BP3 0xa8
  198. #define RT5645_EQ_BW_BP3 0xa9
  199. #define RT5645_EQ_GN_BP3 0xaa
  200. #define RT5645_EQ_FC_BP4 0xab
  201. #define RT5645_EQ_BW_BP4 0xac
  202. #define RT5645_EQ_GN_BP4 0xad
  203. #define RT5645_EQ_FC_HIP1 0xae
  204. #define RT5645_EQ_GN_HIP1 0xaf
  205. #define RT5645_EQ_FC_HIP2 0xb0
  206. #define RT5645_EQ_BW_HIP2 0xb1
  207. #define RT5645_EQ_GN_HIP2 0xb2
  208. #define RT5645_EQ_PRE_VOL 0xb3
  209. #define RT5645_EQ_PST_VOL 0xb4
  210. /* global definition */
  211. #define RT5645_L_MUTE (0x1 << 15)
  212. #define RT5645_L_MUTE_SFT 15
  213. #define RT5645_VOL_L_MUTE (0x1 << 14)
  214. #define RT5645_VOL_L_SFT 14
  215. #define RT5645_R_MUTE (0x1 << 7)
  216. #define RT5645_R_MUTE_SFT 7
  217. #define RT5645_VOL_R_MUTE (0x1 << 6)
  218. #define RT5645_VOL_R_SFT 6
  219. #define RT5645_L_VOL_MASK (0x3f << 8)
  220. #define RT5645_L_VOL_SFT 8
  221. #define RT5645_R_VOL_MASK (0x3f)
  222. #define RT5645_R_VOL_SFT 0
  223. /* IN1 Control 1 (0x0a) */
  224. #define RT5645_CBJ_BST1_MASK (0xf << 12)
  225. #define RT5645_CBJ_BST1_SFT (12)
  226. #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
  227. #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
  228. #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
  229. #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
  230. #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
  231. #define RT5645_CBJ_MIC_SW (0x1 << 4)
  232. #define RT5645_CBJ_BST1_EN (0x1 << 2)
  233. /* IN1 Control 2 (0x0b) */
  234. #define RT5645_CBJ_MN_JD (0x1 << 12)
  235. #define RT5645_CAPLESS_EN (0x1 << 11)
  236. #define RT5645_CBJ_DET_MODE (0x1 << 7)
  237. /* IN1 Control 3 (0x0c) */
  238. #define RT5645_CBJ_TIE_G_L (0x1 << 15)
  239. #define RT5645_CBJ_TIE_G_R (0x1 << 14)
  240. /* IN2 Control (0x0d) */
  241. #define RT5645_BST_MASK1 (0xf<<12)
  242. #define RT5645_BST_SFT1 12
  243. #define RT5645_BST_MASK2 (0xf<<8)
  244. #define RT5645_BST_SFT2 8
  245. #define RT5645_IN_DF2 (0x1 << 6)
  246. #define RT5645_IN_SFT2 6
  247. /* INL and INR Volume Control (0x0f) */
  248. #define RT5645_INL_SEL_MASK (0x1 << 15)
  249. #define RT5645_INL_SEL_SFT 15
  250. #define RT5645_INL_SEL_IN4P (0x0 << 15)
  251. #define RT5645_INL_SEL_MONOP (0x1 << 15)
  252. #define RT5645_INL_VOL_MASK (0x1f << 8)
  253. #define RT5645_INL_VOL_SFT 8
  254. #define RT5645_INR_SEL_MASK (0x1 << 7)
  255. #define RT5645_INR_SEL_SFT 7
  256. #define RT5645_INR_SEL_IN4N (0x0 << 7)
  257. #define RT5645_INR_SEL_MONON (0x1 << 7)
  258. #define RT5645_INR_VOL_MASK (0x1f)
  259. #define RT5645_INR_VOL_SFT 0
  260. /* DAC1 Digital Volume (0x19) */
  261. #define RT5645_DAC_L1_VOL_MASK (0xff << 8)
  262. #define RT5645_DAC_L1_VOL_SFT 8
  263. #define RT5645_DAC_R1_VOL_MASK (0xff)
  264. #define RT5645_DAC_R1_VOL_SFT 0
  265. /* DAC2 Digital Volume (0x1a) */
  266. #define RT5645_DAC_L2_VOL_MASK (0xff << 8)
  267. #define RT5645_DAC_L2_VOL_SFT 8
  268. #define RT5645_DAC_R2_VOL_MASK (0xff)
  269. #define RT5645_DAC_R2_VOL_SFT 0
  270. /* DAC2 Control (0x1b) */
  271. #define RT5645_M_DAC_L2_VOL (0x1 << 13)
  272. #define RT5645_M_DAC_L2_VOL_SFT 13
  273. #define RT5645_M_DAC_R2_VOL (0x1 << 12)
  274. #define RT5645_M_DAC_R2_VOL_SFT 12
  275. #define RT5645_DAC2_L_SEL_MASK (0x7 << 4)
  276. #define RT5645_DAC2_L_SEL_SFT 4
  277. #define RT5645_DAC2_R_SEL_MASK (0x7 << 0)
  278. #define RT5645_DAC2_R_SEL_SFT 0
  279. /* ADC Digital Volume Control (0x1c) */
  280. #define RT5645_ADC_L_VOL_MASK (0x7f << 8)
  281. #define RT5645_ADC_L_VOL_SFT 8
  282. #define RT5645_ADC_R_VOL_MASK (0x7f)
  283. #define RT5645_ADC_R_VOL_SFT 0
  284. /* Mono ADC Digital Volume Control (0x1d) */
  285. #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
  286. #define RT5645_MONO_ADC_L_VOL_SFT 8
  287. #define RT5645_MONO_ADC_R_VOL_MASK (0x7f)
  288. #define RT5645_MONO_ADC_R_VOL_SFT 0
  289. /* ADC Boost Volume Control (0x1e) */
  290. #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
  291. #define RT5645_STO1_ADC_L_BST_SFT 14
  292. #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
  293. #define RT5645_STO1_ADC_R_BST_SFT 12
  294. #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
  295. #define RT5645_STO1_ADC_COMP_SFT 10
  296. /* ADC Boost Volume Control (0x20) */
  297. #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
  298. #define RT5645_MONO_ADC_L_BST_SFT 14
  299. #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
  300. #define RT5645_MONO_ADC_R_BST_SFT 12
  301. #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
  302. #define RT5645_MONO_ADC_COMP_SFT 10
  303. /* Stereo2 ADC Mixer Control (0x26) */
  304. #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
  305. #define RT5645_STO2_ADC_SRC_SFT 15
  306. /* Stereo ADC Mixer Control (0x27) */
  307. #define RT5645_M_ADC_L1 (0x1 << 14)
  308. #define RT5645_M_ADC_L1_SFT 14
  309. #define RT5645_M_ADC_L2 (0x1 << 13)
  310. #define RT5645_M_ADC_L2_SFT 13
  311. #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
  312. #define RT5645_ADC_1_SRC_SFT 12
  313. #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
  314. #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
  315. #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
  316. #define RT5645_ADC_2_SRC_SFT 11
  317. #define RT5645_DMIC_SRC_MASK (0x1 << 8)
  318. #define RT5645_DMIC_SRC_SFT 8
  319. #define RT5645_M_ADC_R1 (0x1 << 6)
  320. #define RT5645_M_ADC_R1_SFT 6
  321. #define RT5645_M_ADC_R2 (0x1 << 5)
  322. #define RT5645_M_ADC_R2_SFT 5
  323. #define RT5645_DMIC3_SRC_MASK (0x1 << 1)
  324. #define RT5645_DMIC3_SRC_SFT 0
  325. /* Mono ADC Mixer Control (0x28) */
  326. #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
  327. #define RT5645_M_MONO_ADC_L1_SFT 14
  328. #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
  329. #define RT5645_M_MONO_ADC_L2_SFT 13
  330. #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
  331. #define RT5645_MONO_ADC_L1_SRC_SFT 12
  332. #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
  333. #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
  334. #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
  335. #define RT5645_MONO_ADC_L2_SRC_SFT 11
  336. #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
  337. #define RT5645_MONO_DMIC_L_SRC_SFT 8
  338. #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
  339. #define RT5645_M_MONO_ADC_R1_SFT 6
  340. #define RT5645_M_MONO_ADC_R2 (0x1 << 5)
  341. #define RT5645_M_MONO_ADC_R2_SFT 5
  342. #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
  343. #define RT5645_MONO_ADC_R1_SRC_SFT 4
  344. #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
  345. #define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
  346. #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
  347. #define RT5645_MONO_ADC_R2_SRC_SFT 3
  348. #define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
  349. #define RT5645_MONO_DMIC_R_SRC_SFT 0
  350. /* ADC Mixer to DAC Mixer Control (0x29) */
  351. #define RT5645_M_ADCMIX_L (0x1 << 15)
  352. #define RT5645_M_ADCMIX_L_SFT 15
  353. #define RT5645_M_DAC1_L (0x1 << 14)
  354. #define RT5645_M_DAC1_L_SFT 14
  355. #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
  356. #define RT5645_DAC1_R_SEL_SFT 10
  357. #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
  358. #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
  359. #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
  360. #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
  361. #define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
  362. #define RT5645_DAC1_L_SEL_SFT 8
  363. #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
  364. #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
  365. #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
  366. #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
  367. #define RT5645_M_ADCMIX_R (0x1 << 7)
  368. #define RT5645_M_ADCMIX_R_SFT 7
  369. #define RT5645_M_DAC1_R (0x1 << 6)
  370. #define RT5645_M_DAC1_R_SFT 6
  371. /* Stereo DAC Mixer Control (0x2a) */
  372. #define RT5645_M_DAC_L1 (0x1 << 14)
  373. #define RT5645_M_DAC_L1_SFT 14
  374. #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
  375. #define RT5645_DAC_L1_STO_L_VOL_SFT 13
  376. #define RT5645_M_DAC_L2 (0x1 << 12)
  377. #define RT5645_M_DAC_L2_SFT 12
  378. #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
  379. #define RT5645_DAC_L2_STO_L_VOL_SFT 11
  380. #define RT5645_M_ANC_DAC_L (0x1 << 10)
  381. #define RT5645_M_ANC_DAC_L_SFT 10
  382. #define RT5645_M_DAC_R1_STO_L (0x1 << 9)
  383. #define RT5645_M_DAC_R1_STO_L_SFT 9
  384. #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
  385. #define RT5645_DAC_R1_STO_L_VOL_SFT 8
  386. #define RT5645_M_DAC_R1 (0x1 << 6)
  387. #define RT5645_M_DAC_R1_SFT 6
  388. #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
  389. #define RT5645_DAC_R1_STO_R_VOL_SFT 5
  390. #define RT5645_M_DAC_R2 (0x1 << 4)
  391. #define RT5645_M_DAC_R2_SFT 4
  392. #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
  393. #define RT5645_DAC_R2_STO_R_VOL_SFT 3
  394. #define RT5645_M_ANC_DAC_R (0x1 << 2)
  395. #define RT5645_M_ANC_DAC_R_SFT 2
  396. #define RT5645_M_DAC_L1_STO_R (0x1 << 1)
  397. #define RT5645_M_DAC_L1_STO_R_SFT 1
  398. #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
  399. #define RT5645_DAC_L1_STO_R_VOL_SFT 0
  400. /* Mono DAC Mixer Control (0x2b) */
  401. #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
  402. #define RT5645_M_DAC_L1_MONO_L_SFT 14
  403. #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
  404. #define RT5645_DAC_L1_MONO_L_VOL_SFT 13
  405. #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
  406. #define RT5645_M_DAC_L2_MONO_L_SFT 12
  407. #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
  408. #define RT5645_DAC_L2_MONO_L_VOL_SFT 11
  409. #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
  410. #define RT5645_M_DAC_R2_MONO_L_SFT 10
  411. #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
  412. #define RT5645_DAC_R2_MONO_L_VOL_SFT 9
  413. #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
  414. #define RT5645_M_DAC_R1_MONO_R_SFT 6
  415. #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
  416. #define RT5645_DAC_R1_MONO_R_VOL_SFT 5
  417. #define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
  418. #define RT5645_M_DAC_R2_MONO_R_SFT 4
  419. #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
  420. #define RT5645_DAC_R2_MONO_R_VOL_SFT 3
  421. #define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
  422. #define RT5645_M_DAC_L2_MONO_R_SFT 2
  423. #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
  424. #define RT5645_DAC_L2_MONO_R_VOL_SFT 1
  425. /* Digital Mixer Control (0x2c) */
  426. #define RT5645_M_STO_L_DAC_L (0x1 << 15)
  427. #define RT5645_M_STO_L_DAC_L_SFT 15
  428. #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
  429. #define RT5645_STO_L_DAC_L_VOL_SFT 14
  430. #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
  431. #define RT5645_M_DAC_L2_DAC_L_SFT 13
  432. #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
  433. #define RT5645_DAC_L2_DAC_L_VOL_SFT 12
  434. #define RT5645_M_STO_R_DAC_R (0x1 << 11)
  435. #define RT5645_M_STO_R_DAC_R_SFT 11
  436. #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
  437. #define RT5645_STO_R_DAC_R_VOL_SFT 10
  438. #define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
  439. #define RT5645_M_DAC_R2_DAC_R_SFT 9
  440. #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
  441. #define RT5645_DAC_R2_DAC_R_VOL_SFT 8
  442. #define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
  443. #define RT5645_M_DAC_R2_DAC_L_SFT 7
  444. #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
  445. #define RT5645_DAC_R2_DAC_L_VOL_SFT 6
  446. #define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
  447. #define RT5645_M_DAC_L2_DAC_R_SFT 5
  448. #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
  449. #define RT5645_DAC_L2_DAC_R_VOL_SFT 4
  450. /* Analog DAC1/2 Input Source Control (0x2d) */
  451. #define RT5650_A_DAC1_L_IN_SFT 3
  452. #define RT5650_A_DAC1_R_IN_SFT 2
  453. #define RT5650_A_DAC2_L_IN_SFT 1
  454. #define RT5650_A_DAC2_R_IN_SFT 0
  455. /* Digital Interface Data Control (0x2f) */
  456. #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
  457. #define RT5645_IF1_ADC2_IN_SFT 15
  458. #define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
  459. #define RT5645_IF2_ADC_IN_SFT 12
  460. #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
  461. #define RT5645_IF2_DAC_SEL_SFT 10
  462. #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
  463. #define RT5645_IF2_ADC_SEL_SFT 8
  464. #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
  465. #define RT5645_IF3_DAC_SEL_SFT 6
  466. #define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)
  467. #define RT5645_IF3_ADC_SEL_SFT 4
  468. #define RT5645_IF3_ADC_IN_MASK (0x7)
  469. #define RT5645_IF3_ADC_IN_SFT 0
  470. /* PDM Output Control (0x31) */
  471. #define RT5645_PDM1_L_MASK (0x1 << 15)
  472. #define RT5645_PDM1_L_SFT 15
  473. #define RT5645_M_PDM1_L (0x1 << 14)
  474. #define RT5645_M_PDM1_L_SFT 14
  475. #define RT5645_PDM1_R_MASK (0x1 << 13)
  476. #define RT5645_PDM1_R_SFT 13
  477. #define RT5645_M_PDM1_R (0x1 << 12)
  478. #define RT5645_M_PDM1_R_SFT 12
  479. #define RT5645_PDM2_L_MASK (0x1 << 11)
  480. #define RT5645_PDM2_L_SFT 11
  481. #define RT5645_M_PDM2_L (0x1 << 10)
  482. #define RT5645_M_PDM2_L_SFT 10
  483. #define RT5645_PDM2_R_MASK (0x1 << 9)
  484. #define RT5645_PDM2_R_SFT 9
  485. #define RT5645_M_PDM2_R (0x1 << 8)
  486. #define RT5645_M_PDM2_R_SFT 8
  487. #define RT5645_PDM2_BUSY (0x1 << 7)
  488. #define RT5645_PDM1_BUSY (0x1 << 6)
  489. #define RT5645_PDM_PATTERN (0x1 << 5)
  490. #define RT5645_PDM_GAIN (0x1 << 4)
  491. #define RT5645_PDM_DIV_MASK (0x3)
  492. /* REC Left Mixer Control 1 (0x3b) */
  493. #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
  494. #define RT5645_G_HP_L_RM_L_SFT 13
  495. #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
  496. #define RT5645_G_IN_L_RM_L_SFT 10
  497. #define RT5645_G_BST4_RM_L_MASK (0x7 << 7)
  498. #define RT5645_G_BST4_RM_L_SFT 7
  499. #define RT5645_G_BST3_RM_L_MASK (0x7 << 4)
  500. #define RT5645_G_BST3_RM_L_SFT 4
  501. #define RT5645_G_BST2_RM_L_MASK (0x7 << 1)
  502. #define RT5645_G_BST2_RM_L_SFT 1
  503. /* REC Left Mixer Control 2 (0x3c) */
  504. #define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
  505. #define RT5645_G_BST1_RM_L_SFT 13
  506. #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
  507. #define RT5645_G_OM_L_RM_L_SFT 10
  508. #define RT5645_M_MM_L_RM_L (0x1 << 6)
  509. #define RT5645_M_MM_L_RM_L_SFT 6
  510. #define RT5645_M_IN_L_RM_L (0x1 << 5)
  511. #define RT5645_M_IN_L_RM_L_SFT 5
  512. #define RT5645_M_HP_L_RM_L (0x1 << 4)
  513. #define RT5645_M_HP_L_RM_L_SFT 4
  514. #define RT5645_M_BST3_RM_L (0x1 << 3)
  515. #define RT5645_M_BST3_RM_L_SFT 3
  516. #define RT5645_M_BST2_RM_L (0x1 << 2)
  517. #define RT5645_M_BST2_RM_L_SFT 2
  518. #define RT5645_M_BST1_RM_L (0x1 << 1)
  519. #define RT5645_M_BST1_RM_L_SFT 1
  520. #define RT5645_M_OM_L_RM_L (0x1)
  521. #define RT5645_M_OM_L_RM_L_SFT 0
  522. /* REC Right Mixer Control 1 (0x3d) */
  523. #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
  524. #define RT5645_G_HP_R_RM_R_SFT 13
  525. #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
  526. #define RT5645_G_IN_R_RM_R_SFT 10
  527. #define RT5645_G_BST4_RM_R_MASK (0x7 << 7)
  528. #define RT5645_G_BST4_RM_R_SFT 7
  529. #define RT5645_G_BST3_RM_R_MASK (0x7 << 4)
  530. #define RT5645_G_BST3_RM_R_SFT 4
  531. #define RT5645_G_BST2_RM_R_MASK (0x7 << 1)
  532. #define RT5645_G_BST2_RM_R_SFT 1
  533. /* REC Right Mixer Control 2 (0x3e) */
  534. #define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
  535. #define RT5645_G_BST1_RM_R_SFT 13
  536. #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
  537. #define RT5645_G_OM_R_RM_R_SFT 10
  538. #define RT5645_M_MM_R_RM_R (0x1 << 6)
  539. #define RT5645_M_MM_R_RM_R_SFT 6
  540. #define RT5645_M_IN_R_RM_R (0x1 << 5)
  541. #define RT5645_M_IN_R_RM_R_SFT 5
  542. #define RT5645_M_HP_R_RM_R (0x1 << 4)
  543. #define RT5645_M_HP_R_RM_R_SFT 4
  544. #define RT5645_M_BST3_RM_R (0x1 << 3)
  545. #define RT5645_M_BST3_RM_R_SFT 3
  546. #define RT5645_M_BST2_RM_R (0x1 << 2)
  547. #define RT5645_M_BST2_RM_R_SFT 2
  548. #define RT5645_M_BST1_RM_R (0x1 << 1)
  549. #define RT5645_M_BST1_RM_R_SFT 1
  550. #define RT5645_M_OM_R_RM_R (0x1)
  551. #define RT5645_M_OM_R_RM_R_SFT 0
  552. /* HPOMIX Control (0x40) (0x42) */
  553. #define RT5645_M_BST1_HV (0x1 << 4)
  554. #define RT5645_M_BST1_HV_SFT 4
  555. #define RT5645_M_BST2_HV (0x1 << 4)
  556. #define RT5645_M_BST2_HV_SFT 4
  557. #define RT5645_M_BST3_HV (0x1 << 3)
  558. #define RT5645_M_BST3_HV_SFT 3
  559. #define RT5645_M_IN_HV (0x1 << 2)
  560. #define RT5645_M_IN_HV_SFT 2
  561. #define RT5645_M_DAC2_HV (0x1 << 1)
  562. #define RT5645_M_DAC2_HV_SFT 1
  563. #define RT5645_M_DAC1_HV (0x1 << 0)
  564. #define RT5645_M_DAC1_HV_SFT 0
  565. /* HPMIX Control (0x45) */
  566. #define RT5645_M_DAC1_HM (0x1 << 14)
  567. #define RT5645_M_DAC1_HM_SFT 14
  568. #define RT5645_M_HPVOL_HM (0x1 << 13)
  569. #define RT5645_M_HPVOL_HM_SFT 13
  570. #define RT5645_IRQ_PSV_MODE (0x1 << 12)
  571. /* SPK Left Mixer Control (0x46) */
  572. #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
  573. #define RT5645_G_RM_L_SM_L_SFT 14
  574. #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
  575. #define RT5645_G_IN_L_SM_L_SFT 12
  576. #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
  577. #define RT5645_G_DAC_L1_SM_L_SFT 10
  578. #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
  579. #define RT5645_G_DAC_L2_SM_L_SFT 8
  580. #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
  581. #define RT5645_G_OM_L_SM_L_SFT 6
  582. #define RT5645_M_BST1_L_SM_L (0x1 << 5)
  583. #define RT5645_M_BST1_L_SM_L_SFT 5
  584. #define RT5645_M_BST3_L_SM_L (0x1 << 4)
  585. #define RT5645_M_BST3_L_SM_L_SFT 4
  586. #define RT5645_M_IN_L_SM_L (0x1 << 3)
  587. #define RT5645_M_IN_L_SM_L_SFT 3
  588. #define RT5645_M_DAC_L2_SM_L (0x1 << 2)
  589. #define RT5645_M_DAC_L2_SM_L_SFT 2
  590. #define RT5645_M_DAC_L1_SM_L (0x1 << 1)
  591. #define RT5645_M_DAC_L1_SM_L_SFT 1
  592. /* SPK Right Mixer Control (0x47) */
  593. #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
  594. #define RT5645_G_RM_R_SM_R_SFT 14
  595. #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
  596. #define RT5645_G_IN_R_SM_R_SFT 12
  597. #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
  598. #define RT5645_G_DAC_R1_SM_R_SFT 10
  599. #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
  600. #define RT5645_G_DAC_R2_SM_R_SFT 8
  601. #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
  602. #define RT5645_G_OM_R_SM_R_SFT 6
  603. #define RT5645_M_BST2_R_SM_R (0x1 << 5)
  604. #define RT5645_M_BST2_R_SM_R_SFT 5
  605. #define RT5645_M_BST3_R_SM_R (0x1 << 4)
  606. #define RT5645_M_BST3_R_SM_R_SFT 4
  607. #define RT5645_M_IN_R_SM_R (0x1 << 3)
  608. #define RT5645_M_IN_R_SM_R_SFT 3
  609. #define RT5645_M_DAC_R2_SM_R (0x1 << 2)
  610. #define RT5645_M_DAC_R2_SM_R_SFT 2
  611. #define RT5645_M_DAC_R1_SM_R (0x1 << 1)
  612. #define RT5645_M_DAC_R1_SM_R_SFT 1
  613. /* SPOLMIX Control (0x48) */
  614. #define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
  615. #define RT5645_M_DAC_L1_SPM_L_SFT 15
  616. #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
  617. #define RT5645_M_DAC_R1_SPM_L_SFT 14
  618. #define RT5645_M_SV_L_SPM_L (0x1 << 13)
  619. #define RT5645_M_SV_L_SPM_L_SFT 13
  620. #define RT5645_M_SV_R_SPM_L (0x1 << 12)
  621. #define RT5645_M_SV_R_SPM_L_SFT 12
  622. #define RT5645_M_BST3_SPM_L (0x1 << 11)
  623. #define RT5645_M_BST3_SPM_L_SFT 11
  624. #define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
  625. #define RT5645_M_DAC_R1_SPM_R_SFT 2
  626. #define RT5645_M_BST3_SPM_R (0x1 << 1)
  627. #define RT5645_M_BST3_SPM_R_SFT 1
  628. #define RT5645_M_SV_R_SPM_R (0x1 << 0)
  629. #define RT5645_M_SV_R_SPM_R_SFT 0
  630. /* SPOMIX Ratio Control (0x4a) */
  631. #define RT5645_SPK_G_CLSD_MASK (0x7 << 0)
  632. #define RT5645_SPK_G_CLSD_SFT 0
  633. /* Mono Output Mixer Control (0x4c) */
  634. #define RT5645_G_MONOMIX_MASK (0x1 << 10)
  635. #define RT5645_G_MONOMIX_SFT 10
  636. #define RT5645_M_OV_L_MM (0x1 << 9)
  637. #define RT5645_M_OV_L_MM_SFT 9
  638. #define RT5645_M_DAC_L2_MA (0x1 << 8)
  639. #define RT5645_M_DAC_L2_MA_SFT 8
  640. #define RT5645_M_BST2_MM (0x1 << 4)
  641. #define RT5645_M_BST2_MM_SFT 4
  642. #define RT5645_M_DAC_R1_MM (0x1 << 3)
  643. #define RT5645_M_DAC_R1_MM_SFT 3
  644. #define RT5645_M_DAC_R2_MM (0x1 << 2)
  645. #define RT5645_M_DAC_R2_MM_SFT 2
  646. #define RT5645_M_DAC_L2_MM (0x1 << 1)
  647. #define RT5645_M_DAC_L2_MM_SFT 1
  648. #define RT5645_M_BST3_MM (0x1 << 0)
  649. #define RT5645_M_BST3_MM_SFT 0
  650. /* Output Left Mixer Control 1 (0x4d) */
  651. #define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
  652. #define RT5645_G_BST3_OM_L_SFT 13
  653. #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
  654. #define RT5645_G_BST2_OM_L_SFT 10
  655. #define RT5645_G_BST1_OM_L_MASK (0x7 << 7)
  656. #define RT5645_G_BST1_OM_L_SFT 7
  657. #define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)
  658. #define RT5645_G_IN_L_OM_L_SFT 4
  659. #define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)
  660. #define RT5645_G_RM_L_OM_L_SFT 1
  661. /* Output Left Mixer Control 2 (0x4e) */
  662. #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
  663. #define RT5645_G_DAC_R2_OM_L_SFT 13
  664. #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
  665. #define RT5645_G_DAC_L2_OM_L_SFT 10
  666. #define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)
  667. #define RT5645_G_DAC_L1_OM_L_SFT 7
  668. /* Output Left Mixer Control 3 (0x4f) */
  669. #define RT5645_M_BST3_OM_L (0x1 << 4)
  670. #define RT5645_M_BST3_OM_L_SFT 4
  671. #define RT5645_M_BST1_OM_L (0x1 << 3)
  672. #define RT5645_M_BST1_OM_L_SFT 3
  673. #define RT5645_M_IN_L_OM_L (0x1 << 2)
  674. #define RT5645_M_IN_L_OM_L_SFT 2
  675. #define RT5645_M_DAC_L2_OM_L (0x1 << 1)
  676. #define RT5645_M_DAC_L2_OM_L_SFT 1
  677. #define RT5645_M_DAC_L1_OM_L (0x1)
  678. #define RT5645_M_DAC_L1_OM_L_SFT 0
  679. /* Output Right Mixer Control 1 (0x50) */
  680. #define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
  681. #define RT5645_G_BST4_OM_R_SFT 13
  682. #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
  683. #define RT5645_G_BST2_OM_R_SFT 10
  684. #define RT5645_G_BST1_OM_R_MASK (0x7 << 7)
  685. #define RT5645_G_BST1_OM_R_SFT 7
  686. #define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)
  687. #define RT5645_G_IN_R_OM_R_SFT 4
  688. #define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)
  689. #define RT5645_G_RM_R_OM_R_SFT 1
  690. /* Output Right Mixer Control 2 (0x51) */
  691. #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
  692. #define RT5645_G_DAC_L2_OM_R_SFT 13
  693. #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
  694. #define RT5645_G_DAC_R2_OM_R_SFT 10
  695. #define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)
  696. #define RT5645_G_DAC_R1_OM_R_SFT 7
  697. /* Output Right Mixer Control 3 (0x52) */
  698. #define RT5645_M_BST3_OM_R (0x1 << 4)
  699. #define RT5645_M_BST3_OM_R_SFT 4
  700. #define RT5645_M_BST2_OM_R (0x1 << 3)
  701. #define RT5645_M_BST2_OM_R_SFT 3
  702. #define RT5645_M_IN_R_OM_R (0x1 << 2)
  703. #define RT5645_M_IN_R_OM_R_SFT 2
  704. #define RT5645_M_DAC_R2_OM_R (0x1 << 1)
  705. #define RT5645_M_DAC_R2_OM_R_SFT 1
  706. #define RT5645_M_DAC_R1_OM_R (0x1)
  707. #define RT5645_M_DAC_R1_OM_R_SFT 0
  708. /* LOUT Mixer Control (0x53) */
  709. #define RT5645_M_DAC_L1_LM (0x1 << 15)
  710. #define RT5645_M_DAC_L1_LM_SFT 15
  711. #define RT5645_M_DAC_R1_LM (0x1 << 14)
  712. #define RT5645_M_DAC_R1_LM_SFT 14
  713. #define RT5645_M_OV_L_LM (0x1 << 13)
  714. #define RT5645_M_OV_L_LM_SFT 13
  715. #define RT5645_M_OV_R_LM (0x1 << 12)
  716. #define RT5645_M_OV_R_LM_SFT 12
  717. #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
  718. #define RT5645_G_LOUTMIX_SFT 11
  719. /* Power Management for Digital 1 (0x61) */
  720. #define RT5645_PWR_I2S1 (0x1 << 15)
  721. #define RT5645_PWR_I2S1_BIT 15
  722. #define RT5645_PWR_I2S2 (0x1 << 14)
  723. #define RT5645_PWR_I2S2_BIT 14
  724. #define RT5645_PWR_I2S3 (0x1 << 13)
  725. #define RT5645_PWR_I2S3_BIT 13
  726. #define RT5645_PWR_DAC_L1 (0x1 << 12)
  727. #define RT5645_PWR_DAC_L1_BIT 12
  728. #define RT5645_PWR_DAC_R1 (0x1 << 11)
  729. #define RT5645_PWR_DAC_R1_BIT 11
  730. #define RT5645_PWR_CLS_D_R (0x1 << 9)
  731. #define RT5645_PWR_CLS_D_R_BIT 9
  732. #define RT5645_PWR_CLS_D_L (0x1 << 8)
  733. #define RT5645_PWR_CLS_D_L_BIT 8
  734. #define RT5645_PWR_DAC_L2 (0x1 << 7)
  735. #define RT5645_PWR_DAC_L2_BIT 7
  736. #define RT5645_PWR_DAC_R2 (0x1 << 6)
  737. #define RT5645_PWR_DAC_R2_BIT 6
  738. #define RT5645_PWR_ADC_L (0x1 << 2)
  739. #define RT5645_PWR_ADC_L_BIT 2
  740. #define RT5645_PWR_ADC_R (0x1 << 1)
  741. #define RT5645_PWR_ADC_R_BIT 1
  742. #define RT5645_PWR_CLS_D (0x1)
  743. #define RT5645_PWR_CLS_D_BIT 0
  744. /* Power Management for Digital 2 (0x62) */
  745. #define RT5645_PWR_ADC_S1F (0x1 << 15)
  746. #define RT5645_PWR_ADC_S1F_BIT 15
  747. #define RT5645_PWR_ADC_MF_L (0x1 << 14)
  748. #define RT5645_PWR_ADC_MF_L_BIT 14
  749. #define RT5645_PWR_ADC_MF_R (0x1 << 13)
  750. #define RT5645_PWR_ADC_MF_R_BIT 13
  751. #define RT5645_PWR_I2S_DSP (0x1 << 12)
  752. #define RT5645_PWR_I2S_DSP_BIT 12
  753. #define RT5645_PWR_DAC_S1F (0x1 << 11)
  754. #define RT5645_PWR_DAC_S1F_BIT 11
  755. #define RT5645_PWR_DAC_MF_L (0x1 << 10)
  756. #define RT5645_PWR_DAC_MF_L_BIT 10
  757. #define RT5645_PWR_DAC_MF_R (0x1 << 9)
  758. #define RT5645_PWR_DAC_MF_R_BIT 9
  759. #define RT5645_PWR_PDM1 (0x1 << 7)
  760. #define RT5645_PWR_PDM1_BIT 7
  761. #define RT5645_PWR_PDM2 (0x1 << 6)
  762. #define RT5645_PWR_PDM2_BIT 6
  763. #define RT5645_PWR_IPTV (0x1 << 1)
  764. #define RT5645_PWR_IPTV_BIT 1
  765. #define RT5645_PWR_PAD (0x1)
  766. #define RT5645_PWR_PAD_BIT 0
  767. /* Power Management for Analog 1 (0x63) */
  768. #define RT5645_PWR_VREF1 (0x1 << 15)
  769. #define RT5645_PWR_VREF1_BIT 15
  770. #define RT5645_PWR_FV1 (0x1 << 14)
  771. #define RT5645_PWR_FV1_BIT 14
  772. #define RT5645_PWR_MB (0x1 << 13)
  773. #define RT5645_PWR_MB_BIT 13
  774. #define RT5645_PWR_LM (0x1 << 12)
  775. #define RT5645_PWR_LM_BIT 12
  776. #define RT5645_PWR_BG (0x1 << 11)
  777. #define RT5645_PWR_BG_BIT 11
  778. #define RT5645_PWR_MA (0x1 << 10)
  779. #define RT5645_PWR_MA_BIT 10
  780. #define RT5645_PWR_HP_L (0x1 << 7)
  781. #define RT5645_PWR_HP_L_BIT 7
  782. #define RT5645_PWR_HP_R (0x1 << 6)
  783. #define RT5645_PWR_HP_R_BIT 6
  784. #define RT5645_PWR_HA (0x1 << 5)
  785. #define RT5645_PWR_HA_BIT 5
  786. #define RT5645_PWR_VREF2 (0x1 << 4)
  787. #define RT5645_PWR_VREF2_BIT 4
  788. #define RT5645_PWR_FV2 (0x1 << 3)
  789. #define RT5645_PWR_FV2_BIT 3
  790. #define RT5645_LDO_SEL_MASK (0x3)
  791. #define RT5645_LDO_SEL_SFT 0
  792. /* Power Management for Analog 2 (0x64) */
  793. #define RT5645_PWR_BST1 (0x1 << 15)
  794. #define RT5645_PWR_BST1_BIT 15
  795. #define RT5645_PWR_BST2 (0x1 << 14)
  796. #define RT5645_PWR_BST2_BIT 14
  797. #define RT5645_PWR_BST3 (0x1 << 13)
  798. #define RT5645_PWR_BST3_BIT 13
  799. #define RT5645_PWR_BST4 (0x1 << 12)
  800. #define RT5645_PWR_BST4_BIT 12
  801. #define RT5645_PWR_MB1 (0x1 << 11)
  802. #define RT5645_PWR_MB1_BIT 11
  803. #define RT5645_PWR_MB2 (0x1 << 10)
  804. #define RT5645_PWR_MB2_BIT 10
  805. #define RT5645_PWR_PLL (0x1 << 9)
  806. #define RT5645_PWR_PLL_BIT 9
  807. #define RT5645_PWR_BST2_P (0x1 << 5)
  808. #define RT5645_PWR_BST2_P_BIT 5
  809. #define RT5645_PWR_BST3_P (0x1 << 4)
  810. #define RT5645_PWR_BST3_P_BIT 4
  811. #define RT5645_PWR_BST4_P (0x1 << 3)
  812. #define RT5645_PWR_BST4_P_BIT 3
  813. #define RT5645_PWR_JD1 (0x1 << 2)
  814. #define RT5645_PWR_JD1_BIT 2
  815. #define RT5645_PWR_JD (0x1 << 1)
  816. #define RT5645_PWR_JD_BIT 1
  817. /* Power Management for Mixer (0x65) */
  818. #define RT5645_PWR_OM_L (0x1 << 15)
  819. #define RT5645_PWR_OM_L_BIT 15
  820. #define RT5645_PWR_OM_R (0x1 << 14)
  821. #define RT5645_PWR_OM_R_BIT 14
  822. #define RT5645_PWR_SM_L (0x1 << 13)
  823. #define RT5645_PWR_SM_L_BIT 13
  824. #define RT5645_PWR_SM_R (0x1 << 12)
  825. #define RT5645_PWR_SM_R_BIT 12
  826. #define RT5645_PWR_RM_L (0x1 << 11)
  827. #define RT5645_PWR_RM_L_BIT 11
  828. #define RT5645_PWR_RM_R (0x1 << 10)
  829. #define RT5645_PWR_RM_R_BIT 10
  830. #define RT5645_PWR_MM (0x1 << 8)
  831. #define RT5645_PWR_MM_BIT 8
  832. #define RT5645_PWR_HM_L (0x1 << 7)
  833. #define RT5645_PWR_HM_L_BIT 7
  834. #define RT5645_PWR_HM_R (0x1 << 6)
  835. #define RT5645_PWR_HM_R_BIT 6
  836. #define RT5645_PWR_LDO2 (0x1 << 1)
  837. #define RT5645_PWR_LDO2_BIT 1
  838. /* Power Management for Volume (0x66) */
  839. #define RT5645_PWR_SV_L (0x1 << 15)
  840. #define RT5645_PWR_SV_L_BIT 15
  841. #define RT5645_PWR_SV_R (0x1 << 14)
  842. #define RT5645_PWR_SV_R_BIT 14
  843. #define RT5645_PWR_HV_L (0x1 << 11)
  844. #define RT5645_PWR_HV_L_BIT 11
  845. #define RT5645_PWR_HV_R (0x1 << 10)
  846. #define RT5645_PWR_HV_R_BIT 10
  847. #define RT5645_PWR_IN_L (0x1 << 9)
  848. #define RT5645_PWR_IN_L_BIT 9
  849. #define RT5645_PWR_IN_R (0x1 << 8)
  850. #define RT5645_PWR_IN_R_BIT 8
  851. #define RT5645_PWR_MIC_DET (0x1 << 5)
  852. #define RT5645_PWR_MIC_DET_BIT 5
  853. /* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */
  854. #define RT5645_I2S_MS_MASK (0x1 << 15)
  855. #define RT5645_I2S_MS_SFT 15
  856. #define RT5645_I2S_MS_M (0x0 << 15)
  857. #define RT5645_I2S_MS_S (0x1 << 15)
  858. #define RT5645_I2S_O_CP_MASK (0x3 << 10)
  859. #define RT5645_I2S_O_CP_SFT 10
  860. #define RT5645_I2S_O_CP_OFF (0x0 << 10)
  861. #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
  862. #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
  863. #define RT5645_I2S_I_CP_MASK (0x3 << 8)
  864. #define RT5645_I2S_I_CP_SFT 8
  865. #define RT5645_I2S_I_CP_OFF (0x0 << 8)
  866. #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
  867. #define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
  868. #define RT5645_I2S_BP_MASK (0x1 << 7)
  869. #define RT5645_I2S_BP_SFT 7
  870. #define RT5645_I2S_BP_NOR (0x0 << 7)
  871. #define RT5645_I2S_BP_INV (0x1 << 7)
  872. #define RT5645_I2S_DL_MASK (0x3 << 2)
  873. #define RT5645_I2S_DL_SFT 2
  874. #define RT5645_I2S_DL_16 (0x0 << 2)
  875. #define RT5645_I2S_DL_20 (0x1 << 2)
  876. #define RT5645_I2S_DL_24 (0x2 << 2)
  877. #define RT5645_I2S_DL_8 (0x3 << 2)
  878. #define RT5645_I2S_DF_MASK (0x3)
  879. #define RT5645_I2S_DF_SFT 0
  880. #define RT5645_I2S_DF_I2S (0x0)
  881. #define RT5645_I2S_DF_LEFT (0x1)
  882. #define RT5645_I2S_DF_PCM_A (0x2)
  883. #define RT5645_I2S_DF_PCM_B (0x3)
  884. /* I2S2 Audio Serial Data Port Control (0x71) */
  885. #define RT5645_I2S2_SDI_MASK (0x1 << 6)
  886. #define RT5645_I2S2_SDI_SFT 6
  887. #define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
  888. #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
  889. /* ADC/DAC Clock Control 1 (0x73) */
  890. #define RT5645_I2S_PD1_MASK (0x7 << 12)
  891. #define RT5645_I2S_PD1_SFT 12
  892. #define RT5645_I2S_PD1_1 (0x0 << 12)
  893. #define RT5645_I2S_PD1_2 (0x1 << 12)
  894. #define RT5645_I2S_PD1_3 (0x2 << 12)
  895. #define RT5645_I2S_PD1_4 (0x3 << 12)
  896. #define RT5645_I2S_PD1_6 (0x4 << 12)
  897. #define RT5645_I2S_PD1_8 (0x5 << 12)
  898. #define RT5645_I2S_PD1_12 (0x6 << 12)
  899. #define RT5645_I2S_PD1_16 (0x7 << 12)
  900. #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
  901. #define RT5645_I2S_BCLK_MS2_SFT 11
  902. #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
  903. #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
  904. #define RT5645_I2S_PD2_MASK (0x7 << 8)
  905. #define RT5645_I2S_PD2_SFT 8
  906. #define RT5645_I2S_PD2_1 (0x0 << 8)
  907. #define RT5645_I2S_PD2_2 (0x1 << 8)
  908. #define RT5645_I2S_PD2_3 (0x2 << 8)
  909. #define RT5645_I2S_PD2_4 (0x3 << 8)
  910. #define RT5645_I2S_PD2_6 (0x4 << 8)
  911. #define RT5645_I2S_PD2_8 (0x5 << 8)
  912. #define RT5645_I2S_PD2_12 (0x6 << 8)
  913. #define RT5645_I2S_PD2_16 (0x7 << 8)
  914. #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
  915. #define RT5645_I2S_BCLK_MS3_SFT 7
  916. #define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)
  917. #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
  918. #define RT5645_I2S_PD3_MASK (0x7 << 4)
  919. #define RT5645_I2S_PD3_SFT 4
  920. #define RT5645_I2S_PD3_1 (0x0 << 4)
  921. #define RT5645_I2S_PD3_2 (0x1 << 4)
  922. #define RT5645_I2S_PD3_3 (0x2 << 4)
  923. #define RT5645_I2S_PD3_4 (0x3 << 4)
  924. #define RT5645_I2S_PD3_6 (0x4 << 4)
  925. #define RT5645_I2S_PD3_8 (0x5 << 4)
  926. #define RT5645_I2S_PD3_12 (0x6 << 4)
  927. #define RT5645_I2S_PD3_16 (0x7 << 4)
  928. #define RT5645_DAC_OSR_MASK (0x3 << 2)
  929. #define RT5645_DAC_OSR_SFT 2
  930. #define RT5645_DAC_OSR_128 (0x0 << 2)
  931. #define RT5645_DAC_OSR_64 (0x1 << 2)
  932. #define RT5645_DAC_OSR_32 (0x2 << 2)
  933. #define RT5645_DAC_OSR_16 (0x3 << 2)
  934. #define RT5645_ADC_OSR_MASK (0x3)
  935. #define RT5645_ADC_OSR_SFT 0
  936. #define RT5645_ADC_OSR_128 (0x0)
  937. #define RT5645_ADC_OSR_64 (0x1)
  938. #define RT5645_ADC_OSR_32 (0x2)
  939. #define RT5645_ADC_OSR_16 (0x3)
  940. /* ADC/DAC Clock Control 2 (0x74) */
  941. #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
  942. #define RT5645_DAC_L_OSR_SFT 14
  943. #define RT5645_DAC_L_OSR_128 (0x0 << 14)
  944. #define RT5645_DAC_L_OSR_64 (0x1 << 14)
  945. #define RT5645_DAC_L_OSR_32 (0x2 << 14)
  946. #define RT5645_DAC_L_OSR_16 (0x3 << 14)
  947. #define RT5645_ADC_R_OSR_MASK (0x3 << 12)
  948. #define RT5645_ADC_R_OSR_SFT 12
  949. #define RT5645_ADC_R_OSR_128 (0x0 << 12)
  950. #define RT5645_ADC_R_OSR_64 (0x1 << 12)
  951. #define RT5645_ADC_R_OSR_32 (0x2 << 12)
  952. #define RT5645_ADC_R_OSR_16 (0x3 << 12)
  953. #define RT5645_DAHPF_EN (0x1 << 11)
  954. #define RT5645_DAHPF_EN_SFT 11
  955. #define RT5645_ADHPF_EN (0x1 << 10)
  956. #define RT5645_ADHPF_EN_SFT 10
  957. /* Digital Microphone Control (0x75) */
  958. #define RT5645_DMIC_1_EN_MASK (0x1 << 15)
  959. #define RT5645_DMIC_1_EN_SFT 15
  960. #define RT5645_DMIC_1_DIS (0x0 << 15)
  961. #define RT5645_DMIC_1_EN (0x1 << 15)
  962. #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
  963. #define RT5645_DMIC_2_EN_SFT 14
  964. #define RT5645_DMIC_2_DIS (0x0 << 14)
  965. #define RT5645_DMIC_2_EN (0x1 << 14)
  966. #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
  967. #define RT5645_DMIC_1L_LH_SFT 13
  968. #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
  969. #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
  970. #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
  971. #define RT5645_DMIC_1R_LH_SFT 12
  972. #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
  973. #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
  974. #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
  975. #define RT5645_DMIC_2_DP_SFT 10
  976. #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
  977. #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
  978. #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
  979. #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
  980. #define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
  981. #define RT5645_DMIC_2L_LH_SFT 9
  982. #define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)
  983. #define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
  984. #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
  985. #define RT5645_DMIC_2R_LH_SFT 8
  986. #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
  987. #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
  988. #define RT5645_DMIC_CLK_MASK (0x7 << 5)
  989. #define RT5645_DMIC_CLK_SFT 5
  990. #define RT5645_DMIC_3_EN_MASK (0x1 << 4)
  991. #define RT5645_DMIC_3_EN_SFT 4
  992. #define RT5645_DMIC_3_DIS (0x0 << 4)
  993. #define RT5645_DMIC_3_EN (0x1 << 4)
  994. #define RT5645_DMIC_1_DP_MASK (0x3 << 0)
  995. #define RT5645_DMIC_1_DP_SFT 0
  996. #define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)
  997. #define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
  998. #define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)
  999. /* TDM Control 1 (0x77) */
  1000. #define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
  1001. #define RT5645_IF1_ADC_IN_SFT 8
  1002. /* Global Clock Control (0x80) */
  1003. #define RT5645_SCLK_SRC_MASK (0x3 << 14)
  1004. #define RT5645_SCLK_SRC_SFT 14
  1005. #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
  1006. #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
  1007. #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
  1008. #define RT5645_PLL1_SRC_MASK (0x7 << 11)
  1009. #define RT5645_PLL1_SRC_SFT 11
  1010. #define RT5645_PLL1_SRC_MCLK (0x0 << 11)
  1011. #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
  1012. #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
  1013. #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
  1014. #define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
  1015. #define RT5645_PLL1_PD_MASK (0x1 << 3)
  1016. #define RT5645_PLL1_PD_SFT 3
  1017. #define RT5645_PLL1_PD_1 (0x0 << 3)
  1018. #define RT5645_PLL1_PD_2 (0x1 << 3)
  1019. #define RT5645_PLL_INP_MAX 40000000
  1020. #define RT5645_PLL_INP_MIN 256000
  1021. /* PLL M/N/K Code Control 1 (0x81) */
  1022. #define RT5645_PLL_N_MAX 0x1ff
  1023. #define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)
  1024. #define RT5645_PLL_N_SFT 7
  1025. #define RT5645_PLL_K_MAX 0x1f
  1026. #define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)
  1027. #define RT5645_PLL_K_SFT 0
  1028. /* PLL M/N/K Code Control 2 (0x82) */
  1029. #define RT5645_PLL_M_MAX 0xf
  1030. #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
  1031. #define RT5645_PLL_M_SFT 12
  1032. #define RT5645_PLL_M_BP (0x1 << 11)
  1033. #define RT5645_PLL_M_BP_SFT 11
  1034. /* ASRC Control 1 (0x83) */
  1035. #define RT5645_STO_T_MASK (0x1 << 15)
  1036. #define RT5645_STO_T_SFT 15
  1037. #define RT5645_STO_T_SCLK (0x0 << 15)
  1038. #define RT5645_STO_T_LRCK1 (0x1 << 15)
  1039. #define RT5645_M1_T_MASK (0x1 << 14)
  1040. #define RT5645_M1_T_SFT 14
  1041. #define RT5645_M1_T_I2S2 (0x0 << 14)
  1042. #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
  1043. #define RT5645_I2S2_F_MASK (0x1 << 12)
  1044. #define RT5645_I2S2_F_SFT 12
  1045. #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
  1046. #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
  1047. #define RT5645_DMIC_1_M_MASK (0x1 << 9)
  1048. #define RT5645_DMIC_1_M_SFT 9
  1049. #define RT5645_DMIC_1_M_NOR (0x0 << 9)
  1050. #define RT5645_DMIC_1_M_ASYN (0x1 << 9)
  1051. #define RT5645_DMIC_2_M_MASK (0x1 << 8)
  1052. #define RT5645_DMIC_2_M_SFT 8
  1053. #define RT5645_DMIC_2_M_NOR (0x0 << 8)
  1054. #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
  1055. /* ASRC clock source selection (0x84, 0x85) */
  1056. #define RT5645_CLK_SEL_SYS (0x0)
  1057. #define RT5645_CLK_SEL_I2S1_ASRC (0x1)
  1058. #define RT5645_CLK_SEL_I2S2_ASRC (0x2)
  1059. #define RT5645_CLK_SEL_SYS2 (0x5)
  1060. /* ASRC Control 2 (0x84) */
  1061. #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
  1062. #define RT5645_DA_STO_CLK_SEL_SFT 12
  1063. #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
  1064. #define RT5645_DA_MONOL_CLK_SEL_SFT 8
  1065. #define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4)
  1066. #define RT5645_DA_MONOR_CLK_SEL_SFT 4
  1067. #define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0)
  1068. #define RT5645_AD_STO1_CLK_SEL_SFT 0
  1069. /* ASRC Control 3 (0x85) */
  1070. #define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4)
  1071. #define RT5645_AD_MONOL_CLK_SEL_SFT 4
  1072. #define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0)
  1073. #define RT5645_AD_MONOR_CLK_SEL_SFT 0
  1074. /* ASRC Control 4 (0x89) */
  1075. #define RT5645_I2S1_PD_MASK (0x7 << 12)
  1076. #define RT5645_I2S1_PD_SFT 12
  1077. #define RT5645_I2S2_PD_MASK (0x7 << 8)
  1078. #define RT5645_I2S2_PD_SFT 8
  1079. /* HPOUT Over Current Detection (0x8b) */
  1080. #define RT5645_HP_OVCD_MASK (0x1 << 10)
  1081. #define RT5645_HP_OVCD_SFT 10
  1082. #define RT5645_HP_OVCD_DIS (0x0 << 10)
  1083. #define RT5645_HP_OVCD_EN (0x1 << 10)
  1084. #define RT5645_HP_OC_TH_MASK (0x3 << 8)
  1085. #define RT5645_HP_OC_TH_SFT 8
  1086. #define RT5645_HP_OC_TH_90 (0x0 << 8)
  1087. #define RT5645_HP_OC_TH_105 (0x1 << 8)
  1088. #define RT5645_HP_OC_TH_120 (0x2 << 8)
  1089. #define RT5645_HP_OC_TH_135 (0x3 << 8)
  1090. /* Class D Over Current Control (0x8c) */
  1091. #define RT5645_CLSD_OC_MASK (0x1 << 9)
  1092. #define RT5645_CLSD_OC_SFT 9
  1093. #define RT5645_CLSD_OC_PU (0x0 << 9)
  1094. #define RT5645_CLSD_OC_PD (0x1 << 9)
  1095. #define RT5645_AUTO_PD_MASK (0x1 << 8)
  1096. #define RT5645_AUTO_PD_SFT 8
  1097. #define RT5645_AUTO_PD_DIS (0x0 << 8)
  1098. #define RT5645_AUTO_PD_EN (0x1 << 8)
  1099. #define RT5645_CLSD_OC_TH_MASK (0x3f)
  1100. #define RT5645_CLSD_OC_TH_SFT 0
  1101. /* Class D Output Control (0x8d) */
  1102. #define RT5645_CLSD_RATIO_MASK (0xf << 12)
  1103. #define RT5645_CLSD_RATIO_SFT 12
  1104. #define RT5645_CLSD_OM_MASK (0x1 << 11)
  1105. #define RT5645_CLSD_OM_SFT 11
  1106. #define RT5645_CLSD_OM_MONO (0x0 << 11)
  1107. #define RT5645_CLSD_OM_STO (0x1 << 11)
  1108. #define RT5645_CLSD_SCH_MASK (0x1 << 10)
  1109. #define RT5645_CLSD_SCH_SFT 10
  1110. #define RT5645_CLSD_SCH_L (0x0 << 10)
  1111. #define RT5645_CLSD_SCH_S (0x1 << 10)
  1112. /* Depop Mode Control 1 (0x8e) */
  1113. #define RT5645_SMT_TRIG_MASK (0x1 << 15)
  1114. #define RT5645_SMT_TRIG_SFT 15
  1115. #define RT5645_SMT_TRIG_DIS (0x0 << 15)
  1116. #define RT5645_SMT_TRIG_EN (0x1 << 15)
  1117. #define RT5645_HP_L_SMT_MASK (0x1 << 9)
  1118. #define RT5645_HP_L_SMT_SFT 9
  1119. #define RT5645_HP_L_SMT_DIS (0x0 << 9)
  1120. #define RT5645_HP_L_SMT_EN (0x1 << 9)
  1121. #define RT5645_HP_R_SMT_MASK (0x1 << 8)
  1122. #define RT5645_HP_R_SMT_SFT 8
  1123. #define RT5645_HP_R_SMT_DIS (0x0 << 8)
  1124. #define RT5645_HP_R_SMT_EN (0x1 << 8)
  1125. #define RT5645_HP_CD_PD_MASK (0x1 << 7)
  1126. #define RT5645_HP_CD_PD_SFT 7
  1127. #define RT5645_HP_CD_PD_DIS (0x0 << 7)
  1128. #define RT5645_HP_CD_PD_EN (0x1 << 7)
  1129. #define RT5645_RSTN_MASK (0x1 << 6)
  1130. #define RT5645_RSTN_SFT 6
  1131. #define RT5645_RSTN_DIS (0x0 << 6)
  1132. #define RT5645_RSTN_EN (0x1 << 6)
  1133. #define RT5645_RSTP_MASK (0x1 << 5)
  1134. #define RT5645_RSTP_SFT 5
  1135. #define RT5645_RSTP_DIS (0x0 << 5)
  1136. #define RT5645_RSTP_EN (0x1 << 5)
  1137. #define RT5645_HP_CO_MASK (0x1 << 4)
  1138. #define RT5645_HP_CO_SFT 4
  1139. #define RT5645_HP_CO_DIS (0x0 << 4)
  1140. #define RT5645_HP_CO_EN (0x1 << 4)
  1141. #define RT5645_HP_CP_MASK (0x1 << 3)
  1142. #define RT5645_HP_CP_SFT 3
  1143. #define RT5645_HP_CP_PD (0x0 << 3)
  1144. #define RT5645_HP_CP_PU (0x1 << 3)
  1145. #define RT5645_HP_SG_MASK (0x1 << 2)
  1146. #define RT5645_HP_SG_SFT 2
  1147. #define RT5645_HP_SG_DIS (0x0 << 2)
  1148. #define RT5645_HP_SG_EN (0x1 << 2)
  1149. #define RT5645_HP_DP_MASK (0x1 << 1)
  1150. #define RT5645_HP_DP_SFT 1
  1151. #define RT5645_HP_DP_PD (0x0 << 1)
  1152. #define RT5645_HP_DP_PU (0x1 << 1)
  1153. #define RT5645_HP_CB_MASK (0x1)
  1154. #define RT5645_HP_CB_SFT 0
  1155. #define RT5645_HP_CB_PD (0x0)
  1156. #define RT5645_HP_CB_PU (0x1)
  1157. /* Depop Mode Control 2 (0x8f) */
  1158. #define RT5645_DEPOP_MASK (0x1 << 13)
  1159. #define RT5645_DEPOP_SFT 13
  1160. #define RT5645_DEPOP_AUTO (0x0 << 13)
  1161. #define RT5645_DEPOP_MAN (0x1 << 13)
  1162. #define RT5645_RAMP_MASK (0x1 << 12)
  1163. #define RT5645_RAMP_SFT 12
  1164. #define RT5645_RAMP_DIS (0x0 << 12)
  1165. #define RT5645_RAMP_EN (0x1 << 12)
  1166. #define RT5645_BPS_MASK (0x1 << 11)
  1167. #define RT5645_BPS_SFT 11
  1168. #define RT5645_BPS_DIS (0x0 << 11)
  1169. #define RT5645_BPS_EN (0x1 << 11)
  1170. #define RT5645_FAST_UPDN_MASK (0x1 << 10)
  1171. #define RT5645_FAST_UPDN_SFT 10
  1172. #define RT5645_FAST_UPDN_DIS (0x0 << 10)
  1173. #define RT5645_FAST_UPDN_EN (0x1 << 10)
  1174. #define RT5645_MRES_MASK (0x3 << 8)
  1175. #define RT5645_MRES_SFT 8
  1176. #define RT5645_MRES_15MO (0x0 << 8)
  1177. #define RT5645_MRES_25MO (0x1 << 8)
  1178. #define RT5645_MRES_35MO (0x2 << 8)
  1179. #define RT5645_MRES_45MO (0x3 << 8)
  1180. #define RT5645_VLO_MASK (0x1 << 7)
  1181. #define RT5645_VLO_SFT 7
  1182. #define RT5645_VLO_3V (0x0 << 7)
  1183. #define RT5645_VLO_32V (0x1 << 7)
  1184. #define RT5645_DIG_DP_MASK (0x1 << 6)
  1185. #define RT5645_DIG_DP_SFT 6
  1186. #define RT5645_DIG_DP_DIS (0x0 << 6)
  1187. #define RT5645_DIG_DP_EN (0x1 << 6)
  1188. #define RT5645_DP_TH_MASK (0x3 << 4)
  1189. #define RT5645_DP_TH_SFT 4
  1190. /* Depop Mode Control 3 (0x90) */
  1191. #define RT5645_CP_SYS_MASK (0x7 << 12)
  1192. #define RT5645_CP_SYS_SFT 12
  1193. #define RT5645_CP_FQ1_MASK (0x7 << 8)
  1194. #define RT5645_CP_FQ1_SFT 8
  1195. #define RT5645_CP_FQ2_MASK (0x7 << 4)
  1196. #define RT5645_CP_FQ2_SFT 4
  1197. #define RT5645_CP_FQ3_MASK (0x7)
  1198. #define RT5645_CP_FQ3_SFT 0
  1199. #define RT5645_CP_FQ_1_5_KHZ 0
  1200. #define RT5645_CP_FQ_3_KHZ 1
  1201. #define RT5645_CP_FQ_6_KHZ 2
  1202. #define RT5645_CP_FQ_12_KHZ 3
  1203. #define RT5645_CP_FQ_24_KHZ 4
  1204. #define RT5645_CP_FQ_48_KHZ 5
  1205. #define RT5645_CP_FQ_96_KHZ 6
  1206. #define RT5645_CP_FQ_192_KHZ 7
  1207. /* PV detection and SPK gain control (0x92) */
  1208. #define RT5645_PVDD_DET_MASK (0x1 << 15)
  1209. #define RT5645_PVDD_DET_SFT 15
  1210. #define RT5645_PVDD_DET_DIS (0x0 << 15)
  1211. #define RT5645_PVDD_DET_EN (0x1 << 15)
  1212. #define RT5645_SPK_AG_MASK (0x1 << 14)
  1213. #define RT5645_SPK_AG_SFT 14
  1214. #define RT5645_SPK_AG_DIS (0x0 << 14)
  1215. #define RT5645_SPK_AG_EN (0x1 << 14)
  1216. /* Micbias Control (0x93) */
  1217. #define RT5645_MIC1_BS_MASK (0x1 << 15)
  1218. #define RT5645_MIC1_BS_SFT 15
  1219. #define RT5645_MIC1_BS_9AV (0x0 << 15)
  1220. #define RT5645_MIC1_BS_75AV (0x1 << 15)
  1221. #define RT5645_MIC2_BS_MASK (0x1 << 14)
  1222. #define RT5645_MIC2_BS_SFT 14
  1223. #define RT5645_MIC2_BS_9AV (0x0 << 14)
  1224. #define RT5645_MIC2_BS_75AV (0x1 << 14)
  1225. #define RT5645_MIC1_CLK_MASK (0x1 << 13)
  1226. #define RT5645_MIC1_CLK_SFT 13
  1227. #define RT5645_MIC1_CLK_DIS (0x0 << 13)
  1228. #define RT5645_MIC1_CLK_EN (0x1 << 13)
  1229. #define RT5645_MIC2_CLK_MASK (0x1 << 12)
  1230. #define RT5645_MIC2_CLK_SFT 12
  1231. #define RT5645_MIC2_CLK_DIS (0x0 << 12)
  1232. #define RT5645_MIC2_CLK_EN (0x1 << 12)
  1233. #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
  1234. #define RT5645_MIC1_OVCD_SFT 11
  1235. #define RT5645_MIC1_OVCD_DIS (0x0 << 11)
  1236. #define RT5645_MIC1_OVCD_EN (0x1 << 11)
  1237. #define RT5645_MIC1_OVTH_MASK (0x3 << 9)
  1238. #define RT5645_MIC1_OVTH_SFT 9
  1239. #define RT5645_MIC1_OVTH_600UA (0x0 << 9)
  1240. #define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
  1241. #define RT5645_MIC1_OVTH_2000UA (0x2 << 9)
  1242. #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
  1243. #define RT5645_MIC2_OVCD_SFT 8
  1244. #define RT5645_MIC2_OVCD_DIS (0x0 << 8)
  1245. #define RT5645_MIC2_OVCD_EN (0x1 << 8)
  1246. #define RT5645_MIC2_OVTH_MASK (0x3 << 6)
  1247. #define RT5645_MIC2_OVTH_SFT 6
  1248. #define RT5645_MIC2_OVTH_600UA (0x0 << 6)
  1249. #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
  1250. #define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
  1251. #define RT5645_PWR_MB_MASK (0x1 << 5)
  1252. #define RT5645_PWR_MB_SFT 5
  1253. #define RT5645_PWR_MB_PD (0x0 << 5)
  1254. #define RT5645_PWR_MB_PU (0x1 << 5)
  1255. #define RT5645_PWR_CLK25M_MASK (0x1 << 4)
  1256. #define RT5645_PWR_CLK25M_SFT 4
  1257. #define RT5645_PWR_CLK25M_PD (0x0 << 4)
  1258. #define RT5645_PWR_CLK25M_PU (0x1 << 4)
  1259. #define RT5645_IRQ_CLK_MCLK (0x0 << 3)
  1260. #define RT5645_IRQ_CLK_INT (0x1 << 3)
  1261. #define RT5645_JD1_MODE_MASK (0x3 << 0)
  1262. #define RT5645_JD1_MODE_0 (0x0 << 0)
  1263. #define RT5645_JD1_MODE_1 (0x1 << 0)
  1264. #define RT5645_JD1_MODE_2 (0x2 << 0)
  1265. /* VAD Control 4 (0x9d) */
  1266. #define RT5645_VAD_SEL_MASK (0x3 << 8)
  1267. #define RT5645_VAD_SEL_SFT 8
  1268. /* EQ Control 1 (0xb0) */
  1269. #define RT5645_EQ_SRC_MASK (0x1 << 15)
  1270. #define RT5645_EQ_SRC_SFT 15
  1271. #define RT5645_EQ_SRC_DAC (0x0 << 15)
  1272. #define RT5645_EQ_SRC_ADC (0x1 << 15)
  1273. #define RT5645_EQ_UPD (0x1 << 14)
  1274. #define RT5645_EQ_UPD_BIT 14
  1275. #define RT5645_EQ_CD_MASK (0x1 << 13)
  1276. #define RT5645_EQ_CD_SFT 13
  1277. #define RT5645_EQ_CD_DIS (0x0 << 13)
  1278. #define RT5645_EQ_CD_EN (0x1 << 13)
  1279. #define RT5645_EQ_DITH_MASK (0x3 << 8)
  1280. #define RT5645_EQ_DITH_SFT 8
  1281. #define RT5645_EQ_DITH_NOR (0x0 << 8)
  1282. #define RT5645_EQ_DITH_LSB (0x1 << 8)
  1283. #define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
  1284. #define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
  1285. /* EQ Control 2 (0xb1) */
  1286. #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
  1287. #define RT5645_EQ_HPF1_M_SFT 8
  1288. #define RT5645_EQ_HPF1_M_HI (0x0 << 8)
  1289. #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
  1290. #define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
  1291. #define RT5645_EQ_LPF1_M_SFT 7
  1292. #define RT5645_EQ_LPF1_M_LO (0x0 << 7)
  1293. #define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
  1294. #define RT5645_EQ_HPF2_MASK (0x1 << 6)
  1295. #define RT5645_EQ_HPF2_SFT 6
  1296. #define RT5645_EQ_HPF2_DIS (0x0 << 6)
  1297. #define RT5645_EQ_HPF2_EN (0x1 << 6)
  1298. #define RT5645_EQ_HPF1_MASK (0x1 << 5)
  1299. #define RT5645_EQ_HPF1_SFT 5
  1300. #define RT5645_EQ_HPF1_DIS (0x0 << 5)
  1301. #define RT5645_EQ_HPF1_EN (0x1 << 5)
  1302. #define RT5645_EQ_BPF4_MASK (0x1 << 4)
  1303. #define RT5645_EQ_BPF4_SFT 4
  1304. #define RT5645_EQ_BPF4_DIS (0x0 << 4)
  1305. #define RT5645_EQ_BPF4_EN (0x1 << 4)
  1306. #define RT5645_EQ_BPF3_MASK (0x1 << 3)
  1307. #define RT5645_EQ_BPF3_SFT 3
  1308. #define RT5645_EQ_BPF3_DIS (0x0 << 3)
  1309. #define RT5645_EQ_BPF3_EN (0x1 << 3)
  1310. #define RT5645_EQ_BPF2_MASK (0x1 << 2)
  1311. #define RT5645_EQ_BPF2_SFT 2
  1312. #define RT5645_EQ_BPF2_DIS (0x0 << 2)
  1313. #define RT5645_EQ_BPF2_EN (0x1 << 2)
  1314. #define RT5645_EQ_BPF1_MASK (0x1 << 1)
  1315. #define RT5645_EQ_BPF1_SFT 1
  1316. #define RT5645_EQ_BPF1_DIS (0x0 << 1)
  1317. #define RT5645_EQ_BPF1_EN (0x1 << 1)
  1318. #define RT5645_EQ_LPF_MASK (0x1)
  1319. #define RT5645_EQ_LPF_SFT 0
  1320. #define RT5645_EQ_LPF_DIS (0x0)
  1321. #define RT5645_EQ_LPF_EN (0x1)
  1322. #define RT5645_EQ_CTRL_MASK (0x7f)
  1323. /* Memory Test (0xb2) */
  1324. #define RT5645_MT_MASK (0x1 << 15)
  1325. #define RT5645_MT_SFT 15
  1326. #define RT5645_MT_DIS (0x0 << 15)
  1327. #define RT5645_MT_EN (0x1 << 15)
  1328. /* DRC/AGC Control 1 (0xb4) */
  1329. #define RT5645_DRC_AGC_P_MASK (0x1 << 15)
  1330. #define RT5645_DRC_AGC_P_SFT 15
  1331. #define RT5645_DRC_AGC_P_DAC (0x0 << 15)
  1332. #define RT5645_DRC_AGC_P_ADC (0x1 << 15)
  1333. #define RT5645_DRC_AGC_MASK (0x1 << 14)
  1334. #define RT5645_DRC_AGC_SFT 14
  1335. #define RT5645_DRC_AGC_DIS (0x0 << 14)
  1336. #define RT5645_DRC_AGC_EN (0x1 << 14)
  1337. #define RT5645_DRC_AGC_UPD (0x1 << 13)
  1338. #define RT5645_DRC_AGC_UPD_BIT 13
  1339. #define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
  1340. #define RT5645_DRC_AGC_AR_SFT 8
  1341. #define RT5645_DRC_AGC_R_MASK (0x7 << 5)
  1342. #define RT5645_DRC_AGC_R_SFT 5
  1343. #define RT5645_DRC_AGC_R_48K (0x1 << 5)
  1344. #define RT5645_DRC_AGC_R_96K (0x2 << 5)
  1345. #define RT5645_DRC_AGC_R_192K (0x3 << 5)
  1346. #define RT5645_DRC_AGC_R_441K (0x5 << 5)
  1347. #define RT5645_DRC_AGC_R_882K (0x6 << 5)
  1348. #define RT5645_DRC_AGC_R_1764K (0x7 << 5)
  1349. #define RT5645_DRC_AGC_RC_MASK (0x1f)
  1350. #define RT5645_DRC_AGC_RC_SFT 0
  1351. /* DRC/AGC Control 2 (0xb5) */
  1352. #define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
  1353. #define RT5645_DRC_AGC_POB_SFT 8
  1354. #define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
  1355. #define RT5645_DRC_AGC_CP_SFT 7
  1356. #define RT5645_DRC_AGC_CP_DIS (0x0 << 7)
  1357. #define RT5645_DRC_AGC_CP_EN (0x1 << 7)
  1358. #define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)
  1359. #define RT5645_DRC_AGC_CPR_SFT 5
  1360. #define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)
  1361. #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
  1362. #define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)
  1363. #define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)
  1364. #define RT5645_DRC_AGC_PRB_MASK (0x1f)
  1365. #define RT5645_DRC_AGC_PRB_SFT 0
  1366. /* DRC/AGC Control 3 (0xb6) */
  1367. #define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
  1368. #define RT5645_DRC_AGC_NGB_SFT 12
  1369. #define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)
  1370. #define RT5645_DRC_AGC_TAR_SFT 7
  1371. #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
  1372. #define RT5645_DRC_AGC_NG_SFT 6
  1373. #define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
  1374. #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
  1375. #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
  1376. #define RT5645_DRC_AGC_NGH_SFT 5
  1377. #define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)
  1378. #define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
  1379. #define RT5645_DRC_AGC_NGT_MASK (0x1f)
  1380. #define RT5645_DRC_AGC_NGT_SFT 0
  1381. /* ANC Control 1 (0xb8) */
  1382. #define RT5645_ANC_M_MASK (0x1 << 15)
  1383. #define RT5645_ANC_M_SFT 15
  1384. #define RT5645_ANC_M_NOR (0x0 << 15)
  1385. #define RT5645_ANC_M_REV (0x1 << 15)
  1386. #define RT5645_ANC_MASK (0x1 << 14)
  1387. #define RT5645_ANC_SFT 14
  1388. #define RT5645_ANC_DIS (0x0 << 14)
  1389. #define RT5645_ANC_EN (0x1 << 14)
  1390. #define RT5645_ANC_MD_MASK (0x3 << 12)
  1391. #define RT5645_ANC_MD_SFT 12
  1392. #define RT5645_ANC_MD_DIS (0x0 << 12)
  1393. #define RT5645_ANC_MD_67MS (0x1 << 12)
  1394. #define RT5645_ANC_MD_267MS (0x2 << 12)
  1395. #define RT5645_ANC_MD_1067MS (0x3 << 12)
  1396. #define RT5645_ANC_SN_MASK (0x1 << 11)
  1397. #define RT5645_ANC_SN_SFT 11
  1398. #define RT5645_ANC_SN_DIS (0x0 << 11)
  1399. #define RT5645_ANC_SN_EN (0x1 << 11)
  1400. #define RT5645_ANC_CLK_MASK (0x1 << 10)
  1401. #define RT5645_ANC_CLK_SFT 10
  1402. #define RT5645_ANC_CLK_ANC (0x0 << 10)
  1403. #define RT5645_ANC_CLK_REG (0x1 << 10)
  1404. #define RT5645_ANC_ZCD_MASK (0x3 << 8)
  1405. #define RT5645_ANC_ZCD_SFT 8
  1406. #define RT5645_ANC_ZCD_DIS (0x0 << 8)
  1407. #define RT5645_ANC_ZCD_T1 (0x1 << 8)
  1408. #define RT5645_ANC_ZCD_T2 (0x2 << 8)
  1409. #define RT5645_ANC_ZCD_WT (0x3 << 8)
  1410. #define RT5645_ANC_CS_MASK (0x1 << 7)
  1411. #define RT5645_ANC_CS_SFT 7
  1412. #define RT5645_ANC_CS_DIS (0x0 << 7)
  1413. #define RT5645_ANC_CS_EN (0x1 << 7)
  1414. #define RT5645_ANC_SW_MASK (0x1 << 6)
  1415. #define RT5645_ANC_SW_SFT 6
  1416. #define RT5645_ANC_SW_NOR (0x0 << 6)
  1417. #define RT5645_ANC_SW_AUTO (0x1 << 6)
  1418. #define RT5645_ANC_CO_L_MASK (0x3f)
  1419. #define RT5645_ANC_CO_L_SFT 0
  1420. /* ANC Control 2 (0xb6) */
  1421. #define RT5645_ANC_FG_R_MASK (0xf << 12)
  1422. #define RT5645_ANC_FG_R_SFT 12
  1423. #define RT5645_ANC_FG_L_MASK (0xf << 8)
  1424. #define RT5645_ANC_FG_L_SFT 8
  1425. #define RT5645_ANC_CG_R_MASK (0xf << 4)
  1426. #define RT5645_ANC_CG_R_SFT 4
  1427. #define RT5645_ANC_CG_L_MASK (0xf)
  1428. #define RT5645_ANC_CG_L_SFT 0
  1429. /* ANC Control 3 (0xb6) */
  1430. #define RT5645_ANC_CD_MASK (0x1 << 6)
  1431. #define RT5645_ANC_CD_SFT 6
  1432. #define RT5645_ANC_CD_BOTH (0x0 << 6)
  1433. #define RT5645_ANC_CD_IND (0x1 << 6)
  1434. #define RT5645_ANC_CO_R_MASK (0x3f)
  1435. #define RT5645_ANC_CO_R_SFT 0
  1436. /* Jack Detect Control (0xbb) */
  1437. #define RT5645_JD_MASK (0x7 << 13)
  1438. #define RT5645_JD_SFT 13
  1439. #define RT5645_JD_DIS (0x0 << 13)
  1440. #define RT5645_JD_GPIO1 (0x1 << 13)
  1441. #define RT5645_JD_JD1_IN4P (0x2 << 13)
  1442. #define RT5645_JD_JD2_IN4N (0x3 << 13)
  1443. #define RT5645_JD_GPIO2 (0x4 << 13)
  1444. #define RT5645_JD_GPIO3 (0x5 << 13)
  1445. #define RT5645_JD_GPIO4 (0x6 << 13)
  1446. #define RT5645_JD_HP_MASK (0x1 << 11)
  1447. #define RT5645_JD_HP_SFT 11
  1448. #define RT5645_JD_HP_DIS (0x0 << 11)
  1449. #define RT5645_JD_HP_EN (0x1 << 11)
  1450. #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
  1451. #define RT5645_JD_HP_TRG_SFT 10
  1452. #define RT5645_JD_HP_TRG_LO (0x0 << 10)
  1453. #define RT5645_JD_HP_TRG_HI (0x1 << 10)
  1454. #define RT5645_JD_SPL_MASK (0x1 << 9)
  1455. #define RT5645_JD_SPL_SFT 9
  1456. #define RT5645_JD_SPL_DIS (0x0 << 9)
  1457. #define RT5645_JD_SPL_EN (0x1 << 9)
  1458. #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
  1459. #define RT5645_JD_SPL_TRG_SFT 8
  1460. #define RT5645_JD_SPL_TRG_LO (0x0 << 8)
  1461. #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
  1462. #define RT5645_JD_SPR_MASK (0x1 << 7)
  1463. #define RT5645_JD_SPR_SFT 7
  1464. #define RT5645_JD_SPR_DIS (0x0 << 7)
  1465. #define RT5645_JD_SPR_EN (0x1 << 7)
  1466. #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
  1467. #define RT5645_JD_SPR_TRG_SFT 6
  1468. #define RT5645_JD_SPR_TRG_LO (0x0 << 6)
  1469. #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
  1470. #define RT5645_JD_MO_MASK (0x1 << 5)
  1471. #define RT5645_JD_MO_SFT 5
  1472. #define RT5645_JD_MO_DIS (0x0 << 5)
  1473. #define RT5645_JD_MO_EN (0x1 << 5)
  1474. #define RT5645_JD_MO_TRG_MASK (0x1 << 4)
  1475. #define RT5645_JD_MO_TRG_SFT 4
  1476. #define RT5645_JD_MO_TRG_LO (0x0 << 4)
  1477. #define RT5645_JD_MO_TRG_HI (0x1 << 4)
  1478. #define RT5645_JD_LO_MASK (0x1 << 3)
  1479. #define RT5645_JD_LO_SFT 3
  1480. #define RT5645_JD_LO_DIS (0x0 << 3)
  1481. #define RT5645_JD_LO_EN (0x1 << 3)
  1482. #define RT5645_JD_LO_TRG_MASK (0x1 << 2)
  1483. #define RT5645_JD_LO_TRG_SFT 2
  1484. #define RT5645_JD_LO_TRG_LO (0x0 << 2)
  1485. #define RT5645_JD_LO_TRG_HI (0x1 << 2)
  1486. #define RT5645_JD1_IN4P_MASK (0x1 << 1)
  1487. #define RT5645_JD1_IN4P_SFT 1
  1488. #define RT5645_JD1_IN4P_DIS (0x0 << 1)
  1489. #define RT5645_JD1_IN4P_EN (0x1 << 1)
  1490. #define RT5645_JD2_IN4N_MASK (0x1)
  1491. #define RT5645_JD2_IN4N_SFT 0
  1492. #define RT5645_JD2_IN4N_DIS (0x0)
  1493. #define RT5645_JD2_IN4N_EN (0x1)
  1494. /* Jack detect for ANC (0xbc) */
  1495. #define RT5645_ANC_DET_MASK (0x3 << 4)
  1496. #define RT5645_ANC_DET_SFT 4
  1497. #define RT5645_ANC_DET_DIS (0x0 << 4)
  1498. #define RT5645_ANC_DET_MB1 (0x1 << 4)
  1499. #define RT5645_ANC_DET_MB2 (0x2 << 4)
  1500. #define RT5645_ANC_DET_JD (0x3 << 4)
  1501. #define RT5645_AD_TRG_MASK (0x1 << 3)
  1502. #define RT5645_AD_TRG_SFT 3
  1503. #define RT5645_AD_TRG_LO (0x0 << 3)
  1504. #define RT5645_AD_TRG_HI (0x1 << 3)
  1505. #define RT5645_ANCM_DET_MASK (0x3 << 4)
  1506. #define RT5645_ANCM_DET_SFT 4
  1507. #define RT5645_ANCM_DET_DIS (0x0 << 4)
  1508. #define RT5645_ANCM_DET_MB1 (0x1 << 4)
  1509. #define RT5645_ANCM_DET_MB2 (0x2 << 4)
  1510. #define RT5645_ANCM_DET_JD (0x3 << 4)
  1511. #define RT5645_AMD_TRG_MASK (0x1 << 3)
  1512. #define RT5645_AMD_TRG_SFT 3
  1513. #define RT5645_AMD_TRG_LO (0x0 << 3)
  1514. #define RT5645_AMD_TRG_HI (0x1 << 3)
  1515. /* IRQ Control 1 (0xbd) */
  1516. #define RT5645_IRQ_JD_MASK (0x1 << 15)
  1517. #define RT5645_IRQ_JD_SFT 15
  1518. #define RT5645_IRQ_JD_BP (0x0 << 15)
  1519. #define RT5645_IRQ_JD_NOR (0x1 << 15)
  1520. #define RT5645_IRQ_OT_MASK (0x1 << 14)
  1521. #define RT5645_IRQ_OT_SFT 14
  1522. #define RT5645_IRQ_OT_BP (0x0 << 14)
  1523. #define RT5645_IRQ_OT_NOR (0x1 << 14)
  1524. #define RT5645_JD_STKY_MASK (0x1 << 13)
  1525. #define RT5645_JD_STKY_SFT 13
  1526. #define RT5645_JD_STKY_DIS (0x0 << 13)
  1527. #define RT5645_JD_STKY_EN (0x1 << 13)
  1528. #define RT5645_OT_STKY_MASK (0x1 << 12)
  1529. #define RT5645_OT_STKY_SFT 12
  1530. #define RT5645_OT_STKY_DIS (0x0 << 12)
  1531. #define RT5645_OT_STKY_EN (0x1 << 12)
  1532. #define RT5645_JD_P_MASK (0x1 << 11)
  1533. #define RT5645_JD_P_SFT 11
  1534. #define RT5645_JD_P_NOR (0x0 << 11)
  1535. #define RT5645_JD_P_INV (0x1 << 11)
  1536. #define RT5645_OT_P_MASK (0x1 << 10)
  1537. #define RT5645_OT_P_SFT 10
  1538. #define RT5645_OT_P_NOR (0x0 << 10)
  1539. #define RT5645_OT_P_INV (0x1 << 10)
  1540. #define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
  1541. #define RT5645_JD_1_1_MASK (0x1 << 7)
  1542. #define RT5645_JD_1_1_SFT 7
  1543. #define RT5645_JD_1_1_NOR (0x0 << 7)
  1544. #define RT5645_JD_1_1_INV (0x1 << 7)
  1545. /* IRQ Control 2 (0xbe) */
  1546. #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
  1547. #define RT5645_IRQ_MB1_OC_SFT 15
  1548. #define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
  1549. #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
  1550. #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
  1551. #define RT5645_IRQ_MB2_OC_SFT 14
  1552. #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
  1553. #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
  1554. #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
  1555. #define RT5645_MB1_OC_STKY_SFT 13
  1556. #define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
  1557. #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
  1558. #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
  1559. #define RT5645_MB2_OC_STKY_SFT 12
  1560. #define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
  1561. #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
  1562. #define RT5645_MB1_OC_P_MASK (0x1 << 7)
  1563. #define RT5645_MB1_OC_P_SFT 7
  1564. #define RT5645_MB1_OC_P_NOR (0x0 << 7)
  1565. #define RT5645_MB1_OC_P_INV (0x1 << 7)
  1566. #define RT5645_MB2_OC_P_MASK (0x1 << 6)
  1567. #define RT5645_MB2_OC_P_SFT 6
  1568. #define RT5645_MB2_OC_P_NOR (0x0 << 6)
  1569. #define RT5645_MB2_OC_P_INV (0x1 << 6)
  1570. #define RT5645_MB1_OC_CLR (0x1 << 3)
  1571. #define RT5645_MB1_OC_CLR_SFT 3
  1572. #define RT5645_MB2_OC_CLR (0x1 << 2)
  1573. #define RT5645_MB2_OC_CLR_SFT 2
  1574. /* GPIO Control 1 (0xc0) */
  1575. #define RT5645_GP1_PIN_MASK (0x1 << 15)
  1576. #define RT5645_GP1_PIN_SFT 15
  1577. #define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
  1578. #define RT5645_GP1_PIN_IRQ (0x1 << 15)
  1579. #define RT5645_GP2_PIN_MASK (0x1 << 14)
  1580. #define RT5645_GP2_PIN_SFT 14
  1581. #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
  1582. #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
  1583. #define RT5645_GP3_PIN_MASK (0x3 << 12)
  1584. #define RT5645_GP3_PIN_SFT 12
  1585. #define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
  1586. #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
  1587. #define RT5645_GP3_PIN_IRQ (0x2 << 12)
  1588. #define RT5645_GP4_PIN_MASK (0x1 << 11)
  1589. #define RT5645_GP4_PIN_SFT 11
  1590. #define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
  1591. #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
  1592. #define RT5645_DP_SIG_MASK (0x1 << 10)
  1593. #define RT5645_DP_SIG_SFT 10
  1594. #define RT5645_DP_SIG_TEST (0x0 << 10)
  1595. #define RT5645_DP_SIG_AP (0x1 << 10)
  1596. #define RT5645_GPIO_M_MASK (0x1 << 9)
  1597. #define RT5645_GPIO_M_SFT 9
  1598. #define RT5645_GPIO_M_FLT (0x0 << 9)
  1599. #define RT5645_GPIO_M_PH (0x1 << 9)
  1600. #define RT5645_I2S2_SEL (0x1 << 8)
  1601. #define RT5645_I2S2_SEL_SFT 8
  1602. #define RT5645_GP5_PIN_MASK (0x1 << 7)
  1603. #define RT5645_GP5_PIN_SFT 7
  1604. #define RT5645_GP5_PIN_GPIO5 (0x0 << 7)
  1605. #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
  1606. #define RT5645_GP6_PIN_MASK (0x1 << 6)
  1607. #define RT5645_GP6_PIN_SFT 6
  1608. #define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
  1609. #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
  1610. #define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4)
  1611. #define RT5645_I2S2_DAC_PIN_SFT 4
  1612. #define RT5645_I2S2_DAC_PIN_I2S (0x0 << 4)
  1613. #define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4)
  1614. #define RT5645_GP8_PIN_MASK (0x1 << 3)
  1615. #define RT5645_GP8_PIN_SFT 3
  1616. #define RT5645_GP8_PIN_GPIO8 (0x0 << 3)
  1617. #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
  1618. #define RT5645_GP12_PIN_MASK (0x1 << 2)
  1619. #define RT5645_GP12_PIN_SFT 2
  1620. #define RT5645_GP12_PIN_GPIO12 (0x0 << 2)
  1621. #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
  1622. #define RT5645_GP11_PIN_MASK (0x1 << 1)
  1623. #define RT5645_GP11_PIN_SFT 1
  1624. #define RT5645_GP11_PIN_GPIO11 (0x0 << 1)
  1625. #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
  1626. #define RT5645_GP10_PIN_MASK (0x1)
  1627. #define RT5645_GP10_PIN_SFT 0
  1628. #define RT5645_GP10_PIN_GPIO10 (0x0)
  1629. #define RT5645_GP10_PIN_DMIC2_SDA (0x1)
  1630. /* GPIO Control 3 (0xc2) */
  1631. #define RT5645_GP4_PF_MASK (0x1 << 11)
  1632. #define RT5645_GP4_PF_SFT 11
  1633. #define RT5645_GP4_PF_IN (0x0 << 11)
  1634. #define RT5645_GP4_PF_OUT (0x1 << 11)
  1635. #define RT5645_GP4_OUT_MASK (0x1 << 10)
  1636. #define RT5645_GP4_OUT_SFT 10
  1637. #define RT5645_GP4_OUT_LO (0x0 << 10)
  1638. #define RT5645_GP4_OUT_HI (0x1 << 10)
  1639. #define RT5645_GP4_P_MASK (0x1 << 9)
  1640. #define RT5645_GP4_P_SFT 9
  1641. #define RT5645_GP4_P_NOR (0x0 << 9)
  1642. #define RT5645_GP4_P_INV (0x1 << 9)
  1643. #define RT5645_GP3_PF_MASK (0x1 << 8)
  1644. #define RT5645_GP3_PF_SFT 8
  1645. #define RT5645_GP3_PF_IN (0x0 << 8)
  1646. #define RT5645_GP3_PF_OUT (0x1 << 8)
  1647. #define RT5645_GP3_OUT_MASK (0x1 << 7)
  1648. #define RT5645_GP3_OUT_SFT 7
  1649. #define RT5645_GP3_OUT_LO (0x0 << 7)
  1650. #define RT5645_GP3_OUT_HI (0x1 << 7)
  1651. #define RT5645_GP3_P_MASK (0x1 << 6)
  1652. #define RT5645_GP3_P_SFT 6
  1653. #define RT5645_GP3_P_NOR (0x0 << 6)
  1654. #define RT5645_GP3_P_INV (0x1 << 6)
  1655. #define RT5645_GP2_PF_MASK (0x1 << 5)
  1656. #define RT5645_GP2_PF_SFT 5
  1657. #define RT5645_GP2_PF_IN (0x0 << 5)
  1658. #define RT5645_GP2_PF_OUT (0x1 << 5)
  1659. #define RT5645_GP2_OUT_MASK (0x1 << 4)
  1660. #define RT5645_GP2_OUT_SFT 4
  1661. #define RT5645_GP2_OUT_LO (0x0 << 4)
  1662. #define RT5645_GP2_OUT_HI (0x1 << 4)
  1663. #define RT5645_GP2_P_MASK (0x1 << 3)
  1664. #define RT5645_GP2_P_SFT 3
  1665. #define RT5645_GP2_P_NOR (0x0 << 3)
  1666. #define RT5645_GP2_P_INV (0x1 << 3)
  1667. #define RT5645_GP1_PF_MASK (0x1 << 2)
  1668. #define RT5645_GP1_PF_SFT 2
  1669. #define RT5645_GP1_PF_IN (0x0 << 2)
  1670. #define RT5645_GP1_PF_OUT (0x1 << 2)
  1671. #define RT5645_GP1_OUT_MASK (0x1 << 1)
  1672. #define RT5645_GP1_OUT_SFT 1
  1673. #define RT5645_GP1_OUT_LO (0x0 << 1)
  1674. #define RT5645_GP1_OUT_HI (0x1 << 1)
  1675. #define RT5645_GP1_P_MASK (0x1)
  1676. #define RT5645_GP1_P_SFT 0
  1677. #define RT5645_GP1_P_NOR (0x0)
  1678. #define RT5645_GP1_P_INV (0x1)
  1679. /* Programmable Register Array Control 1 (0xc8) */
  1680. #define RT5645_REG_SEQ_MASK (0xf << 12)
  1681. #define RT5645_REG_SEQ_SFT 12
  1682. #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
  1683. #define RT5645_SEQ1_ST_SFT 11
  1684. #define RT5645_SEQ1_ST_RUN (0x0 << 11)
  1685. #define RT5645_SEQ1_ST_FIN (0x1 << 11)
  1686. #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
  1687. #define RT5645_SEQ2_ST_SFT 10
  1688. #define RT5645_SEQ2_ST_RUN (0x0 << 10)
  1689. #define RT5645_SEQ2_ST_FIN (0x1 << 10)
  1690. #define RT5645_REG_LV_MASK (0x1 << 9)
  1691. #define RT5645_REG_LV_SFT 9
  1692. #define RT5645_REG_LV_MX (0x0 << 9)
  1693. #define RT5645_REG_LV_PR (0x1 << 9)
  1694. #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
  1695. #define RT5645_SEQ_2_PT_BIT 8
  1696. #define RT5645_REG_IDX_MASK (0xff)
  1697. #define RT5645_REG_IDX_SFT 0
  1698. /* Programmable Register Array Control 2 (0xc9) */
  1699. #define RT5645_REG_DAT_MASK (0xffff)
  1700. #define RT5645_REG_DAT_SFT 0
  1701. /* Programmable Register Array Control 3 (0xca) */
  1702. #define RT5645_SEQ_DLY_MASK (0xff << 8)
  1703. #define RT5645_SEQ_DLY_SFT 8
  1704. #define RT5645_PROG_MASK (0x1 << 7)
  1705. #define RT5645_PROG_SFT 7
  1706. #define RT5645_PROG_DIS (0x0 << 7)
  1707. #define RT5645_PROG_EN (0x1 << 7)
  1708. #define RT5645_SEQ1_PT_RUN (0x1 << 6)
  1709. #define RT5645_SEQ1_PT_RUN_BIT 6
  1710. #define RT5645_SEQ2_PT_RUN (0x1 << 5)
  1711. #define RT5645_SEQ2_PT_RUN_BIT 5
  1712. /* Programmable Register Array Control 4 (0xcb) */
  1713. #define RT5645_SEQ1_START_MASK (0xf << 8)
  1714. #define RT5645_SEQ1_START_SFT 8
  1715. #define RT5645_SEQ1_END_MASK (0xf)
  1716. #define RT5645_SEQ1_END_SFT 0
  1717. /* Programmable Register Array Control 5 (0xcc) */
  1718. #define RT5645_SEQ2_START_MASK (0xf << 8)
  1719. #define RT5645_SEQ2_START_SFT 8
  1720. #define RT5645_SEQ2_END_MASK (0xf)
  1721. #define RT5645_SEQ2_END_SFT 0
  1722. /* Scramble Function (0xcd) */
  1723. #define RT5645_SCB_KEY_MASK (0xff)
  1724. #define RT5645_SCB_KEY_SFT 0
  1725. /* Scramble Control (0xce) */
  1726. #define RT5645_SCB_SWAP_MASK (0x1 << 15)
  1727. #define RT5645_SCB_SWAP_SFT 15
  1728. #define RT5645_SCB_SWAP_DIS (0x0 << 15)
  1729. #define RT5645_SCB_SWAP_EN (0x1 << 15)
  1730. #define RT5645_SCB_MASK (0x1 << 14)
  1731. #define RT5645_SCB_SFT 14
  1732. #define RT5645_SCB_DIS (0x0 << 14)
  1733. #define RT5645_SCB_EN (0x1 << 14)
  1734. /* Baseback Control (0xcf) */
  1735. #define RT5645_BB_MASK (0x1 << 15)
  1736. #define RT5645_BB_SFT 15
  1737. #define RT5645_BB_DIS (0x0 << 15)
  1738. #define RT5645_BB_EN (0x1 << 15)
  1739. #define RT5645_BB_CT_MASK (0x7 << 12)
  1740. #define RT5645_BB_CT_SFT 12
  1741. #define RT5645_BB_CT_A (0x0 << 12)
  1742. #define RT5645_BB_CT_B (0x1 << 12)
  1743. #define RT5645_BB_CT_C (0x2 << 12)
  1744. #define RT5645_BB_CT_D (0x3 << 12)
  1745. #define RT5645_M_BB_L_MASK (0x1 << 9)
  1746. #define RT5645_M_BB_L_SFT 9
  1747. #define RT5645_M_BB_R_MASK (0x1 << 8)
  1748. #define RT5645_M_BB_R_SFT 8
  1749. #define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
  1750. #define RT5645_M_BB_HPF_L_SFT 7
  1751. #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
  1752. #define RT5645_M_BB_HPF_R_SFT 6
  1753. #define RT5645_G_BB_BST_MASK (0x3f)
  1754. #define RT5645_G_BB_BST_SFT 0
  1755. #define RT5645_G_BB_BST_25DB 0x14
  1756. /* MP3 Plus Control 1 (0xd0) */
  1757. #define RT5645_M_MP3_L_MASK (0x1 << 15)
  1758. #define RT5645_M_MP3_L_SFT 15
  1759. #define RT5645_M_MP3_R_MASK (0x1 << 14)
  1760. #define RT5645_M_MP3_R_SFT 14
  1761. #define RT5645_M_MP3_MASK (0x1 << 13)
  1762. #define RT5645_M_MP3_SFT 13
  1763. #define RT5645_M_MP3_DIS (0x0 << 13)
  1764. #define RT5645_M_MP3_EN (0x1 << 13)
  1765. #define RT5645_EG_MP3_MASK (0x1f << 8)
  1766. #define RT5645_EG_MP3_SFT 8
  1767. #define RT5645_MP3_HLP_MASK (0x1 << 7)
  1768. #define RT5645_MP3_HLP_SFT 7
  1769. #define RT5645_MP3_HLP_DIS (0x0 << 7)
  1770. #define RT5645_MP3_HLP_EN (0x1 << 7)
  1771. #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
  1772. #define RT5645_M_MP3_ORG_L_SFT 6
  1773. #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
  1774. #define RT5645_M_MP3_ORG_R_SFT 5
  1775. /* MP3 Plus Control 2 (0xd1) */
  1776. #define RT5645_MP3_WT_MASK (0x1 << 13)
  1777. #define RT5645_MP3_WT_SFT 13
  1778. #define RT5645_MP3_WT_1_4 (0x0 << 13)
  1779. #define RT5645_MP3_WT_1_2 (0x1 << 13)
  1780. #define RT5645_OG_MP3_MASK (0x1f << 8)
  1781. #define RT5645_OG_MP3_SFT 8
  1782. #define RT5645_HG_MP3_MASK (0x3f)
  1783. #define RT5645_HG_MP3_SFT 0
  1784. /* 3D HP Control 1 (0xd2) */
  1785. #define RT5645_3D_CF_MASK (0x1 << 15)
  1786. #define RT5645_3D_CF_SFT 15
  1787. #define RT5645_3D_CF_DIS (0x0 << 15)
  1788. #define RT5645_3D_CF_EN (0x1 << 15)
  1789. #define RT5645_3D_HP_MASK (0x1 << 14)
  1790. #define RT5645_3D_HP_SFT 14
  1791. #define RT5645_3D_HP_DIS (0x0 << 14)
  1792. #define RT5645_3D_HP_EN (0x1 << 14)
  1793. #define RT5645_3D_BT_MASK (0x1 << 13)
  1794. #define RT5645_3D_BT_SFT 13
  1795. #define RT5645_3D_BT_DIS (0x0 << 13)
  1796. #define RT5645_3D_BT_EN (0x1 << 13)
  1797. #define RT5645_3D_1F_MIX_MASK (0x3 << 11)
  1798. #define RT5645_3D_1F_MIX_SFT 11
  1799. #define RT5645_3D_HP_M_MASK (0x1 << 10)
  1800. #define RT5645_3D_HP_M_SFT 10
  1801. #define RT5645_3D_HP_M_SUR (0x0 << 10)
  1802. #define RT5645_3D_HP_M_FRO (0x1 << 10)
  1803. #define RT5645_M_3D_HRTF_MASK (0x1 << 9)
  1804. #define RT5645_M_3D_HRTF_SFT 9
  1805. #define RT5645_M_3D_D2H_MASK (0x1 << 8)
  1806. #define RT5645_M_3D_D2H_SFT 8
  1807. #define RT5645_M_3D_D2R_MASK (0x1 << 7)
  1808. #define RT5645_M_3D_D2R_SFT 7
  1809. #define RT5645_M_3D_REVB_MASK (0x1 << 6)
  1810. #define RT5645_M_3D_REVB_SFT 6
  1811. /* Adjustable high pass filter control 1 (0xd3) */
  1812. #define RT5645_2ND_HPF_MASK (0x1 << 15)
  1813. #define RT5645_2ND_HPF_SFT 15
  1814. #define RT5645_2ND_HPF_DIS (0x0 << 15)
  1815. #define RT5645_2ND_HPF_EN (0x1 << 15)
  1816. #define RT5645_HPF_CF_L_MASK (0x7 << 12)
  1817. #define RT5645_HPF_CF_L_SFT 12
  1818. #define RT5645_1ST_HPF_MASK (0x1 << 11)
  1819. #define RT5645_1ST_HPF_SFT 11
  1820. #define RT5645_1ST_HPF_DIS (0x0 << 11)
  1821. #define RT5645_1ST_HPF_EN (0x1 << 11)
  1822. #define RT5645_HPF_CF_R_MASK (0x7 << 8)
  1823. #define RT5645_HPF_CF_R_SFT 8
  1824. #define RT5645_ZD_T_MASK (0x3 << 6)
  1825. #define RT5645_ZD_T_SFT 6
  1826. #define RT5645_ZD_F_MASK (0x3 << 4)
  1827. #define RT5645_ZD_F_SFT 4
  1828. #define RT5645_ZD_F_IM (0x0 << 4)
  1829. #define RT5645_ZD_F_ZC_IM (0x1 << 4)
  1830. #define RT5645_ZD_F_ZC_IOD (0x2 << 4)
  1831. #define RT5645_ZD_F_UN (0x3 << 4)
  1832. /* HP calibration control and Amp detection (0xd6) */
  1833. #define RT5645_SI_DAC_MASK (0x1 << 11)
  1834. #define RT5645_SI_DAC_SFT 11
  1835. #define RT5645_SI_DAC_AUTO (0x0 << 11)
  1836. #define RT5645_SI_DAC_TEST (0x1 << 11)
  1837. #define RT5645_DC_CAL_M_MASK (0x1 << 10)
  1838. #define RT5645_DC_CAL_M_SFT 10
  1839. #define RT5645_DC_CAL_M_CAL (0x0 << 10)
  1840. #define RT5645_DC_CAL_M_NOR (0x1 << 10)
  1841. #define RT5645_DC_CAL_MASK (0x1 << 9)
  1842. #define RT5645_DC_CAL_SFT 9
  1843. #define RT5645_DC_CAL_DIS (0x0 << 9)
  1844. #define RT5645_DC_CAL_EN (0x1 << 9)
  1845. #define RT5645_HPD_RCV_MASK (0x7 << 6)
  1846. #define RT5645_HPD_RCV_SFT 6
  1847. #define RT5645_HPD_PS_MASK (0x1 << 5)
  1848. #define RT5645_HPD_PS_SFT 5
  1849. #define RT5645_HPD_PS_DIS (0x0 << 5)
  1850. #define RT5645_HPD_PS_EN (0x1 << 5)
  1851. #define RT5645_CAL_M_MASK (0x1 << 4)
  1852. #define RT5645_CAL_M_SFT 4
  1853. #define RT5645_CAL_M_DEP (0x0 << 4)
  1854. #define RT5645_CAL_M_CAL (0x1 << 4)
  1855. #define RT5645_CAL_MASK (0x1 << 3)
  1856. #define RT5645_CAL_SFT 3
  1857. #define RT5645_CAL_DIS (0x0 << 3)
  1858. #define RT5645_CAL_EN (0x1 << 3)
  1859. #define RT5645_CAL_TEST_MASK (0x1 << 2)
  1860. #define RT5645_CAL_TEST_SFT 2
  1861. #define RT5645_CAL_TEST_DIS (0x0 << 2)
  1862. #define RT5645_CAL_TEST_EN (0x1 << 2)
  1863. #define RT5645_CAL_P_MASK (0x3)
  1864. #define RT5645_CAL_P_SFT 0
  1865. #define RT5645_CAL_P_NONE (0x0)
  1866. #define RT5645_CAL_P_CAL (0x1)
  1867. #define RT5645_CAL_P_DAC_CAL (0x2)
  1868. /* Soft volume and zero cross control 1 (0xd9) */
  1869. #define RT5645_SV_MASK (0x1 << 15)
  1870. #define RT5645_SV_SFT 15
  1871. #define RT5645_SV_DIS (0x0 << 15)
  1872. #define RT5645_SV_EN (0x1 << 15)
  1873. #define RT5645_SPO_SV_MASK (0x1 << 14)
  1874. #define RT5645_SPO_SV_SFT 14
  1875. #define RT5645_SPO_SV_DIS (0x0 << 14)
  1876. #define RT5645_SPO_SV_EN (0x1 << 14)
  1877. #define RT5645_OUT_SV_MASK (0x1 << 13)
  1878. #define RT5645_OUT_SV_SFT 13
  1879. #define RT5645_OUT_SV_DIS (0x0 << 13)
  1880. #define RT5645_OUT_SV_EN (0x1 << 13)
  1881. #define RT5645_HP_SV_MASK (0x1 << 12)
  1882. #define RT5645_HP_SV_SFT 12
  1883. #define RT5645_HP_SV_DIS (0x0 << 12)
  1884. #define RT5645_HP_SV_EN (0x1 << 12)
  1885. #define RT5645_ZCD_DIG_MASK (0x1 << 11)
  1886. #define RT5645_ZCD_DIG_SFT 11
  1887. #define RT5645_ZCD_DIG_DIS (0x0 << 11)
  1888. #define RT5645_ZCD_DIG_EN (0x1 << 11)
  1889. #define RT5645_ZCD_MASK (0x1 << 10)
  1890. #define RT5645_ZCD_SFT 10
  1891. #define RT5645_ZCD_PD (0x0 << 10)
  1892. #define RT5645_ZCD_PU (0x1 << 10)
  1893. #define RT5645_M_ZCD_MASK (0x3f << 4)
  1894. #define RT5645_M_ZCD_SFT 4
  1895. #define RT5645_M_ZCD_RM_L (0x1 << 9)
  1896. #define RT5645_M_ZCD_RM_R (0x1 << 8)
  1897. #define RT5645_M_ZCD_SM_L (0x1 << 7)
  1898. #define RT5645_M_ZCD_SM_R (0x1 << 6)
  1899. #define RT5645_M_ZCD_OM_L (0x1 << 5)
  1900. #define RT5645_M_ZCD_OM_R (0x1 << 4)
  1901. #define RT5645_SV_DLY_MASK (0xf)
  1902. #define RT5645_SV_DLY_SFT 0
  1903. /* Soft volume and zero cross control 2 (0xda) */
  1904. #define RT5645_ZCD_HP_MASK (0x1 << 15)
  1905. #define RT5645_ZCD_HP_SFT 15
  1906. #define RT5645_ZCD_HP_DIS (0x0 << 15)
  1907. #define RT5645_ZCD_HP_EN (0x1 << 15)
  1908. /* Codec Private Register definition */
  1909. /* DAC ADC Digital Volume (0x00) */
  1910. #define RT5645_DA1_ZDET_SFT 6
  1911. /* 3D Speaker Control (0x63) */
  1912. #define RT5645_3D_SPK_MASK (0x1 << 15)
  1913. #define RT5645_3D_SPK_SFT 15
  1914. #define RT5645_3D_SPK_DIS (0x0 << 15)
  1915. #define RT5645_3D_SPK_EN (0x1 << 15)
  1916. #define RT5645_3D_SPK_M_MASK (0x3 << 13)
  1917. #define RT5645_3D_SPK_M_SFT 13
  1918. #define RT5645_3D_SPK_CG_MASK (0x1f << 8)
  1919. #define RT5645_3D_SPK_CG_SFT 8
  1920. #define RT5645_3D_SPK_SG_MASK (0x1f)
  1921. #define RT5645_3D_SPK_SG_SFT 0
  1922. /* Wind Noise Detection Control 1 (0x6c) */
  1923. #define RT5645_WND_MASK (0x1 << 15)
  1924. #define RT5645_WND_SFT 15
  1925. #define RT5645_WND_DIS (0x0 << 15)
  1926. #define RT5645_WND_EN (0x1 << 15)
  1927. /* Wind Noise Detection Control 2 (0x6d) */
  1928. #define RT5645_WND_FC_NW_MASK (0x3f << 10)
  1929. #define RT5645_WND_FC_NW_SFT 10
  1930. #define RT5645_WND_FC_WK_MASK (0x3f << 4)
  1931. #define RT5645_WND_FC_WK_SFT 4
  1932. /* Wind Noise Detection Control 3 (0x6e) */
  1933. #define RT5645_HPF_FC_MASK (0x3f << 6)
  1934. #define RT5645_HPF_FC_SFT 6
  1935. #define RT5645_WND_FC_ST_MASK (0x3f)
  1936. #define RT5645_WND_FC_ST_SFT 0
  1937. /* Wind Noise Detection Control 4 (0x6f) */
  1938. #define RT5645_WND_TH_LO_MASK (0x3ff)
  1939. #define RT5645_WND_TH_LO_SFT 0
  1940. /* Wind Noise Detection Control 5 (0x70) */
  1941. #define RT5645_WND_TH_HI_MASK (0x3ff)
  1942. #define RT5645_WND_TH_HI_SFT 0
  1943. /* Wind Noise Detection Control 8 (0x73) */
  1944. #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
  1945. #define RT5645_WND_WIND_SFT 13
  1946. #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
  1947. #define RT5645_WND_STRONG_SFT 12
  1948. enum {
  1949. RT5645_NO_WIND,
  1950. RT5645_BREEZE,
  1951. RT5645_STORM,
  1952. };
  1953. /* Dipole Speaker Interface (0x75) */
  1954. #define RT5645_DP_ATT_MASK (0x3 << 14)
  1955. #define RT5645_DP_ATT_SFT 14
  1956. #define RT5645_DP_SPK_MASK (0x1 << 10)
  1957. #define RT5645_DP_SPK_SFT 10
  1958. #define RT5645_DP_SPK_DIS (0x0 << 10)
  1959. #define RT5645_DP_SPK_EN (0x1 << 10)
  1960. /* EQ Pre Volume Control (0xb3) */
  1961. #define RT5645_EQ_PRE_VOL_MASK (0xffff)
  1962. #define RT5645_EQ_PRE_VOL_SFT 0
  1963. /* EQ Post Volume Control (0xb4) */
  1964. #define RT5645_EQ_PST_VOL_MASK (0xffff)
  1965. #define RT5645_EQ_PST_VOL_SFT 0
  1966. /* Jack Detect Control 3 (0xf8) */
  1967. #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
  1968. #define RT5645_JD_CBJ_EN (0x1 << 7)
  1969. #define RT5645_JD_CBJ_POL (0x1 << 6)
  1970. #define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
  1971. #define RT5645_JD_TRI_CBJ_SEL_SFT (3)
  1972. #define RT5645_JD_TRI_HPO_SEL_MASK (0x7)
  1973. #define RT5645_JD_TRI_HPO_SEL_SFT (0)
  1974. #define RT5645_JD_F_GPIO_JD1 (0x0)
  1975. #define RT5645_JD_F_JD1_1 (0x1)
  1976. #define RT5645_JD_F_JD1_2 (0x2)
  1977. #define RT5645_JD_F_JD2 (0x3)
  1978. #define RT5645_JD_F_JD3 (0x4)
  1979. #define RT5645_JD_F_GPIO_JD2 (0x5)
  1980. #define RT5645_JD_F_MX0B_12 (0x6)
  1981. /* Digital Misc Control (0xfa) */
  1982. #define RT5645_RST_DSP (0x1 << 13)
  1983. #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
  1984. #define RT5645_IF1_ADC1_IN1_SFT 12
  1985. #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
  1986. #define RT5645_IF1_ADC1_IN2_SFT 11
  1987. #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
  1988. #define RT5645_IF1_ADC2_IN1_SFT 10
  1989. #define RT5645_DIG_GATE_CTRL 0x1
  1990. /* General Control2 (0xfb) */
  1991. #define RT5645_RXDC_SRC_MASK (0x1 << 7)
  1992. #define RT5645_RXDC_SRC_STO (0x0 << 7)
  1993. #define RT5645_RXDC_SRC_MONO (0x1 << 7)
  1994. #define RT5645_RXDC_SRC_SFT (7)
  1995. #define RT5645_MICBIAS1_POW_CTRL_SEL_MASK (0x1 << 5)
  1996. #define RT5645_MICBIAS1_POW_CTRL_SEL_A (0x0 << 5)
  1997. #define RT5645_MICBIAS1_POW_CTRL_SEL_M (0x1 << 5)
  1998. #define RT5645_MICBIAS2_POW_CTRL_SEL_MASK (0x1 << 4)
  1999. #define RT5645_MICBIAS2_POW_CTRL_SEL_A (0x0 << 4)
  2000. #define RT5645_MICBIAS2_POW_CTRL_SEL_M (0x1 << 4)
  2001. #define RT5645_RXDP2_SEL_MASK (0x1 << 3)
  2002. #define RT5645_RXDP2_SEL_IF2 (0x0 << 3)
  2003. #define RT5645_RXDP2_SEL_ADC (0x1 << 3)
  2004. #define RT5645_RXDP2_SEL_SFT (3)
  2005. /* General Control3 (0xfc) */
  2006. #define RT5645_JD_PSV_MODE (0x1 << 12)
  2007. #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
  2008. #define RT5645_DET_CLK_MASK (0x3 << 9)
  2009. #define RT5645_DET_CLK_DIS (0x0 << 9)
  2010. #define RT5645_DET_CLK_MODE1 (0x1 << 9)
  2011. #define RT5645_DET_CLK_MODE2 (0x2 << 9)
  2012. #define RT5645_MICINDET_MANU (0x1 << 7)
  2013. #define RT5645_RING2_SLEEVE_GND (0x1 << 5)
  2014. /* Vendor ID (0xfd) */
  2015. #define RT5645_VER_C 0x2
  2016. #define RT5645_VER_D 0x3
  2017. /* Volume Rescale */
  2018. #define RT5645_VOL_RSCL_MAX 0x27
  2019. #define RT5645_VOL_RSCL_RANGE 0x1F
  2020. /* Debug String Length */
  2021. #define RT5645_REG_DISP_LEN 23
  2022. /* System Clock Source */
  2023. enum {
  2024. RT5645_SCLK_S_MCLK,
  2025. RT5645_SCLK_S_PLL1,
  2026. RT5645_SCLK_S_RCCLK,
  2027. };
  2028. /* PLL1 Source */
  2029. enum {
  2030. RT5645_PLL1_S_MCLK,
  2031. RT5645_PLL1_S_BCLK1,
  2032. RT5645_PLL1_S_BCLK2,
  2033. };
  2034. enum {
  2035. RT5645_AIF1,
  2036. RT5645_AIF2,
  2037. RT5645_AIFS,
  2038. };
  2039. enum {
  2040. RT5645_DMIC1_DISABLE,
  2041. RT5645_DMIC_DATA_IN2P,
  2042. RT5645_DMIC_DATA_GPIO6,
  2043. RT5645_DMIC_DATA_GPIO10,
  2044. RT5645_DMIC_DATA_GPIO12,
  2045. };
  2046. enum {
  2047. RT5645_DMIC2_DISABLE,
  2048. RT5645_DMIC_DATA_IN2N,
  2049. RT5645_DMIC_DATA_GPIO5,
  2050. RT5645_DMIC_DATA_GPIO11,
  2051. };
  2052. enum {
  2053. CODEC_TYPE_RT5645,
  2054. CODEC_TYPE_RT5650,
  2055. };
  2056. /* filter mask */
  2057. enum {
  2058. RT5645_DA_STEREO_FILTER = 0x1,
  2059. RT5645_DA_MONO_L_FILTER = (0x1 << 1),
  2060. RT5645_DA_MONO_R_FILTER = (0x1 << 2),
  2061. RT5645_AD_STEREO_FILTER = (0x1 << 3),
  2062. RT5645_AD_MONO_L_FILTER = (0x1 << 4),
  2063. RT5645_AD_MONO_R_FILTER = (0x1 << 5),
  2064. };
  2065. int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
  2066. unsigned int filter_mask, unsigned int clk_src);
  2067. int rt5645_set_jack_detect(struct snd_soc_component *component,
  2068. struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
  2069. struct snd_soc_jack *btn_jack);
  2070. #endif /* __RT5645_H__ */