rt5645.c 123 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5645.c -- RT5645 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/gpio.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/acpi.h>
  19. #include <linux/dmi.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/jack.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include "rl6231.h"
  30. #include "rt5645.h"
  31. #define QUIRK_INV_JD1_1(q) ((q) & 1)
  32. #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
  33. #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
  34. #define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
  35. #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
  36. #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
  37. static unsigned int quirk = -1;
  38. module_param(quirk, uint, 0444);
  39. MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
  40. #define RT5645_DEVICE_ID 0x6308
  41. #define RT5650_DEVICE_ID 0x6419
  42. #define RT5645_PR_RANGE_BASE (0xff + 1)
  43. #define RT5645_PR_SPACING 0x100
  44. #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
  45. #define RT5645_HWEQ_NUM 57
  46. #define TIME_TO_POWER_MS 400
  47. static const struct regmap_range_cfg rt5645_ranges[] = {
  48. {
  49. .name = "PR",
  50. .range_min = RT5645_PR_BASE,
  51. .range_max = RT5645_PR_BASE + 0xf8,
  52. .selector_reg = RT5645_PRIV_INDEX,
  53. .selector_mask = 0xff,
  54. .selector_shift = 0x0,
  55. .window_start = RT5645_PRIV_DATA,
  56. .window_len = 0x1,
  57. },
  58. };
  59. static const struct reg_sequence init_list[] = {
  60. {RT5645_PR_BASE + 0x3d, 0x3600},
  61. {RT5645_PR_BASE + 0x1c, 0xfd70},
  62. {RT5645_PR_BASE + 0x20, 0x611f},
  63. {RT5645_PR_BASE + 0x21, 0x4040},
  64. {RT5645_PR_BASE + 0x23, 0x0004},
  65. {RT5645_ASRC_4, 0x0120},
  66. };
  67. static const struct reg_sequence rt5650_init_list[] = {
  68. {0xf6, 0x0100},
  69. };
  70. static const struct reg_default rt5645_reg[] = {
  71. { 0x00, 0x0000 },
  72. { 0x01, 0xc8c8 },
  73. { 0x02, 0xc8c8 },
  74. { 0x03, 0xc8c8 },
  75. { 0x0a, 0x0002 },
  76. { 0x0b, 0x2827 },
  77. { 0x0c, 0xe000 },
  78. { 0x0d, 0x0000 },
  79. { 0x0e, 0x0000 },
  80. { 0x0f, 0x0808 },
  81. { 0x14, 0x3333 },
  82. { 0x16, 0x4b00 },
  83. { 0x18, 0x018b },
  84. { 0x19, 0xafaf },
  85. { 0x1a, 0xafaf },
  86. { 0x1b, 0x0001 },
  87. { 0x1c, 0x2f2f },
  88. { 0x1d, 0x2f2f },
  89. { 0x1e, 0x0000 },
  90. { 0x20, 0x0000 },
  91. { 0x27, 0x7060 },
  92. { 0x28, 0x7070 },
  93. { 0x29, 0x8080 },
  94. { 0x2a, 0x5656 },
  95. { 0x2b, 0x5454 },
  96. { 0x2c, 0xaaa0 },
  97. { 0x2d, 0x0000 },
  98. { 0x2f, 0x1002 },
  99. { 0x31, 0x5000 },
  100. { 0x32, 0x0000 },
  101. { 0x33, 0x0000 },
  102. { 0x34, 0x0000 },
  103. { 0x35, 0x0000 },
  104. { 0x3b, 0x0000 },
  105. { 0x3c, 0x007f },
  106. { 0x3d, 0x0000 },
  107. { 0x3e, 0x007f },
  108. { 0x3f, 0x0000 },
  109. { 0x40, 0x001f },
  110. { 0x41, 0x0000 },
  111. { 0x42, 0x001f },
  112. { 0x45, 0x6000 },
  113. { 0x46, 0x003e },
  114. { 0x47, 0x003e },
  115. { 0x48, 0xf807 },
  116. { 0x4a, 0x0004 },
  117. { 0x4d, 0x0000 },
  118. { 0x4e, 0x0000 },
  119. { 0x4f, 0x01ff },
  120. { 0x50, 0x0000 },
  121. { 0x51, 0x0000 },
  122. { 0x52, 0x01ff },
  123. { 0x53, 0xf000 },
  124. { 0x56, 0x0111 },
  125. { 0x57, 0x0064 },
  126. { 0x58, 0xef0e },
  127. { 0x59, 0xf0f0 },
  128. { 0x5a, 0xef0e },
  129. { 0x5b, 0xf0f0 },
  130. { 0x5c, 0xef0e },
  131. { 0x5d, 0xf0f0 },
  132. { 0x5e, 0xf000 },
  133. { 0x5f, 0x0000 },
  134. { 0x61, 0x0300 },
  135. { 0x62, 0x0000 },
  136. { 0x63, 0x00c2 },
  137. { 0x64, 0x0000 },
  138. { 0x65, 0x0000 },
  139. { 0x66, 0x0000 },
  140. { 0x6a, 0x0000 },
  141. { 0x6c, 0x0aaa },
  142. { 0x70, 0x8000 },
  143. { 0x71, 0x8000 },
  144. { 0x72, 0x8000 },
  145. { 0x73, 0x7770 },
  146. { 0x74, 0x3e00 },
  147. { 0x75, 0x2409 },
  148. { 0x76, 0x000a },
  149. { 0x77, 0x0c00 },
  150. { 0x78, 0x0000 },
  151. { 0x79, 0x0123 },
  152. { 0x80, 0x0000 },
  153. { 0x81, 0x0000 },
  154. { 0x82, 0x0000 },
  155. { 0x83, 0x0000 },
  156. { 0x84, 0x0000 },
  157. { 0x85, 0x0000 },
  158. { 0x8a, 0x0120 },
  159. { 0x8e, 0x0004 },
  160. { 0x8f, 0x1100 },
  161. { 0x90, 0x0646 },
  162. { 0x91, 0x0c06 },
  163. { 0x93, 0x0000 },
  164. { 0x94, 0x0200 },
  165. { 0x95, 0x0000 },
  166. { 0x9a, 0x2184 },
  167. { 0x9b, 0x010a },
  168. { 0x9c, 0x0aea },
  169. { 0x9d, 0x000c },
  170. { 0x9e, 0x0400 },
  171. { 0xa0, 0xa0a8 },
  172. { 0xa1, 0x0059 },
  173. { 0xa2, 0x0001 },
  174. { 0xae, 0x6000 },
  175. { 0xaf, 0x0000 },
  176. { 0xb0, 0x6000 },
  177. { 0xb1, 0x0000 },
  178. { 0xb2, 0x0000 },
  179. { 0xb3, 0x001f },
  180. { 0xb4, 0x020c },
  181. { 0xb5, 0x1f00 },
  182. { 0xb6, 0x0000 },
  183. { 0xbb, 0x0000 },
  184. { 0xbc, 0x0000 },
  185. { 0xbd, 0x0000 },
  186. { 0xbe, 0x0000 },
  187. { 0xbf, 0x3100 },
  188. { 0xc0, 0x0000 },
  189. { 0xc1, 0x0000 },
  190. { 0xc2, 0x0000 },
  191. { 0xc3, 0x2000 },
  192. { 0xcd, 0x0000 },
  193. { 0xce, 0x0000 },
  194. { 0xcf, 0x1813 },
  195. { 0xd0, 0x0690 },
  196. { 0xd1, 0x1c17 },
  197. { 0xd3, 0xb320 },
  198. { 0xd4, 0x0000 },
  199. { 0xd6, 0x0400 },
  200. { 0xd9, 0x0809 },
  201. { 0xda, 0x0000 },
  202. { 0xdb, 0x0003 },
  203. { 0xdc, 0x0049 },
  204. { 0xdd, 0x001b },
  205. { 0xdf, 0x0008 },
  206. { 0xe0, 0x4000 },
  207. { 0xe6, 0x8000 },
  208. { 0xe7, 0x0200 },
  209. { 0xec, 0xb300 },
  210. { 0xed, 0x0000 },
  211. { 0xf0, 0x001f },
  212. { 0xf1, 0x020c },
  213. { 0xf2, 0x1f00 },
  214. { 0xf3, 0x0000 },
  215. { 0xf4, 0x4000 },
  216. { 0xf8, 0x0000 },
  217. { 0xf9, 0x0000 },
  218. { 0xfa, 0x2060 },
  219. { 0xfb, 0x4040 },
  220. { 0xfc, 0x0000 },
  221. { 0xfd, 0x0002 },
  222. { 0xfe, 0x10ec },
  223. { 0xff, 0x6308 },
  224. };
  225. static const struct reg_default rt5650_reg[] = {
  226. { 0x00, 0x0000 },
  227. { 0x01, 0xc8c8 },
  228. { 0x02, 0xc8c8 },
  229. { 0x03, 0xc8c8 },
  230. { 0x0a, 0x0002 },
  231. { 0x0b, 0x2827 },
  232. { 0x0c, 0xe000 },
  233. { 0x0d, 0x0000 },
  234. { 0x0e, 0x0000 },
  235. { 0x0f, 0x0808 },
  236. { 0x14, 0x3333 },
  237. { 0x16, 0x4b00 },
  238. { 0x18, 0x018b },
  239. { 0x19, 0xafaf },
  240. { 0x1a, 0xafaf },
  241. { 0x1b, 0x0001 },
  242. { 0x1c, 0x2f2f },
  243. { 0x1d, 0x2f2f },
  244. { 0x1e, 0x0000 },
  245. { 0x20, 0x0000 },
  246. { 0x27, 0x7060 },
  247. { 0x28, 0x7070 },
  248. { 0x29, 0x8080 },
  249. { 0x2a, 0x5656 },
  250. { 0x2b, 0x5454 },
  251. { 0x2c, 0xaaa0 },
  252. { 0x2d, 0x0000 },
  253. { 0x2f, 0x5002 },
  254. { 0x31, 0x5000 },
  255. { 0x32, 0x0000 },
  256. { 0x33, 0x0000 },
  257. { 0x34, 0x0000 },
  258. { 0x35, 0x0000 },
  259. { 0x3b, 0x0000 },
  260. { 0x3c, 0x007f },
  261. { 0x3d, 0x0000 },
  262. { 0x3e, 0x007f },
  263. { 0x3f, 0x0000 },
  264. { 0x40, 0x001f },
  265. { 0x41, 0x0000 },
  266. { 0x42, 0x001f },
  267. { 0x45, 0x6000 },
  268. { 0x46, 0x003e },
  269. { 0x47, 0x003e },
  270. { 0x48, 0xf807 },
  271. { 0x4a, 0x0004 },
  272. { 0x4d, 0x0000 },
  273. { 0x4e, 0x0000 },
  274. { 0x4f, 0x01ff },
  275. { 0x50, 0x0000 },
  276. { 0x51, 0x0000 },
  277. { 0x52, 0x01ff },
  278. { 0x53, 0xf000 },
  279. { 0x56, 0x0111 },
  280. { 0x57, 0x0064 },
  281. { 0x58, 0xef0e },
  282. { 0x59, 0xf0f0 },
  283. { 0x5a, 0xef0e },
  284. { 0x5b, 0xf0f0 },
  285. { 0x5c, 0xef0e },
  286. { 0x5d, 0xf0f0 },
  287. { 0x5e, 0xf000 },
  288. { 0x5f, 0x0000 },
  289. { 0x61, 0x0300 },
  290. { 0x62, 0x0000 },
  291. { 0x63, 0x00c2 },
  292. { 0x64, 0x0000 },
  293. { 0x65, 0x0000 },
  294. { 0x66, 0x0000 },
  295. { 0x6a, 0x0000 },
  296. { 0x6c, 0x0aaa },
  297. { 0x70, 0x8000 },
  298. { 0x71, 0x8000 },
  299. { 0x72, 0x8000 },
  300. { 0x73, 0x7770 },
  301. { 0x74, 0x3e00 },
  302. { 0x75, 0x2409 },
  303. { 0x76, 0x000a },
  304. { 0x77, 0x0c00 },
  305. { 0x78, 0x0000 },
  306. { 0x79, 0x0123 },
  307. { 0x7a, 0x0123 },
  308. { 0x80, 0x0000 },
  309. { 0x81, 0x0000 },
  310. { 0x82, 0x0000 },
  311. { 0x83, 0x0000 },
  312. { 0x84, 0x0000 },
  313. { 0x85, 0x0000 },
  314. { 0x8a, 0x0120 },
  315. { 0x8e, 0x0004 },
  316. { 0x8f, 0x1100 },
  317. { 0x90, 0x0646 },
  318. { 0x91, 0x0c06 },
  319. { 0x93, 0x0000 },
  320. { 0x94, 0x0200 },
  321. { 0x95, 0x0000 },
  322. { 0x9a, 0x2184 },
  323. { 0x9b, 0x010a },
  324. { 0x9c, 0x0aea },
  325. { 0x9d, 0x000c },
  326. { 0x9e, 0x0400 },
  327. { 0xa0, 0xa0a8 },
  328. { 0xa1, 0x0059 },
  329. { 0xa2, 0x0001 },
  330. { 0xae, 0x6000 },
  331. { 0xaf, 0x0000 },
  332. { 0xb0, 0x6000 },
  333. { 0xb1, 0x0000 },
  334. { 0xb2, 0x0000 },
  335. { 0xb3, 0x001f },
  336. { 0xb4, 0x020c },
  337. { 0xb5, 0x1f00 },
  338. { 0xb6, 0x0000 },
  339. { 0xbb, 0x0000 },
  340. { 0xbc, 0x0000 },
  341. { 0xbd, 0x0000 },
  342. { 0xbe, 0x0000 },
  343. { 0xbf, 0x3100 },
  344. { 0xc0, 0x0000 },
  345. { 0xc1, 0x0000 },
  346. { 0xc2, 0x0000 },
  347. { 0xc3, 0x2000 },
  348. { 0xcd, 0x0000 },
  349. { 0xce, 0x0000 },
  350. { 0xcf, 0x1813 },
  351. { 0xd0, 0x0690 },
  352. { 0xd1, 0x1c17 },
  353. { 0xd3, 0xb320 },
  354. { 0xd4, 0x0000 },
  355. { 0xd6, 0x0400 },
  356. { 0xd9, 0x0809 },
  357. { 0xda, 0x0000 },
  358. { 0xdb, 0x0003 },
  359. { 0xdc, 0x0049 },
  360. { 0xdd, 0x001b },
  361. { 0xdf, 0x0008 },
  362. { 0xe0, 0x4000 },
  363. { 0xe6, 0x8000 },
  364. { 0xe7, 0x0200 },
  365. { 0xec, 0xb300 },
  366. { 0xed, 0x0000 },
  367. { 0xf0, 0x001f },
  368. { 0xf1, 0x020c },
  369. { 0xf2, 0x1f00 },
  370. { 0xf3, 0x0000 },
  371. { 0xf4, 0x4000 },
  372. { 0xf8, 0x0000 },
  373. { 0xf9, 0x0000 },
  374. { 0xfa, 0x2060 },
  375. { 0xfb, 0x4040 },
  376. { 0xfc, 0x0000 },
  377. { 0xfd, 0x0002 },
  378. { 0xfe, 0x10ec },
  379. { 0xff, 0x6308 },
  380. };
  381. struct rt5645_eq_param_s {
  382. unsigned short reg;
  383. unsigned short val;
  384. };
  385. struct rt5645_eq_param_s_be16 {
  386. __be16 reg;
  387. __be16 val;
  388. };
  389. static const char *const rt5645_supply_names[] = {
  390. "avdd",
  391. "cpvdd",
  392. };
  393. struct rt5645_priv {
  394. struct snd_soc_component *component;
  395. struct rt5645_platform_data pdata;
  396. struct regmap *regmap;
  397. struct i2c_client *i2c;
  398. struct gpio_desc *gpiod_hp_det;
  399. struct snd_soc_jack *hp_jack;
  400. struct snd_soc_jack *mic_jack;
  401. struct snd_soc_jack *btn_jack;
  402. struct delayed_work jack_detect_work, rcclock_work;
  403. struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
  404. struct rt5645_eq_param_s *eq_param;
  405. struct timer_list btn_check_timer;
  406. int codec_type;
  407. int sysclk;
  408. int sysclk_src;
  409. int lrck[RT5645_AIFS];
  410. int bclk[RT5645_AIFS];
  411. int master[RT5645_AIFS];
  412. int pll_src;
  413. int pll_in;
  414. int pll_out;
  415. int jack_type;
  416. bool en_button_func;
  417. bool hp_on;
  418. int v_id;
  419. };
  420. static int rt5645_reset(struct snd_soc_component *component)
  421. {
  422. return snd_soc_component_write(component, RT5645_RESET, 0);
  423. }
  424. static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
  425. {
  426. int i;
  427. for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
  428. if (reg >= rt5645_ranges[i].range_min &&
  429. reg <= rt5645_ranges[i].range_max) {
  430. return true;
  431. }
  432. }
  433. switch (reg) {
  434. case RT5645_RESET:
  435. case RT5645_PRIV_INDEX:
  436. case RT5645_PRIV_DATA:
  437. case RT5645_IN1_CTRL1:
  438. case RT5645_IN1_CTRL2:
  439. case RT5645_IN1_CTRL3:
  440. case RT5645_A_JD_CTRL1:
  441. case RT5645_ADC_EQ_CTRL1:
  442. case RT5645_EQ_CTRL1:
  443. case RT5645_ALC_CTRL_1:
  444. case RT5645_IRQ_CTRL2:
  445. case RT5645_IRQ_CTRL3:
  446. case RT5645_INT_IRQ_ST:
  447. case RT5645_IL_CMD:
  448. case RT5650_4BTN_IL_CMD1:
  449. case RT5645_VENDOR_ID:
  450. case RT5645_VENDOR_ID1:
  451. case RT5645_VENDOR_ID2:
  452. return true;
  453. default:
  454. return false;
  455. }
  456. }
  457. static bool rt5645_readable_register(struct device *dev, unsigned int reg)
  458. {
  459. int i;
  460. for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
  461. if (reg >= rt5645_ranges[i].range_min &&
  462. reg <= rt5645_ranges[i].range_max) {
  463. return true;
  464. }
  465. }
  466. switch (reg) {
  467. case RT5645_RESET:
  468. case RT5645_SPK_VOL:
  469. case RT5645_HP_VOL:
  470. case RT5645_LOUT1:
  471. case RT5645_IN1_CTRL1:
  472. case RT5645_IN1_CTRL2:
  473. case RT5645_IN1_CTRL3:
  474. case RT5645_IN2_CTRL:
  475. case RT5645_INL1_INR1_VOL:
  476. case RT5645_SPK_FUNC_LIM:
  477. case RT5645_ADJ_HPF_CTRL:
  478. case RT5645_DAC1_DIG_VOL:
  479. case RT5645_DAC2_DIG_VOL:
  480. case RT5645_DAC_CTRL:
  481. case RT5645_STO1_ADC_DIG_VOL:
  482. case RT5645_MONO_ADC_DIG_VOL:
  483. case RT5645_ADC_BST_VOL1:
  484. case RT5645_ADC_BST_VOL2:
  485. case RT5645_STO1_ADC_MIXER:
  486. case RT5645_MONO_ADC_MIXER:
  487. case RT5645_AD_DA_MIXER:
  488. case RT5645_STO_DAC_MIXER:
  489. case RT5645_MONO_DAC_MIXER:
  490. case RT5645_DIG_MIXER:
  491. case RT5650_A_DAC_SOUR:
  492. case RT5645_DIG_INF1_DATA:
  493. case RT5645_PDM_OUT_CTRL:
  494. case RT5645_REC_L1_MIXER:
  495. case RT5645_REC_L2_MIXER:
  496. case RT5645_REC_R1_MIXER:
  497. case RT5645_REC_R2_MIXER:
  498. case RT5645_HPMIXL_CTRL:
  499. case RT5645_HPOMIXL_CTRL:
  500. case RT5645_HPMIXR_CTRL:
  501. case RT5645_HPOMIXR_CTRL:
  502. case RT5645_HPO_MIXER:
  503. case RT5645_SPK_L_MIXER:
  504. case RT5645_SPK_R_MIXER:
  505. case RT5645_SPO_MIXER:
  506. case RT5645_SPO_CLSD_RATIO:
  507. case RT5645_OUT_L1_MIXER:
  508. case RT5645_OUT_R1_MIXER:
  509. case RT5645_OUT_L_GAIN1:
  510. case RT5645_OUT_L_GAIN2:
  511. case RT5645_OUT_R_GAIN1:
  512. case RT5645_OUT_R_GAIN2:
  513. case RT5645_LOUT_MIXER:
  514. case RT5645_HAPTIC_CTRL1:
  515. case RT5645_HAPTIC_CTRL2:
  516. case RT5645_HAPTIC_CTRL3:
  517. case RT5645_HAPTIC_CTRL4:
  518. case RT5645_HAPTIC_CTRL5:
  519. case RT5645_HAPTIC_CTRL6:
  520. case RT5645_HAPTIC_CTRL7:
  521. case RT5645_HAPTIC_CTRL8:
  522. case RT5645_HAPTIC_CTRL9:
  523. case RT5645_HAPTIC_CTRL10:
  524. case RT5645_PWR_DIG1:
  525. case RT5645_PWR_DIG2:
  526. case RT5645_PWR_ANLG1:
  527. case RT5645_PWR_ANLG2:
  528. case RT5645_PWR_MIXER:
  529. case RT5645_PWR_VOL:
  530. case RT5645_PRIV_INDEX:
  531. case RT5645_PRIV_DATA:
  532. case RT5645_I2S1_SDP:
  533. case RT5645_I2S2_SDP:
  534. case RT5645_ADDA_CLK1:
  535. case RT5645_ADDA_CLK2:
  536. case RT5645_DMIC_CTRL1:
  537. case RT5645_DMIC_CTRL2:
  538. case RT5645_TDM_CTRL_1:
  539. case RT5645_TDM_CTRL_2:
  540. case RT5645_TDM_CTRL_3:
  541. case RT5650_TDM_CTRL_4:
  542. case RT5645_GLB_CLK:
  543. case RT5645_PLL_CTRL1:
  544. case RT5645_PLL_CTRL2:
  545. case RT5645_ASRC_1:
  546. case RT5645_ASRC_2:
  547. case RT5645_ASRC_3:
  548. case RT5645_ASRC_4:
  549. case RT5645_DEPOP_M1:
  550. case RT5645_DEPOP_M2:
  551. case RT5645_DEPOP_M3:
  552. case RT5645_CHARGE_PUMP:
  553. case RT5645_MICBIAS:
  554. case RT5645_A_JD_CTRL1:
  555. case RT5645_VAD_CTRL4:
  556. case RT5645_CLSD_OUT_CTRL:
  557. case RT5645_ADC_EQ_CTRL1:
  558. case RT5645_ADC_EQ_CTRL2:
  559. case RT5645_EQ_CTRL1:
  560. case RT5645_EQ_CTRL2:
  561. case RT5645_ALC_CTRL_1:
  562. case RT5645_ALC_CTRL_2:
  563. case RT5645_ALC_CTRL_3:
  564. case RT5645_ALC_CTRL_4:
  565. case RT5645_ALC_CTRL_5:
  566. case RT5645_JD_CTRL:
  567. case RT5645_IRQ_CTRL1:
  568. case RT5645_IRQ_CTRL2:
  569. case RT5645_IRQ_CTRL3:
  570. case RT5645_INT_IRQ_ST:
  571. case RT5645_GPIO_CTRL1:
  572. case RT5645_GPIO_CTRL2:
  573. case RT5645_GPIO_CTRL3:
  574. case RT5645_BASS_BACK:
  575. case RT5645_MP3_PLUS1:
  576. case RT5645_MP3_PLUS2:
  577. case RT5645_ADJ_HPF1:
  578. case RT5645_ADJ_HPF2:
  579. case RT5645_HP_CALIB_AMP_DET:
  580. case RT5645_SV_ZCD1:
  581. case RT5645_SV_ZCD2:
  582. case RT5645_IL_CMD:
  583. case RT5645_IL_CMD2:
  584. case RT5645_IL_CMD3:
  585. case RT5650_4BTN_IL_CMD1:
  586. case RT5650_4BTN_IL_CMD2:
  587. case RT5645_DRC1_HL_CTRL1:
  588. case RT5645_DRC2_HL_CTRL1:
  589. case RT5645_ADC_MONO_HP_CTRL1:
  590. case RT5645_ADC_MONO_HP_CTRL2:
  591. case RT5645_DRC2_CTRL1:
  592. case RT5645_DRC2_CTRL2:
  593. case RT5645_DRC2_CTRL3:
  594. case RT5645_DRC2_CTRL4:
  595. case RT5645_DRC2_CTRL5:
  596. case RT5645_JD_CTRL3:
  597. case RT5645_JD_CTRL4:
  598. case RT5645_GEN_CTRL1:
  599. case RT5645_GEN_CTRL2:
  600. case RT5645_GEN_CTRL3:
  601. case RT5645_VENDOR_ID:
  602. case RT5645_VENDOR_ID1:
  603. case RT5645_VENDOR_ID2:
  604. return true;
  605. default:
  606. return false;
  607. }
  608. }
  609. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
  610. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
  611. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
  612. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
  613. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  614. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  615. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  616. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  617. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  618. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  619. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  620. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  621. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  622. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  623. );
  624. /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
  625. static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
  626. 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
  627. 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
  628. 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
  629. 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
  630. );
  631. static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
  632. struct snd_ctl_elem_info *uinfo)
  633. {
  634. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  635. uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
  636. return 0;
  637. }
  638. static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
  639. struct snd_ctl_elem_value *ucontrol)
  640. {
  641. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  642. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  643. struct rt5645_eq_param_s_be16 *eq_param =
  644. (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
  645. int i;
  646. for (i = 0; i < RT5645_HWEQ_NUM; i++) {
  647. eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
  648. eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
  649. }
  650. return 0;
  651. }
  652. static bool rt5645_validate_hweq(unsigned short reg)
  653. {
  654. if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
  655. (reg == RT5645_EQ_CTRL2))
  656. return true;
  657. return false;
  658. }
  659. static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
  660. struct snd_ctl_elem_value *ucontrol)
  661. {
  662. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  663. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  664. struct rt5645_eq_param_s_be16 *eq_param =
  665. (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
  666. int i;
  667. for (i = 0; i < RT5645_HWEQ_NUM; i++) {
  668. rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
  669. rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
  670. }
  671. /* The final setting of the table should be RT5645_EQ_CTRL2 */
  672. for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
  673. if (rt5645->eq_param[i].reg == 0)
  674. continue;
  675. else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
  676. return 0;
  677. else
  678. break;
  679. }
  680. for (i = 0; i < RT5645_HWEQ_NUM; i++) {
  681. if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
  682. rt5645->eq_param[i].reg != 0)
  683. return 0;
  684. else if (rt5645->eq_param[i].reg == 0)
  685. break;
  686. }
  687. return 0;
  688. }
  689. #define RT5645_HWEQ(xname) \
  690. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  691. .info = rt5645_hweq_info, \
  692. .get = rt5645_hweq_get, \
  693. .put = rt5645_hweq_put \
  694. }
  695. static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
  696. struct snd_ctl_elem_value *ucontrol)
  697. {
  698. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  699. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  700. int ret;
  701. regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
  702. RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
  703. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  704. mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
  705. msecs_to_jiffies(200));
  706. return ret;
  707. }
  708. static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
  709. "immediately", "zero crossing", "soft ramp"
  710. };
  711. static SOC_ENUM_SINGLE_DECL(
  712. rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
  713. RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
  714. static const struct snd_kcontrol_new rt5645_snd_controls[] = {
  715. /* Speaker Output Volume */
  716. SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
  717. RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
  718. SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
  719. RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
  720. rt5645_spk_put_volsw, out_vol_tlv),
  721. /* ClassD modulator Speaker Gain Ratio */
  722. SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
  723. RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
  724. /* Headphone Output Volume */
  725. SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
  726. RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
  727. SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
  728. RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
  729. /* OUTPUT Control */
  730. SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
  731. RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
  732. SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
  733. RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
  734. SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
  735. RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
  736. /* DAC Digital Volume */
  737. SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
  738. RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
  739. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
  740. RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
  741. SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
  742. RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
  743. /* IN1/IN2 Control */
  744. SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
  745. RT5645_BST_SFT1, 12, 0, bst_tlv),
  746. SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
  747. RT5645_BST_SFT2, 8, 0, bst_tlv),
  748. /* INL/INR Volume Control */
  749. SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
  750. RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
  751. /* ADC Digital Volume Control */
  752. SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
  753. RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
  754. SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
  755. RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
  756. SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
  757. RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
  758. SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
  759. RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
  760. /* ADC Boost Volume Control */
  761. SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
  762. RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
  763. adc_bst_tlv),
  764. SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
  765. RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
  766. adc_bst_tlv),
  767. /* I2S2 function select */
  768. SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
  769. 1, 1),
  770. RT5645_HWEQ("Speaker HWEQ"),
  771. /* Digital Soft Volume Control */
  772. SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
  773. };
  774. /**
  775. * set_dmic_clk - Set parameter of dmic.
  776. *
  777. * @w: DAPM widget.
  778. * @kcontrol: The kcontrol of this widget.
  779. * @event: Event id.
  780. *
  781. */
  782. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  783. struct snd_kcontrol *kcontrol, int event)
  784. {
  785. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  786. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  787. int idx, rate;
  788. rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
  789. RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
  790. idx = rl6231_calc_dmic_clk(rate);
  791. if (idx < 0)
  792. dev_err(component->dev, "Failed to set DMIC clock\n");
  793. else
  794. snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
  795. RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
  796. return idx;
  797. }
  798. static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  799. struct snd_soc_dapm_widget *sink)
  800. {
  801. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  802. unsigned int val;
  803. val = snd_soc_component_read(component, RT5645_GLB_CLK);
  804. val &= RT5645_SCLK_SRC_MASK;
  805. if (val == RT5645_SCLK_SRC_PLL1)
  806. return 1;
  807. else
  808. return 0;
  809. }
  810. static int is_using_asrc(struct snd_soc_dapm_widget *source,
  811. struct snd_soc_dapm_widget *sink)
  812. {
  813. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  814. unsigned int reg, shift, val;
  815. switch (source->shift) {
  816. case 0:
  817. reg = RT5645_ASRC_3;
  818. shift = 0;
  819. break;
  820. case 1:
  821. reg = RT5645_ASRC_3;
  822. shift = 4;
  823. break;
  824. case 3:
  825. reg = RT5645_ASRC_2;
  826. shift = 0;
  827. break;
  828. case 8:
  829. reg = RT5645_ASRC_2;
  830. shift = 4;
  831. break;
  832. case 9:
  833. reg = RT5645_ASRC_2;
  834. shift = 8;
  835. break;
  836. case 10:
  837. reg = RT5645_ASRC_2;
  838. shift = 12;
  839. break;
  840. default:
  841. return 0;
  842. }
  843. val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
  844. switch (val) {
  845. case 1:
  846. case 2:
  847. case 3:
  848. case 4:
  849. return 1;
  850. default:
  851. return 0;
  852. }
  853. }
  854. static int rt5645_enable_hweq(struct snd_soc_component *component)
  855. {
  856. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  857. int i;
  858. for (i = 0; i < RT5645_HWEQ_NUM; i++) {
  859. if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
  860. regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
  861. rt5645->eq_param[i].val);
  862. else
  863. break;
  864. }
  865. return 0;
  866. }
  867. /**
  868. * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
  869. * @component: SoC audio component device.
  870. * @filter_mask: mask of filters.
  871. * @clk_src: clock source
  872. *
  873. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
  874. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  875. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  876. * ASRC function will track i2s clock and generate a corresponding system clock
  877. * for codec. This function provides an API to select the clock source for a
  878. * set of filters specified by the mask. And the codec driver will turn on ASRC
  879. * for these filters if ASRC is selected as their clock source.
  880. */
  881. int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
  882. unsigned int filter_mask, unsigned int clk_src)
  883. {
  884. unsigned int asrc2_mask = 0;
  885. unsigned int asrc2_value = 0;
  886. unsigned int asrc3_mask = 0;
  887. unsigned int asrc3_value = 0;
  888. switch (clk_src) {
  889. case RT5645_CLK_SEL_SYS:
  890. case RT5645_CLK_SEL_I2S1_ASRC:
  891. case RT5645_CLK_SEL_I2S2_ASRC:
  892. case RT5645_CLK_SEL_SYS2:
  893. break;
  894. default:
  895. return -EINVAL;
  896. }
  897. if (filter_mask & RT5645_DA_STEREO_FILTER) {
  898. asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
  899. asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
  900. | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
  901. }
  902. if (filter_mask & RT5645_DA_MONO_L_FILTER) {
  903. asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
  904. asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
  905. | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
  906. }
  907. if (filter_mask & RT5645_DA_MONO_R_FILTER) {
  908. asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
  909. asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
  910. | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
  911. }
  912. if (filter_mask & RT5645_AD_STEREO_FILTER) {
  913. asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
  914. asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
  915. | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
  916. }
  917. if (filter_mask & RT5645_AD_MONO_L_FILTER) {
  918. asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
  919. asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
  920. | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
  921. }
  922. if (filter_mask & RT5645_AD_MONO_R_FILTER) {
  923. asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
  924. asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
  925. | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
  926. }
  927. if (asrc2_mask)
  928. snd_soc_component_update_bits(component, RT5645_ASRC_2,
  929. asrc2_mask, asrc2_value);
  930. if (asrc3_mask)
  931. snd_soc_component_update_bits(component, RT5645_ASRC_3,
  932. asrc3_mask, asrc3_value);
  933. return 0;
  934. }
  935. EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
  936. /* Digital Mixer */
  937. static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
  938. SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
  939. RT5645_M_ADC_L1_SFT, 1, 1),
  940. SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
  941. RT5645_M_ADC_L2_SFT, 1, 1),
  942. };
  943. static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
  944. SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
  945. RT5645_M_ADC_R1_SFT, 1, 1),
  946. SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
  947. RT5645_M_ADC_R2_SFT, 1, 1),
  948. };
  949. static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
  950. SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
  951. RT5645_M_MONO_ADC_L1_SFT, 1, 1),
  952. SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
  953. RT5645_M_MONO_ADC_L2_SFT, 1, 1),
  954. };
  955. static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
  956. SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
  957. RT5645_M_MONO_ADC_R1_SFT, 1, 1),
  958. SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
  959. RT5645_M_MONO_ADC_R2_SFT, 1, 1),
  960. };
  961. static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
  962. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
  963. RT5645_M_ADCMIX_L_SFT, 1, 1),
  964. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
  965. RT5645_M_DAC1_L_SFT, 1, 1),
  966. };
  967. static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
  968. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
  969. RT5645_M_ADCMIX_R_SFT, 1, 1),
  970. SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
  971. RT5645_M_DAC1_R_SFT, 1, 1),
  972. };
  973. static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
  974. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
  975. RT5645_M_DAC_L1_SFT, 1, 1),
  976. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
  977. RT5645_M_DAC_L2_SFT, 1, 1),
  978. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
  979. RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
  980. };
  981. static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
  982. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
  983. RT5645_M_DAC_R1_SFT, 1, 1),
  984. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
  985. RT5645_M_DAC_R2_SFT, 1, 1),
  986. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
  987. RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
  988. };
  989. static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
  990. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
  991. RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
  992. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
  993. RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
  994. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
  995. RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
  996. };
  997. static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
  998. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
  999. RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
  1000. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
  1001. RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
  1002. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
  1003. RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
  1004. };
  1005. static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
  1006. SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
  1007. RT5645_M_STO_L_DAC_L_SFT, 1, 1),
  1008. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
  1009. RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
  1010. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
  1011. RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
  1012. };
  1013. static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
  1014. SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
  1015. RT5645_M_STO_R_DAC_R_SFT, 1, 1),
  1016. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
  1017. RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
  1018. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
  1019. RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
  1020. };
  1021. /* Analog Input Mixer */
  1022. static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
  1023. SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
  1024. RT5645_M_HP_L_RM_L_SFT, 1, 1),
  1025. SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
  1026. RT5645_M_IN_L_RM_L_SFT, 1, 1),
  1027. SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
  1028. RT5645_M_BST2_RM_L_SFT, 1, 1),
  1029. SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
  1030. RT5645_M_BST1_RM_L_SFT, 1, 1),
  1031. SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
  1032. RT5645_M_OM_L_RM_L_SFT, 1, 1),
  1033. };
  1034. static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
  1035. SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
  1036. RT5645_M_HP_R_RM_R_SFT, 1, 1),
  1037. SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
  1038. RT5645_M_IN_R_RM_R_SFT, 1, 1),
  1039. SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
  1040. RT5645_M_BST2_RM_R_SFT, 1, 1),
  1041. SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
  1042. RT5645_M_BST1_RM_R_SFT, 1, 1),
  1043. SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
  1044. RT5645_M_OM_R_RM_R_SFT, 1, 1),
  1045. };
  1046. static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
  1047. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
  1048. RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
  1049. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
  1050. RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
  1051. SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
  1052. RT5645_M_IN_L_SM_L_SFT, 1, 1),
  1053. SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
  1054. RT5645_M_BST1_L_SM_L_SFT, 1, 1),
  1055. };
  1056. static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
  1057. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
  1058. RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
  1059. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
  1060. RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
  1061. SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
  1062. RT5645_M_IN_R_SM_R_SFT, 1, 1),
  1063. SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
  1064. RT5645_M_BST2_R_SM_R_SFT, 1, 1),
  1065. };
  1066. static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
  1067. SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
  1068. RT5645_M_BST1_OM_L_SFT, 1, 1),
  1069. SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
  1070. RT5645_M_IN_L_OM_L_SFT, 1, 1),
  1071. SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
  1072. RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
  1073. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
  1074. RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
  1075. };
  1076. static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
  1077. SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
  1078. RT5645_M_BST2_OM_R_SFT, 1, 1),
  1079. SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
  1080. RT5645_M_IN_R_OM_R_SFT, 1, 1),
  1081. SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
  1082. RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
  1083. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
  1084. RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
  1085. };
  1086. static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
  1087. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
  1088. RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
  1089. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
  1090. RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
  1091. SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
  1092. RT5645_M_SV_R_SPM_L_SFT, 1, 1),
  1093. SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
  1094. RT5645_M_SV_L_SPM_L_SFT, 1, 1),
  1095. };
  1096. static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
  1097. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
  1098. RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
  1099. SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
  1100. RT5645_M_SV_R_SPM_R_SFT, 1, 1),
  1101. };
  1102. static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
  1103. SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
  1104. RT5645_M_DAC1_HM_SFT, 1, 1),
  1105. SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
  1106. RT5645_M_HPVOL_HM_SFT, 1, 1),
  1107. };
  1108. static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
  1109. SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
  1110. RT5645_M_DAC1_HV_SFT, 1, 1),
  1111. SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
  1112. RT5645_M_DAC2_HV_SFT, 1, 1),
  1113. SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
  1114. RT5645_M_IN_HV_SFT, 1, 1),
  1115. SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
  1116. RT5645_M_BST1_HV_SFT, 1, 1),
  1117. };
  1118. static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
  1119. SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
  1120. RT5645_M_DAC1_HV_SFT, 1, 1),
  1121. SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
  1122. RT5645_M_DAC2_HV_SFT, 1, 1),
  1123. SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
  1124. RT5645_M_IN_HV_SFT, 1, 1),
  1125. SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
  1126. RT5645_M_BST2_HV_SFT, 1, 1),
  1127. };
  1128. static const struct snd_kcontrol_new rt5645_lout_mix[] = {
  1129. SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
  1130. RT5645_M_DAC_L1_LM_SFT, 1, 1),
  1131. SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
  1132. RT5645_M_DAC_R1_LM_SFT, 1, 1),
  1133. SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
  1134. RT5645_M_OV_L_LM_SFT, 1, 1),
  1135. SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
  1136. RT5645_M_OV_R_LM_SFT, 1, 1),
  1137. };
  1138. /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
  1139. static const char * const rt5645_dac1_src[] = {
  1140. "IF1 DAC", "IF2 DAC", "IF3 DAC"
  1141. };
  1142. static SOC_ENUM_SINGLE_DECL(
  1143. rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
  1144. RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
  1145. static const struct snd_kcontrol_new rt5645_dac1l_mux =
  1146. SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
  1147. static SOC_ENUM_SINGLE_DECL(
  1148. rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
  1149. RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
  1150. static const struct snd_kcontrol_new rt5645_dac1r_mux =
  1151. SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
  1152. /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
  1153. static const char * const rt5645_dac12_src[] = {
  1154. "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
  1155. };
  1156. static SOC_ENUM_SINGLE_DECL(
  1157. rt5645_dac2l_enum, RT5645_DAC_CTRL,
  1158. RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
  1159. static const struct snd_kcontrol_new rt5645_dac_l2_mux =
  1160. SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
  1161. static const char * const rt5645_dacr2_src[] = {
  1162. "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
  1163. };
  1164. static SOC_ENUM_SINGLE_DECL(
  1165. rt5645_dac2r_enum, RT5645_DAC_CTRL,
  1166. RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
  1167. static const struct snd_kcontrol_new rt5645_dac_r2_mux =
  1168. SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
  1169. /* Stereo1 ADC source */
  1170. /* MX-27 [12] */
  1171. static const char * const rt5645_stereo_adc1_src[] = {
  1172. "DAC MIX", "ADC"
  1173. };
  1174. static SOC_ENUM_SINGLE_DECL(
  1175. rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
  1176. RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
  1177. static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
  1178. SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
  1179. /* MX-27 [11] */
  1180. static const char * const rt5645_stereo_adc2_src[] = {
  1181. "DAC MIX", "DMIC"
  1182. };
  1183. static SOC_ENUM_SINGLE_DECL(
  1184. rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
  1185. RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
  1186. static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
  1187. SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
  1188. /* MX-27 [8] */
  1189. static const char * const rt5645_stereo_dmic_src[] = {
  1190. "DMIC1", "DMIC2"
  1191. };
  1192. static SOC_ENUM_SINGLE_DECL(
  1193. rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
  1194. RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
  1195. static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
  1196. SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
  1197. /* Mono ADC source */
  1198. /* MX-28 [12] */
  1199. static const char * const rt5645_mono_adc_l1_src[] = {
  1200. "Mono DAC MIXL", "ADC"
  1201. };
  1202. static SOC_ENUM_SINGLE_DECL(
  1203. rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
  1204. RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
  1205. static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
  1206. SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
  1207. /* MX-28 [11] */
  1208. static const char * const rt5645_mono_adc_l2_src[] = {
  1209. "Mono DAC MIXL", "DMIC"
  1210. };
  1211. static SOC_ENUM_SINGLE_DECL(
  1212. rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
  1213. RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
  1214. static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
  1215. SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
  1216. /* MX-28 [8] */
  1217. static const char * const rt5645_mono_dmic_src[] = {
  1218. "DMIC1", "DMIC2"
  1219. };
  1220. static SOC_ENUM_SINGLE_DECL(
  1221. rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
  1222. RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
  1223. static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
  1224. SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
  1225. /* MX-28 [1:0] */
  1226. static SOC_ENUM_SINGLE_DECL(
  1227. rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
  1228. RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
  1229. static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
  1230. SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
  1231. /* MX-28 [4] */
  1232. static const char * const rt5645_mono_adc_r1_src[] = {
  1233. "Mono DAC MIXR", "ADC"
  1234. };
  1235. static SOC_ENUM_SINGLE_DECL(
  1236. rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
  1237. RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
  1238. static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
  1239. SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
  1240. /* MX-28 [3] */
  1241. static const char * const rt5645_mono_adc_r2_src[] = {
  1242. "Mono DAC MIXR", "DMIC"
  1243. };
  1244. static SOC_ENUM_SINGLE_DECL(
  1245. rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
  1246. RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
  1247. static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
  1248. SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
  1249. /* MX-77 [9:8] */
  1250. static const char * const rt5645_if1_adc_in_src[] = {
  1251. "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
  1252. "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
  1253. };
  1254. static SOC_ENUM_SINGLE_DECL(
  1255. rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
  1256. RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
  1257. static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
  1258. SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
  1259. /* MX-78 [4:0] */
  1260. static const char * const rt5650_if1_adc_in_src[] = {
  1261. "IF_ADC1/IF_ADC2/DAC_REF/Null",
  1262. "IF_ADC1/IF_ADC2/Null/DAC_REF",
  1263. "IF_ADC1/DAC_REF/IF_ADC2/Null",
  1264. "IF_ADC1/DAC_REF/Null/IF_ADC2",
  1265. "IF_ADC1/Null/DAC_REF/IF_ADC2",
  1266. "IF_ADC1/Null/IF_ADC2/DAC_REF",
  1267. "IF_ADC2/IF_ADC1/DAC_REF/Null",
  1268. "IF_ADC2/IF_ADC1/Null/DAC_REF",
  1269. "IF_ADC2/DAC_REF/IF_ADC1/Null",
  1270. "IF_ADC2/DAC_REF/Null/IF_ADC1",
  1271. "IF_ADC2/Null/DAC_REF/IF_ADC1",
  1272. "IF_ADC2/Null/IF_ADC1/DAC_REF",
  1273. "DAC_REF/IF_ADC1/IF_ADC2/Null",
  1274. "DAC_REF/IF_ADC1/Null/IF_ADC2",
  1275. "DAC_REF/IF_ADC2/IF_ADC1/Null",
  1276. "DAC_REF/IF_ADC2/Null/IF_ADC1",
  1277. "DAC_REF/Null/IF_ADC1/IF_ADC2",
  1278. "DAC_REF/Null/IF_ADC2/IF_ADC1",
  1279. "Null/IF_ADC1/IF_ADC2/DAC_REF",
  1280. "Null/IF_ADC1/DAC_REF/IF_ADC2",
  1281. "Null/IF_ADC2/IF_ADC1/DAC_REF",
  1282. "Null/IF_ADC2/DAC_REF/IF_ADC1",
  1283. "Null/DAC_REF/IF_ADC1/IF_ADC2",
  1284. "Null/DAC_REF/IF_ADC2/IF_ADC1",
  1285. };
  1286. static SOC_ENUM_SINGLE_DECL(
  1287. rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
  1288. 0, rt5650_if1_adc_in_src);
  1289. static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
  1290. SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
  1291. /* MX-78 [15:14][13:12][11:10] */
  1292. static const char * const rt5645_tdm_adc_swap_select[] = {
  1293. "L/R", "R/L", "L/L", "R/R"
  1294. };
  1295. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
  1296. RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
  1297. static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
  1298. SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
  1299. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
  1300. RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
  1301. static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
  1302. SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
  1303. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
  1304. RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
  1305. static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
  1306. SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
  1307. /* MX-77 [7:6][5:4][3:2] */
  1308. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
  1309. RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
  1310. static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
  1311. SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
  1312. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
  1313. RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
  1314. static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
  1315. SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
  1316. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
  1317. RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
  1318. static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
  1319. SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
  1320. /* MX-79 [14:12][10:8][6:4][2:0] */
  1321. static const char * const rt5645_tdm_dac_swap_select[] = {
  1322. "Slot0", "Slot1", "Slot2", "Slot3"
  1323. };
  1324. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
  1325. RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
  1326. static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
  1327. SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
  1328. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
  1329. RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
  1330. static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
  1331. SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
  1332. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
  1333. RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
  1334. static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
  1335. SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
  1336. static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
  1337. RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
  1338. static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
  1339. SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
  1340. /* MX-7a [14:12][10:8][6:4][2:0] */
  1341. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
  1342. RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
  1343. static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
  1344. SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
  1345. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
  1346. RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
  1347. static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
  1348. SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
  1349. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
  1350. RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
  1351. static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
  1352. SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
  1353. static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
  1354. RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
  1355. static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
  1356. SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
  1357. /* MX-2d [3] [2] */
  1358. static const char * const rt5650_a_dac1_src[] = {
  1359. "DAC1", "Stereo DAC Mixer"
  1360. };
  1361. static SOC_ENUM_SINGLE_DECL(
  1362. rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
  1363. RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
  1364. static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
  1365. SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
  1366. static SOC_ENUM_SINGLE_DECL(
  1367. rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
  1368. RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
  1369. static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
  1370. SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
  1371. /* MX-2d [1] [0] */
  1372. static const char * const rt5650_a_dac2_src[] = {
  1373. "Stereo DAC Mixer", "Mono DAC Mixer"
  1374. };
  1375. static SOC_ENUM_SINGLE_DECL(
  1376. rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
  1377. RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
  1378. static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
  1379. SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
  1380. static SOC_ENUM_SINGLE_DECL(
  1381. rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
  1382. RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
  1383. static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
  1384. SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
  1385. /* MX-2F [13:12] */
  1386. static const char * const rt5645_if2_adc_in_src[] = {
  1387. "IF_ADC1", "IF_ADC2", "VAD_ADC"
  1388. };
  1389. static SOC_ENUM_SINGLE_DECL(
  1390. rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
  1391. RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
  1392. static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
  1393. SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
  1394. /* MX-31 [15] [13] [11] [9] */
  1395. static const char * const rt5645_pdm_src[] = {
  1396. "Mono DAC", "Stereo DAC"
  1397. };
  1398. static SOC_ENUM_SINGLE_DECL(
  1399. rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
  1400. RT5645_PDM1_L_SFT, rt5645_pdm_src);
  1401. static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
  1402. SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
  1403. static SOC_ENUM_SINGLE_DECL(
  1404. rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
  1405. RT5645_PDM1_R_SFT, rt5645_pdm_src);
  1406. static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
  1407. SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
  1408. /* MX-9D [9:8] */
  1409. static const char * const rt5645_vad_adc_src[] = {
  1410. "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
  1411. };
  1412. static SOC_ENUM_SINGLE_DECL(
  1413. rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
  1414. RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
  1415. static const struct snd_kcontrol_new rt5645_vad_adc_mux =
  1416. SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
  1417. static const struct snd_kcontrol_new spk_l_vol_control =
  1418. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
  1419. RT5645_L_MUTE_SFT, 1, 1);
  1420. static const struct snd_kcontrol_new spk_r_vol_control =
  1421. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
  1422. RT5645_R_MUTE_SFT, 1, 1);
  1423. static const struct snd_kcontrol_new hp_l_vol_control =
  1424. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
  1425. RT5645_L_MUTE_SFT, 1, 1);
  1426. static const struct snd_kcontrol_new hp_r_vol_control =
  1427. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
  1428. RT5645_R_MUTE_SFT, 1, 1);
  1429. static const struct snd_kcontrol_new pdm1_l_vol_control =
  1430. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
  1431. RT5645_M_PDM1_L, 1, 1);
  1432. static const struct snd_kcontrol_new pdm1_r_vol_control =
  1433. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
  1434. RT5645_M_PDM1_R, 1, 1);
  1435. static void hp_amp_power(struct snd_soc_component *component, int on)
  1436. {
  1437. static int hp_amp_power_count;
  1438. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  1439. if (on) {
  1440. if (hp_amp_power_count <= 0) {
  1441. if (rt5645->codec_type == CODEC_TYPE_RT5650) {
  1442. snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
  1443. snd_soc_component_write(component, RT5645_CHARGE_PUMP,
  1444. 0x0e06);
  1445. snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
  1446. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1447. RT5645_HP_DCC_INT1, 0x9f01);
  1448. msleep(20);
  1449. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1450. RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
  1451. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1452. 0x3e, 0x7400);
  1453. snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
  1454. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1455. RT5645_MAMP_INT_REG2, 0xfc00);
  1456. snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
  1457. msleep(90);
  1458. rt5645->hp_on = true;
  1459. } else {
  1460. /* depop parameters */
  1461. snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
  1462. RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
  1463. snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
  1464. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1465. RT5645_HP_DCC_INT1, 0x9f01);
  1466. mdelay(150);
  1467. /* headphone amp power on */
  1468. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1469. RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
  1470. snd_soc_component_update_bits(component, RT5645_PWR_VOL,
  1471. RT5645_PWR_HV_L | RT5645_PWR_HV_R,
  1472. RT5645_PWR_HV_L | RT5645_PWR_HV_R);
  1473. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1474. RT5645_PWR_HP_L | RT5645_PWR_HP_R |
  1475. RT5645_PWR_HA,
  1476. RT5645_PWR_HP_L | RT5645_PWR_HP_R |
  1477. RT5645_PWR_HA);
  1478. mdelay(5);
  1479. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1480. RT5645_PWR_FV1 | RT5645_PWR_FV2,
  1481. RT5645_PWR_FV1 | RT5645_PWR_FV2);
  1482. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1483. RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
  1484. RT5645_HP_CO_EN | RT5645_HP_SG_EN);
  1485. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1486. 0x14, 0x1aaa);
  1487. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1488. 0x24, 0x0430);
  1489. }
  1490. }
  1491. hp_amp_power_count++;
  1492. } else {
  1493. hp_amp_power_count--;
  1494. if (hp_amp_power_count <= 0) {
  1495. if (rt5645->codec_type == CODEC_TYPE_RT5650) {
  1496. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1497. 0x3e, 0x7400);
  1498. snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
  1499. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1500. RT5645_MAMP_INT_REG2, 0xfc00);
  1501. snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
  1502. msleep(100);
  1503. snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
  1504. } else {
  1505. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1506. RT5645_HP_SG_MASK |
  1507. RT5645_HP_L_SMT_MASK |
  1508. RT5645_HP_R_SMT_MASK,
  1509. RT5645_HP_SG_DIS |
  1510. RT5645_HP_L_SMT_DIS |
  1511. RT5645_HP_R_SMT_DIS);
  1512. /* headphone amp power down */
  1513. snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
  1514. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1515. RT5645_PWR_HP_L | RT5645_PWR_HP_R |
  1516. RT5645_PWR_HA, 0);
  1517. snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
  1518. RT5645_DEPOP_MASK, 0);
  1519. }
  1520. }
  1521. }
  1522. }
  1523. static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
  1524. struct snd_kcontrol *kcontrol, int event)
  1525. {
  1526. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1527. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  1528. switch (event) {
  1529. case SND_SOC_DAPM_POST_PMU:
  1530. hp_amp_power(component, 1);
  1531. /* headphone unmute sequence */
  1532. if (rt5645->codec_type == CODEC_TYPE_RT5645) {
  1533. snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
  1534. RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
  1535. RT5645_CP_FQ3_MASK,
  1536. (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
  1537. (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
  1538. (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
  1539. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1540. RT5645_MAMP_INT_REG2, 0xfc00);
  1541. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1542. RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
  1543. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1544. RT5645_RSTN_MASK, RT5645_RSTN_EN);
  1545. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1546. RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
  1547. RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
  1548. RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
  1549. msleep(40);
  1550. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1551. RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
  1552. RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
  1553. RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
  1554. }
  1555. break;
  1556. case SND_SOC_DAPM_PRE_PMD:
  1557. /* headphone mute sequence */
  1558. if (rt5645->codec_type == CODEC_TYPE_RT5645) {
  1559. snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
  1560. RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
  1561. RT5645_CP_FQ3_MASK,
  1562. (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
  1563. (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
  1564. (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
  1565. regmap_write(rt5645->regmap, RT5645_PR_BASE +
  1566. RT5645_MAMP_INT_REG2, 0xfc00);
  1567. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1568. RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
  1569. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1570. RT5645_RSTP_MASK, RT5645_RSTP_EN);
  1571. snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
  1572. RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
  1573. RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
  1574. RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
  1575. msleep(30);
  1576. }
  1577. hp_amp_power(component, 0);
  1578. break;
  1579. default:
  1580. return 0;
  1581. }
  1582. return 0;
  1583. }
  1584. static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
  1585. struct snd_kcontrol *kcontrol, int event)
  1586. {
  1587. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1588. switch (event) {
  1589. case SND_SOC_DAPM_POST_PMU:
  1590. rt5645_enable_hweq(component);
  1591. snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
  1592. RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
  1593. RT5645_PWR_CLS_D_L,
  1594. RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
  1595. RT5645_PWR_CLS_D_L);
  1596. snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
  1597. RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
  1598. break;
  1599. case SND_SOC_DAPM_PRE_PMD:
  1600. snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
  1601. RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
  1602. snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
  1603. snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
  1604. RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
  1605. RT5645_PWR_CLS_D_L, 0);
  1606. break;
  1607. default:
  1608. return 0;
  1609. }
  1610. return 0;
  1611. }
  1612. static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
  1613. struct snd_kcontrol *kcontrol, int event)
  1614. {
  1615. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1616. switch (event) {
  1617. case SND_SOC_DAPM_POST_PMU:
  1618. hp_amp_power(component, 1);
  1619. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1620. RT5645_PWR_LM, RT5645_PWR_LM);
  1621. snd_soc_component_update_bits(component, RT5645_LOUT1,
  1622. RT5645_L_MUTE | RT5645_R_MUTE, 0);
  1623. break;
  1624. case SND_SOC_DAPM_PRE_PMD:
  1625. snd_soc_component_update_bits(component, RT5645_LOUT1,
  1626. RT5645_L_MUTE | RT5645_R_MUTE,
  1627. RT5645_L_MUTE | RT5645_R_MUTE);
  1628. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  1629. RT5645_PWR_LM, 0);
  1630. hp_amp_power(component, 0);
  1631. break;
  1632. default:
  1633. return 0;
  1634. }
  1635. return 0;
  1636. }
  1637. static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
  1638. struct snd_kcontrol *kcontrol, int event)
  1639. {
  1640. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1641. switch (event) {
  1642. case SND_SOC_DAPM_POST_PMU:
  1643. snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
  1644. RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
  1645. break;
  1646. case SND_SOC_DAPM_PRE_PMD:
  1647. snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
  1648. RT5645_PWR_BST2_P, 0);
  1649. break;
  1650. default:
  1651. return 0;
  1652. }
  1653. return 0;
  1654. }
  1655. static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
  1656. struct snd_kcontrol *k, int event)
  1657. {
  1658. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1659. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  1660. switch (event) {
  1661. case SND_SOC_DAPM_POST_PMU:
  1662. if (rt5645->hp_on) {
  1663. msleep(100);
  1664. rt5645->hp_on = false;
  1665. }
  1666. break;
  1667. default:
  1668. return 0;
  1669. }
  1670. return 0;
  1671. }
  1672. static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
  1673. struct snd_kcontrol *k, int event)
  1674. {
  1675. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1676. switch (event) {
  1677. case SND_SOC_DAPM_PRE_PMU:
  1678. snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
  1679. RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
  1680. RT5645_MICBIAS1_POW_CTRL_SEL_M);
  1681. break;
  1682. case SND_SOC_DAPM_POST_PMD:
  1683. snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
  1684. RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
  1685. RT5645_MICBIAS1_POW_CTRL_SEL_A);
  1686. break;
  1687. default:
  1688. return 0;
  1689. }
  1690. return 0;
  1691. }
  1692. static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
  1693. struct snd_kcontrol *k, int event)
  1694. {
  1695. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1696. switch (event) {
  1697. case SND_SOC_DAPM_PRE_PMU:
  1698. snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
  1699. RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
  1700. RT5645_MICBIAS2_POW_CTRL_SEL_M);
  1701. break;
  1702. case SND_SOC_DAPM_POST_PMD:
  1703. snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
  1704. RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
  1705. RT5645_MICBIAS2_POW_CTRL_SEL_A);
  1706. break;
  1707. default:
  1708. return 0;
  1709. }
  1710. return 0;
  1711. }
  1712. static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
  1713. SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
  1714. RT5645_PWR_LDO2_BIT, 0, NULL, 0),
  1715. SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
  1716. RT5645_PWR_PLL_BIT, 0, NULL, 0),
  1717. SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
  1718. RT5645_PWR_JD1_BIT, 0, NULL, 0),
  1719. SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
  1720. RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
  1721. /* ASRC */
  1722. SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
  1723. 11, 0, NULL, 0),
  1724. SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
  1725. 12, 0, NULL, 0),
  1726. SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
  1727. 10, 0, NULL, 0),
  1728. SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
  1729. 9, 0, NULL, 0),
  1730. SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
  1731. 8, 0, NULL, 0),
  1732. SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
  1733. 7, 0, NULL, 0),
  1734. SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
  1735. 5, 0, NULL, 0),
  1736. SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
  1737. 4, 0, NULL, 0),
  1738. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
  1739. 3, 0, NULL, 0),
  1740. SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
  1741. 1, 0, NULL, 0),
  1742. SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
  1743. 0, 0, NULL, 0),
  1744. /* Input Side */
  1745. /* micbias */
  1746. SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
  1747. RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1749. SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
  1750. RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
  1751. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1752. /* Input Lines */
  1753. SND_SOC_DAPM_INPUT("DMIC L1"),
  1754. SND_SOC_DAPM_INPUT("DMIC R1"),
  1755. SND_SOC_DAPM_INPUT("DMIC L2"),
  1756. SND_SOC_DAPM_INPUT("DMIC R2"),
  1757. SND_SOC_DAPM_INPUT("IN1P"),
  1758. SND_SOC_DAPM_INPUT("IN1N"),
  1759. SND_SOC_DAPM_INPUT("IN2P"),
  1760. SND_SOC_DAPM_INPUT("IN2N"),
  1761. SND_SOC_DAPM_INPUT("Haptic Generator"),
  1762. SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1763. SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1764. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  1765. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  1766. SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
  1767. RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
  1768. SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
  1769. RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
  1770. /* Boost */
  1771. SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
  1772. RT5645_PWR_BST1_BIT, 0, NULL, 0),
  1773. SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
  1774. RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
  1775. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  1776. /* Input Volume */
  1777. SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
  1778. RT5645_PWR_IN_L_BIT, 0, NULL, 0),
  1779. SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
  1780. RT5645_PWR_IN_R_BIT, 0, NULL, 0),
  1781. /* REC Mixer */
  1782. SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
  1783. 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
  1784. SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
  1785. 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
  1786. /* ADCs */
  1787. SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
  1788. SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
  1789. SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
  1790. RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
  1791. SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
  1792. RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
  1793. /* ADC Mux */
  1794. SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
  1795. &rt5645_sto1_dmic_mux),
  1796. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  1797. &rt5645_sto_adc2_mux),
  1798. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  1799. &rt5645_sto_adc2_mux),
  1800. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  1801. &rt5645_sto_adc1_mux),
  1802. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  1803. &rt5645_sto_adc1_mux),
  1804. SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
  1805. &rt5645_mono_dmic_l_mux),
  1806. SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
  1807. &rt5645_mono_dmic_r_mux),
  1808. SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  1809. &rt5645_mono_adc_l2_mux),
  1810. SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  1811. &rt5645_mono_adc_l1_mux),
  1812. SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  1813. &rt5645_mono_adc_r1_mux),
  1814. SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  1815. &rt5645_mono_adc_r2_mux),
  1816. /* ADC Mixer */
  1817. SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
  1818. RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
  1819. SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  1820. rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
  1821. NULL, 0),
  1822. SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  1823. rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
  1824. NULL, 0),
  1825. SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
  1826. RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
  1827. SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
  1828. rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
  1829. NULL, 0),
  1830. SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
  1831. RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
  1832. SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
  1833. rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
  1834. NULL, 0),
  1835. /* ADC PGA */
  1836. SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  1837. SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  1838. SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  1839. SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  1840. SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1841. SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1842. SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1843. SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1844. SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  1845. SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
  1846. /* IF1 2 Mux */
  1847. SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
  1848. 0, 0, &rt5645_if2_adc_in_mux),
  1849. /* Digital Interface */
  1850. SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
  1851. RT5645_PWR_I2S1_BIT, 0, NULL, 0),
  1852. SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
  1853. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1854. SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1855. SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  1856. SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  1857. SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1858. SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1859. SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
  1860. RT5645_PWR_I2S2_BIT, 0, NULL, 0),
  1861. SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  1862. SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1863. SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1864. SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  1865. /* Digital Interface Select */
  1866. SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
  1867. 0, 0, &rt5645_vad_adc_mux),
  1868. /* Audio Interface */
  1869. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  1870. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  1871. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  1872. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  1873. /* Output Side */
  1874. /* DAC mixer before sound effect */
  1875. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  1876. rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
  1877. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  1878. rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
  1879. /* DAC2 channel Mux */
  1880. SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
  1881. SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
  1882. SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
  1883. RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
  1884. SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
  1885. RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
  1886. SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
  1887. SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
  1888. /* DAC Mixer */
  1889. SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
  1890. RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
  1891. SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
  1892. RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
  1893. SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
  1894. RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
  1895. SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
  1896. rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
  1897. SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
  1898. rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
  1899. SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
  1900. rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
  1901. SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
  1902. rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
  1903. SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
  1904. rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
  1905. SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
  1906. rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
  1907. /* DACs */
  1908. SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
  1909. 0),
  1910. SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
  1911. 0),
  1912. SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
  1913. 0),
  1914. SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
  1915. 0),
  1916. /* OUT Mixer */
  1917. SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
  1918. 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
  1919. SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
  1920. 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
  1921. SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
  1922. 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
  1923. SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
  1924. 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
  1925. /* Ouput Volume */
  1926. SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
  1927. &spk_l_vol_control),
  1928. SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
  1929. &spk_r_vol_control),
  1930. SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
  1931. 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
  1932. SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
  1933. 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
  1934. SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
  1935. RT5645_PWR_HM_L_BIT, 0, NULL, 0),
  1936. SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
  1937. RT5645_PWR_HM_R_BIT, 0, NULL, 0),
  1938. SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1939. SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1940. SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
  1941. SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
  1942. SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
  1943. /* HPO/LOUT/Mono Mixer */
  1944. SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
  1945. ARRAY_SIZE(rt5645_spo_l_mix)),
  1946. SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
  1947. ARRAY_SIZE(rt5645_spo_r_mix)),
  1948. SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
  1949. ARRAY_SIZE(rt5645_hpo_mix)),
  1950. SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
  1951. ARRAY_SIZE(rt5645_lout_mix)),
  1952. SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
  1953. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  1954. SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
  1955. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  1956. SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
  1957. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  1958. /* PDM */
  1959. SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
  1960. 0, NULL, 0),
  1961. SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
  1962. SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
  1963. SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
  1964. SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
  1965. /* Output Lines */
  1966. SND_SOC_DAPM_OUTPUT("HPOL"),
  1967. SND_SOC_DAPM_OUTPUT("HPOR"),
  1968. SND_SOC_DAPM_OUTPUT("LOUTL"),
  1969. SND_SOC_DAPM_OUTPUT("LOUTR"),
  1970. SND_SOC_DAPM_OUTPUT("PDM1L"),
  1971. SND_SOC_DAPM_OUTPUT("PDM1R"),
  1972. SND_SOC_DAPM_OUTPUT("SPOL"),
  1973. SND_SOC_DAPM_OUTPUT("SPOR"),
  1974. SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
  1975. };
  1976. static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
  1977. SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
  1978. &rt5645_if1_dac0_tdm_sel_mux),
  1979. SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
  1980. &rt5645_if1_dac1_tdm_sel_mux),
  1981. SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
  1982. &rt5645_if1_dac2_tdm_sel_mux),
  1983. SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
  1984. &rt5645_if1_dac3_tdm_sel_mux),
  1985. SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
  1986. 0, 0, &rt5645_if1_adc_in_mux),
  1987. SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
  1988. 0, 0, &rt5645_if1_adc1_in_mux),
  1989. SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
  1990. 0, 0, &rt5645_if1_adc2_in_mux),
  1991. SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
  1992. 0, 0, &rt5645_if1_adc3_in_mux),
  1993. };
  1994. static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
  1995. SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
  1996. 0, 0, &rt5650_a_dac1_l_mux),
  1997. SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
  1998. 0, 0, &rt5650_a_dac1_r_mux),
  1999. SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
  2000. 0, 0, &rt5650_a_dac2_l_mux),
  2001. SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
  2002. 0, 0, &rt5650_a_dac2_r_mux),
  2003. SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
  2004. 0, 0, &rt5650_if1_adc1_in_mux),
  2005. SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
  2006. 0, 0, &rt5650_if1_adc2_in_mux),
  2007. SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
  2008. 0, 0, &rt5650_if1_adc3_in_mux),
  2009. SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
  2010. 0, 0, &rt5650_if1_adc_in_mux),
  2011. SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
  2012. &rt5650_if1_dac0_tdm_sel_mux),
  2013. SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
  2014. &rt5650_if1_dac1_tdm_sel_mux),
  2015. SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
  2016. &rt5650_if1_dac2_tdm_sel_mux),
  2017. SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
  2018. &rt5650_if1_dac3_tdm_sel_mux),
  2019. };
  2020. static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
  2021. { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
  2022. { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
  2023. { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
  2024. { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
  2025. { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
  2026. { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
  2027. { "I2S1", NULL, "I2S1 ASRC" },
  2028. { "I2S2", NULL, "I2S2 ASRC" },
  2029. { "IN1P", NULL, "LDO2" },
  2030. { "IN2P", NULL, "LDO2" },
  2031. { "DMIC1", NULL, "DMIC L1" },
  2032. { "DMIC1", NULL, "DMIC R1" },
  2033. { "DMIC2", NULL, "DMIC L2" },
  2034. { "DMIC2", NULL, "DMIC R2" },
  2035. { "BST1", NULL, "IN1P" },
  2036. { "BST1", NULL, "IN1N" },
  2037. { "BST1", NULL, "JD Power" },
  2038. { "BST1", NULL, "Mic Det Power" },
  2039. { "BST2", NULL, "IN2P" },
  2040. { "BST2", NULL, "IN2N" },
  2041. { "INL VOL", NULL, "IN2P" },
  2042. { "INR VOL", NULL, "IN2N" },
  2043. { "RECMIXL", "HPOL Switch", "HPOL" },
  2044. { "RECMIXL", "INL Switch", "INL VOL" },
  2045. { "RECMIXL", "BST2 Switch", "BST2" },
  2046. { "RECMIXL", "BST1 Switch", "BST1" },
  2047. { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
  2048. { "RECMIXR", "HPOR Switch", "HPOR" },
  2049. { "RECMIXR", "INR Switch", "INR VOL" },
  2050. { "RECMIXR", "BST2 Switch", "BST2" },
  2051. { "RECMIXR", "BST1 Switch", "BST1" },
  2052. { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
  2053. { "ADC L", NULL, "RECMIXL" },
  2054. { "ADC L", NULL, "ADC L power" },
  2055. { "ADC R", NULL, "RECMIXR" },
  2056. { "ADC R", NULL, "ADC R power" },
  2057. {"DMIC L1", NULL, "DMIC CLK"},
  2058. {"DMIC L1", NULL, "DMIC1 Power"},
  2059. {"DMIC R1", NULL, "DMIC CLK"},
  2060. {"DMIC R1", NULL, "DMIC1 Power"},
  2061. {"DMIC L2", NULL, "DMIC CLK"},
  2062. {"DMIC L2", NULL, "DMIC2 Power"},
  2063. {"DMIC R2", NULL, "DMIC CLK"},
  2064. {"DMIC R2", NULL, "DMIC2 Power"},
  2065. { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
  2066. { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
  2067. { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
  2068. { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
  2069. { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
  2070. { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
  2071. { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
  2072. { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
  2073. { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
  2074. { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
  2075. { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
  2076. { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
  2077. { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
  2078. { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
  2079. { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
  2080. { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
  2081. { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
  2082. { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
  2083. { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
  2084. { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
  2085. { "Mono ADC L1 Mux", "ADC", "ADC L" },
  2086. { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
  2087. { "Mono ADC R1 Mux", "ADC", "ADC R" },
  2088. { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
  2089. { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
  2090. { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
  2091. { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
  2092. { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
  2093. { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
  2094. { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
  2095. { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
  2096. { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
  2097. { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
  2098. { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
  2099. { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
  2100. { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
  2101. { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
  2102. { "Mono ADC MIXL", NULL, "adc mono left filter" },
  2103. { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
  2104. { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
  2105. { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
  2106. { "Mono ADC MIXR", NULL, "adc mono right filter" },
  2107. { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
  2108. { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
  2109. { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
  2110. { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
  2111. { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
  2112. { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
  2113. { "IF_ADC2", NULL, "Mono ADC MIXL" },
  2114. { "IF_ADC2", NULL, "Mono ADC MIXR" },
  2115. { "VAD_ADC", NULL, "VAD ADC Mux" },
  2116. { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
  2117. { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
  2118. { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
  2119. { "IF1 ADC", NULL, "I2S1" },
  2120. { "IF2 ADC", NULL, "I2S2" },
  2121. { "IF2 ADC", NULL, "IF2 ADC Mux" },
  2122. { "AIF2TX", NULL, "IF2 ADC" },
  2123. { "IF1 DAC0", NULL, "AIF1RX" },
  2124. { "IF1 DAC1", NULL, "AIF1RX" },
  2125. { "IF1 DAC2", NULL, "AIF1RX" },
  2126. { "IF1 DAC3", NULL, "AIF1RX" },
  2127. { "IF2 DAC", NULL, "AIF2RX" },
  2128. { "IF1 DAC0", NULL, "I2S1" },
  2129. { "IF1 DAC1", NULL, "I2S1" },
  2130. { "IF1 DAC2", NULL, "I2S1" },
  2131. { "IF1 DAC3", NULL, "I2S1" },
  2132. { "IF2 DAC", NULL, "I2S2" },
  2133. { "IF2 DAC L", NULL, "IF2 DAC" },
  2134. { "IF2 DAC R", NULL, "IF2 DAC" },
  2135. { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
  2136. { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
  2137. { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
  2138. { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
  2139. { "DAC1 MIXL", NULL, "dac stereo1 filter" },
  2140. { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
  2141. { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
  2142. { "DAC1 MIXR", NULL, "dac stereo1 filter" },
  2143. { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
  2144. { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
  2145. { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
  2146. { "DAC L2 Volume", NULL, "DAC L2 Mux" },
  2147. { "DAC L2 Volume", NULL, "dac mono left filter" },
  2148. { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
  2149. { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
  2150. { "DAC R2 Mux", "Haptic", "Haptic Generator" },
  2151. { "DAC R2 Volume", NULL, "DAC R2 Mux" },
  2152. { "DAC R2 Volume", NULL, "dac mono right filter" },
  2153. { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
  2154. { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
  2155. { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  2156. { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
  2157. { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
  2158. { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
  2159. { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  2160. { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
  2161. { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
  2162. { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  2163. { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
  2164. { "Mono DAC MIXL", NULL, "dac mono left filter" },
  2165. { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
  2166. { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  2167. { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
  2168. { "Mono DAC MIXR", NULL, "dac mono right filter" },
  2169. { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
  2170. { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  2171. { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
  2172. { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
  2173. { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  2174. { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
  2175. { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
  2176. { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
  2177. { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
  2178. { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
  2179. { "SPK MIXL", "BST1 Switch", "BST1" },
  2180. { "SPK MIXL", "INL Switch", "INL VOL" },
  2181. { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
  2182. { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
  2183. { "SPK MIXR", "BST2 Switch", "BST2" },
  2184. { "SPK MIXR", "INR Switch", "INR VOL" },
  2185. { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
  2186. { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
  2187. { "OUT MIXL", "BST1 Switch", "BST1" },
  2188. { "OUT MIXL", "INL Switch", "INL VOL" },
  2189. { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
  2190. { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
  2191. { "OUT MIXR", "BST2 Switch", "BST2" },
  2192. { "OUT MIXR", "INR Switch", "INR VOL" },
  2193. { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
  2194. { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
  2195. { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
  2196. { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
  2197. { "HPOVOL MIXL", "INL Switch", "INL VOL" },
  2198. { "HPOVOL MIXL", "BST1 Switch", "BST1" },
  2199. { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
  2200. { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
  2201. { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
  2202. { "HPOVOL MIXR", "INR Switch", "INR VOL" },
  2203. { "HPOVOL MIXR", "BST2 Switch", "BST2" },
  2204. { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
  2205. { "DAC 2", NULL, "DAC L2" },
  2206. { "DAC 2", NULL, "DAC R2" },
  2207. { "DAC 1", NULL, "DAC L1" },
  2208. { "DAC 1", NULL, "DAC R1" },
  2209. { "HPOVOL L", "Switch", "HPOVOL MIXL" },
  2210. { "HPOVOL R", "Switch", "HPOVOL MIXR" },
  2211. { "HPOVOL", NULL, "HPOVOL L" },
  2212. { "HPOVOL", NULL, "HPOVOL R" },
  2213. { "HPO MIX", "DAC1 Switch", "DAC 1" },
  2214. { "HPO MIX", "HPVOL Switch", "HPOVOL" },
  2215. { "SPKVOL L", "Switch", "SPK MIXL" },
  2216. { "SPKVOL R", "Switch", "SPK MIXR" },
  2217. { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
  2218. { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
  2219. { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
  2220. { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
  2221. { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
  2222. { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
  2223. { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
  2224. { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
  2225. { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
  2226. { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
  2227. { "PDM1 L Mux", NULL, "PDM1 Power" },
  2228. { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
  2229. { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
  2230. { "PDM1 R Mux", NULL, "PDM1 Power" },
  2231. { "HP amp", NULL, "HPO MIX" },
  2232. { "HP amp", NULL, "JD Power" },
  2233. { "HP amp", NULL, "Mic Det Power" },
  2234. { "HP amp", NULL, "LDO2" },
  2235. { "HPOL", NULL, "HP amp" },
  2236. { "HPOR", NULL, "HP amp" },
  2237. { "LOUT amp", NULL, "LOUT MIX" },
  2238. { "LOUTL", NULL, "LOUT amp" },
  2239. { "LOUTR", NULL, "LOUT amp" },
  2240. { "PDM1 L", "Switch", "PDM1 L Mux" },
  2241. { "PDM1 R", "Switch", "PDM1 R Mux" },
  2242. { "PDM1L", NULL, "PDM1 L" },
  2243. { "PDM1R", NULL, "PDM1 R" },
  2244. { "SPK amp", NULL, "SPOL MIX" },
  2245. { "SPK amp", NULL, "SPOR MIX" },
  2246. { "SPOL", NULL, "SPK amp" },
  2247. { "SPOR", NULL, "SPK amp" },
  2248. };
  2249. static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
  2250. { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
  2251. { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
  2252. { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
  2253. { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
  2254. { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
  2255. { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
  2256. { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
  2257. { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
  2258. { "DAC L1", NULL, "A DAC1 L Mux" },
  2259. { "DAC R1", NULL, "A DAC1 R Mux" },
  2260. { "DAC L2", NULL, "A DAC2 L Mux" },
  2261. { "DAC R2", NULL, "A DAC2 R Mux" },
  2262. { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
  2263. { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
  2264. { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
  2265. { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
  2266. { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
  2267. { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
  2268. { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
  2269. { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
  2270. { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
  2271. { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
  2272. { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
  2273. { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
  2274. { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
  2275. { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
  2276. { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
  2277. { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
  2278. { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
  2279. { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
  2280. { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
  2281. { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
  2282. { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
  2283. { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
  2284. { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
  2285. { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
  2286. { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
  2287. { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
  2288. { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
  2289. { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
  2290. { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
  2291. { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
  2292. { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
  2293. { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
  2294. { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
  2295. { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
  2296. { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
  2297. { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
  2298. { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
  2299. { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
  2300. { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
  2301. { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
  2302. { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
  2303. { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
  2304. { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
  2305. { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
  2306. { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
  2307. { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
  2308. { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
  2309. { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
  2310. { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
  2311. { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
  2312. { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
  2313. { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
  2314. { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
  2315. { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
  2316. { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
  2317. { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
  2318. { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
  2319. { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
  2320. { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
  2321. { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
  2322. };
  2323. static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
  2324. { "DAC L1", NULL, "Stereo DAC MIXL" },
  2325. { "DAC R1", NULL, "Stereo DAC MIXR" },
  2326. { "DAC L2", NULL, "Mono DAC MIXL" },
  2327. { "DAC R2", NULL, "Mono DAC MIXR" },
  2328. { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
  2329. { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
  2330. { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
  2331. { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
  2332. { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
  2333. { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
  2334. { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
  2335. { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
  2336. { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
  2337. { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
  2338. { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
  2339. { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
  2340. { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
  2341. { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
  2342. { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
  2343. { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
  2344. { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
  2345. { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
  2346. { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
  2347. { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
  2348. { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
  2349. { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
  2350. { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
  2351. { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
  2352. { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
  2353. { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
  2354. { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
  2355. { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
  2356. { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
  2357. { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
  2358. { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
  2359. { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
  2360. { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
  2361. { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
  2362. { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
  2363. { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
  2364. { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
  2365. { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
  2366. { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
  2367. { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
  2368. };
  2369. static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
  2370. { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
  2371. { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
  2372. };
  2373. static int rt5645_hw_params(struct snd_pcm_substream *substream,
  2374. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  2375. {
  2376. struct snd_soc_component *component = dai->component;
  2377. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2378. unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
  2379. int pre_div, bclk_ms, frame_size;
  2380. rt5645->lrck[dai->id] = params_rate(params);
  2381. pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
  2382. if (pre_div < 0) {
  2383. dev_err(component->dev, "Unsupported clock setting\n");
  2384. return -EINVAL;
  2385. }
  2386. frame_size = snd_soc_params_to_frame_size(params);
  2387. if (frame_size < 0) {
  2388. dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
  2389. return -EINVAL;
  2390. }
  2391. switch (rt5645->codec_type) {
  2392. case CODEC_TYPE_RT5650:
  2393. dl_sft = 4;
  2394. break;
  2395. default:
  2396. dl_sft = 2;
  2397. break;
  2398. }
  2399. bclk_ms = frame_size > 32;
  2400. rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
  2401. dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  2402. rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
  2403. dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  2404. bclk_ms, pre_div, dai->id);
  2405. switch (params_width(params)) {
  2406. case 16:
  2407. break;
  2408. case 20:
  2409. val_len = 0x1;
  2410. break;
  2411. case 24:
  2412. val_len = 0x2;
  2413. break;
  2414. case 8:
  2415. val_len = 0x3;
  2416. break;
  2417. default:
  2418. return -EINVAL;
  2419. }
  2420. switch (dai->id) {
  2421. case RT5645_AIF1:
  2422. mask_clk = RT5645_I2S_PD1_MASK;
  2423. val_clk = pre_div << RT5645_I2S_PD1_SFT;
  2424. snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
  2425. (0x3 << dl_sft), (val_len << dl_sft));
  2426. snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
  2427. break;
  2428. case RT5645_AIF2:
  2429. mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
  2430. val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
  2431. pre_div << RT5645_I2S_PD2_SFT;
  2432. snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
  2433. (0x3 << dl_sft), (val_len << dl_sft));
  2434. snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
  2435. break;
  2436. default:
  2437. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  2438. return -EINVAL;
  2439. }
  2440. return 0;
  2441. }
  2442. static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2443. {
  2444. struct snd_soc_component *component = dai->component;
  2445. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2446. unsigned int reg_val = 0, pol_sft;
  2447. switch (rt5645->codec_type) {
  2448. case CODEC_TYPE_RT5650:
  2449. pol_sft = 8;
  2450. break;
  2451. default:
  2452. pol_sft = 7;
  2453. break;
  2454. }
  2455. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2456. case SND_SOC_DAIFMT_CBM_CFM:
  2457. rt5645->master[dai->id] = 1;
  2458. break;
  2459. case SND_SOC_DAIFMT_CBS_CFS:
  2460. reg_val |= RT5645_I2S_MS_S;
  2461. rt5645->master[dai->id] = 0;
  2462. break;
  2463. default:
  2464. return -EINVAL;
  2465. }
  2466. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2467. case SND_SOC_DAIFMT_NB_NF:
  2468. break;
  2469. case SND_SOC_DAIFMT_IB_NF:
  2470. reg_val |= (1 << pol_sft);
  2471. break;
  2472. default:
  2473. return -EINVAL;
  2474. }
  2475. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2476. case SND_SOC_DAIFMT_I2S:
  2477. break;
  2478. case SND_SOC_DAIFMT_LEFT_J:
  2479. reg_val |= RT5645_I2S_DF_LEFT;
  2480. break;
  2481. case SND_SOC_DAIFMT_DSP_A:
  2482. reg_val |= RT5645_I2S_DF_PCM_A;
  2483. break;
  2484. case SND_SOC_DAIFMT_DSP_B:
  2485. reg_val |= RT5645_I2S_DF_PCM_B;
  2486. break;
  2487. default:
  2488. return -EINVAL;
  2489. }
  2490. switch (dai->id) {
  2491. case RT5645_AIF1:
  2492. snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
  2493. RT5645_I2S_MS_MASK | (1 << pol_sft) |
  2494. RT5645_I2S_DF_MASK, reg_val);
  2495. break;
  2496. case RT5645_AIF2:
  2497. snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
  2498. RT5645_I2S_MS_MASK | (1 << pol_sft) |
  2499. RT5645_I2S_DF_MASK, reg_val);
  2500. break;
  2501. default:
  2502. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  2503. return -EINVAL;
  2504. }
  2505. return 0;
  2506. }
  2507. static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
  2508. int clk_id, unsigned int freq, int dir)
  2509. {
  2510. struct snd_soc_component *component = dai->component;
  2511. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2512. unsigned int reg_val = 0;
  2513. if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
  2514. return 0;
  2515. switch (clk_id) {
  2516. case RT5645_SCLK_S_MCLK:
  2517. reg_val |= RT5645_SCLK_SRC_MCLK;
  2518. break;
  2519. case RT5645_SCLK_S_PLL1:
  2520. reg_val |= RT5645_SCLK_SRC_PLL1;
  2521. break;
  2522. case RT5645_SCLK_S_RCCLK:
  2523. reg_val |= RT5645_SCLK_SRC_RCCLK;
  2524. break;
  2525. default:
  2526. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  2527. return -EINVAL;
  2528. }
  2529. snd_soc_component_update_bits(component, RT5645_GLB_CLK,
  2530. RT5645_SCLK_SRC_MASK, reg_val);
  2531. rt5645->sysclk = freq;
  2532. rt5645->sysclk_src = clk_id;
  2533. dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  2534. return 0;
  2535. }
  2536. static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  2537. unsigned int freq_in, unsigned int freq_out)
  2538. {
  2539. struct snd_soc_component *component = dai->component;
  2540. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2541. struct rl6231_pll_code pll_code;
  2542. int ret;
  2543. if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
  2544. freq_out == rt5645->pll_out)
  2545. return 0;
  2546. if (!freq_in || !freq_out) {
  2547. dev_dbg(component->dev, "PLL disabled\n");
  2548. rt5645->pll_in = 0;
  2549. rt5645->pll_out = 0;
  2550. snd_soc_component_update_bits(component, RT5645_GLB_CLK,
  2551. RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
  2552. return 0;
  2553. }
  2554. switch (source) {
  2555. case RT5645_PLL1_S_MCLK:
  2556. snd_soc_component_update_bits(component, RT5645_GLB_CLK,
  2557. RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
  2558. break;
  2559. case RT5645_PLL1_S_BCLK1:
  2560. case RT5645_PLL1_S_BCLK2:
  2561. switch (dai->id) {
  2562. case RT5645_AIF1:
  2563. snd_soc_component_update_bits(component, RT5645_GLB_CLK,
  2564. RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
  2565. break;
  2566. case RT5645_AIF2:
  2567. snd_soc_component_update_bits(component, RT5645_GLB_CLK,
  2568. RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
  2569. break;
  2570. default:
  2571. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  2572. return -EINVAL;
  2573. }
  2574. break;
  2575. default:
  2576. dev_err(component->dev, "Unknown PLL source %d\n", source);
  2577. return -EINVAL;
  2578. }
  2579. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  2580. if (ret < 0) {
  2581. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  2582. return ret;
  2583. }
  2584. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  2585. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  2586. pll_code.n_code, pll_code.k_code);
  2587. snd_soc_component_write(component, RT5645_PLL_CTRL1,
  2588. pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
  2589. snd_soc_component_write(component, RT5645_PLL_CTRL2,
  2590. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
  2591. pll_code.m_bp << RT5645_PLL_M_BP_SFT);
  2592. rt5645->pll_in = freq_in;
  2593. rt5645->pll_out = freq_out;
  2594. rt5645->pll_src = source;
  2595. return 0;
  2596. }
  2597. static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  2598. unsigned int rx_mask, int slots, int slot_width)
  2599. {
  2600. struct snd_soc_component *component = dai->component;
  2601. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2602. unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
  2603. unsigned int mask, val = 0;
  2604. switch (rt5645->codec_type) {
  2605. case CODEC_TYPE_RT5650:
  2606. en_sft = 15;
  2607. i_slot_sft = 10;
  2608. o_slot_sft = 8;
  2609. i_width_sht = 6;
  2610. o_width_sht = 4;
  2611. mask = 0x8ff0;
  2612. break;
  2613. default:
  2614. en_sft = 14;
  2615. i_slot_sft = o_slot_sft = 12;
  2616. i_width_sht = o_width_sht = 10;
  2617. mask = 0x7c00;
  2618. break;
  2619. }
  2620. if (rx_mask || tx_mask) {
  2621. val |= (1 << en_sft);
  2622. if (rt5645->codec_type == CODEC_TYPE_RT5645)
  2623. snd_soc_component_update_bits(component, RT5645_BASS_BACK,
  2624. RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
  2625. }
  2626. switch (slots) {
  2627. case 4:
  2628. val |= (1 << i_slot_sft) | (1 << o_slot_sft);
  2629. break;
  2630. case 6:
  2631. val |= (2 << i_slot_sft) | (2 << o_slot_sft);
  2632. break;
  2633. case 8:
  2634. val |= (3 << i_slot_sft) | (3 << o_slot_sft);
  2635. break;
  2636. case 2:
  2637. default:
  2638. break;
  2639. }
  2640. switch (slot_width) {
  2641. case 20:
  2642. val |= (1 << i_width_sht) | (1 << o_width_sht);
  2643. break;
  2644. case 24:
  2645. val |= (2 << i_width_sht) | (2 << o_width_sht);
  2646. break;
  2647. case 32:
  2648. val |= (3 << i_width_sht) | (3 << o_width_sht);
  2649. break;
  2650. case 16:
  2651. default:
  2652. break;
  2653. }
  2654. snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
  2655. return 0;
  2656. }
  2657. static int rt5645_set_bias_level(struct snd_soc_component *component,
  2658. enum snd_soc_bias_level level)
  2659. {
  2660. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2661. switch (level) {
  2662. case SND_SOC_BIAS_PREPARE:
  2663. if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
  2664. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  2665. RT5645_PWR_VREF1 | RT5645_PWR_MB |
  2666. RT5645_PWR_BG | RT5645_PWR_VREF2,
  2667. RT5645_PWR_VREF1 | RT5645_PWR_MB |
  2668. RT5645_PWR_BG | RT5645_PWR_VREF2);
  2669. mdelay(10);
  2670. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  2671. RT5645_PWR_FV1 | RT5645_PWR_FV2,
  2672. RT5645_PWR_FV1 | RT5645_PWR_FV2);
  2673. snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
  2674. RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
  2675. }
  2676. break;
  2677. case SND_SOC_BIAS_STANDBY:
  2678. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  2679. RT5645_PWR_VREF1 | RT5645_PWR_MB |
  2680. RT5645_PWR_BG | RT5645_PWR_VREF2,
  2681. RT5645_PWR_VREF1 | RT5645_PWR_MB |
  2682. RT5645_PWR_BG | RT5645_PWR_VREF2);
  2683. mdelay(10);
  2684. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  2685. RT5645_PWR_FV1 | RT5645_PWR_FV2,
  2686. RT5645_PWR_FV1 | RT5645_PWR_FV2);
  2687. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  2688. snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
  2689. msleep(40);
  2690. if (rt5645->en_button_func)
  2691. queue_delayed_work(system_power_efficient_wq,
  2692. &rt5645->jack_detect_work,
  2693. msecs_to_jiffies(0));
  2694. }
  2695. break;
  2696. case SND_SOC_BIAS_OFF:
  2697. snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
  2698. if (!rt5645->en_button_func)
  2699. snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
  2700. RT5645_DIG_GATE_CTRL, 0);
  2701. snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
  2702. RT5645_PWR_VREF1 | RT5645_PWR_MB |
  2703. RT5645_PWR_BG | RT5645_PWR_VREF2 |
  2704. RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
  2705. break;
  2706. default:
  2707. break;
  2708. }
  2709. return 0;
  2710. }
  2711. static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
  2712. bool enable)
  2713. {
  2714. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2715. if (enable) {
  2716. snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
  2717. snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
  2718. snd_soc_dapm_sync(dapm);
  2719. snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
  2720. snd_soc_component_update_bits(component,
  2721. RT5645_INT_IRQ_ST, 0x8, 0x8);
  2722. snd_soc_component_update_bits(component,
  2723. RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
  2724. snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
  2725. pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
  2726. snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
  2727. } else {
  2728. snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
  2729. snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
  2730. snd_soc_dapm_disable_pin(dapm, "ADC L power");
  2731. snd_soc_dapm_disable_pin(dapm, "ADC R power");
  2732. snd_soc_dapm_sync(dapm);
  2733. }
  2734. }
  2735. static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
  2736. {
  2737. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2738. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2739. unsigned int val;
  2740. if (jack_insert) {
  2741. regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
  2742. /* for jack type detect */
  2743. snd_soc_dapm_force_enable_pin(dapm, "LDO2");
  2744. snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
  2745. snd_soc_dapm_sync(dapm);
  2746. if (!dapm->card->instantiated) {
  2747. /* Power up necessary bits for JD if dapm is
  2748. not ready yet */
  2749. regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
  2750. RT5645_PWR_MB | RT5645_PWR_VREF2,
  2751. RT5645_PWR_MB | RT5645_PWR_VREF2);
  2752. regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
  2753. RT5645_PWR_LDO2, RT5645_PWR_LDO2);
  2754. regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
  2755. RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
  2756. }
  2757. regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
  2758. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
  2759. RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
  2760. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
  2761. RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
  2762. msleep(100);
  2763. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
  2764. RT5645_CBJ_MN_JD, 0);
  2765. msleep(600);
  2766. regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
  2767. val &= 0x7;
  2768. dev_dbg(component->dev, "val = %d\n", val);
  2769. if (val == 1 || val == 2) {
  2770. rt5645->jack_type = SND_JACK_HEADSET;
  2771. if (rt5645->en_button_func) {
  2772. rt5645_enable_push_button_irq(component, true);
  2773. }
  2774. } else {
  2775. snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
  2776. snd_soc_dapm_sync(dapm);
  2777. rt5645->jack_type = SND_JACK_HEADPHONE;
  2778. }
  2779. if (rt5645->pdata.level_trigger_irq)
  2780. regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
  2781. RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
  2782. } else { /* jack out */
  2783. rt5645->jack_type = 0;
  2784. regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
  2785. RT5645_L_MUTE | RT5645_R_MUTE,
  2786. RT5645_L_MUTE | RT5645_R_MUTE);
  2787. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
  2788. RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
  2789. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
  2790. RT5645_CBJ_BST1_EN, 0);
  2791. if (rt5645->en_button_func)
  2792. rt5645_enable_push_button_irq(component, false);
  2793. if (rt5645->pdata.jd_mode == 0)
  2794. snd_soc_dapm_disable_pin(dapm, "LDO2");
  2795. snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
  2796. snd_soc_dapm_sync(dapm);
  2797. if (rt5645->pdata.level_trigger_irq)
  2798. regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
  2799. RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
  2800. }
  2801. return rt5645->jack_type;
  2802. }
  2803. static int rt5645_button_detect(struct snd_soc_component *component)
  2804. {
  2805. int btn_type, val;
  2806. val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
  2807. pr_debug("val=0x%x\n", val);
  2808. btn_type = val & 0xfff0;
  2809. snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
  2810. return btn_type;
  2811. }
  2812. static irqreturn_t rt5645_irq(int irq, void *data);
  2813. int rt5645_set_jack_detect(struct snd_soc_component *component,
  2814. struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
  2815. struct snd_soc_jack *btn_jack)
  2816. {
  2817. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2818. rt5645->hp_jack = hp_jack;
  2819. rt5645->mic_jack = mic_jack;
  2820. rt5645->btn_jack = btn_jack;
  2821. if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
  2822. rt5645->en_button_func = true;
  2823. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  2824. RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
  2825. regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
  2826. RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
  2827. }
  2828. rt5645_irq(0, rt5645);
  2829. return 0;
  2830. }
  2831. EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
  2832. static void rt5645_jack_detect_work(struct work_struct *work)
  2833. {
  2834. struct rt5645_priv *rt5645 =
  2835. container_of(work, struct rt5645_priv, jack_detect_work.work);
  2836. int val, btn_type, gpio_state = 0, report = 0;
  2837. if (!rt5645->component)
  2838. return;
  2839. switch (rt5645->pdata.jd_mode) {
  2840. case 0: /* Not using rt5645 JD */
  2841. if (rt5645->gpiod_hp_det) {
  2842. gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
  2843. dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
  2844. gpio_state);
  2845. report = rt5645_jack_detect(rt5645->component, gpio_state);
  2846. }
  2847. snd_soc_jack_report(rt5645->hp_jack,
  2848. report, SND_JACK_HEADPHONE);
  2849. snd_soc_jack_report(rt5645->mic_jack,
  2850. report, SND_JACK_MICROPHONE);
  2851. return;
  2852. case 4:
  2853. val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
  2854. break;
  2855. default: /* read rt5645 jd1_1 status */
  2856. val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
  2857. break;
  2858. }
  2859. if (!val && (rt5645->jack_type == 0)) { /* jack in */
  2860. report = rt5645_jack_detect(rt5645->component, 1);
  2861. } else if (!val && rt5645->jack_type != 0) {
  2862. /* for push button and jack out */
  2863. btn_type = 0;
  2864. if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
  2865. /* button pressed */
  2866. report = SND_JACK_HEADSET;
  2867. btn_type = rt5645_button_detect(rt5645->component);
  2868. /* rt5650 can report three kinds of button behavior,
  2869. one click, double click and hold. However,
  2870. currently we will report button pressed/released
  2871. event. So all the three button behaviors are
  2872. treated as button pressed. */
  2873. switch (btn_type) {
  2874. case 0x8000:
  2875. case 0x4000:
  2876. case 0x2000:
  2877. report |= SND_JACK_BTN_0;
  2878. break;
  2879. case 0x1000:
  2880. case 0x0800:
  2881. case 0x0400:
  2882. report |= SND_JACK_BTN_1;
  2883. break;
  2884. case 0x0200:
  2885. case 0x0100:
  2886. case 0x0080:
  2887. report |= SND_JACK_BTN_2;
  2888. break;
  2889. case 0x0040:
  2890. case 0x0020:
  2891. case 0x0010:
  2892. report |= SND_JACK_BTN_3;
  2893. break;
  2894. case 0x0000: /* unpressed */
  2895. break;
  2896. default:
  2897. dev_err(rt5645->component->dev,
  2898. "Unexpected button code 0x%04x\n",
  2899. btn_type);
  2900. break;
  2901. }
  2902. }
  2903. if (btn_type == 0)/* button release */
  2904. report = rt5645->jack_type;
  2905. else {
  2906. mod_timer(&rt5645->btn_check_timer,
  2907. msecs_to_jiffies(100));
  2908. }
  2909. } else {
  2910. /* jack out */
  2911. report = 0;
  2912. snd_soc_component_update_bits(rt5645->component,
  2913. RT5645_INT_IRQ_ST, 0x1, 0x0);
  2914. rt5645_jack_detect(rt5645->component, 0);
  2915. }
  2916. snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
  2917. snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
  2918. if (rt5645->en_button_func)
  2919. snd_soc_jack_report(rt5645->btn_jack,
  2920. report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  2921. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  2922. }
  2923. static void rt5645_rcclock_work(struct work_struct *work)
  2924. {
  2925. struct rt5645_priv *rt5645 =
  2926. container_of(work, struct rt5645_priv, rcclock_work.work);
  2927. regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
  2928. RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
  2929. }
  2930. static irqreturn_t rt5645_irq(int irq, void *data)
  2931. {
  2932. struct rt5645_priv *rt5645 = data;
  2933. queue_delayed_work(system_power_efficient_wq,
  2934. &rt5645->jack_detect_work, msecs_to_jiffies(250));
  2935. return IRQ_HANDLED;
  2936. }
  2937. static void rt5645_btn_check_callback(struct timer_list *t)
  2938. {
  2939. struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
  2940. queue_delayed_work(system_power_efficient_wq,
  2941. &rt5645->jack_detect_work, msecs_to_jiffies(5));
  2942. }
  2943. static int rt5645_probe(struct snd_soc_component *component)
  2944. {
  2945. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2946. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2947. rt5645->component = component;
  2948. switch (rt5645->codec_type) {
  2949. case CODEC_TYPE_RT5645:
  2950. snd_soc_dapm_new_controls(dapm,
  2951. rt5645_specific_dapm_widgets,
  2952. ARRAY_SIZE(rt5645_specific_dapm_widgets));
  2953. snd_soc_dapm_add_routes(dapm,
  2954. rt5645_specific_dapm_routes,
  2955. ARRAY_SIZE(rt5645_specific_dapm_routes));
  2956. if (rt5645->v_id < 3) {
  2957. snd_soc_dapm_add_routes(dapm,
  2958. rt5645_old_dapm_routes,
  2959. ARRAY_SIZE(rt5645_old_dapm_routes));
  2960. }
  2961. break;
  2962. case CODEC_TYPE_RT5650:
  2963. snd_soc_dapm_new_controls(dapm,
  2964. rt5650_specific_dapm_widgets,
  2965. ARRAY_SIZE(rt5650_specific_dapm_widgets));
  2966. snd_soc_dapm_add_routes(dapm,
  2967. rt5650_specific_dapm_routes,
  2968. ARRAY_SIZE(rt5650_specific_dapm_routes));
  2969. break;
  2970. }
  2971. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  2972. /* for JD function */
  2973. if (rt5645->pdata.jd_mode) {
  2974. snd_soc_dapm_force_enable_pin(dapm, "JD Power");
  2975. snd_soc_dapm_force_enable_pin(dapm, "LDO2");
  2976. snd_soc_dapm_sync(dapm);
  2977. }
  2978. if (rt5645->pdata.long_name)
  2979. component->card->long_name = rt5645->pdata.long_name;
  2980. rt5645->eq_param = devm_kcalloc(component->dev,
  2981. RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
  2982. GFP_KERNEL);
  2983. if (!rt5645->eq_param)
  2984. return -ENOMEM;
  2985. return 0;
  2986. }
  2987. static void rt5645_remove(struct snd_soc_component *component)
  2988. {
  2989. rt5645_reset(component);
  2990. }
  2991. #ifdef CONFIG_PM
  2992. static int rt5645_suspend(struct snd_soc_component *component)
  2993. {
  2994. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  2995. regcache_cache_only(rt5645->regmap, true);
  2996. regcache_mark_dirty(rt5645->regmap);
  2997. return 0;
  2998. }
  2999. static int rt5645_resume(struct snd_soc_component *component)
  3000. {
  3001. struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
  3002. regcache_cache_only(rt5645->regmap, false);
  3003. regcache_sync(rt5645->regmap);
  3004. return 0;
  3005. }
  3006. #else
  3007. #define rt5645_suspend NULL
  3008. #define rt5645_resume NULL
  3009. #endif
  3010. #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
  3011. #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  3012. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  3013. static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
  3014. .hw_params = rt5645_hw_params,
  3015. .set_fmt = rt5645_set_dai_fmt,
  3016. .set_sysclk = rt5645_set_dai_sysclk,
  3017. .set_tdm_slot = rt5645_set_tdm_slot,
  3018. .set_pll = rt5645_set_dai_pll,
  3019. };
  3020. static struct snd_soc_dai_driver rt5645_dai[] = {
  3021. {
  3022. .name = "rt5645-aif1",
  3023. .id = RT5645_AIF1,
  3024. .playback = {
  3025. .stream_name = "AIF1 Playback",
  3026. .channels_min = 1,
  3027. .channels_max = 2,
  3028. .rates = RT5645_STEREO_RATES,
  3029. .formats = RT5645_FORMATS,
  3030. },
  3031. .capture = {
  3032. .stream_name = "AIF1 Capture",
  3033. .channels_min = 1,
  3034. .channels_max = 4,
  3035. .rates = RT5645_STEREO_RATES,
  3036. .formats = RT5645_FORMATS,
  3037. },
  3038. .ops = &rt5645_aif_dai_ops,
  3039. },
  3040. {
  3041. .name = "rt5645-aif2",
  3042. .id = RT5645_AIF2,
  3043. .playback = {
  3044. .stream_name = "AIF2 Playback",
  3045. .channels_min = 1,
  3046. .channels_max = 2,
  3047. .rates = RT5645_STEREO_RATES,
  3048. .formats = RT5645_FORMATS,
  3049. },
  3050. .capture = {
  3051. .stream_name = "AIF2 Capture",
  3052. .channels_min = 1,
  3053. .channels_max = 2,
  3054. .rates = RT5645_STEREO_RATES,
  3055. .formats = RT5645_FORMATS,
  3056. },
  3057. .ops = &rt5645_aif_dai_ops,
  3058. },
  3059. };
  3060. static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
  3061. .probe = rt5645_probe,
  3062. .remove = rt5645_remove,
  3063. .suspend = rt5645_suspend,
  3064. .resume = rt5645_resume,
  3065. .set_bias_level = rt5645_set_bias_level,
  3066. .controls = rt5645_snd_controls,
  3067. .num_controls = ARRAY_SIZE(rt5645_snd_controls),
  3068. .dapm_widgets = rt5645_dapm_widgets,
  3069. .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
  3070. .dapm_routes = rt5645_dapm_routes,
  3071. .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
  3072. .use_pmdown_time = 1,
  3073. .endianness = 1,
  3074. .non_legacy_dai_naming = 1,
  3075. };
  3076. static const struct regmap_config rt5645_regmap = {
  3077. .reg_bits = 8,
  3078. .val_bits = 16,
  3079. .use_single_read = true,
  3080. .use_single_write = true,
  3081. .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
  3082. RT5645_PR_SPACING),
  3083. .volatile_reg = rt5645_volatile_register,
  3084. .readable_reg = rt5645_readable_register,
  3085. .cache_type = REGCACHE_RBTREE,
  3086. .reg_defaults = rt5645_reg,
  3087. .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
  3088. .ranges = rt5645_ranges,
  3089. .num_ranges = ARRAY_SIZE(rt5645_ranges),
  3090. };
  3091. static const struct regmap_config rt5650_regmap = {
  3092. .reg_bits = 8,
  3093. .val_bits = 16,
  3094. .use_single_read = true,
  3095. .use_single_write = true,
  3096. .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
  3097. RT5645_PR_SPACING),
  3098. .volatile_reg = rt5645_volatile_register,
  3099. .readable_reg = rt5645_readable_register,
  3100. .cache_type = REGCACHE_RBTREE,
  3101. .reg_defaults = rt5650_reg,
  3102. .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
  3103. .ranges = rt5645_ranges,
  3104. .num_ranges = ARRAY_SIZE(rt5645_ranges),
  3105. };
  3106. static const struct regmap_config temp_regmap = {
  3107. .name="nocache",
  3108. .reg_bits = 8,
  3109. .val_bits = 16,
  3110. .use_single_read = true,
  3111. .use_single_write = true,
  3112. .max_register = RT5645_VENDOR_ID2 + 1,
  3113. .cache_type = REGCACHE_NONE,
  3114. };
  3115. static const struct i2c_device_id rt5645_i2c_id[] = {
  3116. { "rt5645", 0 },
  3117. { "rt5650", 0 },
  3118. { }
  3119. };
  3120. MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
  3121. #ifdef CONFIG_OF
  3122. static const struct of_device_id rt5645_of_match[] = {
  3123. { .compatible = "realtek,rt5645", },
  3124. { .compatible = "realtek,rt5650", },
  3125. { }
  3126. };
  3127. MODULE_DEVICE_TABLE(of, rt5645_of_match);
  3128. #endif
  3129. #ifdef CONFIG_ACPI
  3130. static const struct acpi_device_id rt5645_acpi_match[] = {
  3131. { "10EC5645", 0 },
  3132. { "10EC5648", 0 },
  3133. { "10EC5650", 0 },
  3134. { "10EC5640", 0 },
  3135. { "10EC3270", 0 },
  3136. {},
  3137. };
  3138. MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
  3139. #endif
  3140. static const struct rt5645_platform_data intel_braswell_platform_data = {
  3141. .dmic1_data_pin = RT5645_DMIC1_DISABLE,
  3142. .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
  3143. .jd_mode = 3,
  3144. };
  3145. static const struct rt5645_platform_data buddy_platform_data = {
  3146. .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
  3147. .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
  3148. .jd_mode = 4,
  3149. .level_trigger_irq = true,
  3150. };
  3151. static const struct rt5645_platform_data gpd_win_platform_data = {
  3152. .jd_mode = 3,
  3153. .inv_jd1_1 = true,
  3154. .long_name = "gpd-win-pocket-rt5645",
  3155. /* The GPD pocket has a diff. mic, for the win this does not matter. */
  3156. .in2_diff = true,
  3157. };
  3158. static const struct rt5645_platform_data asus_t100ha_platform_data = {
  3159. .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
  3160. .dmic2_data_pin = RT5645_DMIC2_DISABLE,
  3161. .jd_mode = 3,
  3162. .inv_jd1_1 = true,
  3163. };
  3164. static const struct rt5645_platform_data asus_t101ha_platform_data = {
  3165. .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
  3166. .dmic2_data_pin = RT5645_DMIC2_DISABLE,
  3167. .jd_mode = 3,
  3168. };
  3169. static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
  3170. .jd_mode = 3,
  3171. .in2_diff = true,
  3172. };
  3173. static const struct rt5645_platform_data jd_mode3_platform_data = {
  3174. .jd_mode = 3,
  3175. };
  3176. static const struct rt5645_platform_data lattepanda_board_platform_data = {
  3177. .jd_mode = 2,
  3178. .inv_jd1_1 = true
  3179. };
  3180. static const struct rt5645_platform_data kahlee_platform_data = {
  3181. .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
  3182. .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
  3183. .jd_mode = 3,
  3184. };
  3185. static const struct dmi_system_id dmi_platform_data[] = {
  3186. {
  3187. .ident = "Chrome Buddy",
  3188. .matches = {
  3189. DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
  3190. },
  3191. .driver_data = (void *)&buddy_platform_data,
  3192. },
  3193. {
  3194. .ident = "Intel Strago",
  3195. .matches = {
  3196. DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
  3197. },
  3198. .driver_data = (void *)&intel_braswell_platform_data,
  3199. },
  3200. {
  3201. .ident = "Google Chrome",
  3202. .matches = {
  3203. DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
  3204. },
  3205. .driver_data = (void *)&intel_braswell_platform_data,
  3206. },
  3207. {
  3208. .ident = "Google Setzer",
  3209. .matches = {
  3210. DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
  3211. },
  3212. .driver_data = (void *)&intel_braswell_platform_data,
  3213. },
  3214. {
  3215. .ident = "Microsoft Surface 3",
  3216. .matches = {
  3217. DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
  3218. },
  3219. .driver_data = (void *)&intel_braswell_platform_data,
  3220. },
  3221. {
  3222. /*
  3223. * Match for the GPDwin which unfortunately uses somewhat
  3224. * generic dmi strings, which is why we test for 4 strings.
  3225. * Comparing against 23 other byt/cht boards, board_vendor
  3226. * and board_name are unique to the GPDwin, where as only one
  3227. * other board has the same board_serial and 3 others have
  3228. * the same default product_name. Also the GPDwin is the
  3229. * only device to have both board_ and product_name not set.
  3230. */
  3231. .ident = "GPD Win / Pocket",
  3232. .matches = {
  3233. DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
  3234. DMI_MATCH(DMI_BOARD_NAME, "Default string"),
  3235. DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
  3236. DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
  3237. },
  3238. .driver_data = (void *)&gpd_win_platform_data,
  3239. },
  3240. {
  3241. .ident = "ASUS T100HAN",
  3242. .matches = {
  3243. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  3244. DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
  3245. },
  3246. .driver_data = (void *)&asus_t100ha_platform_data,
  3247. },
  3248. {
  3249. .ident = "ASUS T101HA",
  3250. .matches = {
  3251. DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  3252. DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
  3253. },
  3254. .driver_data = (void *)&asus_t101ha_platform_data,
  3255. },
  3256. {
  3257. .ident = "MINIX Z83-4",
  3258. .matches = {
  3259. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
  3260. DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
  3261. },
  3262. .driver_data = (void *)&jd_mode3_platform_data,
  3263. },
  3264. {
  3265. .ident = "Teclast X80 Pro",
  3266. .matches = {
  3267. DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
  3268. DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
  3269. },
  3270. .driver_data = (void *)&jd_mode3_platform_data,
  3271. },
  3272. {
  3273. .ident = "Lenovo Ideapad Miix 310",
  3274. .matches = {
  3275. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  3276. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
  3277. DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
  3278. },
  3279. .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
  3280. },
  3281. {
  3282. .ident = "Lenovo Ideapad Miix 320",
  3283. .matches = {
  3284. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  3285. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
  3286. DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
  3287. },
  3288. .driver_data = (void *)&intel_braswell_platform_data,
  3289. },
  3290. {
  3291. .ident = "LattePanda board",
  3292. .matches = {
  3293. DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
  3294. DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
  3295. DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
  3296. },
  3297. .driver_data = (void *)&lattepanda_board_platform_data,
  3298. },
  3299. {
  3300. .ident = "Chrome Kahlee",
  3301. .matches = {
  3302. DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
  3303. },
  3304. .driver_data = (void *)&kahlee_platform_data,
  3305. },
  3306. {
  3307. .ident = "Medion E1239T",
  3308. .matches = {
  3309. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
  3310. DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
  3311. },
  3312. .driver_data = (void *)&intel_braswell_platform_data,
  3313. },
  3314. { }
  3315. };
  3316. static bool rt5645_check_dp(struct device *dev)
  3317. {
  3318. if (device_property_present(dev, "realtek,in2-differential") ||
  3319. device_property_present(dev, "realtek,dmic1-data-pin") ||
  3320. device_property_present(dev, "realtek,dmic2-data-pin") ||
  3321. device_property_present(dev, "realtek,jd-mode"))
  3322. return true;
  3323. return false;
  3324. }
  3325. static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
  3326. {
  3327. rt5645->pdata.in2_diff = device_property_read_bool(dev,
  3328. "realtek,in2-differential");
  3329. device_property_read_u32(dev,
  3330. "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
  3331. device_property_read_u32(dev,
  3332. "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
  3333. device_property_read_u32(dev,
  3334. "realtek,jd-mode", &rt5645->pdata.jd_mode);
  3335. return 0;
  3336. }
  3337. static int rt5645_i2c_probe(struct i2c_client *i2c,
  3338. const struct i2c_device_id *id)
  3339. {
  3340. struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
  3341. const struct dmi_system_id *dmi_data;
  3342. struct rt5645_priv *rt5645;
  3343. int ret, i;
  3344. unsigned int val;
  3345. struct regmap *regmap;
  3346. rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
  3347. GFP_KERNEL);
  3348. if (rt5645 == NULL)
  3349. return -ENOMEM;
  3350. rt5645->i2c = i2c;
  3351. i2c_set_clientdata(i2c, rt5645);
  3352. dmi_data = dmi_first_match(dmi_platform_data);
  3353. if (dmi_data) {
  3354. dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
  3355. pdata = dmi_data->driver_data;
  3356. }
  3357. if (pdata)
  3358. rt5645->pdata = *pdata;
  3359. else if (rt5645_check_dp(&i2c->dev))
  3360. rt5645_parse_dt(rt5645, &i2c->dev);
  3361. else
  3362. rt5645->pdata = jd_mode3_platform_data;
  3363. if (quirk != -1) {
  3364. rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
  3365. rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
  3366. rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
  3367. rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
  3368. rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
  3369. rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
  3370. }
  3371. rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
  3372. GPIOD_IN);
  3373. if (IS_ERR(rt5645->gpiod_hp_det)) {
  3374. dev_info(&i2c->dev, "failed to initialize gpiod\n");
  3375. ret = PTR_ERR(rt5645->gpiod_hp_det);
  3376. /*
  3377. * Continue if optional gpiod is missing, bail for all other
  3378. * errors, including -EPROBE_DEFER
  3379. */
  3380. if (ret != -ENOENT)
  3381. return ret;
  3382. }
  3383. for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
  3384. rt5645->supplies[i].supply = rt5645_supply_names[i];
  3385. ret = devm_regulator_bulk_get(&i2c->dev,
  3386. ARRAY_SIZE(rt5645->supplies),
  3387. rt5645->supplies);
  3388. if (ret) {
  3389. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  3390. return ret;
  3391. }
  3392. ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
  3393. rt5645->supplies);
  3394. if (ret) {
  3395. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  3396. return ret;
  3397. }
  3398. regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
  3399. if (IS_ERR(regmap)) {
  3400. ret = PTR_ERR(regmap);
  3401. dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
  3402. ret);
  3403. return ret;
  3404. }
  3405. /*
  3406. * Read after 400msec, as it is the interval required between
  3407. * read and power On.
  3408. */
  3409. msleep(TIME_TO_POWER_MS);
  3410. regmap_read(regmap, RT5645_VENDOR_ID2, &val);
  3411. switch (val) {
  3412. case RT5645_DEVICE_ID:
  3413. rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
  3414. rt5645->codec_type = CODEC_TYPE_RT5645;
  3415. break;
  3416. case RT5650_DEVICE_ID:
  3417. rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
  3418. rt5645->codec_type = CODEC_TYPE_RT5650;
  3419. break;
  3420. default:
  3421. dev_err(&i2c->dev,
  3422. "Device with ID register %#x is not rt5645 or rt5650\n",
  3423. val);
  3424. ret = -ENODEV;
  3425. goto err_enable;
  3426. }
  3427. if (IS_ERR(rt5645->regmap)) {
  3428. ret = PTR_ERR(rt5645->regmap);
  3429. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  3430. ret);
  3431. return ret;
  3432. }
  3433. regmap_write(rt5645->regmap, RT5645_RESET, 0);
  3434. regmap_read(regmap, RT5645_VENDOR_ID, &val);
  3435. rt5645->v_id = val & 0xff;
  3436. regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
  3437. ret = regmap_register_patch(rt5645->regmap, init_list,
  3438. ARRAY_SIZE(init_list));
  3439. if (ret != 0)
  3440. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  3441. if (rt5645->codec_type == CODEC_TYPE_RT5650) {
  3442. ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
  3443. ARRAY_SIZE(rt5650_init_list));
  3444. if (ret != 0)
  3445. dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
  3446. ret);
  3447. }
  3448. regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
  3449. if (rt5645->pdata.in2_diff)
  3450. regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
  3451. RT5645_IN_DF2, RT5645_IN_DF2);
  3452. if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
  3453. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3454. RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
  3455. }
  3456. switch (rt5645->pdata.dmic1_data_pin) {
  3457. case RT5645_DMIC_DATA_IN2N:
  3458. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3459. RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
  3460. break;
  3461. case RT5645_DMIC_DATA_GPIO5:
  3462. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3463. RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
  3464. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3465. RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
  3466. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3467. RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
  3468. break;
  3469. case RT5645_DMIC_DATA_GPIO11:
  3470. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3471. RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
  3472. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3473. RT5645_GP11_PIN_MASK,
  3474. RT5645_GP11_PIN_DMIC1_SDA);
  3475. break;
  3476. default:
  3477. break;
  3478. }
  3479. switch (rt5645->pdata.dmic2_data_pin) {
  3480. case RT5645_DMIC_DATA_IN2P:
  3481. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3482. RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
  3483. break;
  3484. case RT5645_DMIC_DATA_GPIO6:
  3485. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3486. RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
  3487. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3488. RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
  3489. break;
  3490. case RT5645_DMIC_DATA_GPIO10:
  3491. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3492. RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
  3493. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3494. RT5645_GP10_PIN_MASK,
  3495. RT5645_GP10_PIN_DMIC2_SDA);
  3496. break;
  3497. case RT5645_DMIC_DATA_GPIO12:
  3498. regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
  3499. RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
  3500. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3501. RT5645_GP12_PIN_MASK,
  3502. RT5645_GP12_PIN_DMIC2_SDA);
  3503. break;
  3504. default:
  3505. break;
  3506. }
  3507. if (rt5645->pdata.jd_mode) {
  3508. regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
  3509. RT5645_IRQ_CLK_GATE_CTRL,
  3510. RT5645_IRQ_CLK_GATE_CTRL);
  3511. regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
  3512. RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
  3513. regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
  3514. RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
  3515. regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
  3516. RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
  3517. regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
  3518. RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
  3519. regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
  3520. RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
  3521. regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
  3522. RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
  3523. switch (rt5645->pdata.jd_mode) {
  3524. case 1:
  3525. regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
  3526. RT5645_JD1_MODE_MASK,
  3527. RT5645_JD1_MODE_0);
  3528. break;
  3529. case 2:
  3530. regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
  3531. RT5645_JD1_MODE_MASK,
  3532. RT5645_JD1_MODE_1);
  3533. break;
  3534. case 3:
  3535. case 4:
  3536. regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
  3537. RT5645_JD1_MODE_MASK,
  3538. RT5645_JD1_MODE_2);
  3539. break;
  3540. default:
  3541. break;
  3542. }
  3543. if (rt5645->pdata.inv_jd1_1) {
  3544. regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
  3545. RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
  3546. }
  3547. }
  3548. regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
  3549. RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
  3550. if (rt5645->pdata.level_trigger_irq) {
  3551. regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
  3552. RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
  3553. }
  3554. timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
  3555. INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
  3556. INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
  3557. if (rt5645->i2c->irq) {
  3558. ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
  3559. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  3560. | IRQF_ONESHOT, "rt5645", rt5645);
  3561. if (ret) {
  3562. dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
  3563. goto err_enable;
  3564. }
  3565. }
  3566. ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
  3567. rt5645_dai, ARRAY_SIZE(rt5645_dai));
  3568. if (ret)
  3569. goto err_irq;
  3570. return 0;
  3571. err_irq:
  3572. if (rt5645->i2c->irq)
  3573. free_irq(rt5645->i2c->irq, rt5645);
  3574. err_enable:
  3575. regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
  3576. return ret;
  3577. }
  3578. static int rt5645_i2c_remove(struct i2c_client *i2c)
  3579. {
  3580. struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
  3581. if (i2c->irq)
  3582. free_irq(i2c->irq, rt5645);
  3583. cancel_delayed_work_sync(&rt5645->jack_detect_work);
  3584. cancel_delayed_work_sync(&rt5645->rcclock_work);
  3585. del_timer_sync(&rt5645->btn_check_timer);
  3586. regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
  3587. return 0;
  3588. }
  3589. static void rt5645_i2c_shutdown(struct i2c_client *i2c)
  3590. {
  3591. struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
  3592. regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
  3593. RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
  3594. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
  3595. RT5645_CBJ_MN_JD);
  3596. regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
  3597. 0);
  3598. msleep(20);
  3599. regmap_write(rt5645->regmap, RT5645_RESET, 0);
  3600. }
  3601. static struct i2c_driver rt5645_i2c_driver = {
  3602. .driver = {
  3603. .name = "rt5645",
  3604. .of_match_table = of_match_ptr(rt5645_of_match),
  3605. .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
  3606. },
  3607. .probe = rt5645_i2c_probe,
  3608. .remove = rt5645_i2c_remove,
  3609. .shutdown = rt5645_i2c_shutdown,
  3610. .id_table = rt5645_i2c_id,
  3611. };
  3612. module_i2c_driver(rt5645_i2c_driver);
  3613. MODULE_DESCRIPTION("ASoC RT5645 driver");
  3614. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  3615. MODULE_LICENSE("GPL v2");