rt274.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt274.c -- RT274 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2017 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <bardliao@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/dmi.h>
  17. #include <linux/acpi.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <sound/jack.h>
  26. #include <linux/workqueue.h>
  27. #include "rl6347a.h"
  28. #include "rt274.h"
  29. #define RT274_VENDOR_ID 0x10ec0274
  30. struct rt274_priv {
  31. struct reg_default *index_cache;
  32. int index_cache_size;
  33. struct regmap *regmap;
  34. struct snd_soc_component *component;
  35. struct i2c_client *i2c;
  36. struct snd_soc_jack *jack;
  37. struct delayed_work jack_detect_work;
  38. int sys_clk;
  39. int clk_id;
  40. int fs;
  41. bool master;
  42. };
  43. static const struct reg_default rt274_index_def[] = {
  44. { 0x00, 0x1004 },
  45. { 0x01, 0xaaaa },
  46. { 0x02, 0x88aa },
  47. { 0x03, 0x0002 },
  48. { 0x04, 0xaa09 },
  49. { 0x05, 0x0700 },
  50. { 0x06, 0x6110 },
  51. { 0x07, 0x0200 },
  52. { 0x08, 0xa807 },
  53. { 0x09, 0x0021 },
  54. { 0x0a, 0x7770 },
  55. { 0x0b, 0x7770 },
  56. { 0x0c, 0x002b },
  57. { 0x0d, 0x2420 },
  58. { 0x0e, 0x65c0 },
  59. { 0x0f, 0x7770 },
  60. { 0x10, 0x0420 },
  61. { 0x11, 0x7418 },
  62. { 0x12, 0x6bd0 },
  63. { 0x13, 0x645f },
  64. { 0x14, 0x0400 },
  65. { 0x15, 0x8ccc },
  66. { 0x16, 0x4c50 },
  67. { 0x17, 0xff00 },
  68. { 0x18, 0x0003 },
  69. { 0x19, 0x2c11 },
  70. { 0x1a, 0x830b },
  71. { 0x1b, 0x4e4b },
  72. { 0x1c, 0x0000 },
  73. { 0x1d, 0x0000 },
  74. { 0x1e, 0x0000 },
  75. { 0x1f, 0x0000 },
  76. { 0x20, 0x51ff },
  77. { 0x21, 0x8000 },
  78. { 0x22, 0x8f00 },
  79. { 0x23, 0x88f4 },
  80. { 0x24, 0x0000 },
  81. { 0x25, 0x0000 },
  82. { 0x26, 0x0000 },
  83. { 0x27, 0x0000 },
  84. { 0x28, 0x0000 },
  85. { 0x29, 0x3000 },
  86. { 0x2a, 0x0000 },
  87. { 0x2b, 0x0000 },
  88. { 0x2c, 0x0f00 },
  89. { 0x2d, 0x100f },
  90. { 0x2e, 0x2902 },
  91. { 0x2f, 0xe280 },
  92. { 0x30, 0x1000 },
  93. { 0x31, 0x8400 },
  94. { 0x32, 0x5aaa },
  95. { 0x33, 0x8420 },
  96. { 0x34, 0xa20c },
  97. { 0x35, 0x096a },
  98. { 0x36, 0x5757 },
  99. { 0x37, 0xfe05 },
  100. { 0x38, 0x4901 },
  101. { 0x39, 0x110a },
  102. { 0x3a, 0x0010 },
  103. { 0x3b, 0x60d9 },
  104. { 0x3c, 0xf214 },
  105. { 0x3d, 0xc2ba },
  106. { 0x3e, 0xa928 },
  107. { 0x3f, 0x0000 },
  108. { 0x40, 0x9800 },
  109. { 0x41, 0x0000 },
  110. { 0x42, 0x2000 },
  111. { 0x43, 0x3d90 },
  112. { 0x44, 0x4900 },
  113. { 0x45, 0x5289 },
  114. { 0x46, 0x0004 },
  115. { 0x47, 0xa47a },
  116. { 0x48, 0xd049 },
  117. { 0x49, 0x0049 },
  118. { 0x4a, 0xa83b },
  119. { 0x4b, 0x0777 },
  120. { 0x4c, 0x065c },
  121. { 0x4d, 0x7fff },
  122. { 0x4e, 0x7fff },
  123. { 0x4f, 0x0000 },
  124. { 0x50, 0x0000 },
  125. { 0x51, 0x0000 },
  126. { 0x52, 0xbf5f },
  127. { 0x53, 0x3320 },
  128. { 0x54, 0xcc00 },
  129. { 0x55, 0x0000 },
  130. { 0x56, 0x3f00 },
  131. { 0x57, 0x0000 },
  132. { 0x58, 0x0000 },
  133. { 0x59, 0x0000 },
  134. { 0x5a, 0x1300 },
  135. { 0x5b, 0x005f },
  136. { 0x5c, 0x0000 },
  137. { 0x5d, 0x1001 },
  138. { 0x5e, 0x1000 },
  139. { 0x5f, 0x0000 },
  140. { 0x60, 0x5554 },
  141. { 0x61, 0xffc0 },
  142. { 0x62, 0xa000 },
  143. { 0x63, 0xd010 },
  144. { 0x64, 0x0000 },
  145. { 0x65, 0x3fb1 },
  146. { 0x66, 0x1881 },
  147. { 0x67, 0xc810 },
  148. { 0x68, 0x2000 },
  149. { 0x69, 0xfff0 },
  150. { 0x6a, 0x0300 },
  151. { 0x6b, 0x5060 },
  152. { 0x6c, 0x0000 },
  153. { 0x6d, 0x0000 },
  154. { 0x6e, 0x0c25 },
  155. { 0x6f, 0x0c0b },
  156. { 0x70, 0x8000 },
  157. { 0x71, 0x4008 },
  158. { 0x72, 0x0000 },
  159. { 0x73, 0x0800 },
  160. { 0x74, 0xa28f },
  161. { 0x75, 0xa050 },
  162. { 0x76, 0x7fe8 },
  163. { 0x77, 0xdb8c },
  164. { 0x78, 0x0000 },
  165. { 0x79, 0x0000 },
  166. { 0x7a, 0x2a96 },
  167. { 0x7b, 0x800f },
  168. { 0x7c, 0x0200 },
  169. { 0x7d, 0x1600 },
  170. { 0x7e, 0x0000 },
  171. { 0x7f, 0x0000 },
  172. };
  173. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def)
  174. static const struct reg_default rt274_reg[] = {
  175. { 0x00170500, 0x00000400 },
  176. { 0x00220000, 0x00000031 },
  177. { 0x00239000, 0x00000057 },
  178. { 0x0023a000, 0x00000057 },
  179. { 0x00270500, 0x00000400 },
  180. { 0x00370500, 0x00000400 },
  181. { 0x00870500, 0x00000400 },
  182. { 0x00920000, 0x00000031 },
  183. { 0x00935000, 0x00000097 },
  184. { 0x00936000, 0x00000097 },
  185. { 0x00970500, 0x00000400 },
  186. { 0x00b37000, 0x00000400 },
  187. { 0x00b37200, 0x00000400 },
  188. { 0x00b37300, 0x00000400 },
  189. { 0x00c37000, 0x00000400 },
  190. { 0x00c37100, 0x00000400 },
  191. { 0x01270500, 0x00000400 },
  192. { 0x01370500, 0x00000400 },
  193. { 0x01371f00, 0x411111f0 },
  194. { 0x01937000, 0x00000000 },
  195. { 0x01970500, 0x00000400 },
  196. { 0x02050000, 0x0000001b },
  197. { 0x02139000, 0x00000080 },
  198. { 0x0213a000, 0x00000080 },
  199. { 0x02170100, 0x00000001 },
  200. { 0x02170500, 0x00000400 },
  201. { 0x02170700, 0x00000000 },
  202. { 0x02270100, 0x00000000 },
  203. { 0x02370100, 0x00000000 },
  204. { 0x01970700, 0x00000020 },
  205. { 0x00830000, 0x00000097 },
  206. { 0x00930000, 0x00000097 },
  207. { 0x01270700, 0x00000000 },
  208. };
  209. static bool rt274_volatile_register(struct device *dev, unsigned int reg)
  210. {
  211. switch (reg) {
  212. case 0 ... 0xff:
  213. case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  214. case RT274_GET_HP_SENSE:
  215. case RT274_GET_MIC_SENSE:
  216. case RT274_PROC_COEF:
  217. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
  218. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
  219. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
  220. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
  221. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
  222. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
  223. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
  224. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
  225. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
  226. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
  227. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
  228. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
  229. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
  230. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
  231. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
  232. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
  233. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
  234. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
  235. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
  236. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
  237. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
  238. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
  239. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
  240. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
  241. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
  242. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
  243. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
  244. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
  245. return true;
  246. default:
  247. return false;
  248. }
  249. }
  250. static bool rt274_readable_register(struct device *dev, unsigned int reg)
  251. {
  252. switch (reg) {
  253. case 0 ... 0xff:
  254. case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  255. case RT274_GET_HP_SENSE:
  256. case RT274_GET_MIC_SENSE:
  257. case RT274_SET_AUDIO_POWER:
  258. case RT274_SET_HPO_POWER:
  259. case RT274_SET_DMIC1_POWER:
  260. case RT274_LOUT_MUX:
  261. case RT274_HPO_MUX:
  262. case RT274_ADC0_MUX:
  263. case RT274_ADC1_MUX:
  264. case RT274_SET_MIC:
  265. case RT274_SET_PIN_HPO:
  266. case RT274_SET_PIN_LOUT3:
  267. case RT274_SET_PIN_DMIC1:
  268. case RT274_SET_AMP_GAIN_HPO:
  269. case RT274_SET_DMIC2_DEFAULT:
  270. case RT274_DAC0L_GAIN:
  271. case RT274_DAC0R_GAIN:
  272. case RT274_DAC1L_GAIN:
  273. case RT274_DAC1R_GAIN:
  274. case RT274_ADCL_GAIN:
  275. case RT274_ADCR_GAIN:
  276. case RT274_MIC_GAIN:
  277. case RT274_HPOL_GAIN:
  278. case RT274_HPOR_GAIN:
  279. case RT274_LOUTL_GAIN:
  280. case RT274_LOUTR_GAIN:
  281. case RT274_DAC_FORMAT:
  282. case RT274_ADC_FORMAT:
  283. case RT274_COEF_INDEX:
  284. case RT274_PROC_COEF:
  285. case RT274_SET_AMP_GAIN_ADC_IN1:
  286. case RT274_SET_AMP_GAIN_ADC_IN2:
  287. case RT274_SET_POWER(RT274_DAC_OUT0):
  288. case RT274_SET_POWER(RT274_DAC_OUT1):
  289. case RT274_SET_POWER(RT274_ADC_IN1):
  290. case RT274_SET_POWER(RT274_ADC_IN2):
  291. case RT274_SET_POWER(RT274_DMIC2):
  292. case RT274_SET_POWER(RT274_MIC):
  293. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
  294. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
  295. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
  296. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
  297. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
  298. case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
  299. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
  300. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
  301. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
  302. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
  303. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
  304. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
  305. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
  306. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
  307. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
  308. case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
  309. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
  310. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
  311. case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
  312. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
  313. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
  314. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
  315. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
  316. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
  317. case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
  318. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
  319. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
  320. case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
  321. return true;
  322. default:
  323. return false;
  324. }
  325. }
  326. #ifdef CONFIG_PM
  327. static void rt274_index_sync(struct snd_soc_component *component)
  328. {
  329. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  330. int i;
  331. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  332. snd_soc_component_write(component, rt274->index_cache[i].reg,
  333. rt274->index_cache[i].def);
  334. }
  335. }
  336. #endif
  337. static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic)
  338. {
  339. unsigned int buf;
  340. int ret;
  341. *hp = false;
  342. *mic = false;
  343. if (!rt274->component)
  344. return -EINVAL;
  345. ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf);
  346. if (ret)
  347. return ret;
  348. *hp = buf & 0x80000000;
  349. ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf);
  350. if (ret)
  351. return ret;
  352. *mic = buf & 0x80000000;
  353. pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
  354. return 0;
  355. }
  356. static void rt274_jack_detect_work(struct work_struct *work)
  357. {
  358. struct rt274_priv *rt274 =
  359. container_of(work, struct rt274_priv, jack_detect_work.work);
  360. int status = 0;
  361. bool hp = false;
  362. bool mic = false;
  363. if (rt274_jack_detect(rt274, &hp, &mic) < 0)
  364. return;
  365. if (hp)
  366. status |= SND_JACK_HEADPHONE;
  367. if (mic)
  368. status |= SND_JACK_MICROPHONE;
  369. snd_soc_jack_report(rt274->jack, status,
  370. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  371. }
  372. static irqreturn_t rt274_irq(int irq, void *data);
  373. static int rt274_mic_detect(struct snd_soc_component *component,
  374. struct snd_soc_jack *jack, void *data)
  375. {
  376. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  377. rt274->jack = jack;
  378. if (jack == NULL) {
  379. /* Disable jack detection */
  380. regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
  381. RT274_IRQ_EN, RT274_IRQ_DIS);
  382. return 0;
  383. }
  384. regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
  385. RT274_IRQ_EN, RT274_IRQ_EN);
  386. /* Send an initial report */
  387. rt274_irq(0, rt274);
  388. return 0;
  389. }
  390. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  391. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  392. static const struct snd_kcontrol_new rt274_snd_controls[] = {
  393. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN,
  394. RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv),
  395. SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN,
  396. RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv),
  397. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN,
  398. RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  399. SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN,
  400. RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1),
  401. SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN,
  402. 0, 0x3, 0, mic_vol_tlv),
  403. };
  404. static const struct snd_kcontrol_new hpol_enable_control =
  405. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN,
  406. RT274_MUTE_SFT, 1, 1);
  407. static const struct snd_kcontrol_new hpor_enable_control =
  408. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN,
  409. RT274_MUTE_SFT, 1, 1);
  410. static const struct snd_kcontrol_new loutl_enable_control =
  411. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN,
  412. RT274_MUTE_SFT, 1, 1);
  413. static const struct snd_kcontrol_new loutr_enable_control =
  414. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN,
  415. RT274_MUTE_SFT, 1, 1);
  416. /* ADC0 source */
  417. static const char * const rt274_adc_src[] = {
  418. "Mic", "Line1", "Line2", "Dmic"
  419. };
  420. static SOC_ENUM_SINGLE_DECL(
  421. rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT,
  422. rt274_adc_src);
  423. static const struct snd_kcontrol_new rt274_adc0_mux =
  424. SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum);
  425. static SOC_ENUM_SINGLE_DECL(
  426. rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT,
  427. rt274_adc_src);
  428. static const struct snd_kcontrol_new rt274_adc1_mux =
  429. SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum);
  430. static const char * const rt274_dac_src[] = {
  431. "DAC OUT0", "DAC OUT1"
  432. };
  433. /* HP-OUT source */
  434. static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX,
  435. 0, rt274_dac_src);
  436. static const struct snd_kcontrol_new rt274_hpo_mux =
  437. SOC_DAPM_ENUM("HPO source", rt274_hpo_enum);
  438. /* Line out source */
  439. static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX,
  440. 0, rt274_dac_src);
  441. static const struct snd_kcontrol_new rt274_lout_mux =
  442. SOC_DAPM_ENUM("LOUT source", rt274_lout_enum);
  443. static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = {
  444. /* Input Lines */
  445. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  446. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  447. SND_SOC_DAPM_INPUT("MIC"),
  448. SND_SOC_DAPM_INPUT("LINE1"),
  449. SND_SOC_DAPM_INPUT("LINE2"),
  450. /* DMIC */
  451. SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  452. SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  453. /* ADCs */
  454. SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0),
  455. SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0),
  456. /* ADC Mux */
  457. SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0,
  458. &rt274_adc0_mux),
  459. SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0,
  460. &rt274_adc1_mux),
  461. /* Audio Interface */
  462. SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  463. SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0),
  464. SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  465. SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0),
  466. SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0),
  467. SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0),
  468. SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0),
  469. SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0),
  470. /* Output Side */
  471. /* DACs */
  472. SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0),
  473. SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0),
  474. /* Output Mux */
  475. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux),
  476. SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux),
  477. SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO,
  478. RT274_SET_PIN_SFT, 0, NULL, 0),
  479. SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3,
  480. RT274_SET_PIN_SFT, 0, NULL, 0),
  481. /* Output Mixer */
  482. SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0,
  483. NULL, 0),
  484. SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0,
  485. NULL, 0),
  486. /* Output Pga */
  487. SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0,
  488. &loutl_enable_control),
  489. SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0,
  490. &loutr_enable_control),
  491. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  492. &hpol_enable_control),
  493. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  494. &hpor_enable_control),
  495. /* Output Lines */
  496. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  497. SND_SOC_DAPM_OUTPUT("SPDIF"),
  498. SND_SOC_DAPM_OUTPUT("LINE3"),
  499. };
  500. static const struct snd_soc_dapm_route rt274_dapm_routes[] = {
  501. {"DMIC1", NULL, "DMIC1 Pin"},
  502. {"DMIC2", NULL, "DMIC2 Pin"},
  503. {"ADC 0 Mux", "Mic", "MIC"},
  504. {"ADC 0 Mux", "Dmic", "DMIC1"},
  505. {"ADC 0 Mux", "Line1", "LINE1"},
  506. {"ADC 0 Mux", "Line2", "LINE2"},
  507. {"ADC 1 Mux", "Mic", "MIC"},
  508. {"ADC 1 Mux", "Dmic", "DMIC2"},
  509. {"ADC 1 Mux", "Line1", "LINE1"},
  510. {"ADC 1 Mux", "Line2", "LINE2"},
  511. {"ADC 0", NULL, "ADC 0 Mux"},
  512. {"ADC 1", NULL, "ADC 1 Mux"},
  513. {"AIF1TXL", NULL, "ADC 0"},
  514. {"AIF1TXR", NULL, "ADC 0"},
  515. {"AIF2TXL", NULL, "ADC 1"},
  516. {"AIF2TXR", NULL, "ADC 1"},
  517. {"DAC 0", NULL, "AIF1RXL"},
  518. {"DAC 0", NULL, "AIF1RXR"},
  519. {"DAC 1", NULL, "AIF2RXL"},
  520. {"DAC 1", NULL, "AIF2RXR"},
  521. {"DAC OUT0", NULL, "DAC 0"},
  522. {"DAC OUT1", NULL, "DAC 1"},
  523. {"LOUT Mux", "DAC OUT0", "DAC OUT0"},
  524. {"LOUT Mux", "DAC OUT1", "DAC OUT1"},
  525. {"LOUT L", "Switch", "LOUT Mux"},
  526. {"LOUT R", "Switch", "LOUT Mux"},
  527. {"LOUT L", NULL, "LOUT Power"},
  528. {"LOUT R", NULL, "LOUT Power"},
  529. {"LINE3", NULL, "LOUT L"},
  530. {"LINE3", NULL, "LOUT R"},
  531. {"HPO Mux", "DAC OUT0", "DAC OUT0"},
  532. {"HPO Mux", "DAC OUT1", "DAC OUT1"},
  533. {"HPO L", "Switch", "HPO Mux"},
  534. {"HPO R", "Switch", "HPO Mux"},
  535. {"HPO L", NULL, "HP Power"},
  536. {"HPO R", NULL, "HP Power"},
  537. {"HPO Pin", NULL, "HPO L"},
  538. {"HPO Pin", NULL, "HPO R"},
  539. };
  540. static int rt274_hw_params(struct snd_pcm_substream *substream,
  541. struct snd_pcm_hw_params *params,
  542. struct snd_soc_dai *dai)
  543. {
  544. struct snd_soc_component *component = dai->component;
  545. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  546. unsigned int val = 0;
  547. int d_len_code = 0, c_len_code = 0;
  548. switch (params_rate(params)) {
  549. /* bit 14 0:48K 1:44.1K */
  550. case 44100:
  551. case 48000:
  552. break;
  553. default:
  554. dev_err(component->dev, "Unsupported sample rate %d\n",
  555. params_rate(params));
  556. return -EINVAL;
  557. }
  558. switch (rt274->sys_clk) {
  559. case 12288000:
  560. case 24576000:
  561. if (params_rate(params) != 48000) {
  562. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  563. params_rate(params), rt274->sys_clk);
  564. return -EINVAL;
  565. }
  566. break;
  567. case 11289600:
  568. case 22579200:
  569. if (params_rate(params) != 44100) {
  570. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  571. params_rate(params), rt274->sys_clk);
  572. return -EINVAL;
  573. }
  574. break;
  575. }
  576. if (params_channels(params) <= 16) {
  577. /* bit 3:0 Number of Channel */
  578. val |= (params_channels(params) - 1);
  579. } else {
  580. dev_err(component->dev, "Unsupported channels %d\n",
  581. params_channels(params));
  582. return -EINVAL;
  583. }
  584. switch (params_width(params)) {
  585. /* bit 6:4 Bits per Sample */
  586. case 16:
  587. d_len_code = 0;
  588. c_len_code = 0;
  589. val |= (0x1 << 4);
  590. break;
  591. case 32:
  592. d_len_code = 2;
  593. c_len_code = 3;
  594. val |= (0x4 << 4);
  595. break;
  596. case 20:
  597. d_len_code = 1;
  598. c_len_code = 1;
  599. val |= (0x2 << 4);
  600. break;
  601. case 24:
  602. d_len_code = 2;
  603. c_len_code = 2;
  604. val |= (0x3 << 4);
  605. break;
  606. case 8:
  607. d_len_code = 3;
  608. c_len_code = 0;
  609. break;
  610. default:
  611. return -EINVAL;
  612. }
  613. if (rt274->master)
  614. c_len_code = 0x3;
  615. snd_soc_component_update_bits(component,
  616. RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14);
  617. dev_dbg(component->dev, "format val = 0x%x\n", val);
  618. snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val);
  619. snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val);
  620. return 0;
  621. }
  622. static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  623. {
  624. struct snd_soc_component *component = dai->component;
  625. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  626. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  627. case SND_SOC_DAIFMT_CBM_CFM:
  628. snd_soc_component_update_bits(component,
  629. RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M);
  630. rt274->master = true;
  631. break;
  632. case SND_SOC_DAIFMT_CBS_CFS:
  633. snd_soc_component_update_bits(component,
  634. RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S);
  635. rt274->master = false;
  636. break;
  637. default:
  638. return -EINVAL;
  639. }
  640. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  641. case SND_SOC_DAIFMT_I2S:
  642. snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
  643. RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S);
  644. break;
  645. case SND_SOC_DAIFMT_LEFT_J:
  646. snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
  647. RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ);
  648. break;
  649. case SND_SOC_DAIFMT_DSP_A:
  650. snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
  651. RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA);
  652. break;
  653. case SND_SOC_DAIFMT_DSP_B:
  654. snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
  655. RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB);
  656. break;
  657. default:
  658. return -EINVAL;
  659. }
  660. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  661. snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0);
  662. snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0);
  663. return 0;
  664. }
  665. static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  666. unsigned int freq_in, unsigned int freq_out)
  667. {
  668. struct snd_soc_component *component = dai->component;
  669. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  670. switch (source) {
  671. case RT274_PLL2_S_MCLK:
  672. snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
  673. RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK);
  674. break;
  675. default:
  676. dev_warn(component->dev, "invalid pll source, use BCLK\n");
  677. fallthrough;
  678. case RT274_PLL2_S_BCLK:
  679. snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
  680. RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK);
  681. break;
  682. }
  683. if (source == RT274_PLL2_S_BCLK) {
  684. snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
  685. (0x3 << 12), (0x3 << 12));
  686. switch (rt274->fs) {
  687. case 50:
  688. snd_soc_component_write(component, 0x7a, 0xaab6);
  689. snd_soc_component_write(component, 0x7b, 0x0301);
  690. snd_soc_component_write(component, 0x7c, 0x04fe);
  691. break;
  692. case 64:
  693. snd_soc_component_write(component, 0x7a, 0xaa96);
  694. snd_soc_component_write(component, 0x7b, 0x8003);
  695. snd_soc_component_write(component, 0x7c, 0x081e);
  696. break;
  697. case 128:
  698. snd_soc_component_write(component, 0x7a, 0xaa96);
  699. snd_soc_component_write(component, 0x7b, 0x8003);
  700. snd_soc_component_write(component, 0x7c, 0x080e);
  701. break;
  702. default:
  703. dev_warn(component->dev, "invalid freq_in, assume 4.8M\n");
  704. fallthrough;
  705. case 100:
  706. snd_soc_component_write(component, 0x7a, 0xaab6);
  707. snd_soc_component_write(component, 0x7b, 0x0301);
  708. snd_soc_component_write(component, 0x7c, 0x047e);
  709. break;
  710. }
  711. }
  712. return 0;
  713. }
  714. static int rt274_set_dai_sysclk(struct snd_soc_dai *dai,
  715. int clk_id, unsigned int freq, int dir)
  716. {
  717. struct snd_soc_component *component = dai->component;
  718. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  719. unsigned int clk_src, mclk_en;
  720. dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
  721. switch (clk_id) {
  722. case RT274_SCLK_S_MCLK:
  723. mclk_en = RT274_MCLK_MODE_EN;
  724. clk_src = RT274_CLK_SRC_MCLK;
  725. break;
  726. case RT274_SCLK_S_PLL1:
  727. mclk_en = RT274_MCLK_MODE_DIS;
  728. clk_src = RT274_CLK_SRC_MCLK;
  729. break;
  730. case RT274_SCLK_S_PLL2:
  731. mclk_en = RT274_MCLK_MODE_EN;
  732. clk_src = RT274_CLK_SRC_PLL2;
  733. break;
  734. default:
  735. mclk_en = RT274_MCLK_MODE_DIS;
  736. clk_src = RT274_CLK_SRC_MCLK;
  737. dev_warn(component->dev, "invalid sysclk source, use PLL1\n");
  738. break;
  739. }
  740. snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
  741. RT274_MCLK_MODE_MASK, mclk_en);
  742. snd_soc_component_update_bits(component, RT274_CLK_CTRL,
  743. RT274_CLK_SRC_MASK, clk_src);
  744. switch (freq) {
  745. case 19200000:
  746. if (clk_id == RT274_SCLK_S_MCLK) {
  747. dev_err(component->dev, "Should not use MCLK\n");
  748. return -EINVAL;
  749. }
  750. snd_soc_component_update_bits(component,
  751. RT274_I2S_CTRL2, 0x40, 0x40);
  752. break;
  753. case 24000000:
  754. if (clk_id == RT274_SCLK_S_MCLK) {
  755. dev_err(component->dev, "Should not use MCLK\n");
  756. return -EINVAL;
  757. }
  758. snd_soc_component_update_bits(component,
  759. RT274_I2S_CTRL2, 0x40, 0x0);
  760. break;
  761. case 12288000:
  762. case 11289600:
  763. snd_soc_component_update_bits(component,
  764. RT274_MCLK_CTRL, 0x1fcf, 0x0008);
  765. break;
  766. case 24576000:
  767. case 22579200:
  768. snd_soc_component_update_bits(component,
  769. RT274_MCLK_CTRL, 0x1fcf, 0x1543);
  770. break;
  771. default:
  772. dev_err(component->dev, "Unsupported system clock\n");
  773. return -EINVAL;
  774. }
  775. rt274->sys_clk = freq;
  776. rt274->clk_id = clk_id;
  777. return 0;
  778. }
  779. static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  780. {
  781. struct snd_soc_component *component = dai->component;
  782. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  783. dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
  784. rt274->fs = ratio;
  785. if ((ratio / 50) == 0)
  786. snd_soc_component_update_bits(component,
  787. RT274_I2S_CTRL1, 0x1000, 0x1000);
  788. else
  789. snd_soc_component_update_bits(component,
  790. RT274_I2S_CTRL1, 0x1000, 0x0);
  791. return 0;
  792. }
  793. static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  794. unsigned int rx_mask, int slots, int slot_width)
  795. {
  796. struct snd_soc_component *component = dai->component;
  797. if (rx_mask || tx_mask) {
  798. snd_soc_component_update_bits(component,
  799. RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN);
  800. } else {
  801. snd_soc_component_update_bits(component,
  802. RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS);
  803. return 0;
  804. }
  805. switch (slots) {
  806. case 4:
  807. snd_soc_component_update_bits(component,
  808. RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH);
  809. break;
  810. case 2:
  811. snd_soc_component_update_bits(component,
  812. RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH);
  813. break;
  814. default:
  815. dev_err(component->dev,
  816. "Support 2 or 4 slots TDM only\n");
  817. return -EINVAL;
  818. }
  819. return 0;
  820. }
  821. static int rt274_set_bias_level(struct snd_soc_component *component,
  822. enum snd_soc_bias_level level)
  823. {
  824. switch (level) {
  825. case SND_SOC_BIAS_PREPARE:
  826. if (SND_SOC_BIAS_STANDBY ==
  827. snd_soc_component_get_bias_level(component)) {
  828. snd_soc_component_write(component,
  829. RT274_SET_AUDIO_POWER, AC_PWRST_D0);
  830. }
  831. break;
  832. case SND_SOC_BIAS_STANDBY:
  833. snd_soc_component_write(component,
  834. RT274_SET_AUDIO_POWER, AC_PWRST_D3);
  835. break;
  836. default:
  837. break;
  838. }
  839. return 0;
  840. }
  841. static irqreturn_t rt274_irq(int irq, void *data)
  842. {
  843. struct rt274_priv *rt274 = data;
  844. bool hp = false;
  845. bool mic = false;
  846. int ret, status = 0;
  847. /* Clear IRQ */
  848. regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
  849. RT274_IRQ_CLR, RT274_IRQ_CLR);
  850. ret = rt274_jack_detect(rt274, &hp, &mic);
  851. if (ret == 0) {
  852. if (hp)
  853. status |= SND_JACK_HEADPHONE;
  854. if (mic)
  855. status |= SND_JACK_MICROPHONE;
  856. snd_soc_jack_report(rt274->jack, status,
  857. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  858. pm_wakeup_event(&rt274->i2c->dev, 300);
  859. }
  860. return IRQ_HANDLED;
  861. }
  862. static int rt274_probe(struct snd_soc_component *component)
  863. {
  864. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  865. rt274->component = component;
  866. if (rt274->i2c->irq) {
  867. INIT_DELAYED_WORK(&rt274->jack_detect_work,
  868. rt274_jack_detect_work);
  869. schedule_delayed_work(&rt274->jack_detect_work,
  870. msecs_to_jiffies(1250));
  871. }
  872. return 0;
  873. }
  874. static void rt274_remove(struct snd_soc_component *component)
  875. {
  876. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  877. cancel_delayed_work_sync(&rt274->jack_detect_work);
  878. }
  879. #ifdef CONFIG_PM
  880. static int rt274_suspend(struct snd_soc_component *component)
  881. {
  882. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  883. regcache_cache_only(rt274->regmap, true);
  884. regcache_mark_dirty(rt274->regmap);
  885. return 0;
  886. }
  887. static int rt274_resume(struct snd_soc_component *component)
  888. {
  889. struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
  890. regcache_cache_only(rt274->regmap, false);
  891. rt274_index_sync(component);
  892. regcache_sync(rt274->regmap);
  893. return 0;
  894. }
  895. #else
  896. #define rt274_suspend NULL
  897. #define rt274_resume NULL
  898. #endif
  899. #define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  900. #define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  901. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  902. static const struct snd_soc_dai_ops rt274_aif_dai_ops = {
  903. .hw_params = rt274_hw_params,
  904. .set_fmt = rt274_set_dai_fmt,
  905. .set_sysclk = rt274_set_dai_sysclk,
  906. .set_pll = rt274_set_dai_pll,
  907. .set_bclk_ratio = rt274_set_bclk_ratio,
  908. .set_tdm_slot = rt274_set_tdm_slot,
  909. };
  910. static struct snd_soc_dai_driver rt274_dai[] = {
  911. {
  912. .name = "rt274-aif1",
  913. .id = RT274_AIF1,
  914. .playback = {
  915. .stream_name = "AIF1 Playback",
  916. .channels_min = 1,
  917. .channels_max = 2,
  918. .rates = RT274_STEREO_RATES,
  919. .formats = RT274_FORMATS,
  920. },
  921. .capture = {
  922. .stream_name = "AIF1 Capture",
  923. .channels_min = 1,
  924. .channels_max = 2,
  925. .rates = RT274_STEREO_RATES,
  926. .formats = RT274_FORMATS,
  927. },
  928. .ops = &rt274_aif_dai_ops,
  929. .symmetric_rates = 1,
  930. },
  931. };
  932. static const struct snd_soc_component_driver soc_component_dev_rt274 = {
  933. .probe = rt274_probe,
  934. .remove = rt274_remove,
  935. .suspend = rt274_suspend,
  936. .resume = rt274_resume,
  937. .set_bias_level = rt274_set_bias_level,
  938. .set_jack = rt274_mic_detect,
  939. .controls = rt274_snd_controls,
  940. .num_controls = ARRAY_SIZE(rt274_snd_controls),
  941. .dapm_widgets = rt274_dapm_widgets,
  942. .num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets),
  943. .dapm_routes = rt274_dapm_routes,
  944. .num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes),
  945. .use_pmdown_time = 1,
  946. .endianness = 1,
  947. .non_legacy_dai_naming = 1,
  948. };
  949. static const struct regmap_config rt274_regmap = {
  950. .reg_bits = 32,
  951. .val_bits = 32,
  952. .max_register = 0x05bfffff,
  953. .volatile_reg = rt274_volatile_register,
  954. .readable_reg = rt274_readable_register,
  955. .reg_write = rl6347a_hw_write,
  956. .reg_read = rl6347a_hw_read,
  957. .cache_type = REGCACHE_RBTREE,
  958. .reg_defaults = rt274_reg,
  959. .num_reg_defaults = ARRAY_SIZE(rt274_reg),
  960. };
  961. #ifdef CONFIG_OF
  962. static const struct of_device_id rt274_of_match[] = {
  963. {.compatible = "realtek,rt274"},
  964. {},
  965. };
  966. MODULE_DEVICE_TABLE(of, rt274_of_match);
  967. #endif
  968. static const struct i2c_device_id rt274_i2c_id[] = {
  969. {"rt274", 0},
  970. {}
  971. };
  972. MODULE_DEVICE_TABLE(i2c, rt274_i2c_id);
  973. #ifdef CONFIG_ACPI
  974. static const struct acpi_device_id rt274_acpi_match[] = {
  975. { "10EC0274", 0 },
  976. { "INT34C2", 0 },
  977. {},
  978. };
  979. MODULE_DEVICE_TABLE(acpi, rt274_acpi_match);
  980. #endif
  981. static int rt274_i2c_probe(struct i2c_client *i2c,
  982. const struct i2c_device_id *id)
  983. {
  984. struct rt274_priv *rt274;
  985. int ret;
  986. unsigned int val;
  987. rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274),
  988. GFP_KERNEL);
  989. if (rt274 == NULL)
  990. return -ENOMEM;
  991. rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap);
  992. if (IS_ERR(rt274->regmap)) {
  993. ret = PTR_ERR(rt274->regmap);
  994. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  995. ret);
  996. return ret;
  997. }
  998. ret = regmap_read(rt274->regmap,
  999. RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
  1000. if (ret)
  1001. return ret;
  1002. if (val != RT274_VENDOR_ID) {
  1003. dev_err(&i2c->dev,
  1004. "Device with ID register %#x is not rt274\n", val);
  1005. return -ENODEV;
  1006. }
  1007. rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def,
  1008. sizeof(rt274_index_def), GFP_KERNEL);
  1009. if (!rt274->index_cache)
  1010. return -ENOMEM;
  1011. rt274->index_cache_size = INDEX_CACHE_SIZE;
  1012. rt274->i2c = i2c;
  1013. i2c_set_clientdata(i2c, rt274);
  1014. /* reset codec */
  1015. regmap_write(rt274->regmap, RT274_RESET, 0);
  1016. regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000);
  1017. /* Set Pad PDB is floating */
  1018. regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0);
  1019. regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01);
  1020. regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540);
  1021. regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100);
  1022. /* Combo jack auto detect */
  1023. regmap_write(rt274->regmap, 0x4a, 0x201b);
  1024. /* Aux mode off */
  1025. regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000);
  1026. /* HP DC Calibration */
  1027. regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0);
  1028. /* Set NID=58h.Index 00h [15]= 1b; */
  1029. regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
  1030. regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888);
  1031. msleep(500);
  1032. regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb);
  1033. regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
  1034. regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888);
  1035. /* Set pin widget */
  1036. regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40);
  1037. regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40);
  1038. regmap_write(rt274->regmap, RT274_SET_MIC, 0x20);
  1039. regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20);
  1040. regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004);
  1041. regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
  1042. RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK);
  1043. /* jack detection */
  1044. regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81);
  1045. regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82);
  1046. if (rt274->i2c->irq) {
  1047. ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq,
  1048. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274);
  1049. if (ret != 0) {
  1050. dev_err(&i2c->dev,
  1051. "Failed to reguest IRQ: %d\n", ret);
  1052. return ret;
  1053. }
  1054. }
  1055. ret = devm_snd_soc_register_component(&i2c->dev,
  1056. &soc_component_dev_rt274,
  1057. rt274_dai, ARRAY_SIZE(rt274_dai));
  1058. return ret;
  1059. }
  1060. static int rt274_i2c_remove(struct i2c_client *i2c)
  1061. {
  1062. struct rt274_priv *rt274 = i2c_get_clientdata(i2c);
  1063. if (i2c->irq)
  1064. free_irq(i2c->irq, rt274);
  1065. return 0;
  1066. }
  1067. static struct i2c_driver rt274_i2c_driver = {
  1068. .driver = {
  1069. .name = "rt274",
  1070. .acpi_match_table = ACPI_PTR(rt274_acpi_match),
  1071. #ifdef CONFIG_OF
  1072. .of_match_table = of_match_ptr(rt274_of_match),
  1073. #endif
  1074. },
  1075. .probe = rt274_i2c_probe,
  1076. .remove = rt274_i2c_remove,
  1077. .id_table = rt274_i2c_id,
  1078. };
  1079. module_i2c_driver(rt274_i2c_driver);
  1080. MODULE_DESCRIPTION("ASoC RT274 driver");
  1081. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1082. MODULE_LICENSE("GPL v2");