rt1308.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // rt1308.c -- RT1308 ALSA SoC amplifier component driver
  4. //
  5. // Copyright 2019 Realtek Semiconductor Corp.
  6. // Author: Derek Fang <derek.fang@realtek.com>
  7. //
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/gpio.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/acpi.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/firmware.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "rl6231.h"
  28. #include "rt1308.h"
  29. static const struct reg_sequence init_list[] = {
  30. { RT1308_I2C_I2S_SDW_SET, 0x01014005 },
  31. { RT1308_CLASS_D_SET_2, 0x227f5501 },
  32. { RT1308_PADS_1, 0x50150505 },
  33. { RT1308_VREF, 0x18100000 },
  34. { RT1308_IV_SENSE, 0x87010000 },
  35. { RT1308_DUMMY_REG, 0x00000200 },
  36. { RT1308_SIL_DET, 0xe1c30000 },
  37. { RT1308_DC_CAL_2, 0x00ffff00 },
  38. { RT1308_CLK_DET, 0x01000000 },
  39. { RT1308_POWER_STATUS, 0x08800000 },
  40. { RT1308_DAC_SET, 0xafaf0700 },
  41. };
  42. #define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
  43. struct rt1308_priv {
  44. struct snd_soc_component *component;
  45. struct regmap *regmap;
  46. int sysclk;
  47. int sysclk_src;
  48. int lrck;
  49. int bclk;
  50. int master;
  51. int pll_src;
  52. int pll_in;
  53. int pll_out;
  54. };
  55. static const struct reg_default rt1308_reg[] = {
  56. { 0x01, 0x1f3f5f00 },
  57. { 0x02, 0x07000000 },
  58. { 0x03, 0x80003e00 },
  59. { 0x04, 0x80800600 },
  60. { 0x05, 0x0aaa1a0a },
  61. { 0x06, 0x52000000 },
  62. { 0x07, 0x00000000 },
  63. { 0x08, 0x00600000 },
  64. { 0x09, 0xe1030000 },
  65. { 0x0a, 0x00000000 },
  66. { 0x0b, 0x30000000 },
  67. { 0x0c, 0x7fff7000 },
  68. { 0x10, 0xffff0700 },
  69. { 0x11, 0x0a000000 },
  70. { 0x12, 0x60040000 },
  71. { 0x13, 0x00000000 },
  72. { 0x14, 0x0f300000 },
  73. { 0x15, 0x00000022 },
  74. { 0x16, 0x02000000 },
  75. { 0x17, 0x01004045 },
  76. { 0x18, 0x00000000 },
  77. { 0x19, 0x00000000 },
  78. { 0x1a, 0x80000000 },
  79. { 0x1b, 0x10325476 },
  80. { 0x1c, 0x1d1d0000 },
  81. { 0x20, 0xd2101300 },
  82. { 0x21, 0xf3ffff00 },
  83. { 0x22, 0x00000000 },
  84. { 0x23, 0x00000000 },
  85. { 0x24, 0x00000000 },
  86. { 0x25, 0x00000000 },
  87. { 0x26, 0x00000000 },
  88. { 0x27, 0x00000000 },
  89. { 0x28, 0x00000000 },
  90. { 0x29, 0x00000000 },
  91. { 0x2a, 0x00000000 },
  92. { 0x2b, 0x00000000 },
  93. { 0x2c, 0x00000000 },
  94. { 0x2d, 0x00000000 },
  95. { 0x2e, 0x00000000 },
  96. { 0x2f, 0x00000000 },
  97. { 0x30, 0x01000000 },
  98. { 0x31, 0x20025501 },
  99. { 0x32, 0x00000000 },
  100. { 0x33, 0x105a0000 },
  101. { 0x34, 0x10100000 },
  102. { 0x35, 0x2aaa52aa },
  103. { 0x36, 0x00c00000 },
  104. { 0x37, 0x20046100 },
  105. { 0x50, 0x10022f00 },
  106. { 0x51, 0x003c0000 },
  107. { 0x54, 0x04000000 },
  108. { 0x55, 0x01000000 },
  109. { 0x56, 0x02000000 },
  110. { 0x57, 0x02000000 },
  111. { 0x58, 0x02000000 },
  112. { 0x59, 0x02000000 },
  113. { 0x5b, 0x02000000 },
  114. { 0x5c, 0x00000000 },
  115. { 0x5d, 0x00000000 },
  116. { 0x5e, 0x00000000 },
  117. { 0x5f, 0x00000000 },
  118. { 0x60, 0x02000000 },
  119. { 0x61, 0x00000000 },
  120. { 0x62, 0x00000000 },
  121. { 0x63, 0x00000000 },
  122. { 0x64, 0x00000000 },
  123. { 0x65, 0x02000000 },
  124. { 0x66, 0x00000000 },
  125. { 0x67, 0x00000000 },
  126. { 0x68, 0x00000000 },
  127. { 0x69, 0x00000000 },
  128. { 0x6a, 0x02000000 },
  129. { 0x6c, 0x00000000 },
  130. { 0x6d, 0x00000000 },
  131. { 0x6e, 0x00000000 },
  132. { 0x70, 0x10EC1308 },
  133. { 0x71, 0x00000000 },
  134. { 0x72, 0x00000000 },
  135. { 0x73, 0x00000000 },
  136. { 0x74, 0x00000000 },
  137. { 0x75, 0x00000000 },
  138. { 0x76, 0x00000000 },
  139. { 0x77, 0x00000000 },
  140. { 0x78, 0x00000000 },
  141. { 0x79, 0x00000000 },
  142. { 0x7a, 0x00000000 },
  143. { 0x7b, 0x00000000 },
  144. { 0x7c, 0x00000000 },
  145. { 0x7d, 0x00000000 },
  146. { 0x7e, 0x00000000 },
  147. { 0x7f, 0x00020f00 },
  148. { 0x80, 0x00000000 },
  149. { 0x81, 0x00000000 },
  150. { 0x82, 0x00000000 },
  151. { 0x83, 0x00000000 },
  152. { 0x84, 0x00000000 },
  153. { 0x85, 0x00000000 },
  154. { 0x86, 0x00000000 },
  155. { 0x87, 0x00000000 },
  156. { 0x88, 0x00000000 },
  157. { 0x89, 0x00000000 },
  158. { 0x8a, 0x00000000 },
  159. { 0x8b, 0x00000000 },
  160. { 0x8c, 0x00000000 },
  161. { 0x8d, 0x00000000 },
  162. { 0x8e, 0x00000000 },
  163. { 0x90, 0x50250905 },
  164. { 0x91, 0x15050000 },
  165. { 0xa0, 0x00000000 },
  166. { 0xa1, 0x00000000 },
  167. { 0xa2, 0x00000000 },
  168. { 0xa3, 0x00000000 },
  169. { 0xa4, 0x00000000 },
  170. { 0xb0, 0x00000000 },
  171. { 0xb1, 0x00000000 },
  172. { 0xb2, 0x00000000 },
  173. { 0xb3, 0x00000000 },
  174. { 0xb4, 0x00000000 },
  175. { 0xb5, 0x00000000 },
  176. { 0xb6, 0x00000000 },
  177. { 0xb7, 0x00000000 },
  178. { 0xb8, 0x00000000 },
  179. { 0xb9, 0x00000000 },
  180. { 0xba, 0x00000000 },
  181. { 0xbb, 0x00000000 },
  182. { 0xc0, 0x01000000 },
  183. { 0xc1, 0x00000000 },
  184. { 0xf0, 0x00000000 },
  185. };
  186. static int rt1308_reg_init(struct snd_soc_component *component)
  187. {
  188. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  189. return regmap_multi_reg_write(rt1308->regmap, init_list,
  190. RT1308_INIT_REG_LEN);
  191. }
  192. static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
  193. {
  194. switch (reg) {
  195. case RT1308_RESET:
  196. case RT1308_RESET_N:
  197. case RT1308_CLK_2:
  198. case RT1308_SIL_DET:
  199. case RT1308_CLK_DET:
  200. case RT1308_DC_DET:
  201. case RT1308_DAC_SET:
  202. case RT1308_DAC_BUF:
  203. case RT1308_SDW_REG_RDATA:
  204. case RT1308_DC_CAL_1:
  205. case RT1308_PVDD_OFFSET_CTL:
  206. case RT1308_CAL_OFFSET_DAC_PBTL:
  207. case RT1308_CAL_OFFSET_DAC_L:
  208. case RT1308_CAL_OFFSET_DAC_R:
  209. case RT1308_CAL_OFFSET_PWM_L:
  210. case RT1308_CAL_OFFSET_PWM_R:
  211. case RT1308_CAL_PWM_VOS_ADC_L:
  212. case RT1308_CAL_PWM_VOS_ADC_R:
  213. case RT1308_MBIAS:
  214. case RT1308_POWER_STATUS:
  215. case RT1308_POWER_INT:
  216. case RT1308_SINE_TONE_GEN_2:
  217. case RT1308_BQ_SET:
  218. case RT1308_BQ_PARA_UPDATE:
  219. case RT1308_VEN_DEV_ID:
  220. case RT1308_VERSION_ID:
  221. case RT1308_EFUSE_1:
  222. case RT1308_EFUSE_READ_PVDD_L:
  223. case RT1308_EFUSE_READ_PVDD_R:
  224. case RT1308_EFUSE_READ_PVDD_PTBL:
  225. case RT1308_EFUSE_READ_DEV:
  226. case RT1308_EFUSE_READ_R0:
  227. case RT1308_EFUSE_READ_ADC_L:
  228. case RT1308_EFUSE_READ_ADC_R:
  229. case RT1308_EFUSE_READ_ADC_PBTL:
  230. case RT1308_EFUSE_RESERVE:
  231. case RT1308_EFUSE_DATA_0_MSB:
  232. case RT1308_EFUSE_DATA_0_LSB:
  233. case RT1308_EFUSE_DATA_1_MSB:
  234. case RT1308_EFUSE_DATA_1_LSB:
  235. case RT1308_EFUSE_DATA_2_MSB:
  236. case RT1308_EFUSE_DATA_2_LSB:
  237. case RT1308_EFUSE_DATA_3_MSB:
  238. case RT1308_EFUSE_DATA_3_LSB:
  239. case RT1308_EFUSE_STATUS_1:
  240. case RT1308_EFUSE_STATUS_2:
  241. case RT1308_DUMMY_REG:
  242. return true;
  243. default:
  244. return false;
  245. }
  246. }
  247. static bool rt1308_readable_register(struct device *dev, unsigned int reg)
  248. {
  249. switch (reg) {
  250. case RT1308_RESET:
  251. case RT1308_RESET_N:
  252. case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
  253. case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
  254. case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
  255. case RT1308_SINE_TONE_GEN_1:
  256. case RT1308_SINE_TONE_GEN_2:
  257. case RT1308_BQ_SET:
  258. case RT1308_BQ_PARA_UPDATE:
  259. case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
  260. case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
  261. case RT1308_VEN_DEV_ID:
  262. case RT1308_VERSION_ID:
  263. case RT1308_SPK_BOUND:
  264. case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
  265. case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
  266. case RT1308_PADS_1:
  267. case RT1308_PADS_2:
  268. case RT1308_TEST_MODE:
  269. case RT1308_TEST_1:
  270. case RT1308_TEST_2:
  271. case RT1308_TEST_3:
  272. case RT1308_TEST_4:
  273. case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
  274. case RT1308_TCON_1:
  275. case RT1308_TCON_2:
  276. case RT1308_DUMMY_REG:
  277. case RT1308_MAX_REG:
  278. return true;
  279. default:
  280. return false;
  281. }
  282. }
  283. static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
  284. struct snd_kcontrol *kcontrol, int event)
  285. {
  286. struct snd_soc_component *component =
  287. snd_soc_dapm_to_component(w->dapm);
  288. switch (event) {
  289. case SND_SOC_DAPM_POST_PMU:
  290. msleep(30);
  291. snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
  292. RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT,
  293. RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT);
  294. msleep(40);
  295. break;
  296. case SND_SOC_DAPM_PRE_PMD:
  297. snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
  298. RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);
  299. usleep_range(150000, 200000);
  300. break;
  301. default:
  302. break;
  303. }
  304. return 0;
  305. }
  306. static const char * const rt1308_rx_data_ch_select[] = {
  307. "LR",
  308. "LL",
  309. "RL",
  310. "RR",
  311. };
  312. static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
  313. rt1308_rx_data_ch_select);
  314. static const struct snd_kcontrol_new rt1308_snd_controls[] = {
  315. /* I2S Data Channel Selection */
  316. SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
  317. };
  318. static const struct snd_kcontrol_new rt1308_sto_dac_l =
  319. SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
  320. RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
  321. static const struct snd_kcontrol_new rt1308_sto_dac_r =
  322. SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
  323. RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
  324. static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
  325. /* Audio Interface */
  326. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  327. /* Supply Widgets */
  328. SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
  329. RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
  330. SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
  331. RT1308_POW_ALDO_BIT, 0, NULL, 0),
  332. SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
  333. RT1308_POW_DBG_BIT, 0, NULL, 0),
  334. SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
  335. RT1308_POW_DACL_BIT, 0, NULL, 0),
  336. SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
  337. RT1308_POW_CLK25M_BIT, 0, NULL, 0),
  338. SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
  339. RT1308_POW_ADC_R_BIT, 0, NULL, 0),
  340. SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
  341. RT1308_POW_ADC_L_BIT, 0, NULL, 0),
  342. SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
  343. RT1308_POW_DLDO_BIT, 0, NULL, 0),
  344. SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
  345. RT1308_POW_VREF_BIT, 0, NULL, 0),
  346. SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
  347. RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
  348. SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
  349. RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
  350. SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
  351. RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
  352. SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
  353. RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
  354. SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
  355. RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
  356. SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
  357. RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
  358. SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
  359. RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
  360. SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
  361. RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
  362. /* Digital Interface */
  363. SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
  364. RT1308_POW_DAC1_BIT, 0, NULL, 0),
  365. SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
  366. SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
  367. SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
  368. /* Output Lines */
  369. SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
  370. rt1308_classd_event,
  371. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  372. SND_SOC_DAPM_OUTPUT("SPOL"),
  373. SND_SOC_DAPM_OUTPUT("SPOR"),
  374. };
  375. static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
  376. { "DAC", NULL, "AIF1RX" },
  377. { "DAC", NULL, "MBIAS20U" },
  378. { "DAC", NULL, "ALDO" },
  379. { "DAC", NULL, "DBG" },
  380. { "DAC", NULL, "DACL" },
  381. { "DAC", NULL, "CLK25M" },
  382. { "DAC", NULL, "ADC_R" },
  383. { "DAC", NULL, "ADC_L" },
  384. { "DAC", NULL, "DLDO" },
  385. { "DAC", NULL, "VREF" },
  386. { "DAC", NULL, "MIXER_R" },
  387. { "DAC", NULL, "MIXER_L" },
  388. { "DAC", NULL, "MBIAS4U" },
  389. { "DAC", NULL, "PLL2_LDO" },
  390. { "DAC", NULL, "PLL2B" },
  391. { "DAC", NULL, "PLL2F" },
  392. { "DAC", NULL, "PLL2F2" },
  393. { "DAC", NULL, "PLL2B2" },
  394. { "DAC L", "Switch", "DAC" },
  395. { "DAC R", "Switch", "DAC" },
  396. { "DAC L", NULL, "DAC Power" },
  397. { "DAC R", NULL, "DAC Power" },
  398. { "CLASS D", NULL, "DAC L" },
  399. { "CLASS D", NULL, "DAC R" },
  400. { "SPOL", NULL, "CLASS D" },
  401. { "SPOR", NULL, "CLASS D" },
  402. };
  403. static int rt1308_get_clk_info(int sclk, int rate)
  404. {
  405. int i;
  406. static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
  407. if (sclk <= 0 || rate <= 0)
  408. return -EINVAL;
  409. rate = rate << 8;
  410. for (i = 0; i < ARRAY_SIZE(pd); i++)
  411. if (sclk == rate * pd[i])
  412. return i;
  413. return -EINVAL;
  414. }
  415. static int rt1308_hw_params(struct snd_pcm_substream *substream,
  416. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  417. {
  418. struct snd_soc_component *component = dai->component;
  419. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  420. unsigned int val_len = 0, val_clk, mask_clk;
  421. int pre_div, bclk_ms, frame_size;
  422. rt1308->lrck = params_rate(params);
  423. pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
  424. if (pre_div < 0) {
  425. dev_err(component->dev,
  426. "Unsupported clock setting %d\n", rt1308->lrck);
  427. return -EINVAL;
  428. }
  429. frame_size = snd_soc_params_to_frame_size(params);
  430. if (frame_size < 0) {
  431. dev_err(component->dev, "Unsupported frame size: %d\n",
  432. frame_size);
  433. return -EINVAL;
  434. }
  435. bclk_ms = frame_size > 32;
  436. rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
  437. dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  438. bclk_ms, pre_div, dai->id);
  439. dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  440. rt1308->lrck, pre_div, dai->id);
  441. switch (params_width(params)) {
  442. case 16:
  443. val_len |= RT1308_I2S_DL_SEL_16B;
  444. break;
  445. case 20:
  446. val_len |= RT1308_I2S_DL_SEL_20B;
  447. break;
  448. case 24:
  449. val_len |= RT1308_I2S_DL_SEL_24B;
  450. break;
  451. case 8:
  452. val_len |= RT1308_I2S_DL_SEL_8B;
  453. break;
  454. default:
  455. return -EINVAL;
  456. }
  457. switch (dai->id) {
  458. case RT1308_AIF1:
  459. mask_clk = RT1308_DIV_FS_SYS_MASK;
  460. val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
  461. snd_soc_component_update_bits(component,
  462. RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
  463. val_len);
  464. break;
  465. default:
  466. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  467. return -EINVAL;
  468. }
  469. snd_soc_component_update_bits(component, RT1308_CLK_1,
  470. mask_clk, val_clk);
  471. return 0;
  472. }
  473. static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  474. {
  475. struct snd_soc_component *component = dai->component;
  476. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  477. unsigned int reg_val = 0, reg1_val = 0;
  478. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  479. case SND_SOC_DAIFMT_CBS_CFS:
  480. rt1308->master = 0;
  481. break;
  482. default:
  483. return -EINVAL;
  484. }
  485. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  486. case SND_SOC_DAIFMT_I2S:
  487. break;
  488. case SND_SOC_DAIFMT_LEFT_J:
  489. reg_val |= RT1308_I2S_DF_SEL_LEFT;
  490. break;
  491. case SND_SOC_DAIFMT_DSP_A:
  492. reg_val |= RT1308_I2S_DF_SEL_PCM_A;
  493. break;
  494. case SND_SOC_DAIFMT_DSP_B:
  495. reg_val |= RT1308_I2S_DF_SEL_PCM_B;
  496. break;
  497. default:
  498. return -EINVAL;
  499. }
  500. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  501. case SND_SOC_DAIFMT_NB_NF:
  502. break;
  503. case SND_SOC_DAIFMT_IB_NF:
  504. reg1_val |= RT1308_I2S_BCLK_INV;
  505. break;
  506. default:
  507. return -EINVAL;
  508. }
  509. switch (dai->id) {
  510. case RT1308_AIF1:
  511. snd_soc_component_update_bits(component,
  512. RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
  513. reg_val);
  514. snd_soc_component_update_bits(component,
  515. RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
  516. reg1_val);
  517. break;
  518. default:
  519. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  520. return -EINVAL;
  521. }
  522. return 0;
  523. }
  524. static int rt1308_set_component_sysclk(struct snd_soc_component *component,
  525. int clk_id, int source, unsigned int freq, int dir)
  526. {
  527. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  528. unsigned int reg_val = 0;
  529. if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
  530. return 0;
  531. switch (clk_id) {
  532. case RT1308_FS_SYS_S_MCLK:
  533. reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
  534. snd_soc_component_update_bits(component,
  535. RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
  536. RT1308_MCLK_DET_EN);
  537. break;
  538. case RT1308_FS_SYS_S_BCLK:
  539. reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
  540. break;
  541. case RT1308_FS_SYS_S_PLL:
  542. reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
  543. break;
  544. case RT1308_FS_SYS_S_RCCLK:
  545. reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
  546. break;
  547. default:
  548. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  549. return -EINVAL;
  550. }
  551. snd_soc_component_update_bits(component, RT1308_CLK_1,
  552. RT1308_SEL_FS_SYS_MASK, reg_val);
  553. rt1308->sysclk = freq;
  554. rt1308->sysclk_src = clk_id;
  555. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  556. freq, clk_id);
  557. return 0;
  558. }
  559. static int rt1308_set_component_pll(struct snd_soc_component *component,
  560. int pll_id, int source, unsigned int freq_in,
  561. unsigned int freq_out)
  562. {
  563. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  564. struct rl6231_pll_code pll_code;
  565. int ret;
  566. if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
  567. freq_out == rt1308->pll_out)
  568. return 0;
  569. if (!freq_in || !freq_out) {
  570. dev_dbg(component->dev, "PLL disabled\n");
  571. rt1308->pll_in = 0;
  572. rt1308->pll_out = 0;
  573. snd_soc_component_update_bits(component,
  574. RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
  575. RT1308_SEL_FS_SYS_SRC_MCLK);
  576. return 0;
  577. }
  578. switch (source) {
  579. case RT1308_PLL_S_MCLK:
  580. snd_soc_component_update_bits(component,
  581. RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
  582. RT1308_SEL_PLL_SRC_MCLK);
  583. snd_soc_component_update_bits(component,
  584. RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
  585. RT1308_MCLK_DET_EN);
  586. break;
  587. case RT1308_PLL_S_BCLK:
  588. snd_soc_component_update_bits(component,
  589. RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
  590. RT1308_SEL_PLL_SRC_BCLK);
  591. break;
  592. case RT1308_PLL_S_RCCLK:
  593. snd_soc_component_update_bits(component,
  594. RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
  595. RT1308_SEL_PLL_SRC_RCCLK);
  596. freq_in = 25000000;
  597. break;
  598. default:
  599. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  600. return -EINVAL;
  601. }
  602. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  603. if (ret < 0) {
  604. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  605. return ret;
  606. }
  607. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  608. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  609. pll_code.n_code, pll_code.k_code);
  610. snd_soc_component_write(component, RT1308_PLL_1,
  611. pll_code.k_code << RT1308_PLL1_K_SFT |
  612. pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT |
  613. (pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT |
  614. pll_code.n_code << RT1308_PLL1_N_SFT);
  615. rt1308->pll_in = freq_in;
  616. rt1308->pll_out = freq_out;
  617. rt1308->pll_src = source;
  618. return 0;
  619. }
  620. static int rt1308_probe(struct snd_soc_component *component)
  621. {
  622. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  623. rt1308->component = component;
  624. return rt1308_reg_init(component);
  625. }
  626. static void rt1308_remove(struct snd_soc_component *component)
  627. {
  628. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  629. regmap_write(rt1308->regmap, RT1308_RESET, 0);
  630. }
  631. #ifdef CONFIG_PM
  632. static int rt1308_suspend(struct snd_soc_component *component)
  633. {
  634. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  635. regcache_cache_only(rt1308->regmap, true);
  636. regcache_mark_dirty(rt1308->regmap);
  637. return 0;
  638. }
  639. static int rt1308_resume(struct snd_soc_component *component)
  640. {
  641. struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
  642. regcache_cache_only(rt1308->regmap, false);
  643. regcache_sync(rt1308->regmap);
  644. return 0;
  645. }
  646. #else
  647. #define rt1308_suspend NULL
  648. #define rt1308_resume NULL
  649. #endif
  650. #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
  651. #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
  652. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
  653. SNDRV_PCM_FMTBIT_S24_LE)
  654. static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
  655. .hw_params = rt1308_hw_params,
  656. .set_fmt = rt1308_set_dai_fmt,
  657. };
  658. static struct snd_soc_dai_driver rt1308_dai[] = {
  659. {
  660. .name = "rt1308-aif",
  661. .playback = {
  662. .stream_name = "AIF1 Playback",
  663. .channels_min = 1,
  664. .channels_max = 2,
  665. .rates = RT1308_STEREO_RATES,
  666. .formats = RT1308_FORMATS,
  667. },
  668. .ops = &rt1308_aif_dai_ops,
  669. },
  670. };
  671. static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
  672. .probe = rt1308_probe,
  673. .remove = rt1308_remove,
  674. .suspend = rt1308_suspend,
  675. .resume = rt1308_resume,
  676. .controls = rt1308_snd_controls,
  677. .num_controls = ARRAY_SIZE(rt1308_snd_controls),
  678. .dapm_widgets = rt1308_dapm_widgets,
  679. .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
  680. .dapm_routes = rt1308_dapm_routes,
  681. .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
  682. .set_sysclk = rt1308_set_component_sysclk,
  683. .set_pll = rt1308_set_component_pll,
  684. .use_pmdown_time = 1,
  685. .endianness = 1,
  686. .non_legacy_dai_naming = 1,
  687. };
  688. static const struct regmap_config rt1308_regmap = {
  689. .reg_bits = 8,
  690. .val_bits = 32,
  691. .max_register = RT1308_MAX_REG,
  692. .volatile_reg = rt1308_volatile_register,
  693. .readable_reg = rt1308_readable_register,
  694. .cache_type = REGCACHE_RBTREE,
  695. .reg_defaults = rt1308_reg,
  696. .num_reg_defaults = ARRAY_SIZE(rt1308_reg),
  697. .use_single_read = true,
  698. .use_single_write = true,
  699. };
  700. #ifdef CONFIG_OF
  701. static const struct of_device_id rt1308_of_match[] = {
  702. { .compatible = "realtek,rt1308", },
  703. { },
  704. };
  705. MODULE_DEVICE_TABLE(of, rt1308_of_match);
  706. #endif
  707. #ifdef CONFIG_ACPI
  708. static struct acpi_device_id rt1308_acpi_match[] = {
  709. { "10EC1308", 0, },
  710. { },
  711. };
  712. MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
  713. #endif
  714. static const struct i2c_device_id rt1308_i2c_id[] = {
  715. { "rt1308", 0 },
  716. { }
  717. };
  718. MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
  719. static void rt1308_efuse(struct rt1308_priv *rt1308)
  720. {
  721. regmap_write(rt1308->regmap, RT1308_RESET, 0);
  722. regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
  723. msleep(100);
  724. regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
  725. msleep(20);
  726. regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
  727. }
  728. static int rt1308_i2c_probe(struct i2c_client *i2c,
  729. const struct i2c_device_id *id)
  730. {
  731. struct rt1308_priv *rt1308;
  732. int ret;
  733. unsigned int val;
  734. rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
  735. GFP_KERNEL);
  736. if (rt1308 == NULL)
  737. return -ENOMEM;
  738. i2c_set_clientdata(i2c, rt1308);
  739. rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
  740. if (IS_ERR(rt1308->regmap)) {
  741. ret = PTR_ERR(rt1308->regmap);
  742. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  743. ret);
  744. return ret;
  745. }
  746. regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
  747. /* ignore last byte difference */
  748. if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
  749. dev_err(&i2c->dev,
  750. "Device with ID register %x is not rt1308\n", val);
  751. return -ENODEV;
  752. }
  753. rt1308_efuse(rt1308);
  754. return devm_snd_soc_register_component(&i2c->dev,
  755. &soc_component_dev_rt1308,
  756. rt1308_dai, ARRAY_SIZE(rt1308_dai));
  757. }
  758. static void rt1308_i2c_shutdown(struct i2c_client *client)
  759. {
  760. struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
  761. regmap_write(rt1308->regmap, RT1308_RESET, 0);
  762. }
  763. static struct i2c_driver rt1308_i2c_driver = {
  764. .driver = {
  765. .name = "rt1308",
  766. .of_match_table = of_match_ptr(rt1308_of_match),
  767. .acpi_match_table = ACPI_PTR(rt1308_acpi_match),
  768. },
  769. .probe = rt1308_i2c_probe,
  770. .shutdown = rt1308_i2c_shutdown,
  771. .id_table = rt1308_i2c_id,
  772. };
  773. module_i2c_driver(rt1308_i2c_driver);
  774. MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
  775. MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
  776. MODULE_LICENSE("GPL v2");