rt1305.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * RT1305.h -- RT1305 ALSA SoC amplifier component driver
  4. *
  5. * Copyright 2018 Realtek Semiconductor Corp.
  6. * Author: Shuming Fan <shumingf@realtek.com>
  7. */
  8. #ifndef _RT1305_H_
  9. #define _RT1305_H_
  10. #define RT1305_DEVICE_ID_NUM 0x6251
  11. #define RT1305_RESET 0x00
  12. #define RT1305_CLK_1 0x04
  13. #define RT1305_CLK_2 0x05
  14. #define RT1305_CLK_3 0x06
  15. #define RT1305_DFLL_REG 0x07
  16. #define RT1305_CAL_EFUSE_CLOCK 0x08
  17. #define RT1305_PLL0_1 0x0a
  18. #define RT1305_PLL0_2 0x0b
  19. #define RT1305_PLL1_1 0x0c
  20. #define RT1305_PLL1_2 0x0d
  21. #define RT1305_MIXER_CTRL_1 0x10
  22. #define RT1305_MIXER_CTRL_2 0x11
  23. #define RT1305_DAC_SET_1 0x12
  24. #define RT1305_DAC_SET_2 0x14
  25. #define RT1305_ADC_SET_1 0x16
  26. #define RT1305_ADC_SET_2 0x17
  27. #define RT1305_ADC_SET_3 0x18
  28. #define RT1305_PATH_SET 0x20
  29. #define RT1305_SPDIF_IN_SET_1 0x22
  30. #define RT1305_SPDIF_IN_SET_2 0x24
  31. #define RT1305_SPDIF_IN_SET_3 0x26
  32. #define RT1305_SPDIF_OUT_SET_1 0x28
  33. #define RT1305_SPDIF_OUT_SET_2 0x2a
  34. #define RT1305_SPDIF_OUT_SET_3 0x2b
  35. #define RT1305_I2S_SET_1 0x2d
  36. #define RT1305_I2S_SET_2 0x2e
  37. #define RT1305_PBTL_MONO_MODE_SRC 0x2f
  38. #define RT1305_MANUALLY_I2C_DEVICE 0x32
  39. #define RT1305_POWER_STATUS 0x39
  40. #define RT1305_POWER_CTRL_1 0x3a
  41. #define RT1305_POWER_CTRL_2 0x3b
  42. #define RT1305_POWER_CTRL_3 0x3c
  43. #define RT1305_POWER_CTRL_4 0x3d
  44. #define RT1305_POWER_CTRL_5 0x3e
  45. #define RT1305_CLOCK_DETECT 0x3f
  46. #define RT1305_BIQUAD_SET_1 0x40
  47. #define RT1305_BIQUAD_SET_2 0x42
  48. #define RT1305_ADJUSTED_HPF_1 0x46
  49. #define RT1305_ADJUSTED_HPF_2 0x47
  50. #define RT1305_EQ_SET_1 0x4b
  51. #define RT1305_EQ_SET_2 0x4c
  52. #define RT1305_SPK_TEMP_PROTECTION_0 0x4f
  53. #define RT1305_SPK_TEMP_PROTECTION_1 0x50
  54. #define RT1305_SPK_TEMP_PROTECTION_2 0x51
  55. #define RT1305_SPK_TEMP_PROTECTION_3 0x52
  56. #define RT1305_SPK_DC_DETECT_1 0x53
  57. #define RT1305_SPK_DC_DETECT_2 0x54
  58. #define RT1305_LOUDNESS 0x58
  59. #define RT1305_THERMAL_FOLD_BACK_1 0x5e
  60. #define RT1305_THERMAL_FOLD_BACK_2 0x5f
  61. #define RT1305_SILENCE_DETECT 0x60
  62. #define RT1305_ALC_DRC_1 0x62
  63. #define RT1305_ALC_DRC_2 0x63
  64. #define RT1305_ALC_DRC_3 0x64
  65. #define RT1305_ALC_DRC_4 0x65
  66. #define RT1305_PRIV_INDEX 0x6a
  67. #define RT1305_PRIV_DATA 0x6c
  68. #define RT1305_SPK_EXCURSION_LIMITER_7 0x76
  69. #define RT1305_VERSION_ID 0x7a
  70. #define RT1305_VENDOR_ID 0x7c
  71. #define RT1305_DEVICE_ID 0x7e
  72. #define RT1305_EFUSE_1 0x80
  73. #define RT1305_EFUSE_2 0x81
  74. #define RT1305_EFUSE_3 0x82
  75. #define RT1305_DC_CALIB_1 0x90
  76. #define RT1305_DC_CALIB_2 0x91
  77. #define RT1305_DC_CALIB_3 0x92
  78. #define RT1305_DAC_OFFSET_1 0x93
  79. #define RT1305_DAC_OFFSET_2 0x94
  80. #define RT1305_DAC_OFFSET_3 0x95
  81. #define RT1305_DAC_OFFSET_4 0x96
  82. #define RT1305_DAC_OFFSET_5 0x97
  83. #define RT1305_DAC_OFFSET_6 0x98
  84. #define RT1305_DAC_OFFSET_7 0x99
  85. #define RT1305_DAC_OFFSET_8 0x9a
  86. #define RT1305_DAC_OFFSET_9 0x9b
  87. #define RT1305_DAC_OFFSET_10 0x9c
  88. #define RT1305_DAC_OFFSET_11 0x9d
  89. #define RT1305_DAC_OFFSET_12 0x9e
  90. #define RT1305_DAC_OFFSET_13 0x9f
  91. #define RT1305_DAC_OFFSET_14 0xa0
  92. #define RT1305_TRIM_1 0xb0
  93. #define RT1305_TRIM_2 0xb1
  94. #define RT1305_TUNE_INTERNAL_OSC 0xb2
  95. #define RT1305_BIQUAD1_H0_L_28_16 0xc0
  96. #define RT1305_BIQUAD3_A2_R_15_0 0xfb
  97. #define RT1305_MAX_REG 0xff
  98. /* CLOCK-1 (0x04) */
  99. #define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15)
  100. #define RT1305_SEL_PLL_SRC_2_SFT 15
  101. #define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15)
  102. #define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15)
  103. #define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13)
  104. #define RT1305_DIV_PLL_SRC_2_SFT 13
  105. #define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10)
  106. #define RT1305_SEL_PLL_SRC_1_SFT 10
  107. #define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10)
  108. #define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10)
  109. #define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10)
  110. #define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8)
  111. #define RT1305_SEL_FS_SYS_PRE_SFT 8
  112. #define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8)
  113. #define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8)
  114. #define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8)
  115. #define RT1305_DIV_FS_SYS_MASK (0x7 << 4)
  116. #define RT1305_DIV_FS_SYS_SFT 4
  117. /* PLL1M/N/K Code-1 (0x0c) */
  118. #define RT1305_PLL_1_M_SFT 12
  119. #define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11)
  120. #define RT1305_PLL_1_M_BYPASS_SFT 11
  121. #define RT1305_PLL_1_M_BYPASS (0x1 << 11)
  122. #define RT1305_PLL_1_N_MASK (0x1ff << 0)
  123. /* DAC Setting (0x14) */
  124. #define RT1305_DVOL_MUTE_L_EN_SFT 15
  125. #define RT1305_DVOL_MUTE_R_EN_SFT 14
  126. /* I2S Setting-1 (0x2d) */
  127. #define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15)
  128. #define RT1305_SEL_I2S_OUT_MODE_SFT 15
  129. #define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15)
  130. #define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15)
  131. /* I2S Setting-2 (0x2e) */
  132. #define RT1305_I2S_DF_SEL_MASK (0x3 << 12)
  133. #define RT1305_I2S_DF_SEL_SFT 12
  134. #define RT1305_I2S_DF_SEL_I2S (0x0 << 12)
  135. #define RT1305_I2S_DF_SEL_LEFT (0x1 << 12)
  136. #define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12)
  137. #define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12)
  138. #define RT1305_I2S_DL_SEL_MASK (0x3 << 10)
  139. #define RT1305_I2S_DL_SEL_SFT 10
  140. #define RT1305_I2S_DL_SEL_16B (0x0 << 10)
  141. #define RT1305_I2S_DL_SEL_20B (0x1 << 10)
  142. #define RT1305_I2S_DL_SEL_24B (0x2 << 10)
  143. #define RT1305_I2S_DL_SEL_8B (0x3 << 10)
  144. #define RT1305_I2S_BCLK_MASK (0x1 << 9)
  145. #define RT1305_I2S_BCLK_SFT 9
  146. #define RT1305_I2S_BCLK_NORMAL (0x0 << 9)
  147. #define RT1305_I2S_BCLK_INV (0x1 << 9)
  148. /* Power Control-1 (0x3a) */
  149. #define RT1305_POW_PDB_JD_MASK (0x1 << 12)
  150. #define RT1305_POW_PDB_JD (0x1 << 12)
  151. #define RT1305_POW_PDB_JD_BIT 12
  152. #define RT1305_POW_PLL0_EN (0x1 << 11)
  153. #define RT1305_POW_PLL0_EN_BIT 11
  154. #define RT1305_POW_PLL1_EN (0x1 << 10)
  155. #define RT1305_POW_PLL1_EN_BIT 10
  156. #define RT1305_POW_PDB_JD_POLARITY (0x1 << 9)
  157. #define RT1305_POW_PDB_JD_POLARITY_BIT 9
  158. #define RT1305_POW_MBIAS_LV (0x1 << 8)
  159. #define RT1305_POW_MBIAS_LV_BIT 8
  160. #define RT1305_POW_BG_MBIAS_LV (0x1 << 7)
  161. #define RT1305_POW_BG_MBIAS_LV_BIT 7
  162. #define RT1305_POW_LDO2 (0x1 << 6)
  163. #define RT1305_POW_LDO2_BIT 6
  164. #define RT1305_POW_BG2 (0x1 << 5)
  165. #define RT1305_POW_BG2_BIT 5
  166. #define RT1305_POW_LDO2_IB2 (0x1 << 4)
  167. #define RT1305_POW_LDO2_IB2_BIT 4
  168. #define RT1305_POW_VREF (0x1 << 3)
  169. #define RT1305_POW_VREF_BIT 3
  170. #define RT1305_POW_VREF1 (0x1 << 2)
  171. #define RT1305_POW_VREF1_BIT 2
  172. #define RT1305_POW_VREF2 (0x1 << 1)
  173. #define RT1305_POW_VREF2_BIT 1
  174. /* Power Control-2 (0x3b) */
  175. #define RT1305_POW_DISC_VREF (1 << 15)
  176. #define RT1305_POW_DISC_VREF_BIT 15
  177. #define RT1305_POW_FASTB_VREF (1 << 14)
  178. #define RT1305_POW_FASTB_VREF_BIT 14
  179. #define RT1305_POW_ULTRA_FAST_VREF (1 << 13)
  180. #define RT1305_POW_ULTRA_FAST_VREF_BIT 13
  181. #define RT1305_POW_CKXEN_DAC (1 << 12)
  182. #define RT1305_POW_CKXEN_DAC_BIT 12
  183. #define RT1305_POW_EN_CKGEN_DAC (1 << 11)
  184. #define RT1305_POW_EN_CKGEN_DAC_BIT 11
  185. #define RT1305_POW_DAC1_L (1 << 10)
  186. #define RT1305_POW_DAC1_L_BIT 10
  187. #define RT1305_POW_DAC1_R (1 << 9)
  188. #define RT1305_POW_DAC1_R_BIT 9
  189. #define RT1305_POW_CLAMP (1 << 8)
  190. #define RT1305_POW_CLAMP_BIT 8
  191. #define RT1305_POW_BUFL (1 << 7)
  192. #define RT1305_POW_BUFL_BIT 7
  193. #define RT1305_POW_BUFR (1 << 6)
  194. #define RT1305_POW_BUFR_BIT 6
  195. #define RT1305_POW_EN_CKGEN_ADC (1 << 5)
  196. #define RT1305_POW_EN_CKGEN_ADC_BIT 5
  197. #define RT1305_POW_ADC3_L (1 << 4)
  198. #define RT1305_POW_ADC3_L_BIT 4
  199. #define RT1305_POW_ADC3_R (1 << 3)
  200. #define RT1305_POW_ADC3_R_BIT 3
  201. #define RT1305_POW_TRIOSC (1 << 2)
  202. #define RT1305_POW_TRIOSC_BIT 2
  203. #define RT1305_POR_AVDD1 (1 << 1)
  204. #define RT1305_POR_AVDD1_BIT 1
  205. #define RT1305_POR_AVDD2 (1 << 0)
  206. #define RT1305_POR_AVDD2_BIT 0
  207. /* Power Control-3 (0x3c) */
  208. #define RT1305_POW_VSENSE_RCH (1 << 15)
  209. #define RT1305_POW_VSENSE_RCH_BIT 15
  210. #define RT1305_POW_VSENSE_LCH (1 << 14)
  211. #define RT1305_POW_VSENSE_LCH_BIT 14
  212. #define RT1305_POW_ISENSE_RCH (1 << 13)
  213. #define RT1305_POW_ISENSE_RCH_BIT 13
  214. #define RT1305_POW_ISENSE_LCH (1 << 12)
  215. #define RT1305_POW_ISENSE_LCH_BIT 12
  216. #define RT1305_POW_POR_AVDD1 (1 << 11)
  217. #define RT1305_POW_POR_AVDD1_BIT 11
  218. #define RT1305_POW_POR_AVDD2 (1 << 10)
  219. #define RT1305_POW_POR_AVDD2_BIT 10
  220. #define RT1305_EN_K_HV (1 << 9)
  221. #define RT1305_EN_K_HV_BIT 9
  222. #define RT1305_EN_PRE_K_HV (1 << 8)
  223. #define RT1305_EN_PRE_K_HV_BIT 8
  224. #define RT1305_EN_EFUSE_1P8V (1 << 7)
  225. #define RT1305_EN_EFUSE_1P8V_BIT 7
  226. #define RT1305_EN_EFUSE_5V (1 << 6)
  227. #define RT1305_EN_EFUSE_5V_BIT 6
  228. #define RT1305_EN_VCM_6172 (1 << 5)
  229. #define RT1305_EN_VCM_6172_BIT 5
  230. #define RT1305_POR_EFUSE (1 << 4)
  231. #define RT1305_POR_EFUSE_BIT 4
  232. /* Clock Detect (0x3f) */
  233. #define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12)
  234. #define RT1305_SEL_CLK_DET_SRC_SFT 12
  235. #define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12)
  236. #define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12)
  237. /* System Clock Source */
  238. enum {
  239. RT1305_FS_SYS_PRE_S_MCLK,
  240. RT1305_FS_SYS_PRE_S_PLL1,
  241. RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */
  242. };
  243. /* PLL Source 1/2 */
  244. enum {
  245. RT1305_PLL1_S_BCLK,
  246. RT1305_PLL2_S_MCLK,
  247. RT1305_PLL2_S_RCCLK, /* 98.304M Hz */
  248. };
  249. enum {
  250. RT1305_AIF1,
  251. RT1305_AIFS
  252. };
  253. #define R0_UPPER 0x2E8BA2 //5.5 ohm
  254. #define R0_LOWER 0x666666 //2.5 ohm
  255. #endif /* end of _RT1305_H_ */