rt1305.c 32 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt1305.c -- RT1305 ALSA SoC amplifier component driver
  4. *
  5. * Copyright 2018 Realtek Semiconductor Corp.
  6. * Author: Shuming Fan <shumingf@realtek.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/acpi.h>
  14. #include <linux/gpio.h>
  15. #include <linux/i2c.h>
  16. #include <linux/regmap.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/firmware.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "rl6231.h"
  28. #include "rt1305.h"
  29. #define RT1305_PR_RANGE_BASE (0xff + 1)
  30. #define RT1305_PR_SPACING 0x100
  31. #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
  32. static const struct regmap_range_cfg rt1305_ranges[] = {
  33. {
  34. .name = "PR",
  35. .range_min = RT1305_PR_BASE,
  36. .range_max = RT1305_PR_BASE + 0xff,
  37. .selector_reg = RT1305_PRIV_INDEX,
  38. .selector_mask = 0xff,
  39. .selector_shift = 0x0,
  40. .window_start = RT1305_PRIV_DATA,
  41. .window_len = 0x1,
  42. },
  43. };
  44. static const struct reg_sequence init_list[] = {
  45. { RT1305_PR_BASE + 0xcf, 0x5548 },
  46. { RT1305_PR_BASE + 0x5d, 0x0442 },
  47. { RT1305_PR_BASE + 0xc1, 0x0320 },
  48. { RT1305_POWER_STATUS, 0x0000 },
  49. { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
  50. { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
  51. { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
  52. { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
  53. { RT1305_ADC_SET_3, 0x0219 },
  54. { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
  55. };
  56. #define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
  57. struct rt1305_priv {
  58. struct snd_soc_component *component;
  59. struct regmap *regmap;
  60. int sysclk;
  61. int sysclk_src;
  62. int lrck;
  63. int bclk;
  64. int master;
  65. int pll_src;
  66. int pll_in;
  67. int pll_out;
  68. };
  69. static const struct reg_default rt1305_reg[] = {
  70. { 0x04, 0x0400 },
  71. { 0x05, 0x0880 },
  72. { 0x06, 0x0000 },
  73. { 0x07, 0x3100 },
  74. { 0x08, 0x8000 },
  75. { 0x09, 0x0000 },
  76. { 0x0a, 0x087e },
  77. { 0x0b, 0x0020 },
  78. { 0x0c, 0x0802 },
  79. { 0x0d, 0x0020 },
  80. { 0x10, 0x1d1d },
  81. { 0x11, 0x1d1d },
  82. { 0x12, 0xffff },
  83. { 0x14, 0x000c },
  84. { 0x16, 0x1717 },
  85. { 0x17, 0x4000 },
  86. { 0x18, 0x0019 },
  87. { 0x20, 0x0000 },
  88. { 0x22, 0x0000 },
  89. { 0x24, 0x0000 },
  90. { 0x26, 0x0000 },
  91. { 0x28, 0x0000 },
  92. { 0x2a, 0x4000 },
  93. { 0x2b, 0x3000 },
  94. { 0x2d, 0x6000 },
  95. { 0x2e, 0x0000 },
  96. { 0x2f, 0x8000 },
  97. { 0x32, 0x0000 },
  98. { 0x39, 0x0001 },
  99. { 0x3a, 0x0000 },
  100. { 0x3b, 0x1020 },
  101. { 0x3c, 0x0000 },
  102. { 0x3d, 0x0000 },
  103. { 0x3e, 0x4c00 },
  104. { 0x3f, 0x3000 },
  105. { 0x40, 0x000c },
  106. { 0x42, 0x0400 },
  107. { 0x46, 0xc22c },
  108. { 0x47, 0x0000 },
  109. { 0x4b, 0x0000 },
  110. { 0x4c, 0x0300 },
  111. { 0x4f, 0xf000 },
  112. { 0x50, 0xc200 },
  113. { 0x51, 0x1f1f },
  114. { 0x52, 0x01f0 },
  115. { 0x53, 0x407f },
  116. { 0x54, 0xffff },
  117. { 0x58, 0x4005 },
  118. { 0x5e, 0x0000 },
  119. { 0x5f, 0x0000 },
  120. { 0x60, 0xee13 },
  121. { 0x62, 0x0000 },
  122. { 0x63, 0x5f5f },
  123. { 0x64, 0x0040 },
  124. { 0x65, 0x4000 },
  125. { 0x66, 0x4004 },
  126. { 0x67, 0x0306 },
  127. { 0x68, 0x8c04 },
  128. { 0x69, 0xe021 },
  129. { 0x6a, 0x0000 },
  130. { 0x6c, 0xaaaa },
  131. { 0x70, 0x0333 },
  132. { 0x71, 0x3330 },
  133. { 0x72, 0x3333 },
  134. { 0x73, 0x3300 },
  135. { 0x74, 0x0000 },
  136. { 0x75, 0x0000 },
  137. { 0x76, 0x0000 },
  138. { 0x7a, 0x0003 },
  139. { 0x7c, 0x10ec },
  140. { 0x7e, 0x6251 },
  141. { 0x80, 0x0800 },
  142. { 0x81, 0x4000 },
  143. { 0x82, 0x0000 },
  144. { 0x90, 0x7a01 },
  145. { 0x91, 0x8431 },
  146. { 0x92, 0x0180 },
  147. { 0x93, 0x0000 },
  148. { 0x94, 0x0000 },
  149. { 0x95, 0x0000 },
  150. { 0x96, 0x0000 },
  151. { 0x97, 0x0000 },
  152. { 0x98, 0x0000 },
  153. { 0x99, 0x0000 },
  154. { 0x9a, 0x0000 },
  155. { 0x9b, 0x0000 },
  156. { 0x9c, 0x0000 },
  157. { 0x9d, 0x0000 },
  158. { 0x9e, 0x0000 },
  159. { 0x9f, 0x0000 },
  160. { 0xa0, 0x0000 },
  161. { 0xb0, 0x8200 },
  162. { 0xb1, 0x00ff },
  163. { 0xb2, 0x0008 },
  164. { 0xc0, 0x0200 },
  165. { 0xc1, 0x0000 },
  166. { 0xc2, 0x0000 },
  167. { 0xc3, 0x0000 },
  168. { 0xc4, 0x0000 },
  169. { 0xc5, 0x0000 },
  170. { 0xc6, 0x0000 },
  171. { 0xc7, 0x0000 },
  172. { 0xc8, 0x0000 },
  173. { 0xc9, 0x0000 },
  174. { 0xca, 0x0200 },
  175. { 0xcb, 0x0000 },
  176. { 0xcc, 0x0000 },
  177. { 0xcd, 0x0000 },
  178. { 0xce, 0x0000 },
  179. { 0xcf, 0x0000 },
  180. { 0xd0, 0x0000 },
  181. { 0xd1, 0x0000 },
  182. { 0xd2, 0x0000 },
  183. { 0xd3, 0x0000 },
  184. { 0xd4, 0x0200 },
  185. { 0xd5, 0x0000 },
  186. { 0xd6, 0x0000 },
  187. { 0xd7, 0x0000 },
  188. { 0xd8, 0x0000 },
  189. { 0xd9, 0x0000 },
  190. { 0xda, 0x0000 },
  191. { 0xdb, 0x0000 },
  192. { 0xdc, 0x0000 },
  193. { 0xdd, 0x0000 },
  194. { 0xde, 0x0200 },
  195. { 0xdf, 0x0000 },
  196. { 0xe0, 0x0000 },
  197. { 0xe1, 0x0000 },
  198. { 0xe2, 0x0000 },
  199. { 0xe3, 0x0000 },
  200. { 0xe4, 0x0000 },
  201. { 0xe5, 0x0000 },
  202. { 0xe6, 0x0000 },
  203. { 0xe7, 0x0000 },
  204. { 0xe8, 0x0200 },
  205. { 0xe9, 0x0000 },
  206. { 0xea, 0x0000 },
  207. { 0xeb, 0x0000 },
  208. { 0xec, 0x0000 },
  209. { 0xed, 0x0000 },
  210. { 0xee, 0x0000 },
  211. { 0xef, 0x0000 },
  212. { 0xf0, 0x0000 },
  213. { 0xf1, 0x0000 },
  214. { 0xf2, 0x0200 },
  215. { 0xf3, 0x0000 },
  216. { 0xf4, 0x0000 },
  217. { 0xf5, 0x0000 },
  218. { 0xf6, 0x0000 },
  219. { 0xf7, 0x0000 },
  220. { 0xf8, 0x0000 },
  221. { 0xf9, 0x0000 },
  222. { 0xfa, 0x0000 },
  223. { 0xfb, 0x0000 },
  224. };
  225. static int rt1305_reg_init(struct snd_soc_component *component)
  226. {
  227. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  228. regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
  229. return 0;
  230. }
  231. static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
  232. {
  233. int i;
  234. for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
  235. if (reg >= rt1305_ranges[i].range_min &&
  236. reg <= rt1305_ranges[i].range_max) {
  237. return true;
  238. }
  239. }
  240. switch (reg) {
  241. case RT1305_RESET:
  242. case RT1305_SPDIF_IN_SET_1:
  243. case RT1305_SPDIF_IN_SET_2:
  244. case RT1305_SPDIF_IN_SET_3:
  245. case RT1305_POWER_CTRL_2:
  246. case RT1305_CLOCK_DETECT:
  247. case RT1305_BIQUAD_SET_1:
  248. case RT1305_BIQUAD_SET_2:
  249. case RT1305_EQ_SET_2:
  250. case RT1305_SPK_TEMP_PROTECTION_0:
  251. case RT1305_SPK_TEMP_PROTECTION_2:
  252. case RT1305_SPK_DC_DETECT_1:
  253. case RT1305_SILENCE_DETECT:
  254. case RT1305_VERSION_ID:
  255. case RT1305_VENDOR_ID:
  256. case RT1305_DEVICE_ID:
  257. case RT1305_EFUSE_1:
  258. case RT1305_EFUSE_3:
  259. case RT1305_DC_CALIB_1:
  260. case RT1305_DC_CALIB_3:
  261. case RT1305_DAC_OFFSET_1:
  262. case RT1305_DAC_OFFSET_2:
  263. case RT1305_DAC_OFFSET_3:
  264. case RT1305_DAC_OFFSET_4:
  265. case RT1305_DAC_OFFSET_5:
  266. case RT1305_DAC_OFFSET_6:
  267. case RT1305_DAC_OFFSET_7:
  268. case RT1305_DAC_OFFSET_8:
  269. case RT1305_DAC_OFFSET_9:
  270. case RT1305_DAC_OFFSET_10:
  271. case RT1305_DAC_OFFSET_11:
  272. case RT1305_TRIM_1:
  273. case RT1305_TRIM_2:
  274. return true;
  275. default:
  276. return false;
  277. }
  278. }
  279. static bool rt1305_readable_register(struct device *dev, unsigned int reg)
  280. {
  281. int i;
  282. for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
  283. if (reg >= rt1305_ranges[i].range_min &&
  284. reg <= rt1305_ranges[i].range_max) {
  285. return true;
  286. }
  287. }
  288. switch (reg) {
  289. case RT1305_RESET:
  290. case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
  291. case RT1305_PLL0_1 ... RT1305_PLL1_2:
  292. case RT1305_MIXER_CTRL_1:
  293. case RT1305_MIXER_CTRL_2:
  294. case RT1305_DAC_SET_1:
  295. case RT1305_DAC_SET_2:
  296. case RT1305_ADC_SET_1:
  297. case RT1305_ADC_SET_2:
  298. case RT1305_ADC_SET_3:
  299. case RT1305_PATH_SET:
  300. case RT1305_SPDIF_IN_SET_1:
  301. case RT1305_SPDIF_IN_SET_2:
  302. case RT1305_SPDIF_IN_SET_3:
  303. case RT1305_SPDIF_OUT_SET_1:
  304. case RT1305_SPDIF_OUT_SET_2:
  305. case RT1305_SPDIF_OUT_SET_3:
  306. case RT1305_I2S_SET_1:
  307. case RT1305_I2S_SET_2:
  308. case RT1305_PBTL_MONO_MODE_SRC:
  309. case RT1305_MANUALLY_I2C_DEVICE:
  310. case RT1305_POWER_STATUS:
  311. case RT1305_POWER_CTRL_1:
  312. case RT1305_POWER_CTRL_2:
  313. case RT1305_POWER_CTRL_3:
  314. case RT1305_POWER_CTRL_4:
  315. case RT1305_POWER_CTRL_5:
  316. case RT1305_CLOCK_DETECT:
  317. case RT1305_BIQUAD_SET_1:
  318. case RT1305_BIQUAD_SET_2:
  319. case RT1305_ADJUSTED_HPF_1:
  320. case RT1305_ADJUSTED_HPF_2:
  321. case RT1305_EQ_SET_1:
  322. case RT1305_EQ_SET_2:
  323. case RT1305_SPK_TEMP_PROTECTION_0:
  324. case RT1305_SPK_TEMP_PROTECTION_1:
  325. case RT1305_SPK_TEMP_PROTECTION_2:
  326. case RT1305_SPK_TEMP_PROTECTION_3:
  327. case RT1305_SPK_DC_DETECT_1:
  328. case RT1305_SPK_DC_DETECT_2:
  329. case RT1305_LOUDNESS:
  330. case RT1305_THERMAL_FOLD_BACK_1:
  331. case RT1305_THERMAL_FOLD_BACK_2:
  332. case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
  333. case RT1305_VERSION_ID:
  334. case RT1305_VENDOR_ID:
  335. case RT1305_DEVICE_ID:
  336. case RT1305_EFUSE_1:
  337. case RT1305_EFUSE_2:
  338. case RT1305_EFUSE_3:
  339. case RT1305_DC_CALIB_1:
  340. case RT1305_DC_CALIB_2:
  341. case RT1305_DC_CALIB_3:
  342. case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
  343. case RT1305_TRIM_1:
  344. case RT1305_TRIM_2:
  345. case RT1305_TUNE_INTERNAL_OSC:
  346. case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
  347. return true;
  348. default:
  349. return false;
  350. }
  351. }
  352. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
  353. static const char * const rt1305_rx_data_ch_select[] = {
  354. "LR",
  355. "RL",
  356. "Copy L",
  357. "Copy R",
  358. };
  359. static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
  360. rt1305_rx_data_ch_select);
  361. static void rt1305_reset(struct regmap *regmap)
  362. {
  363. regmap_write(regmap, RT1305_RESET, 0);
  364. }
  365. static const struct snd_kcontrol_new rt1305_snd_controls[] = {
  366. SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
  367. 8, 0, 0xff, 0, dac_vol_tlv),
  368. /* I2S Data Channel Selection */
  369. SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
  370. };
  371. static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
  372. struct snd_soc_dapm_widget *sink)
  373. {
  374. struct snd_soc_component *component =
  375. snd_soc_dapm_to_component(source->dapm);
  376. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  377. unsigned int val;
  378. val = snd_soc_component_read(component, RT1305_CLK_1);
  379. if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
  380. (val & RT1305_SEL_PLL_SRC_2_RCCLK))
  381. return 1;
  382. else
  383. return 0;
  384. }
  385. static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  386. struct snd_soc_dapm_widget *sink)
  387. {
  388. struct snd_soc_component *component =
  389. snd_soc_dapm_to_component(source->dapm);
  390. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  391. if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
  392. return 1;
  393. else
  394. return 0;
  395. }
  396. static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
  397. struct snd_kcontrol *kcontrol, int event)
  398. {
  399. struct snd_soc_component *component =
  400. snd_soc_dapm_to_component(w->dapm);
  401. switch (event) {
  402. case SND_SOC_DAPM_POST_PMU:
  403. snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
  404. RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
  405. break;
  406. case SND_SOC_DAPM_PRE_PMD:
  407. snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
  408. RT1305_POW_PDB_JD_MASK, 0);
  409. usleep_range(150000, 200000);
  410. break;
  411. default:
  412. return 0;
  413. }
  414. return 0;
  415. }
  416. static const struct snd_kcontrol_new rt1305_sto_dac_l =
  417. SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
  418. RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
  419. static const struct snd_kcontrol_new rt1305_sto_dac_r =
  420. SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
  421. RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
  422. static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
  423. SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
  424. RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
  425. SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
  426. RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
  427. SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
  428. RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
  429. SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
  430. RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
  431. SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
  432. RT1305_POW_LDO2_BIT, 0, NULL, 0),
  433. SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
  434. RT1305_POW_BG2_BIT, 0, NULL, 0),
  435. SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
  436. RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
  437. SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
  438. RT1305_POW_VREF_BIT, 0, NULL, 0),
  439. SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
  440. RT1305_POW_VREF1_BIT, 0, NULL, 0),
  441. SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
  442. RT1305_POW_VREF2_BIT, 0, NULL, 0),
  443. SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
  444. RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
  445. SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
  446. RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
  447. SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
  448. RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
  449. SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
  450. RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
  451. SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
  452. RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
  453. SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
  454. RT1305_POW_CLAMP_BIT, 0, NULL, 0),
  455. SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
  456. RT1305_POW_BUFL_BIT, 0, NULL, 0),
  457. SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
  458. RT1305_POW_BUFR_BIT, 0, NULL, 0),
  459. SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
  460. RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
  461. SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
  462. RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
  463. SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
  464. RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
  465. SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
  466. RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
  467. SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
  468. RT1305_POR_AVDD1_BIT, 0, NULL, 0),
  469. SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
  470. RT1305_POR_AVDD2_BIT, 0, NULL, 0),
  471. SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
  472. RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
  473. SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
  474. RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
  475. SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
  476. RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
  477. SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
  478. RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
  479. SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
  480. RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
  481. SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
  482. RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
  483. SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
  484. RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
  485. /* Audio Interface */
  486. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  487. /* Digital Interface */
  488. SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
  489. RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
  490. SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
  491. RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
  492. SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
  493. SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
  494. SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
  495. /* Output Lines */
  496. SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
  497. rt1305_classd_event,
  498. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  499. SND_SOC_DAPM_OUTPUT("SPOL"),
  500. SND_SOC_DAPM_OUTPUT("SPOR"),
  501. };
  502. static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
  503. { "DAC", NULL, "AIF1RX" },
  504. { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
  505. { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
  506. { "DAC", NULL, "MBIAS" },
  507. { "DAC", NULL, "BG MBIAS" },
  508. { "DAC", NULL, "LDO2" },
  509. { "DAC", NULL, "BG2" },
  510. { "DAC", NULL, "LDO2 IB2" },
  511. { "DAC", NULL, "VREF" },
  512. { "DAC", NULL, "VREF1" },
  513. { "DAC", NULL, "VREF2" },
  514. { "DAC", NULL, "DISC VREF" },
  515. { "DAC", NULL, "FASTB VREF" },
  516. { "DAC", NULL, "ULTRA FAST VREF" },
  517. { "DAC", NULL, "CHOP DAC" },
  518. { "DAC", NULL, "CKGEN DAC" },
  519. { "DAC", NULL, "CLAMP" },
  520. { "DAC", NULL, "CKGEN ADC" },
  521. { "DAC", NULL, "TRIOSC" },
  522. { "DAC", NULL, "AVDD1" },
  523. { "DAC", NULL, "AVDD2" },
  524. { "DAC", NULL, "POR AVDD1" },
  525. { "DAC", NULL, "POR AVDD2" },
  526. { "DAC", NULL, "VCM 6172" },
  527. { "DAC L", "Switch", "DAC" },
  528. { "DAC R", "Switch", "DAC" },
  529. { "DAC R", NULL, "VSENSE R" },
  530. { "DAC L", NULL, "VSENSE L" },
  531. { "DAC R", NULL, "ISENSE R" },
  532. { "DAC L", NULL, "ISENSE L" },
  533. { "DAC L", NULL, "ADC3 L" },
  534. { "DAC R", NULL, "ADC3 R" },
  535. { "DAC L", NULL, "BUFL" },
  536. { "DAC R", NULL, "BUFR" },
  537. { "DAC L", NULL, "DAC L Power" },
  538. { "DAC R", NULL, "DAC R Power" },
  539. { "CLASS D", NULL, "DAC L" },
  540. { "CLASS D", NULL, "DAC R" },
  541. { "SPOL", NULL, "CLASS D" },
  542. { "SPOR", NULL, "CLASS D" },
  543. };
  544. static int rt1305_get_clk_info(int sclk, int rate)
  545. {
  546. int i;
  547. static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
  548. if (sclk <= 0 || rate <= 0)
  549. return -EINVAL;
  550. rate = rate << 8;
  551. for (i = 0; i < ARRAY_SIZE(pd); i++)
  552. if (sclk == rate * pd[i])
  553. return i;
  554. return -EINVAL;
  555. }
  556. static int rt1305_hw_params(struct snd_pcm_substream *substream,
  557. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  558. {
  559. struct snd_soc_component *component = dai->component;
  560. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  561. unsigned int val_len = 0, val_clk, mask_clk;
  562. int pre_div, bclk_ms, frame_size;
  563. rt1305->lrck = params_rate(params);
  564. pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
  565. if (pre_div < 0) {
  566. dev_warn(component->dev, "Force using PLL ");
  567. snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
  568. rt1305->lrck * 64, rt1305->lrck * 256);
  569. snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
  570. rt1305->lrck * 256, SND_SOC_CLOCK_IN);
  571. pre_div = 0;
  572. }
  573. frame_size = snd_soc_params_to_frame_size(params);
  574. if (frame_size < 0) {
  575. dev_err(component->dev, "Unsupported frame size: %d\n",
  576. frame_size);
  577. return -EINVAL;
  578. }
  579. bclk_ms = frame_size > 32;
  580. rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
  581. dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  582. bclk_ms, pre_div, dai->id);
  583. dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  584. rt1305->lrck, pre_div, dai->id);
  585. switch (params_width(params)) {
  586. case 16:
  587. val_len |= RT1305_I2S_DL_SEL_16B;
  588. break;
  589. case 20:
  590. val_len |= RT1305_I2S_DL_SEL_20B;
  591. break;
  592. case 24:
  593. val_len |= RT1305_I2S_DL_SEL_24B;
  594. break;
  595. case 8:
  596. val_len |= RT1305_I2S_DL_SEL_8B;
  597. break;
  598. default:
  599. return -EINVAL;
  600. }
  601. switch (dai->id) {
  602. case RT1305_AIF1:
  603. mask_clk = RT1305_DIV_FS_SYS_MASK;
  604. val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
  605. snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
  606. RT1305_I2S_DL_SEL_MASK,
  607. val_len);
  608. break;
  609. default:
  610. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  611. return -EINVAL;
  612. }
  613. snd_soc_component_update_bits(component, RT1305_CLK_2,
  614. mask_clk, val_clk);
  615. return 0;
  616. }
  617. static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  618. {
  619. struct snd_soc_component *component = dai->component;
  620. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  621. unsigned int reg_val = 0, reg1_val = 0;
  622. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  623. case SND_SOC_DAIFMT_CBM_CFM:
  624. reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
  625. rt1305->master = 1;
  626. break;
  627. case SND_SOC_DAIFMT_CBS_CFS:
  628. reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
  629. rt1305->master = 0;
  630. break;
  631. default:
  632. return -EINVAL;
  633. }
  634. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  635. case SND_SOC_DAIFMT_NB_NF:
  636. break;
  637. case SND_SOC_DAIFMT_IB_NF:
  638. reg1_val |= RT1305_I2S_BCLK_INV;
  639. break;
  640. default:
  641. return -EINVAL;
  642. }
  643. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  644. case SND_SOC_DAIFMT_I2S:
  645. break;
  646. case SND_SOC_DAIFMT_LEFT_J:
  647. reg1_val |= RT1305_I2S_DF_SEL_LEFT;
  648. break;
  649. case SND_SOC_DAIFMT_DSP_A:
  650. reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
  651. break;
  652. case SND_SOC_DAIFMT_DSP_B:
  653. reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
  654. break;
  655. default:
  656. return -EINVAL;
  657. }
  658. switch (dai->id) {
  659. case RT1305_AIF1:
  660. snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
  661. RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
  662. snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
  663. RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
  664. reg1_val);
  665. break;
  666. default:
  667. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  668. return -EINVAL;
  669. }
  670. return 0;
  671. }
  672. static int rt1305_set_component_sysclk(struct snd_soc_component *component,
  673. int clk_id, int source, unsigned int freq, int dir)
  674. {
  675. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  676. unsigned int reg_val = 0;
  677. if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
  678. return 0;
  679. switch (clk_id) {
  680. case RT1305_FS_SYS_PRE_S_MCLK:
  681. reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
  682. snd_soc_component_update_bits(component,
  683. RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
  684. RT1305_SEL_CLK_DET_SRC_MCLK);
  685. break;
  686. case RT1305_FS_SYS_PRE_S_PLL1:
  687. reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
  688. break;
  689. case RT1305_FS_SYS_PRE_S_RCCLK:
  690. reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
  691. break;
  692. default:
  693. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  694. return -EINVAL;
  695. }
  696. snd_soc_component_update_bits(component, RT1305_CLK_1,
  697. RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
  698. rt1305->sysclk = freq;
  699. rt1305->sysclk_src = clk_id;
  700. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  701. freq, clk_id);
  702. return 0;
  703. }
  704. static int rt1305_set_component_pll(struct snd_soc_component *component,
  705. int pll_id, int source, unsigned int freq_in,
  706. unsigned int freq_out)
  707. {
  708. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  709. struct rl6231_pll_code pll_code;
  710. int ret;
  711. if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
  712. freq_out == rt1305->pll_out)
  713. return 0;
  714. if (!freq_in || !freq_out) {
  715. dev_dbg(component->dev, "PLL disabled\n");
  716. rt1305->pll_in = 0;
  717. rt1305->pll_out = 0;
  718. snd_soc_component_update_bits(component, RT1305_CLK_1,
  719. RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
  720. RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
  721. return 0;
  722. }
  723. switch (source) {
  724. case RT1305_PLL2_S_MCLK:
  725. snd_soc_component_update_bits(component, RT1305_CLK_1,
  726. RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
  727. RT1305_DIV_PLL_SRC_2_MASK,
  728. RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
  729. snd_soc_component_update_bits(component,
  730. RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
  731. RT1305_SEL_CLK_DET_SRC_MCLK);
  732. break;
  733. case RT1305_PLL1_S_BCLK:
  734. snd_soc_component_update_bits(component,
  735. RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
  736. RT1305_SEL_PLL_SRC_1_BCLK);
  737. break;
  738. case RT1305_PLL2_S_RCCLK:
  739. snd_soc_component_update_bits(component, RT1305_CLK_1,
  740. RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
  741. RT1305_DIV_PLL_SRC_2_MASK,
  742. RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
  743. freq_in = 98304000;
  744. break;
  745. default:
  746. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  747. return -EINVAL;
  748. }
  749. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  750. if (ret < 0) {
  751. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  752. return ret;
  753. }
  754. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  755. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  756. pll_code.n_code, pll_code.k_code);
  757. snd_soc_component_write(component, RT1305_PLL1_1,
  758. (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
  759. pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
  760. pll_code.n_code);
  761. snd_soc_component_write(component, RT1305_PLL1_2,
  762. pll_code.k_code);
  763. rt1305->pll_in = freq_in;
  764. rt1305->pll_out = freq_out;
  765. rt1305->pll_src = source;
  766. return 0;
  767. }
  768. static int rt1305_probe(struct snd_soc_component *component)
  769. {
  770. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  771. rt1305->component = component;
  772. /* initial settings */
  773. rt1305_reg_init(component);
  774. return 0;
  775. }
  776. static void rt1305_remove(struct snd_soc_component *component)
  777. {
  778. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  779. rt1305_reset(rt1305->regmap);
  780. }
  781. #ifdef CONFIG_PM
  782. static int rt1305_suspend(struct snd_soc_component *component)
  783. {
  784. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  785. regcache_cache_only(rt1305->regmap, true);
  786. regcache_mark_dirty(rt1305->regmap);
  787. return 0;
  788. }
  789. static int rt1305_resume(struct snd_soc_component *component)
  790. {
  791. struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
  792. regcache_cache_only(rt1305->regmap, false);
  793. regcache_sync(rt1305->regmap);
  794. return 0;
  795. }
  796. #else
  797. #define rt1305_suspend NULL
  798. #define rt1305_resume NULL
  799. #endif
  800. #define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
  801. #define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
  802. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
  803. SNDRV_PCM_FMTBIT_S24_LE)
  804. static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
  805. .hw_params = rt1305_hw_params,
  806. .set_fmt = rt1305_set_dai_fmt,
  807. };
  808. static struct snd_soc_dai_driver rt1305_dai[] = {
  809. {
  810. .name = "rt1305-aif",
  811. .playback = {
  812. .stream_name = "AIF1 Playback",
  813. .channels_min = 1,
  814. .channels_max = 2,
  815. .rates = RT1305_STEREO_RATES,
  816. .formats = RT1305_FORMATS,
  817. },
  818. .ops = &rt1305_aif_dai_ops,
  819. },
  820. };
  821. static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
  822. .probe = rt1305_probe,
  823. .remove = rt1305_remove,
  824. .suspend = rt1305_suspend,
  825. .resume = rt1305_resume,
  826. .controls = rt1305_snd_controls,
  827. .num_controls = ARRAY_SIZE(rt1305_snd_controls),
  828. .dapm_widgets = rt1305_dapm_widgets,
  829. .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
  830. .dapm_routes = rt1305_dapm_routes,
  831. .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
  832. .set_sysclk = rt1305_set_component_sysclk,
  833. .set_pll = rt1305_set_component_pll,
  834. .use_pmdown_time = 1,
  835. .endianness = 1,
  836. .non_legacy_dai_naming = 1,
  837. };
  838. static const struct regmap_config rt1305_regmap = {
  839. .reg_bits = 8,
  840. .val_bits = 16,
  841. .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
  842. RT1305_PR_SPACING),
  843. .volatile_reg = rt1305_volatile_register,
  844. .readable_reg = rt1305_readable_register,
  845. .cache_type = REGCACHE_RBTREE,
  846. .reg_defaults = rt1305_reg,
  847. .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
  848. .ranges = rt1305_ranges,
  849. .num_ranges = ARRAY_SIZE(rt1305_ranges),
  850. .use_single_read = true,
  851. .use_single_write = true,
  852. };
  853. #if defined(CONFIG_OF)
  854. static const struct of_device_id rt1305_of_match[] = {
  855. { .compatible = "realtek,rt1305", },
  856. { .compatible = "realtek,rt1306", },
  857. {},
  858. };
  859. MODULE_DEVICE_TABLE(of, rt1305_of_match);
  860. #endif
  861. #ifdef CONFIG_ACPI
  862. static struct acpi_device_id rt1305_acpi_match[] = {
  863. {"10EC1305", 0,},
  864. {"10EC1306", 0,},
  865. {},
  866. };
  867. MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
  868. #endif
  869. static const struct i2c_device_id rt1305_i2c_id[] = {
  870. { "rt1305", 0 },
  871. { "rt1306", 0 },
  872. { }
  873. };
  874. MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
  875. static void rt1305_calibrate(struct rt1305_priv *rt1305)
  876. {
  877. unsigned int valmsb, vallsb, offsetl, offsetr;
  878. unsigned int rh, rl, rhl, r0ohm;
  879. u64 r0l, r0r;
  880. regcache_cache_bypass(rt1305->regmap, true);
  881. rt1305_reset(rt1305->regmap);
  882. regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
  883. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
  884. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
  885. regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
  886. regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
  887. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
  888. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
  889. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
  890. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
  891. /* Sin Gen */
  892. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
  893. regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
  894. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
  895. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
  896. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
  897. regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
  898. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
  899. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
  900. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
  901. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
  902. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
  903. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
  904. /* EFUSE read */
  905. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
  906. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
  907. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
  908. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
  909. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
  910. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
  911. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
  912. regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
  913. regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
  914. regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
  915. offsetl = valmsb << 16 | vallsb;
  916. regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
  917. regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
  918. offsetr = valmsb << 16 | vallsb;
  919. pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
  920. /* R0 calibration */
  921. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
  922. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
  923. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
  924. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
  925. regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
  926. regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
  927. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
  928. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
  929. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
  930. regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
  931. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
  932. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
  933. msleep(2000);
  934. regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
  935. regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
  936. rhl = (rh << 16) | rl;
  937. r0ohm = (rhl*10) / 33554432;
  938. pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
  939. pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
  940. r0l = 562949953421312ULL;
  941. if (rhl != 0)
  942. do_div(r0l, rhl);
  943. pr_debug("Left_r0 = 0x%llx\n", r0l);
  944. regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
  945. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
  946. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
  947. msleep(2000);
  948. regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
  949. regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
  950. rhl = (rh << 16) | rl;
  951. r0ohm = (rhl*10) / 33554432;
  952. pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
  953. pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
  954. r0r = 562949953421312ULL;
  955. if (rhl != 0)
  956. do_div(r0r, rhl);
  957. pr_debug("Right_r0 = 0x%llx\n", r0r);
  958. regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
  959. if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
  960. (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
  961. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
  962. (r0l >> 16) & 0xffff);
  963. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
  964. r0l & 0xffff);
  965. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
  966. ((r0r >> 16) & 0xffff) | 0xf800);
  967. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
  968. r0r & 0xffff);
  969. } else {
  970. pr_err("R0 calibration failed\n");
  971. }
  972. /* restore some registers */
  973. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
  974. usleep_range(200000, 400000);
  975. regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
  976. regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
  977. regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
  978. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
  979. regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
  980. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
  981. regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
  982. regcache_cache_bypass(rt1305->regmap, false);
  983. }
  984. static int rt1305_i2c_probe(struct i2c_client *i2c,
  985. const struct i2c_device_id *id)
  986. {
  987. struct rt1305_priv *rt1305;
  988. int ret;
  989. unsigned int val;
  990. rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
  991. GFP_KERNEL);
  992. if (rt1305 == NULL)
  993. return -ENOMEM;
  994. i2c_set_clientdata(i2c, rt1305);
  995. rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
  996. if (IS_ERR(rt1305->regmap)) {
  997. ret = PTR_ERR(rt1305->regmap);
  998. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  999. ret);
  1000. return ret;
  1001. }
  1002. regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
  1003. if (val != RT1305_DEVICE_ID_NUM) {
  1004. dev_err(&i2c->dev,
  1005. "Device with ID register %x is not rt1305\n", val);
  1006. return -ENODEV;
  1007. }
  1008. rt1305_reset(rt1305->regmap);
  1009. rt1305_calibrate(rt1305);
  1010. return devm_snd_soc_register_component(&i2c->dev,
  1011. &soc_component_dev_rt1305,
  1012. rt1305_dai, ARRAY_SIZE(rt1305_dai));
  1013. }
  1014. static void rt1305_i2c_shutdown(struct i2c_client *client)
  1015. {
  1016. struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
  1017. rt1305_reset(rt1305->regmap);
  1018. }
  1019. static struct i2c_driver rt1305_i2c_driver = {
  1020. .driver = {
  1021. .name = "rt1305",
  1022. #if defined(CONFIG_OF)
  1023. .of_match_table = rt1305_of_match,
  1024. #endif
  1025. #if defined(CONFIG_ACPI)
  1026. .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
  1027. #endif
  1028. },
  1029. .probe = rt1305_i2c_probe,
  1030. .shutdown = rt1305_i2c_shutdown,
  1031. .id_table = rt1305_i2c_id,
  1032. };
  1033. module_i2c_driver(rt1305_i2c_driver);
  1034. MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
  1035. MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
  1036. MODULE_LICENSE("GPL v2");