rt1016.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // rt1016.c -- RT1016 ALSA SoC audio amplifier driver
  4. //
  5. // Copyright 2020 Realtek Semiconductor Corp.
  6. // Author: Oder Chiou <oder_chiou@realtek.com>
  7. //
  8. #include <linux/fs.h>
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/regmap.h>
  15. #include <linux/i2c.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/firmware.h>
  18. #include <linux/gpio.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/soc-dapm.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include "rl6231.h"
  27. #include "rt1016.h"
  28. static const struct reg_sequence rt1016_patch[] = {
  29. {RT1016_VOL_CTRL_3, 0x8900},
  30. {RT1016_ANA_CTRL_1, 0xa002},
  31. {RT1016_ANA_CTRL_2, 0x0002},
  32. {RT1016_CLOCK_4, 0x6700},
  33. {RT1016_CLASSD_3, 0xdc55},
  34. {RT1016_CLASSD_4, 0x376a},
  35. {RT1016_CLASSD_5, 0x009f},
  36. };
  37. static const struct reg_default rt1016_reg[] = {
  38. {0x00, 0x0000},
  39. {0x01, 0x5400},
  40. {0x02, 0x5506},
  41. {0x03, 0xf800},
  42. {0x04, 0x0000},
  43. {0x05, 0xbfbf},
  44. {0x06, 0x8900},
  45. {0x07, 0xa002},
  46. {0x08, 0x0000},
  47. {0x09, 0x0000},
  48. {0x0a, 0x0000},
  49. {0x0c, 0x0000},
  50. {0x0d, 0x0000},
  51. {0x0e, 0x10ec},
  52. {0x0f, 0x6595},
  53. {0x11, 0x0002},
  54. {0x1c, 0x0000},
  55. {0x1d, 0x0000},
  56. {0x1e, 0x0000},
  57. {0x1f, 0xf000},
  58. {0x20, 0x0000},
  59. {0x21, 0x6000},
  60. {0x22, 0x0000},
  61. {0x23, 0x6700},
  62. {0x24, 0x0000},
  63. {0x25, 0x0000},
  64. {0x26, 0x0000},
  65. {0x40, 0x0018},
  66. {0x60, 0x00a5},
  67. {0x80, 0x0010},
  68. {0x81, 0x0009},
  69. {0x82, 0x0000},
  70. {0x83, 0x0000},
  71. {0xa0, 0x0700},
  72. {0xc0, 0x0080},
  73. {0xc1, 0x02a0},
  74. {0xc2, 0x1400},
  75. {0xc3, 0x0a4a},
  76. {0xc4, 0x552a},
  77. {0xc5, 0x087e},
  78. {0xc6, 0x0020},
  79. {0xc7, 0xa833},
  80. {0xc8, 0x0433},
  81. {0xc9, 0x8040},
  82. {0xca, 0xdc55},
  83. {0xcb, 0x376a},
  84. {0xcc, 0x009f},
  85. {0xcf, 0x0020},
  86. };
  87. static bool rt1016_volatile_register(struct device *dev, unsigned int reg)
  88. {
  89. switch (reg) {
  90. case RT1016_ANA_FLAG:
  91. case RT1016_VERSION2_ID:
  92. case RT1016_VERSION1_ID:
  93. case RT1016_VENDER_ID:
  94. case RT1016_DEVICE_ID:
  95. case RT1016_TEST_SIGNAL:
  96. case RT1016_SC_CTRL_1:
  97. return true;
  98. default:
  99. return false;
  100. }
  101. }
  102. static bool rt1016_readable_register(struct device *dev, unsigned int reg)
  103. {
  104. switch (reg) {
  105. case RT1016_RESET:
  106. case RT1016_PADS_CTRL_1:
  107. case RT1016_PADS_CTRL_2:
  108. case RT1016_I2C_CTRL:
  109. case RT1016_VOL_CTRL_1:
  110. case RT1016_VOL_CTRL_2:
  111. case RT1016_VOL_CTRL_3:
  112. case RT1016_ANA_CTRL_1:
  113. case RT1016_MUX_SEL:
  114. case RT1016_RX_I2S_CTRL:
  115. case RT1016_ANA_FLAG:
  116. case RT1016_VERSION2_ID:
  117. case RT1016_VERSION1_ID:
  118. case RT1016_VENDER_ID:
  119. case RT1016_DEVICE_ID:
  120. case RT1016_ANA_CTRL_2:
  121. case RT1016_TEST_SIGNAL:
  122. case RT1016_TEST_CTRL_1:
  123. case RT1016_TEST_CTRL_2:
  124. case RT1016_TEST_CTRL_3:
  125. case RT1016_CLOCK_1:
  126. case RT1016_CLOCK_2:
  127. case RT1016_CLOCK_3:
  128. case RT1016_CLOCK_4:
  129. case RT1016_CLOCK_5:
  130. case RT1016_CLOCK_6:
  131. case RT1016_CLOCK_7:
  132. case RT1016_I2S_CTRL:
  133. case RT1016_DAC_CTRL_1:
  134. case RT1016_SC_CTRL_1:
  135. case RT1016_SC_CTRL_2:
  136. case RT1016_SC_CTRL_3:
  137. case RT1016_SC_CTRL_4:
  138. case RT1016_SIL_DET:
  139. case RT1016_SYS_CLK:
  140. case RT1016_BIAS_CUR:
  141. case RT1016_DAC_CTRL_2:
  142. case RT1016_LDO_CTRL:
  143. case RT1016_CLASSD_1:
  144. case RT1016_PLL1:
  145. case RT1016_PLL2:
  146. case RT1016_PLL3:
  147. case RT1016_CLASSD_2:
  148. case RT1016_CLASSD_OUT:
  149. case RT1016_CLASSD_3:
  150. case RT1016_CLASSD_4:
  151. case RT1016_CLASSD_5:
  152. case RT1016_PWR_CTRL:
  153. return true;
  154. default:
  155. return false;
  156. }
  157. }
  158. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
  159. static const struct snd_kcontrol_new rt1016_snd_controls[] = {
  160. SOC_DOUBLE_TLV("DAC Playback Volume", RT1016_VOL_CTRL_2,
  161. RT1016_L_VOL_SFT, RT1016_R_VOL_SFT, 191, 0, dac_vol_tlv),
  162. SOC_DOUBLE("DAC Playback Switch", RT1016_VOL_CTRL_1,
  163. RT1016_DA_MUTE_L_SFT, RT1016_DA_MUTE_R_SFT, 1, 1),
  164. };
  165. static int rt1016_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  166. struct snd_soc_dapm_widget *sink)
  167. {
  168. struct snd_soc_component *component =
  169. snd_soc_dapm_to_component(source->dapm);
  170. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  171. if (rt1016->sysclk_src == RT1016_SCLK_S_PLL)
  172. return 1;
  173. else
  174. return 0;
  175. }
  176. /* Interface data select */
  177. static const char * const rt1016_data_select[] = {
  178. "L/R", "R/L", "L/L", "R/R"
  179. };
  180. static SOC_ENUM_SINGLE_DECL(rt1016_if_data_swap_enum,
  181. RT1016_I2S_CTRL, RT1016_I2S_DATA_SWAP_SFT, rt1016_data_select);
  182. static const struct snd_kcontrol_new rt1016_if_data_swap_mux =
  183. SOC_DAPM_ENUM("Data Swap Mux", rt1016_if_data_swap_enum);
  184. static const struct snd_soc_dapm_widget rt1016_dapm_widgets[] = {
  185. SND_SOC_DAPM_MUX("Data Swap Mux", SND_SOC_NOPM, 0, 0,
  186. &rt1016_if_data_swap_mux),
  187. SND_SOC_DAPM_SUPPLY("DAC Filter", RT1016_CLOCK_3,
  188. RT1016_PWR_DAC_FILTER_BIT, 0, NULL, 0),
  189. SND_SOC_DAPM_SUPPLY("DAMOD", RT1016_CLOCK_3, RT1016_PWR_DACMOD_BIT, 0,
  190. NULL, 0),
  191. SND_SOC_DAPM_SUPPLY("FIFO", RT1016_CLOCK_3, RT1016_PWR_CLK_FIFO_BIT, 0,
  192. NULL, 0),
  193. SND_SOC_DAPM_SUPPLY("Pure DC", RT1016_CLOCK_3,
  194. RT1016_PWR_CLK_PUREDC_BIT, 0, NULL, 0),
  195. SND_SOC_DAPM_SUPPLY("CLK Silence Det", RT1016_CLOCK_3,
  196. RT1016_PWR_SIL_DET_BIT, 0, NULL, 0),
  197. SND_SOC_DAPM_SUPPLY("RC 25M", RT1016_CLOCK_3, RT1016_PWR_RC_25M_BIT, 0,
  198. NULL, 0),
  199. SND_SOC_DAPM_SUPPLY("PLL1", RT1016_CLOCK_3, RT1016_PWR_PLL1_BIT, 0,
  200. NULL, 0),
  201. SND_SOC_DAPM_SUPPLY("ANA CTRL", RT1016_CLOCK_3, RT1016_PWR_ANA_CTRL_BIT,
  202. 0, NULL, 0),
  203. SND_SOC_DAPM_SUPPLY("CLK SYS", RT1016_CLOCK_3, RT1016_PWR_CLK_SYS_BIT,
  204. 0, NULL, 0),
  205. SND_SOC_DAPM_SUPPLY("LRCK Det", RT1016_CLOCK_4, RT1016_PWR_LRCK_DET_BIT,
  206. 0, NULL, 0),
  207. SND_SOC_DAPM_SUPPLY("BCLK Det", RT1016_CLOCK_4, RT1016_PWR_BCLK_DET_BIT,
  208. 0, NULL, 0),
  209. SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1016_DAC_CTRL_2,
  210. RT1016_CKGEN_DAC_BIT, 0, NULL, 0),
  211. SND_SOC_DAPM_SUPPLY("VCM SLOW", RT1016_CLASSD_1, RT1016_VCM_SLOW_BIT, 0,
  212. NULL, 0),
  213. SND_SOC_DAPM_SUPPLY("Silence Det", RT1016_SIL_DET,
  214. RT1016_SIL_DET_EN_BIT, 0, NULL, 0),
  215. SND_SOC_DAPM_SUPPLY("PLL2", RT1016_PLL2, RT1016_PLL2_EN_BIT, 0, NULL,
  216. 0),
  217. SND_SOC_DAPM_SUPPLY_S("BG1 BG2", 1, RT1016_PWR_CTRL,
  218. RT1016_PWR_BG_1_2_BIT, 0, NULL, 0),
  219. SND_SOC_DAPM_SUPPLY_S("MBIAS BG", 1, RT1016_PWR_CTRL,
  220. RT1016_PWR_MBIAS_BG_BIT, 0, NULL, 0),
  221. SND_SOC_DAPM_SUPPLY_S("PLL", 1, RT1016_PWR_CTRL, RT1016_PWR_PLL_BIT, 0,
  222. NULL, 0),
  223. SND_SOC_DAPM_SUPPLY_S("BASIC", 1, RT1016_PWR_CTRL, RT1016_PWR_BASIC_BIT,
  224. 0, NULL, 0),
  225. SND_SOC_DAPM_SUPPLY_S("CLASS D", 1, RT1016_PWR_CTRL,
  226. RT1016_PWR_CLSD_BIT, 0, NULL, 0),
  227. SND_SOC_DAPM_SUPPLY_S("25M", 1, RT1016_PWR_CTRL, RT1016_PWR_25M_BIT, 0,
  228. NULL, 0),
  229. SND_SOC_DAPM_SUPPLY_S("DACL", 1, RT1016_PWR_CTRL, RT1016_PWR_DACL_BIT,
  230. 0, NULL, 0),
  231. SND_SOC_DAPM_SUPPLY_S("DACR", 1, RT1016_PWR_CTRL, RT1016_PWR_DACR_BIT,
  232. 0, NULL, 0),
  233. SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT1016_PWR_CTRL, RT1016_PWR_LDO2_BIT,
  234. 0, NULL, 0),
  235. SND_SOC_DAPM_SUPPLY_S("VREF", 1, RT1016_PWR_CTRL, RT1016_PWR_VREF_BIT,
  236. 0, NULL, 0),
  237. SND_SOC_DAPM_SUPPLY_S("MBIAS", 1, RT1016_PWR_CTRL, RT1016_PWR_MBIAS_BIT,
  238. 0, NULL, 0),
  239. SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
  240. SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
  241. SND_SOC_DAPM_OUTPUT("SPO"),
  242. };
  243. static const struct snd_soc_dapm_route rt1016_dapm_routes[] = {
  244. { "Data Swap Mux", "L/R", "AIFRX" },
  245. { "Data Swap Mux", "R/L", "AIFRX" },
  246. { "Data Swap Mux", "L/L", "AIFRX" },
  247. { "Data Swap Mux", "R/R", "AIFRX" },
  248. { "DAC", NULL, "DAC Filter" },
  249. { "DAC", NULL, "DAMOD" },
  250. { "DAC", NULL, "FIFO" },
  251. { "DAC", NULL, "Pure DC" },
  252. { "DAC", NULL, "Silence Det" },
  253. { "DAC", NULL, "ANA CTRL" },
  254. { "DAC", NULL, "CLK SYS" },
  255. { "DAC", NULL, "LRCK Det" },
  256. { "DAC", NULL, "BCLK Det" },
  257. { "DAC", NULL, "CKGEN DAC" },
  258. { "DAC", NULL, "VCM SLOW" },
  259. { "PLL", NULL, "PLL1" },
  260. { "PLL", NULL, "PLL2" },
  261. { "25M", NULL, "RC 25M" },
  262. { "Silence Det", NULL, "CLK Silence Det" },
  263. { "DAC", NULL, "Data Swap Mux" },
  264. { "DAC", NULL, "BG1 BG2" },
  265. { "DAC", NULL, "MBIAS BG" },
  266. { "DAC", NULL, "PLL", rt1016_is_sys_clk_from_pll},
  267. { "DAC", NULL, "BASIC" },
  268. { "DAC", NULL, "CLASS D" },
  269. { "DAC", NULL, "25M" },
  270. { "DAC", NULL, "DACL" },
  271. { "DAC", NULL, "DACR" },
  272. { "DAC", NULL, "LDO2" },
  273. { "DAC", NULL, "VREF" },
  274. { "DAC", NULL, "MBIAS" },
  275. { "SPO", NULL, "DAC" },
  276. };
  277. static int rt1016_hw_params(struct snd_pcm_substream *substream,
  278. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  279. {
  280. struct snd_soc_component *component = dai->component;
  281. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  282. int pre_div, bclk_ms, frame_size;
  283. unsigned int val_len = 0;
  284. rt1016->lrck = params_rate(params);
  285. pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck);
  286. if (pre_div < 0) {
  287. dev_err(component->dev, "Unsupported clock rate\n");
  288. return -EINVAL;
  289. }
  290. frame_size = snd_soc_params_to_frame_size(params);
  291. if (frame_size < 0) {
  292. dev_err(component->dev, "Unsupported frame size: %d\n",
  293. frame_size);
  294. return -EINVAL;
  295. }
  296. bclk_ms = frame_size > 32;
  297. rt1016->bclk = rt1016->lrck * (32 << bclk_ms);
  298. if (bclk_ms && rt1016->master)
  299. snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
  300. RT1016_I2S_BCLK_MS_MASK, RT1016_I2S_BCLK_MS_64);
  301. dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  302. rt1016->lrck, pre_div, dai->id);
  303. switch (params_width(params)) {
  304. case 16:
  305. val_len = RT1016_I2S_DL_16;
  306. break;
  307. case 20:
  308. val_len = RT1016_I2S_DL_20;
  309. break;
  310. case 24:
  311. val_len = RT1016_I2S_DL_24;
  312. break;
  313. case 32:
  314. val_len = RT1016_I2S_DL_32;
  315. break;
  316. default:
  317. return -EINVAL;
  318. }
  319. snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
  320. RT1016_I2S_DL_MASK, val_len);
  321. snd_soc_component_update_bits(component, RT1016_CLOCK_2,
  322. RT1016_FS_PD_MASK | RT1016_OSR_PD_MASK,
  323. ((pre_div + 3) << RT1016_FS_PD_SFT) |
  324. (pre_div << RT1016_OSR_PD_SFT));
  325. return 0;
  326. }
  327. static int rt1016_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  328. {
  329. struct snd_soc_component *component = dai->component;
  330. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  331. unsigned int reg_val = 0;
  332. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  333. case SND_SOC_DAIFMT_CBM_CFM:
  334. reg_val |= RT1016_I2S_MS_M;
  335. rt1016->master = 1;
  336. break;
  337. case SND_SOC_DAIFMT_CBS_CFS:
  338. reg_val |= RT1016_I2S_MS_S;
  339. break;
  340. default:
  341. return -EINVAL;
  342. }
  343. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  344. case SND_SOC_DAIFMT_NB_NF:
  345. break;
  346. case SND_SOC_DAIFMT_IB_NF:
  347. reg_val |= RT1016_I2S_BCLK_POL_INV;
  348. break;
  349. default:
  350. return -EINVAL;
  351. }
  352. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  353. case SND_SOC_DAIFMT_I2S:
  354. break;
  355. case SND_SOC_DAIFMT_LEFT_J:
  356. reg_val |= RT1016_I2S_DF_LEFT;
  357. break;
  358. case SND_SOC_DAIFMT_DSP_A:
  359. reg_val |= RT1016_I2S_DF_PCM_A;
  360. break;
  361. case SND_SOC_DAIFMT_DSP_B:
  362. reg_val |= RT1016_I2S_DF_PCM_B;
  363. break;
  364. default:
  365. return -EINVAL;
  366. }
  367. snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
  368. RT1016_I2S_MS_MASK | RT1016_I2S_BCLK_POL_MASK |
  369. RT1016_I2S_DF_MASK, reg_val);
  370. return 0;
  371. }
  372. static int rt1016_set_component_sysclk(struct snd_soc_component *component,
  373. int clk_id, int source, unsigned int freq, int dir)
  374. {
  375. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  376. unsigned int reg_val = 0;
  377. if (freq == rt1016->sysclk && clk_id == rt1016->sysclk_src)
  378. return 0;
  379. switch (clk_id) {
  380. case RT1016_SCLK_S_MCLK:
  381. reg_val |= RT1016_CLK_SYS_SEL_MCLK;
  382. break;
  383. case RT1016_SCLK_S_PLL:
  384. reg_val |= RT1016_CLK_SYS_SEL_PLL;
  385. break;
  386. default:
  387. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  388. return -EINVAL;
  389. }
  390. rt1016->sysclk = freq;
  391. rt1016->sysclk_src = clk_id;
  392. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  393. freq, clk_id);
  394. snd_soc_component_update_bits(component, RT1016_CLOCK_1,
  395. RT1016_CLK_SYS_SEL_MASK, reg_val);
  396. return 0;
  397. }
  398. static int rt1016_set_component_pll(struct snd_soc_component *component,
  399. int pll_id, int source, unsigned int freq_in,
  400. unsigned int freq_out)
  401. {
  402. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  403. struct rl6231_pll_code pll_code;
  404. int ret;
  405. if (!freq_in || !freq_out) {
  406. dev_dbg(component->dev, "PLL disabled\n");
  407. rt1016->pll_in = 0;
  408. rt1016->pll_out = 0;
  409. return 0;
  410. }
  411. if (source == rt1016->pll_src && freq_in == rt1016->pll_in &&
  412. freq_out == rt1016->pll_out)
  413. return 0;
  414. switch (source) {
  415. case RT1016_PLL_S_MCLK:
  416. snd_soc_component_update_bits(component, RT1016_CLOCK_1,
  417. RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_MCLK);
  418. break;
  419. case RT1016_PLL_S_BCLK:
  420. snd_soc_component_update_bits(component, RT1016_CLOCK_1,
  421. RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_BCLK);
  422. break;
  423. default:
  424. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  425. return -EINVAL;
  426. }
  427. ret = rl6231_pll_calc(freq_in, freq_out * 4, &pll_code);
  428. if (ret < 0) {
  429. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  430. return ret;
  431. }
  432. dev_dbg(component->dev, "mbypass=%d m=%d n=%d kbypass=%d k=%d\n",
  433. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  434. pll_code.n_code, pll_code.k_bp,
  435. (pll_code.k_bp ? 0 : pll_code.k_code));
  436. snd_soc_component_write(component, RT1016_PLL1,
  437. (pll_code.m_bp ? 0 : pll_code.m_code) << RT1016_PLL_M_SFT |
  438. pll_code.m_bp << RT1016_PLL_M_BP_SFT | pll_code.n_code);
  439. snd_soc_component_write(component, RT1016_PLL2,
  440. pll_code.k_bp << RT1016_PLL_K_BP_SFT |
  441. (pll_code.k_bp ? 0 : pll_code.k_code));
  442. rt1016->pll_in = freq_in;
  443. rt1016->pll_out = freq_out;
  444. rt1016->pll_src = source;
  445. return 0;
  446. }
  447. static int rt1016_probe(struct snd_soc_component *component)
  448. {
  449. struct rt1016_priv *rt1016 =
  450. snd_soc_component_get_drvdata(component);
  451. rt1016->component = component;
  452. return 0;
  453. }
  454. static void rt1016_remove(struct snd_soc_component *component)
  455. {
  456. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  457. regmap_write(rt1016->regmap, RT1016_RESET, 0);
  458. }
  459. #define RT1016_STEREO_RATES SNDRV_PCM_RATE_8000_48000
  460. #define RT1016_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  461. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  462. static struct snd_soc_dai_ops rt1016_aif_dai_ops = {
  463. .hw_params = rt1016_hw_params,
  464. .set_fmt = rt1016_set_dai_fmt,
  465. };
  466. static struct snd_soc_dai_driver rt1016_dai[] = {
  467. {
  468. .name = "rt1016-aif",
  469. .id = 0,
  470. .playback = {
  471. .stream_name = "AIF Playback",
  472. .channels_min = 1,
  473. .channels_max = 2,
  474. .rates = RT1016_STEREO_RATES,
  475. .formats = RT1016_FORMATS,
  476. },
  477. .ops = &rt1016_aif_dai_ops,
  478. }
  479. };
  480. #ifdef CONFIG_PM
  481. static int rt1016_suspend(struct snd_soc_component *component)
  482. {
  483. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  484. regcache_cache_only(rt1016->regmap, true);
  485. regcache_mark_dirty(rt1016->regmap);
  486. return 0;
  487. }
  488. static int rt1016_resume(struct snd_soc_component *component)
  489. {
  490. struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
  491. regcache_cache_only(rt1016->regmap, false);
  492. regcache_sync(rt1016->regmap);
  493. return 0;
  494. }
  495. #else
  496. #define rt1016_suspend NULL
  497. #define rt1016_resume NULL
  498. #endif
  499. static const struct snd_soc_component_driver soc_component_dev_rt1016 = {
  500. .probe = rt1016_probe,
  501. .remove = rt1016_remove,
  502. .suspend = rt1016_suspend,
  503. .resume = rt1016_resume,
  504. .controls = rt1016_snd_controls,
  505. .num_controls = ARRAY_SIZE(rt1016_snd_controls),
  506. .dapm_widgets = rt1016_dapm_widgets,
  507. .num_dapm_widgets = ARRAY_SIZE(rt1016_dapm_widgets),
  508. .dapm_routes = rt1016_dapm_routes,
  509. .num_dapm_routes = ARRAY_SIZE(rt1016_dapm_routes),
  510. .set_sysclk = rt1016_set_component_sysclk,
  511. .set_pll = rt1016_set_component_pll,
  512. .use_pmdown_time = 1,
  513. .endianness = 1,
  514. .non_legacy_dai_naming = 1,
  515. };
  516. static const struct regmap_config rt1016_regmap = {
  517. .reg_bits = 8,
  518. .val_bits = 16,
  519. .max_register = RT1016_PWR_CTRL,
  520. .volatile_reg = rt1016_volatile_register,
  521. .readable_reg = rt1016_readable_register,
  522. .cache_type = REGCACHE_RBTREE,
  523. .reg_defaults = rt1016_reg,
  524. .num_reg_defaults = ARRAY_SIZE(rt1016_reg),
  525. };
  526. static const struct i2c_device_id rt1016_i2c_id[] = {
  527. { "rt1016", 0 },
  528. { }
  529. };
  530. MODULE_DEVICE_TABLE(i2c, rt1016_i2c_id);
  531. #if defined(CONFIG_OF)
  532. static const struct of_device_id rt1016_of_match[] = {
  533. { .compatible = "realtek,rt1016", },
  534. {},
  535. };
  536. MODULE_DEVICE_TABLE(of, rt1016_of_match);
  537. #endif
  538. #ifdef CONFIG_ACPI
  539. static struct acpi_device_id rt1016_acpi_match[] = {
  540. {"10EC1016", 0,},
  541. {},
  542. };
  543. MODULE_DEVICE_TABLE(acpi, rt1016_acpi_match);
  544. #endif
  545. static int rt1016_i2c_probe(struct i2c_client *i2c,
  546. const struct i2c_device_id *id)
  547. {
  548. struct rt1016_priv *rt1016;
  549. int ret;
  550. unsigned int val;
  551. rt1016 = devm_kzalloc(&i2c->dev, sizeof(struct rt1016_priv),
  552. GFP_KERNEL);
  553. if (rt1016 == NULL)
  554. return -ENOMEM;
  555. i2c_set_clientdata(i2c, rt1016);
  556. rt1016->regmap = devm_regmap_init_i2c(i2c, &rt1016_regmap);
  557. if (IS_ERR(rt1016->regmap)) {
  558. ret = PTR_ERR(rt1016->regmap);
  559. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  560. ret);
  561. return ret;
  562. }
  563. regmap_read(rt1016->regmap, RT1016_DEVICE_ID, &val);
  564. if (val != RT1016_DEVICE_ID_VAL) {
  565. dev_err(&i2c->dev,
  566. "Device with ID register %x is not rt1016\n", val);
  567. return -ENODEV;
  568. }
  569. regmap_write(rt1016->regmap, RT1016_RESET, 0);
  570. ret = regmap_register_patch(rt1016->regmap, rt1016_patch,
  571. ARRAY_SIZE(rt1016_patch));
  572. if (ret != 0)
  573. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  574. return devm_snd_soc_register_component(&i2c->dev,
  575. &soc_component_dev_rt1016,
  576. rt1016_dai, ARRAY_SIZE(rt1016_dai));
  577. }
  578. static void rt1016_i2c_shutdown(struct i2c_client *client)
  579. {
  580. struct rt1016_priv *rt1016 = i2c_get_clientdata(client);
  581. regmap_write(rt1016->regmap, RT1016_RESET, 0);
  582. }
  583. static struct i2c_driver rt1016_i2c_driver = {
  584. .driver = {
  585. .name = "rt1016",
  586. .of_match_table = of_match_ptr(rt1016_of_match),
  587. .acpi_match_table = ACPI_PTR(rt1016_acpi_match),
  588. },
  589. .probe = rt1016_i2c_probe,
  590. .shutdown = rt1016_i2c_shutdown,
  591. .id_table = rt1016_i2c_id,
  592. };
  593. module_i2c_driver(rt1016_i2c_driver);
  594. MODULE_DESCRIPTION("ASoC RT1016 driver");
  595. MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
  596. MODULE_LICENSE("GPL v2");