rt1015.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
  4. //
  5. // Copyright 2019 Realtek Semiconductor Corp.
  6. //
  7. // Author: Jack Yu <jack.yu@realtek.com>
  8. //
  9. //
  10. #include <linux/acpi.h>
  11. #include <linux/delay.h>
  12. #include <linux/firmware.h>
  13. #include <linux/fs.h>
  14. #include <linux/gpio.h>
  15. #include <linux/i2c.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm.h>
  21. #include <linux/regmap.h>
  22. #include <sound/core.h>
  23. #include <sound/initval.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/soc.h>
  28. #include <sound/tlv.h>
  29. #include <sound/rt1015.h>
  30. #include "rl6231.h"
  31. #include "rt1015.h"
  32. static const struct rt1015_platform_data i2s_default_platform_data = {
  33. .power_up_delay_ms = 50,
  34. };
  35. static const struct reg_default rt1015_reg[] = {
  36. { 0x0000, 0x0000 },
  37. { 0x0004, 0xa000 },
  38. { 0x0006, 0x0003 },
  39. { 0x000a, 0x081e },
  40. { 0x000c, 0x0006 },
  41. { 0x000e, 0x0000 },
  42. { 0x0010, 0x0000 },
  43. { 0x0012, 0x0000 },
  44. { 0x0014, 0x0000 },
  45. { 0x0016, 0x0000 },
  46. { 0x0018, 0x0000 },
  47. { 0x0020, 0x8000 },
  48. { 0x0022, 0x8043 },
  49. { 0x0076, 0x0000 },
  50. { 0x0078, 0x0000 },
  51. { 0x007a, 0x0002 },
  52. { 0x007c, 0x10ec },
  53. { 0x007d, 0x1015 },
  54. { 0x00f0, 0x5000 },
  55. { 0x00f2, 0x004c },
  56. { 0x00f3, 0xecfe },
  57. { 0x00f4, 0x0000 },
  58. { 0x00f6, 0x0400 },
  59. { 0x0100, 0x0028 },
  60. { 0x0102, 0xff02 },
  61. { 0x0104, 0xa213 },
  62. { 0x0106, 0x200c },
  63. { 0x010c, 0x0000 },
  64. { 0x010e, 0x0058 },
  65. { 0x0111, 0x0200 },
  66. { 0x0112, 0x0400 },
  67. { 0x0114, 0x0022 },
  68. { 0x0116, 0x0000 },
  69. { 0x0118, 0x0000 },
  70. { 0x011a, 0x0123 },
  71. { 0x011c, 0x4567 },
  72. { 0x0300, 0x203d },
  73. { 0x0302, 0x001e },
  74. { 0x0311, 0x0000 },
  75. { 0x0313, 0x6014 },
  76. { 0x0314, 0x00a2 },
  77. { 0x031a, 0x00a0 },
  78. { 0x031c, 0x001f },
  79. { 0x031d, 0xffff },
  80. { 0x031e, 0x0000 },
  81. { 0x031f, 0x0000 },
  82. { 0x0320, 0x0000 },
  83. { 0x0321, 0x0000 },
  84. { 0x0322, 0xd7df },
  85. { 0x0328, 0x10b2 },
  86. { 0x0329, 0x0175 },
  87. { 0x032a, 0x36ad },
  88. { 0x032b, 0x7e55 },
  89. { 0x032c, 0x0520 },
  90. { 0x032d, 0xaa00 },
  91. { 0x032e, 0x570e },
  92. { 0x0330, 0xe180 },
  93. { 0x0332, 0x0034 },
  94. { 0x0334, 0x0001 },
  95. { 0x0336, 0x0010 },
  96. { 0x0338, 0x0000 },
  97. { 0x04fa, 0x0030 },
  98. { 0x04fc, 0x35c8 },
  99. { 0x04fe, 0x0800 },
  100. { 0x0500, 0x0400 },
  101. { 0x0502, 0x1000 },
  102. { 0x0504, 0x0000 },
  103. { 0x0506, 0x04ff },
  104. { 0x0508, 0x0010 },
  105. { 0x050a, 0x001a },
  106. { 0x0519, 0x1c68 },
  107. { 0x051a, 0x0ccc },
  108. { 0x051b, 0x0666 },
  109. { 0x051d, 0x0000 },
  110. { 0x051f, 0x0000 },
  111. { 0x0536, 0x061c },
  112. { 0x0538, 0x0000 },
  113. { 0x053a, 0x0000 },
  114. { 0x053c, 0x0000 },
  115. { 0x053d, 0x0000 },
  116. { 0x053e, 0x0000 },
  117. { 0x053f, 0x0000 },
  118. { 0x0540, 0x0000 },
  119. { 0x0541, 0x0000 },
  120. { 0x0542, 0x0000 },
  121. { 0x0543, 0x0000 },
  122. { 0x0544, 0x0000 },
  123. { 0x0568, 0x0000 },
  124. { 0x056a, 0x0000 },
  125. { 0x1000, 0x0040 },
  126. { 0x1002, 0x5405 },
  127. { 0x1006, 0x5515 },
  128. { 0x1007, 0x05f7 },
  129. { 0x1009, 0x0b0a },
  130. { 0x100a, 0x00ef },
  131. { 0x100d, 0x0003 },
  132. { 0x1010, 0xa433 },
  133. { 0x1020, 0x0000 },
  134. { 0x1200, 0x5a01 },
  135. { 0x1202, 0x6524 },
  136. { 0x1204, 0x1f00 },
  137. { 0x1206, 0x0000 },
  138. { 0x1208, 0x0000 },
  139. { 0x120a, 0x0000 },
  140. { 0x120c, 0x0000 },
  141. { 0x120e, 0x0000 },
  142. { 0x1210, 0x0000 },
  143. { 0x1212, 0x0000 },
  144. { 0x1300, 0x10a1 },
  145. { 0x1302, 0x12ff },
  146. { 0x1304, 0x0400 },
  147. { 0x1305, 0x0844 },
  148. { 0x1306, 0x4611 },
  149. { 0x1308, 0x555e },
  150. { 0x130a, 0x0000 },
  151. { 0x130c, 0x2000 },
  152. { 0x130e, 0x0100 },
  153. { 0x130f, 0x0001 },
  154. { 0x1310, 0x0000 },
  155. { 0x1312, 0x0000 },
  156. { 0x1314, 0x0000 },
  157. { 0x1316, 0x0000 },
  158. { 0x1318, 0x0000 },
  159. { 0x131a, 0x0000 },
  160. { 0x1322, 0x0029 },
  161. { 0x1323, 0x4a52 },
  162. { 0x1324, 0x002c },
  163. { 0x1325, 0x0b02 },
  164. { 0x1326, 0x002d },
  165. { 0x1327, 0x6b5a },
  166. { 0x1328, 0x002e },
  167. { 0x1329, 0xcbb2 },
  168. { 0x132a, 0x0030 },
  169. { 0x132b, 0x2c0b },
  170. { 0x1330, 0x0031 },
  171. { 0x1331, 0x8c63 },
  172. { 0x1332, 0x0032 },
  173. { 0x1333, 0xecbb },
  174. { 0x1334, 0x0034 },
  175. { 0x1335, 0x4d13 },
  176. { 0x1336, 0x0037 },
  177. { 0x1337, 0x0dc3 },
  178. { 0x1338, 0x003d },
  179. { 0x1339, 0xef7b },
  180. { 0x133a, 0x0044 },
  181. { 0x133b, 0xd134 },
  182. { 0x133c, 0x0047 },
  183. { 0x133d, 0x91e4 },
  184. { 0x133e, 0x004d },
  185. { 0x133f, 0xc370 },
  186. { 0x1340, 0x0053 },
  187. { 0x1341, 0xf4fd },
  188. { 0x1342, 0x0060 },
  189. { 0x1343, 0x5816 },
  190. { 0x1344, 0x006c },
  191. { 0x1345, 0xbb2e },
  192. { 0x1346, 0x0072 },
  193. { 0x1347, 0xecbb },
  194. { 0x1348, 0x0076 },
  195. { 0x1349, 0x5d97 },
  196. };
  197. static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
  198. {
  199. switch (reg) {
  200. case RT1015_RESET:
  201. case RT1015_CLK_DET:
  202. case RT1015_SIL_DET:
  203. case RT1015_VER_ID:
  204. case RT1015_VENDOR_ID:
  205. case RT1015_DEVICE_ID:
  206. case RT1015_PRO_ALT:
  207. case RT1015_MAN_I2C:
  208. case RT1015_DAC3:
  209. case RT1015_VBAT_TEST_OUT1:
  210. case RT1015_VBAT_TEST_OUT2:
  211. case RT1015_VBAT_PROT_ATT:
  212. case RT1015_VBAT_DET_CODE:
  213. case RT1015_SMART_BST_CTRL1:
  214. case RT1015_SPK_DC_DETECT1:
  215. case RT1015_SPK_DC_DETECT4:
  216. case RT1015_SPK_DC_DETECT5:
  217. case RT1015_DC_CALIB_CLSD1:
  218. case RT1015_DC_CALIB_CLSD5:
  219. case RT1015_DC_CALIB_CLSD6:
  220. case RT1015_DC_CALIB_CLSD7:
  221. case RT1015_DC_CALIB_CLSD8:
  222. case RT1015_S_BST_TIMING_INTER1:
  223. case RT1015_OSCK_STA:
  224. case RT1015_MONO_DYNA_CTRL1:
  225. case RT1015_MONO_DYNA_CTRL5:
  226. return true;
  227. default:
  228. return false;
  229. }
  230. }
  231. static bool rt1015_readable_register(struct device *dev, unsigned int reg)
  232. {
  233. switch (reg) {
  234. case RT1015_RESET:
  235. case RT1015_CLK2:
  236. case RT1015_CLK3:
  237. case RT1015_PLL1:
  238. case RT1015_PLL2:
  239. case RT1015_DUM_RW1:
  240. case RT1015_DUM_RW2:
  241. case RT1015_DUM_RW3:
  242. case RT1015_DUM_RW4:
  243. case RT1015_DUM_RW5:
  244. case RT1015_DUM_RW6:
  245. case RT1015_CLK_DET:
  246. case RT1015_SIL_DET:
  247. case RT1015_CUSTOMER_ID:
  248. case RT1015_PCODE_FWVER:
  249. case RT1015_VER_ID:
  250. case RT1015_VENDOR_ID:
  251. case RT1015_DEVICE_ID:
  252. case RT1015_PAD_DRV1:
  253. case RT1015_PAD_DRV2:
  254. case RT1015_GAT_BOOST:
  255. case RT1015_PRO_ALT:
  256. case RT1015_OSCK_STA:
  257. case RT1015_MAN_I2C:
  258. case RT1015_DAC1:
  259. case RT1015_DAC2:
  260. case RT1015_DAC3:
  261. case RT1015_ADC1:
  262. case RT1015_ADC2:
  263. case RT1015_TDM_MASTER:
  264. case RT1015_TDM_TCON:
  265. case RT1015_TDM1_1:
  266. case RT1015_TDM1_2:
  267. case RT1015_TDM1_3:
  268. case RT1015_TDM1_4:
  269. case RT1015_TDM1_5:
  270. case RT1015_MIXER1:
  271. case RT1015_MIXER2:
  272. case RT1015_ANA_PROTECT1:
  273. case RT1015_ANA_CTRL_SEQ1:
  274. case RT1015_ANA_CTRL_SEQ2:
  275. case RT1015_VBAT_DET_DEB:
  276. case RT1015_VBAT_VOLT_DET1:
  277. case RT1015_VBAT_VOLT_DET2:
  278. case RT1015_VBAT_TEST_OUT1:
  279. case RT1015_VBAT_TEST_OUT2:
  280. case RT1015_VBAT_PROT_ATT:
  281. case RT1015_VBAT_DET_CODE:
  282. case RT1015_PWR1:
  283. case RT1015_PWR4:
  284. case RT1015_PWR5:
  285. case RT1015_PWR6:
  286. case RT1015_PWR7:
  287. case RT1015_PWR8:
  288. case RT1015_PWR9:
  289. case RT1015_CLASSD_SEQ:
  290. case RT1015_SMART_BST_CTRL1:
  291. case RT1015_SMART_BST_CTRL2:
  292. case RT1015_ANA_CTRL1:
  293. case RT1015_ANA_CTRL2:
  294. case RT1015_PWR_STATE_CTRL:
  295. case RT1015_MONO_DYNA_CTRL:
  296. case RT1015_MONO_DYNA_CTRL1:
  297. case RT1015_MONO_DYNA_CTRL2:
  298. case RT1015_MONO_DYNA_CTRL3:
  299. case RT1015_MONO_DYNA_CTRL4:
  300. case RT1015_MONO_DYNA_CTRL5:
  301. case RT1015_SPK_VOL:
  302. case RT1015_SHORT_DETTOP1:
  303. case RT1015_SHORT_DETTOP2:
  304. case RT1015_SPK_DC_DETECT1:
  305. case RT1015_SPK_DC_DETECT2:
  306. case RT1015_SPK_DC_DETECT3:
  307. case RT1015_SPK_DC_DETECT4:
  308. case RT1015_SPK_DC_DETECT5:
  309. case RT1015_BAT_RPO_STEP1:
  310. case RT1015_BAT_RPO_STEP2:
  311. case RT1015_BAT_RPO_STEP3:
  312. case RT1015_BAT_RPO_STEP4:
  313. case RT1015_BAT_RPO_STEP5:
  314. case RT1015_BAT_RPO_STEP6:
  315. case RT1015_BAT_RPO_STEP7:
  316. case RT1015_BAT_RPO_STEP8:
  317. case RT1015_BAT_RPO_STEP9:
  318. case RT1015_BAT_RPO_STEP10:
  319. case RT1015_BAT_RPO_STEP11:
  320. case RT1015_BAT_RPO_STEP12:
  321. case RT1015_SPREAD_SPEC1:
  322. case RT1015_SPREAD_SPEC2:
  323. case RT1015_PAD_STATUS:
  324. case RT1015_PADS_PULLING_CTRL1:
  325. case RT1015_PADS_DRIVING:
  326. case RT1015_SYS_RST1:
  327. case RT1015_SYS_RST2:
  328. case RT1015_SYS_GATING1:
  329. case RT1015_TEST_MODE1:
  330. case RT1015_TEST_MODE2:
  331. case RT1015_TIMING_CTRL1:
  332. case RT1015_PLL_INT:
  333. case RT1015_TEST_OUT1:
  334. case RT1015_DC_CALIB_CLSD1:
  335. case RT1015_DC_CALIB_CLSD2:
  336. case RT1015_DC_CALIB_CLSD3:
  337. case RT1015_DC_CALIB_CLSD4:
  338. case RT1015_DC_CALIB_CLSD5:
  339. case RT1015_DC_CALIB_CLSD6:
  340. case RT1015_DC_CALIB_CLSD7:
  341. case RT1015_DC_CALIB_CLSD8:
  342. case RT1015_DC_CALIB_CLSD9:
  343. case RT1015_DC_CALIB_CLSD10:
  344. case RT1015_CLSD_INTERNAL1:
  345. case RT1015_CLSD_INTERNAL2:
  346. case RT1015_CLSD_INTERNAL3:
  347. case RT1015_CLSD_INTERNAL4:
  348. case RT1015_CLSD_INTERNAL5:
  349. case RT1015_CLSD_INTERNAL6:
  350. case RT1015_CLSD_INTERNAL7:
  351. case RT1015_CLSD_INTERNAL8:
  352. case RT1015_CLSD_INTERNAL9:
  353. case RT1015_CLSD_OCP_CTRL:
  354. case RT1015_VREF_LV:
  355. case RT1015_MBIAS1:
  356. case RT1015_MBIAS2:
  357. case RT1015_MBIAS3:
  358. case RT1015_MBIAS4:
  359. case RT1015_VREF_LV1:
  360. case RT1015_S_BST_TIMING_INTER1:
  361. case RT1015_S_BST_TIMING_INTER2:
  362. case RT1015_S_BST_TIMING_INTER3:
  363. case RT1015_S_BST_TIMING_INTER4:
  364. case RT1015_S_BST_TIMING_INTER5:
  365. case RT1015_S_BST_TIMING_INTER6:
  366. case RT1015_S_BST_TIMING_INTER7:
  367. case RT1015_S_BST_TIMING_INTER8:
  368. case RT1015_S_BST_TIMING_INTER9:
  369. case RT1015_S_BST_TIMING_INTER10:
  370. case RT1015_S_BST_TIMING_INTER11:
  371. case RT1015_S_BST_TIMING_INTER12:
  372. case RT1015_S_BST_TIMING_INTER13:
  373. case RT1015_S_BST_TIMING_INTER14:
  374. case RT1015_S_BST_TIMING_INTER15:
  375. case RT1015_S_BST_TIMING_INTER16:
  376. case RT1015_S_BST_TIMING_INTER17:
  377. case RT1015_S_BST_TIMING_INTER18:
  378. case RT1015_S_BST_TIMING_INTER19:
  379. case RT1015_S_BST_TIMING_INTER20:
  380. case RT1015_S_BST_TIMING_INTER21:
  381. case RT1015_S_BST_TIMING_INTER22:
  382. case RT1015_S_BST_TIMING_INTER23:
  383. case RT1015_S_BST_TIMING_INTER24:
  384. case RT1015_S_BST_TIMING_INTER25:
  385. case RT1015_S_BST_TIMING_INTER26:
  386. case RT1015_S_BST_TIMING_INTER27:
  387. case RT1015_S_BST_TIMING_INTER28:
  388. case RT1015_S_BST_TIMING_INTER29:
  389. case RT1015_S_BST_TIMING_INTER30:
  390. case RT1015_S_BST_TIMING_INTER31:
  391. case RT1015_S_BST_TIMING_INTER32:
  392. case RT1015_S_BST_TIMING_INTER33:
  393. case RT1015_S_BST_TIMING_INTER34:
  394. case RT1015_S_BST_TIMING_INTER35:
  395. case RT1015_S_BST_TIMING_INTER36:
  396. return true;
  397. default:
  398. return false;
  399. }
  400. }
  401. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
  402. static const char * const rt1015_din_source_select[] = {
  403. "Left",
  404. "Right",
  405. "Left + Right average",
  406. };
  407. static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
  408. rt1015_din_source_select);
  409. static const char * const rt1015_boost_mode[] = {
  410. "Bypass", "Adaptive", "Fixed Adaptive"
  411. };
  412. static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
  413. rt1015_boost_mode);
  414. static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
  415. struct snd_ctl_elem_value *ucontrol)
  416. {
  417. struct snd_soc_component *component =
  418. snd_soc_kcontrol_component(kcontrol);
  419. struct rt1015_priv *rt1015 =
  420. snd_soc_component_get_drvdata(component);
  421. ucontrol->value.integer.value[0] = rt1015->boost_mode;
  422. return 0;
  423. }
  424. static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
  425. struct snd_ctl_elem_value *ucontrol)
  426. {
  427. struct snd_soc_component *component =
  428. snd_soc_kcontrol_component(kcontrol);
  429. struct rt1015_priv *rt1015 =
  430. snd_soc_component_get_drvdata(component);
  431. rt1015->boost_mode = ucontrol->value.integer.value[0];
  432. switch (rt1015->boost_mode) {
  433. case BYPASS:
  434. snd_soc_component_update_bits(component,
  435. RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
  436. RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
  437. RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
  438. RT1015_BYPASS_SWRREG_BYPASS);
  439. break;
  440. case ADAPTIVE:
  441. snd_soc_component_update_bits(component,
  442. RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
  443. RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
  444. RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
  445. RT1015_BYPASS_SWRREG_PASS);
  446. break;
  447. case FIXED_ADAPTIVE:
  448. snd_soc_component_update_bits(component,
  449. RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
  450. RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
  451. RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
  452. RT1015_BYPASS_SWRREG_PASS);
  453. break;
  454. default:
  455. dev_err(component->dev, "Unknown boost control.\n");
  456. }
  457. return 0;
  458. }
  459. static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
  460. struct snd_ctl_elem_value *ucontrol)
  461. {
  462. struct snd_soc_component *component =
  463. snd_soc_kcontrol_component(kcontrol);
  464. struct rt1015_priv *rt1015 =
  465. snd_soc_component_get_drvdata(component);
  466. ucontrol->value.integer.value[0] = rt1015->bypass_boost;
  467. return 0;
  468. }
  469. static void rt1015_calibrate(struct rt1015_priv *rt1015)
  470. {
  471. struct snd_soc_component *component = rt1015->component;
  472. struct regmap *regmap = rt1015->regmap;
  473. snd_soc_dapm_mutex_lock(&component->dapm);
  474. regcache_cache_bypass(regmap, true);
  475. regmap_write(regmap, RT1015_PWR1, 0xd7df);
  476. regmap_write(regmap, RT1015_PWR4, 0x00b2);
  477. regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2008);
  478. regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
  479. regmap_write(regmap, RT1015_GAT_BOOST, 0x0efe);
  480. regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000d);
  481. regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000e);
  482. regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a00);
  483. regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a01);
  484. regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a05);
  485. msleep(500);
  486. regmap_write(regmap, RT1015_PWR1, 0x0);
  487. regcache_cache_bypass(regmap, false);
  488. regcache_mark_dirty(regmap);
  489. regcache_sync(regmap);
  490. snd_soc_dapm_mutex_unlock(&component->dapm);
  491. }
  492. static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
  493. struct snd_ctl_elem_value *ucontrol)
  494. {
  495. struct snd_soc_component *component =
  496. snd_soc_kcontrol_component(kcontrol);
  497. struct rt1015_priv *rt1015 =
  498. snd_soc_component_get_drvdata(component);
  499. if (!rt1015->dac_is_used) {
  500. rt1015->bypass_boost = ucontrol->value.integer.value[0];
  501. if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
  502. !rt1015->cali_done) {
  503. rt1015_calibrate(rt1015);
  504. rt1015->cali_done = 1;
  505. regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
  506. }
  507. } else
  508. dev_err(component->dev, "DAC is being used!\n");
  509. return 0;
  510. }
  511. static void rt1015_flush_work(struct work_struct *work)
  512. {
  513. struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv,
  514. flush_work.work);
  515. struct snd_soc_component *component = rt1015->component;
  516. unsigned int val, i = 0, count = 200;
  517. while (i < count) {
  518. usleep_range(1000, 1500);
  519. dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i);
  520. regmap_read(rt1015->regmap, RT1015_CLK_DET, &val);
  521. if (val & 0x800)
  522. break;
  523. i++;
  524. }
  525. regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
  526. regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
  527. regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
  528. if (val & 0x800)
  529. dev_dbg(component->dev, "Flush DAC completed.\n");
  530. else
  531. dev_warn(component->dev, "Fail to flush DAC data.\n");
  532. }
  533. static const struct snd_kcontrol_new rt1015_snd_controls[] = {
  534. SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
  535. 127, 0, dac_vol_tlv),
  536. SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
  537. RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
  538. SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
  539. rt1015_boost_mode_get, rt1015_boost_mode_put),
  540. SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
  541. SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
  542. rt1015_bypass_boost_get, rt1015_bypass_boost_put),
  543. };
  544. static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  545. struct snd_soc_dapm_widget *sink)
  546. {
  547. struct snd_soc_component *component =
  548. snd_soc_dapm_to_component(source->dapm);
  549. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  550. if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
  551. return 1;
  552. else
  553. return 0;
  554. }
  555. static int r1015_dac_event(struct snd_soc_dapm_widget *w,
  556. struct snd_kcontrol *kcontrol, int event)
  557. {
  558. struct snd_soc_component *component =
  559. snd_soc_dapm_to_component(w->dapm);
  560. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  561. switch (event) {
  562. case SND_SOC_DAPM_PRE_PMU:
  563. rt1015->dac_is_used = 1;
  564. if (rt1015->bypass_boost == RT1015_Enable_Boost) {
  565. snd_soc_component_write(component,
  566. RT1015_SYS_RST1, 0x05f7);
  567. snd_soc_component_write(component,
  568. RT1015_GAT_BOOST, 0xacfe);
  569. snd_soc_component_write(component,
  570. RT1015_PWR9, 0xaa00);
  571. snd_soc_component_write(component,
  572. RT1015_GAT_BOOST, 0xecfe);
  573. } else {
  574. snd_soc_component_write(component,
  575. RT1015_SYS_RST1, 0x05f7);
  576. snd_soc_component_write(component,
  577. RT1015_PWR_STATE_CTRL, 0x026e);
  578. }
  579. break;
  580. case SND_SOC_DAPM_POST_PMU:
  581. regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
  582. break;
  583. case SND_SOC_DAPM_POST_PMD:
  584. if (rt1015->bypass_boost == RT1015_Enable_Boost) {
  585. snd_soc_component_write(component,
  586. RT1015_PWR9, 0xa800);
  587. snd_soc_component_write(component,
  588. RT1015_SYS_RST1, 0x05f5);
  589. } else {
  590. snd_soc_component_write(component,
  591. RT1015_PWR_STATE_CTRL, 0x0268);
  592. snd_soc_component_write(component,
  593. RT1015_SYS_RST1, 0x05f5);
  594. }
  595. rt1015->dac_is_used = 0;
  596. cancel_delayed_work_sync(&rt1015->flush_work);
  597. break;
  598. default:
  599. break;
  600. }
  601. return 0;
  602. }
  603. static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
  604. struct snd_kcontrol *kcontrol, int event)
  605. {
  606. struct snd_soc_component *component =
  607. snd_soc_dapm_to_component(w->dapm);
  608. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  609. switch (event) {
  610. case SND_SOC_DAPM_POST_PMU:
  611. if (rt1015->hw_config == RT1015_HW_28)
  612. schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10));
  613. msleep(rt1015->pdata.power_up_delay_ms);
  614. break;
  615. default:
  616. break;
  617. }
  618. return 0;
  619. }
  620. static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
  621. SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0,
  622. NULL, 0),
  623. SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT,
  624. 0, NULL, 0),
  625. SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0,
  626. NULL, 0),
  627. SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0,
  628. NULL, 0),
  629. SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
  630. NULL, 0),
  631. SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0,
  632. NULL, 0),
  633. SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0,
  634. NULL, 0),
  635. SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL,
  636. 0),
  637. SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0,
  638. NULL, 0),
  639. SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL,
  640. 0),
  641. SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0,
  642. NULL, 0),
  643. SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL,
  644. 0),
  645. SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0,
  646. NULL, 0),
  647. SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
  648. SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0,
  649. r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  650. SND_SOC_DAPM_POST_PMD),
  651. SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
  652. rt1015_amp_drv_event, SND_SOC_DAPM_POST_PMU),
  653. SND_SOC_DAPM_OUTPUT("SPO"),
  654. };
  655. static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
  656. { "DAC", NULL, "AIFRX" },
  657. { "DAC", NULL, "LDO2" },
  658. { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
  659. { "DAC", NULL, "INT RC CLK" },
  660. { "DAC", NULL, "ISENSE" },
  661. { "DAC", NULL, "VSENSE" },
  662. { "DAC", NULL, "BG1 BG2" },
  663. { "DAC", NULL, "MBIAS BG" },
  664. { "DAC", NULL, "VBAT" },
  665. { "DAC", NULL, "MBIAS" },
  666. { "DAC", NULL, "ADCV" },
  667. { "DAC", NULL, "MIXERV" },
  668. { "DAC", NULL, "SUMV" },
  669. { "DAC", NULL, "VREFLV" },
  670. { "Amp Drv", NULL, "DAC" },
  671. { "SPO", NULL, "Amp Drv" },
  672. };
  673. static int rt1015_hw_params(struct snd_pcm_substream *substream,
  674. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  675. {
  676. struct snd_soc_component *component = dai->component;
  677. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  678. int pre_div, bclk_ms, frame_size;
  679. unsigned int val_len = 0;
  680. rt1015->lrck = params_rate(params);
  681. pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
  682. if (pre_div < 0) {
  683. dev_err(component->dev, "Unsupported clock rate\n");
  684. return -EINVAL;
  685. }
  686. frame_size = snd_soc_params_to_frame_size(params);
  687. if (frame_size < 0) {
  688. dev_err(component->dev, "Unsupported frame size: %d\n",
  689. frame_size);
  690. return -EINVAL;
  691. }
  692. bclk_ms = frame_size > 32;
  693. rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
  694. dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  695. bclk_ms, pre_div, dai->id);
  696. dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  697. rt1015->lrck, pre_div, dai->id);
  698. switch (params_width(params)) {
  699. case 16:
  700. break;
  701. case 20:
  702. val_len = RT1015_I2S_DL_20;
  703. break;
  704. case 24:
  705. val_len = RT1015_I2S_DL_24;
  706. break;
  707. case 8:
  708. val_len = RT1015_I2S_DL_8;
  709. break;
  710. default:
  711. return -EINVAL;
  712. }
  713. snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
  714. RT1015_I2S_DL_MASK, val_len);
  715. snd_soc_component_update_bits(component, RT1015_CLK2,
  716. RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
  717. return 0;
  718. }
  719. static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  720. {
  721. struct snd_soc_component *component = dai->component;
  722. unsigned int reg_val = 0, reg_val2 = 0;
  723. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  724. case SND_SOC_DAIFMT_CBM_CFM:
  725. reg_val |= RT1015_TCON_TDM_MS_M;
  726. break;
  727. case SND_SOC_DAIFMT_CBS_CFS:
  728. reg_val |= RT1015_TCON_TDM_MS_S;
  729. break;
  730. default:
  731. return -EINVAL;
  732. }
  733. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  734. case SND_SOC_DAIFMT_NB_NF:
  735. break;
  736. case SND_SOC_DAIFMT_IB_NF:
  737. reg_val2 |= RT1015_TDM_INV_BCLK;
  738. break;
  739. default:
  740. return -EINVAL;
  741. }
  742. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  743. case SND_SOC_DAIFMT_I2S:
  744. break;
  745. case SND_SOC_DAIFMT_LEFT_J:
  746. reg_val |= RT1015_I2S_M_DF_LEFT;
  747. break;
  748. case SND_SOC_DAIFMT_DSP_A:
  749. reg_val |= RT1015_I2S_M_DF_PCM_A;
  750. break;
  751. case SND_SOC_DAIFMT_DSP_B:
  752. reg_val |= RT1015_I2S_M_DF_PCM_B;
  753. break;
  754. default:
  755. return -EINVAL;
  756. }
  757. snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
  758. RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
  759. reg_val);
  760. snd_soc_component_update_bits(component, RT1015_TDM1_1,
  761. RT1015_TDM_INV_BCLK_MASK, reg_val2);
  762. return 0;
  763. }
  764. static int rt1015_set_component_sysclk(struct snd_soc_component *component,
  765. int clk_id, int source, unsigned int freq, int dir)
  766. {
  767. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  768. unsigned int reg_val = 0;
  769. if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
  770. return 0;
  771. switch (clk_id) {
  772. case RT1015_SCLK_S_MCLK:
  773. reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
  774. break;
  775. case RT1015_SCLK_S_PLL:
  776. reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
  777. break;
  778. default:
  779. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  780. return -EINVAL;
  781. }
  782. rt1015->sysclk = freq;
  783. rt1015->sysclk_src = clk_id;
  784. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  785. freq, clk_id);
  786. snd_soc_component_update_bits(component, RT1015_CLK2,
  787. RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
  788. return 0;
  789. }
  790. static int rt1015_set_component_pll(struct snd_soc_component *component,
  791. int pll_id, int source, unsigned int freq_in,
  792. unsigned int freq_out)
  793. {
  794. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  795. struct rl6231_pll_code pll_code;
  796. int ret;
  797. if (!freq_in || !freq_out) {
  798. dev_dbg(component->dev, "PLL disabled\n");
  799. rt1015->pll_in = 0;
  800. rt1015->pll_out = 0;
  801. return 0;
  802. }
  803. if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
  804. freq_out == rt1015->pll_out)
  805. return 0;
  806. if (source == RT1015_PLL_S_BCLK) {
  807. if (rt1015->bclk_ratio == 0) {
  808. dev_err(component->dev,
  809. "Can not support bclk ratio as 0.\n");
  810. return -EINVAL;
  811. }
  812. }
  813. switch (source) {
  814. case RT1015_PLL_S_MCLK:
  815. snd_soc_component_update_bits(component, RT1015_CLK2,
  816. RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
  817. break;
  818. case RT1015_PLL_S_BCLK:
  819. snd_soc_component_update_bits(component, RT1015_CLK2,
  820. RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
  821. break;
  822. default:
  823. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  824. return -EINVAL;
  825. }
  826. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  827. if (ret < 0) {
  828. dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
  829. return ret;
  830. }
  831. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  832. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  833. pll_code.n_code, pll_code.k_code);
  834. snd_soc_component_write(component, RT1015_PLL1,
  835. (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
  836. pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
  837. snd_soc_component_write(component, RT1015_PLL2,
  838. pll_code.k_code);
  839. rt1015->pll_in = freq_in;
  840. rt1015->pll_out = freq_out;
  841. rt1015->pll_src = source;
  842. return 0;
  843. }
  844. static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  845. {
  846. struct snd_soc_component *component = dai->component;
  847. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  848. dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
  849. rt1015->bclk_ratio = ratio;
  850. if (ratio == 50) {
  851. dev_dbg(component->dev, "Unsupport bclk ratio\n");
  852. return -EINVAL;
  853. }
  854. return 0;
  855. }
  856. static int rt1015_probe(struct snd_soc_component *component)
  857. {
  858. struct rt1015_priv *rt1015 =
  859. snd_soc_component_get_drvdata(component);
  860. rt1015->component = component;
  861. rt1015->bclk_ratio = 0;
  862. rt1015->cali_done = 0;
  863. snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c);
  864. INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work);
  865. return 0;
  866. }
  867. static void rt1015_remove(struct snd_soc_component *component)
  868. {
  869. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  870. cancel_delayed_work_sync(&rt1015->flush_work);
  871. regmap_write(rt1015->regmap, RT1015_RESET, 0);
  872. }
  873. #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
  874. #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  875. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  876. static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
  877. .hw_params = rt1015_hw_params,
  878. .set_fmt = rt1015_set_dai_fmt,
  879. .set_bclk_ratio = rt1015_set_bclk_ratio,
  880. };
  881. static struct snd_soc_dai_driver rt1015_dai[] = {
  882. {
  883. .name = "rt1015-aif",
  884. .id = 0,
  885. .playback = {
  886. .stream_name = "AIF Playback",
  887. .channels_min = 1,
  888. .channels_max = 4,
  889. .rates = RT1015_STEREO_RATES,
  890. .formats = RT1015_FORMATS,
  891. },
  892. .ops = &rt1015_aif_dai_ops,
  893. }
  894. };
  895. #ifdef CONFIG_PM
  896. static int rt1015_suspend(struct snd_soc_component *component)
  897. {
  898. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  899. regcache_cache_only(rt1015->regmap, true);
  900. regcache_mark_dirty(rt1015->regmap);
  901. return 0;
  902. }
  903. static int rt1015_resume(struct snd_soc_component *component)
  904. {
  905. struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
  906. regcache_cache_only(rt1015->regmap, false);
  907. regcache_sync(rt1015->regmap);
  908. return 0;
  909. }
  910. #else
  911. #define rt1015_suspend NULL
  912. #define rt1015_resume NULL
  913. #endif
  914. static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
  915. .probe = rt1015_probe,
  916. .remove = rt1015_remove,
  917. .suspend = rt1015_suspend,
  918. .resume = rt1015_resume,
  919. .controls = rt1015_snd_controls,
  920. .num_controls = ARRAY_SIZE(rt1015_snd_controls),
  921. .dapm_widgets = rt1015_dapm_widgets,
  922. .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
  923. .dapm_routes = rt1015_dapm_routes,
  924. .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
  925. .set_sysclk = rt1015_set_component_sysclk,
  926. .set_pll = rt1015_set_component_pll,
  927. .use_pmdown_time = 1,
  928. .endianness = 1,
  929. .non_legacy_dai_naming = 1,
  930. };
  931. static const struct regmap_config rt1015_regmap = {
  932. .reg_bits = 16,
  933. .val_bits = 16,
  934. .max_register = RT1015_S_BST_TIMING_INTER36,
  935. .volatile_reg = rt1015_volatile_register,
  936. .readable_reg = rt1015_readable_register,
  937. .cache_type = REGCACHE_RBTREE,
  938. .reg_defaults = rt1015_reg,
  939. .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
  940. };
  941. static const struct i2c_device_id rt1015_i2c_id[] = {
  942. { "rt1015", 0 },
  943. { }
  944. };
  945. MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
  946. #if defined(CONFIG_OF)
  947. static const struct of_device_id rt1015_of_match[] = {
  948. { .compatible = "realtek,rt1015", },
  949. {},
  950. };
  951. MODULE_DEVICE_TABLE(of, rt1015_of_match);
  952. #endif
  953. #ifdef CONFIG_ACPI
  954. static struct acpi_device_id rt1015_acpi_match[] = {
  955. {"10EC1015", 0,},
  956. {},
  957. };
  958. MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
  959. #endif
  960. static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
  961. {
  962. device_property_read_u32(dev, "realtek,power-up-delay-ms",
  963. &rt1015->pdata.power_up_delay_ms);
  964. }
  965. static int rt1015_i2c_probe(struct i2c_client *i2c,
  966. const struct i2c_device_id *id)
  967. {
  968. struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
  969. struct rt1015_priv *rt1015;
  970. int ret;
  971. unsigned int val;
  972. rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
  973. GFP_KERNEL);
  974. if (rt1015 == NULL)
  975. return -ENOMEM;
  976. i2c_set_clientdata(i2c, rt1015);
  977. rt1015->pdata = i2s_default_platform_data;
  978. if (pdata)
  979. rt1015->pdata = *pdata;
  980. else
  981. rt1015_parse_dt(rt1015, &i2c->dev);
  982. rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
  983. if (IS_ERR(rt1015->regmap)) {
  984. ret = PTR_ERR(rt1015->regmap);
  985. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  986. ret);
  987. return ret;
  988. }
  989. rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28;
  990. regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
  991. if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) {
  992. dev_err(&i2c->dev,
  993. "Device with ID register %x is not rt1015\n", val);
  994. return -ENODEV;
  995. }
  996. return devm_snd_soc_register_component(&i2c->dev,
  997. &soc_component_dev_rt1015,
  998. rt1015_dai, ARRAY_SIZE(rt1015_dai));
  999. }
  1000. static void rt1015_i2c_shutdown(struct i2c_client *client)
  1001. {
  1002. struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
  1003. regmap_write(rt1015->regmap, RT1015_RESET, 0);
  1004. }
  1005. static struct i2c_driver rt1015_i2c_driver = {
  1006. .driver = {
  1007. .name = "rt1015",
  1008. .of_match_table = of_match_ptr(rt1015_of_match),
  1009. .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
  1010. },
  1011. .probe = rt1015_i2c_probe,
  1012. .shutdown = rt1015_i2c_shutdown,
  1013. .id_table = rt1015_i2c_id,
  1014. };
  1015. module_i2c_driver(rt1015_i2c_driver);
  1016. MODULE_DESCRIPTION("ASoC RT1015 driver");
  1017. MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
  1018. MODULE_LICENSE("GPL v2");