rl6231.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rl6231.c - RL6231 class device shared support
  4. *
  5. * Copyright 2014 Realtek Semiconductor Corp.
  6. *
  7. * Author: Oder Chiou <oder_chiou@realtek.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/regmap.h>
  11. #include <linux/gcd.h>
  12. #include "rl6231.h"
  13. /**
  14. * rl6231_get_pre_div - Return the value of pre divider.
  15. *
  16. * @map: map for setting.
  17. * @reg: register.
  18. * @sft: shift.
  19. *
  20. * Return the value of pre divider from given register value.
  21. * Return negative error code for unexpected register value.
  22. */
  23. int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
  24. {
  25. int pd, val;
  26. regmap_read(map, reg, &val);
  27. val = (val >> sft) & 0x7;
  28. switch (val) {
  29. case 0:
  30. case 1:
  31. case 2:
  32. case 3:
  33. pd = val + 1;
  34. break;
  35. case 4:
  36. pd = 6;
  37. break;
  38. case 5:
  39. pd = 8;
  40. break;
  41. case 6:
  42. pd = 12;
  43. break;
  44. case 7:
  45. pd = 16;
  46. break;
  47. default:
  48. pd = -EINVAL;
  49. break;
  50. }
  51. return pd;
  52. }
  53. EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
  54. /**
  55. * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
  56. *
  57. * @rate: base clock rate.
  58. *
  59. * Choose divider parameter that gives the highest possible DMIC frequency in
  60. * 1MHz - 3MHz range.
  61. */
  62. int rl6231_calc_dmic_clk(int rate)
  63. {
  64. static const int div[] = {2, 3, 4, 6, 8, 12};
  65. int i;
  66. if (rate < 1000000 * div[0]) {
  67. pr_warn("Base clock rate %d is too low\n", rate);
  68. return -EINVAL;
  69. }
  70. for (i = 0; i < ARRAY_SIZE(div); i++) {
  71. if ((div[i] % 3) == 0)
  72. continue;
  73. /* find divider that gives DMIC frequency below 1.536MHz */
  74. if (1536000 * div[i] >= rate)
  75. return i;
  76. }
  77. pr_warn("Base clock rate %d is too high\n", rate);
  78. return -EINVAL;
  79. }
  80. EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
  81. struct pll_calc_map {
  82. unsigned int pll_in;
  83. unsigned int pll_out;
  84. int k;
  85. int n;
  86. int m;
  87. bool m_bp;
  88. bool k_bp;
  89. };
  90. static const struct pll_calc_map pll_preset_table[] = {
  91. {19200000, 4096000, 23, 14, 1, false, false},
  92. {19200000, 24576000, 3, 30, 3, false, false},
  93. {48000000, 3840000, 23, 2, 0, false, false},
  94. {3840000, 24576000, 3, 30, 0, true, false},
  95. {3840000, 22579200, 3, 5, 0, true, false},
  96. };
  97. static unsigned int find_best_div(unsigned int in,
  98. unsigned int max, unsigned int div)
  99. {
  100. unsigned int d;
  101. if (in <= max)
  102. return 1;
  103. d = in / max;
  104. if (in % max)
  105. d++;
  106. while (div % d != 0)
  107. d++;
  108. return d;
  109. }
  110. /**
  111. * rl6231_pll_calc - Calcualte PLL M/N/K code.
  112. * @freq_in: external clock provided to codec.
  113. * @freq_out: target clock which codec works on.
  114. * @pll_code: Pointer to structure with M, N, K, m_bypass and k_bypass flag.
  115. *
  116. * Calcualte M/N/K code to configure PLL for codec.
  117. *
  118. * Returns 0 for success or negative error code.
  119. */
  120. int rl6231_pll_calc(const unsigned int freq_in,
  121. const unsigned int freq_out, struct rl6231_pll_code *pll_code)
  122. {
  123. int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
  124. int i, k, n_t;
  125. int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
  126. unsigned int red, pll_out, in_t, out_t, div, div_t;
  127. unsigned int red_t = abs(freq_out - freq_in);
  128. unsigned int f_in, f_out, f_max;
  129. bool m_bypass = false, k_bypass = false;
  130. if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
  131. return -EINVAL;
  132. for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
  133. if (freq_in == pll_preset_table[i].pll_in &&
  134. freq_out == pll_preset_table[i].pll_out) {
  135. k = pll_preset_table[i].k;
  136. m = pll_preset_table[i].m;
  137. n = pll_preset_table[i].n;
  138. m_bypass = pll_preset_table[i].m_bp;
  139. k_bypass = pll_preset_table[i].k_bp;
  140. pr_debug("Use preset PLL parameter table\n");
  141. goto code_find;
  142. }
  143. }
  144. min_k = 80000000 / freq_out - 2;
  145. max_k = 150000000 / freq_out - 2;
  146. if (max_k > RL6231_PLL_K_MAX)
  147. max_k = RL6231_PLL_K_MAX;
  148. if (min_k > RL6231_PLL_K_MAX)
  149. min_k = max_k = RL6231_PLL_K_MAX;
  150. div_t = gcd(freq_in, freq_out);
  151. f_max = 0xffffffff / RL6231_PLL_N_MAX;
  152. div = find_best_div(freq_in, f_max, div_t);
  153. f_in = freq_in / div;
  154. f_out = freq_out / div;
  155. k = min_k;
  156. if (min_k < -1)
  157. min_k = -1;
  158. for (k_t = min_k; k_t <= max_k; k_t++) {
  159. for (n_t = 0; n_t <= max_n; n_t++) {
  160. in_t = f_in * (n_t + 2);
  161. pll_out = f_out * (k_t + 2);
  162. if (in_t == pll_out) {
  163. m_bypass = true;
  164. n = n_t;
  165. k = k_t;
  166. goto code_find;
  167. }
  168. out_t = in_t / (k_t + 2);
  169. red = abs(f_out - out_t);
  170. if (red < red_t) {
  171. m_bypass = true;
  172. n = n_t;
  173. m = 0;
  174. k = k_t;
  175. if (red == 0)
  176. goto code_find;
  177. red_t = red;
  178. }
  179. for (m_t = 0; m_t <= max_m; m_t++) {
  180. out_t = in_t / ((m_t + 2) * (k_t + 2));
  181. red = abs(f_out - out_t);
  182. if (red < red_t) {
  183. m_bypass = false;
  184. n = n_t;
  185. m = m_t;
  186. k = k_t;
  187. if (red == 0)
  188. goto code_find;
  189. red_t = red;
  190. }
  191. }
  192. }
  193. }
  194. pr_debug("Only get approximation about PLL\n");
  195. code_find:
  196. if (k == -1) {
  197. k_bypass = true;
  198. k = 0;
  199. }
  200. pll_code->m_bp = m_bypass;
  201. pll_code->k_bp = k_bypass;
  202. pll_code->m_code = m;
  203. pll_code->n_code = n;
  204. pll_code->k_code = k;
  205. return 0;
  206. }
  207. EXPORT_SYMBOL_GPL(rl6231_pll_calc);
  208. int rl6231_get_clk_info(int sclk, int rate)
  209. {
  210. int i;
  211. static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
  212. if (sclk <= 0 || rate <= 0)
  213. return -EINVAL;
  214. rate = rate << 8;
  215. for (i = 0; i < ARRAY_SIZE(pd); i++)
  216. if (sclk == rate * pd[i])
  217. return i;
  218. return -EINVAL;
  219. }
  220. EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
  221. MODULE_DESCRIPTION("RL6231 class device shared support");
  222. MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
  223. MODULE_LICENSE("GPL v2");