pcm512x.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the PCM512x CODECs
  4. *
  5. * Author: Mark Brown <broonie@kernel.org>
  6. * Copyright 2014 Linaro Ltd
  7. */
  8. #include <linux/init.h>
  9. #include <linux/module.h>
  10. #include <linux/clk.h>
  11. #include <linux/kernel.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/regmap.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/gcd.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/tlv.h>
  20. #include "pcm512x.h"
  21. #define PCM512x_NUM_SUPPLIES 3
  22. static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
  23. "AVDD",
  24. "DVDD",
  25. "CPVDD",
  26. };
  27. struct pcm512x_priv {
  28. struct regmap *regmap;
  29. struct clk *sclk;
  30. struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
  31. struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
  32. int fmt;
  33. int pll_in;
  34. int pll_out;
  35. int pll_r;
  36. int pll_j;
  37. int pll_d;
  38. int pll_p;
  39. unsigned long real_pll;
  40. unsigned long overclock_pll;
  41. unsigned long overclock_dac;
  42. unsigned long overclock_dsp;
  43. int mute;
  44. struct mutex mutex;
  45. unsigned int bclk_ratio;
  46. };
  47. /*
  48. * We can't use the same notifier block for more than one supply and
  49. * there's no way I can see to get from a callback to the caller
  50. * except container_of().
  51. */
  52. #define PCM512x_REGULATOR_EVENT(n) \
  53. static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
  54. unsigned long event, void *data) \
  55. { \
  56. struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
  57. supply_nb[n]); \
  58. if (event & REGULATOR_EVENT_DISABLE) { \
  59. regcache_mark_dirty(pcm512x->regmap); \
  60. regcache_cache_only(pcm512x->regmap, true); \
  61. } \
  62. return 0; \
  63. }
  64. PCM512x_REGULATOR_EVENT(0)
  65. PCM512x_REGULATOR_EVENT(1)
  66. PCM512x_REGULATOR_EVENT(2)
  67. static const struct reg_default pcm512x_reg_defaults[] = {
  68. { PCM512x_RESET, 0x00 },
  69. { PCM512x_POWER, 0x00 },
  70. { PCM512x_MUTE, 0x00 },
  71. { PCM512x_DSP, 0x00 },
  72. { PCM512x_PLL_REF, 0x00 },
  73. { PCM512x_DAC_REF, 0x00 },
  74. { PCM512x_DAC_ROUTING, 0x11 },
  75. { PCM512x_DSP_PROGRAM, 0x01 },
  76. { PCM512x_CLKDET, 0x00 },
  77. { PCM512x_AUTO_MUTE, 0x00 },
  78. { PCM512x_ERROR_DETECT, 0x00 },
  79. { PCM512x_DIGITAL_VOLUME_1, 0x00 },
  80. { PCM512x_DIGITAL_VOLUME_2, 0x30 },
  81. { PCM512x_DIGITAL_VOLUME_3, 0x30 },
  82. { PCM512x_DIGITAL_MUTE_1, 0x22 },
  83. { PCM512x_DIGITAL_MUTE_2, 0x00 },
  84. { PCM512x_DIGITAL_MUTE_3, 0x07 },
  85. { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
  86. { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
  87. { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
  88. { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
  89. { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
  90. { PCM512x_VCOM_CTRL_1, 0x00 },
  91. { PCM512x_VCOM_CTRL_2, 0x01 },
  92. { PCM512x_BCLK_LRCLK_CFG, 0x00 },
  93. { PCM512x_MASTER_MODE, 0x7c },
  94. { PCM512x_GPIO_DACIN, 0x00 },
  95. { PCM512x_GPIO_PLLIN, 0x00 },
  96. { PCM512x_SYNCHRONIZE, 0x10 },
  97. { PCM512x_PLL_COEFF_0, 0x00 },
  98. { PCM512x_PLL_COEFF_1, 0x00 },
  99. { PCM512x_PLL_COEFF_2, 0x00 },
  100. { PCM512x_PLL_COEFF_3, 0x00 },
  101. { PCM512x_PLL_COEFF_4, 0x00 },
  102. { PCM512x_DSP_CLKDIV, 0x00 },
  103. { PCM512x_DAC_CLKDIV, 0x00 },
  104. { PCM512x_NCP_CLKDIV, 0x00 },
  105. { PCM512x_OSR_CLKDIV, 0x00 },
  106. { PCM512x_MASTER_CLKDIV_1, 0x00 },
  107. { PCM512x_MASTER_CLKDIV_2, 0x00 },
  108. { PCM512x_FS_SPEED_MODE, 0x00 },
  109. { PCM512x_IDAC_1, 0x01 },
  110. { PCM512x_IDAC_2, 0x00 },
  111. };
  112. static bool pcm512x_readable(struct device *dev, unsigned int reg)
  113. {
  114. switch (reg) {
  115. case PCM512x_RESET:
  116. case PCM512x_POWER:
  117. case PCM512x_MUTE:
  118. case PCM512x_PLL_EN:
  119. case PCM512x_SPI_MISO_FUNCTION:
  120. case PCM512x_DSP:
  121. case PCM512x_GPIO_EN:
  122. case PCM512x_BCLK_LRCLK_CFG:
  123. case PCM512x_DSP_GPIO_INPUT:
  124. case PCM512x_MASTER_MODE:
  125. case PCM512x_PLL_REF:
  126. case PCM512x_DAC_REF:
  127. case PCM512x_GPIO_DACIN:
  128. case PCM512x_GPIO_PLLIN:
  129. case PCM512x_SYNCHRONIZE:
  130. case PCM512x_PLL_COEFF_0:
  131. case PCM512x_PLL_COEFF_1:
  132. case PCM512x_PLL_COEFF_2:
  133. case PCM512x_PLL_COEFF_3:
  134. case PCM512x_PLL_COEFF_4:
  135. case PCM512x_DSP_CLKDIV:
  136. case PCM512x_DAC_CLKDIV:
  137. case PCM512x_NCP_CLKDIV:
  138. case PCM512x_OSR_CLKDIV:
  139. case PCM512x_MASTER_CLKDIV_1:
  140. case PCM512x_MASTER_CLKDIV_2:
  141. case PCM512x_FS_SPEED_MODE:
  142. case PCM512x_IDAC_1:
  143. case PCM512x_IDAC_2:
  144. case PCM512x_ERROR_DETECT:
  145. case PCM512x_I2S_1:
  146. case PCM512x_I2S_2:
  147. case PCM512x_DAC_ROUTING:
  148. case PCM512x_DSP_PROGRAM:
  149. case PCM512x_CLKDET:
  150. case PCM512x_AUTO_MUTE:
  151. case PCM512x_DIGITAL_VOLUME_1:
  152. case PCM512x_DIGITAL_VOLUME_2:
  153. case PCM512x_DIGITAL_VOLUME_3:
  154. case PCM512x_DIGITAL_MUTE_1:
  155. case PCM512x_DIGITAL_MUTE_2:
  156. case PCM512x_DIGITAL_MUTE_3:
  157. case PCM512x_GPIO_OUTPUT_1:
  158. case PCM512x_GPIO_OUTPUT_2:
  159. case PCM512x_GPIO_OUTPUT_3:
  160. case PCM512x_GPIO_OUTPUT_4:
  161. case PCM512x_GPIO_OUTPUT_5:
  162. case PCM512x_GPIO_OUTPUT_6:
  163. case PCM512x_GPIO_CONTROL_1:
  164. case PCM512x_GPIO_CONTROL_2:
  165. case PCM512x_OVERFLOW:
  166. case PCM512x_RATE_DET_1:
  167. case PCM512x_RATE_DET_2:
  168. case PCM512x_RATE_DET_3:
  169. case PCM512x_RATE_DET_4:
  170. case PCM512x_CLOCK_STATUS:
  171. case PCM512x_ANALOG_MUTE_DET:
  172. case PCM512x_GPIN:
  173. case PCM512x_DIGITAL_MUTE_DET:
  174. case PCM512x_OUTPUT_AMPLITUDE:
  175. case PCM512x_ANALOG_GAIN_CTRL:
  176. case PCM512x_UNDERVOLTAGE_PROT:
  177. case PCM512x_ANALOG_MUTE_CTRL:
  178. case PCM512x_ANALOG_GAIN_BOOST:
  179. case PCM512x_VCOM_CTRL_1:
  180. case PCM512x_VCOM_CTRL_2:
  181. case PCM512x_CRAM_CTRL:
  182. case PCM512x_FLEX_A:
  183. case PCM512x_FLEX_B:
  184. return true;
  185. default:
  186. /* There are 256 raw register addresses */
  187. return reg < 0xff;
  188. }
  189. }
  190. static bool pcm512x_volatile(struct device *dev, unsigned int reg)
  191. {
  192. switch (reg) {
  193. case PCM512x_PLL_EN:
  194. case PCM512x_OVERFLOW:
  195. case PCM512x_RATE_DET_1:
  196. case PCM512x_RATE_DET_2:
  197. case PCM512x_RATE_DET_3:
  198. case PCM512x_RATE_DET_4:
  199. case PCM512x_CLOCK_STATUS:
  200. case PCM512x_ANALOG_MUTE_DET:
  201. case PCM512x_GPIN:
  202. case PCM512x_DIGITAL_MUTE_DET:
  203. case PCM512x_CRAM_CTRL:
  204. return true;
  205. default:
  206. /* There are 256 raw register addresses */
  207. return reg < 0xff;
  208. }
  209. }
  210. static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
  211. struct snd_ctl_elem_value *ucontrol)
  212. {
  213. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  214. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  215. ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
  216. return 0;
  217. }
  218. static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
  219. struct snd_ctl_elem_value *ucontrol)
  220. {
  221. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  222. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  223. switch (snd_soc_component_get_bias_level(component)) {
  224. case SND_SOC_BIAS_OFF:
  225. case SND_SOC_BIAS_STANDBY:
  226. break;
  227. default:
  228. return -EBUSY;
  229. }
  230. pcm512x->overclock_pll = ucontrol->value.integer.value[0];
  231. return 0;
  232. }
  233. static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
  234. struct snd_ctl_elem_value *ucontrol)
  235. {
  236. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  237. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  238. ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
  239. return 0;
  240. }
  241. static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
  242. struct snd_ctl_elem_value *ucontrol)
  243. {
  244. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  245. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  246. switch (snd_soc_component_get_bias_level(component)) {
  247. case SND_SOC_BIAS_OFF:
  248. case SND_SOC_BIAS_STANDBY:
  249. break;
  250. default:
  251. return -EBUSY;
  252. }
  253. pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
  254. return 0;
  255. }
  256. static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
  257. struct snd_ctl_elem_value *ucontrol)
  258. {
  259. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  260. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  261. ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
  262. return 0;
  263. }
  264. static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
  265. struct snd_ctl_elem_value *ucontrol)
  266. {
  267. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  268. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  269. switch (snd_soc_component_get_bias_level(component)) {
  270. case SND_SOC_BIAS_OFF:
  271. case SND_SOC_BIAS_STANDBY:
  272. break;
  273. default:
  274. return -EBUSY;
  275. }
  276. pcm512x->overclock_dac = ucontrol->value.integer.value[0];
  277. return 0;
  278. }
  279. static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
  280. static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
  281. static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
  282. static const char * const pcm512x_dsp_program_texts[] = {
  283. "FIR interpolation with de-emphasis",
  284. "Low latency IIR with de-emphasis",
  285. "High attenuation with de-emphasis",
  286. "Fixed process flow",
  287. "Ringing-less low latency FIR",
  288. };
  289. static const unsigned int pcm512x_dsp_program_values[] = {
  290. 1,
  291. 2,
  292. 3,
  293. 5,
  294. 7,
  295. };
  296. static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
  297. PCM512x_DSP_PROGRAM, 0, 0x1f,
  298. pcm512x_dsp_program_texts,
  299. pcm512x_dsp_program_values);
  300. static const char * const pcm512x_clk_missing_text[] = {
  301. "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
  302. };
  303. static const struct soc_enum pcm512x_clk_missing =
  304. SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
  305. static const char * const pcm512x_autom_text[] = {
  306. "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
  307. };
  308. static const struct soc_enum pcm512x_autom_l =
  309. SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
  310. pcm512x_autom_text);
  311. static const struct soc_enum pcm512x_autom_r =
  312. SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
  313. pcm512x_autom_text);
  314. static const char * const pcm512x_ramp_rate_text[] = {
  315. "1 sample/update", "2 samples/update", "4 samples/update",
  316. "Immediate"
  317. };
  318. static const struct soc_enum pcm512x_vndf =
  319. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
  320. pcm512x_ramp_rate_text);
  321. static const struct soc_enum pcm512x_vnuf =
  322. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
  323. pcm512x_ramp_rate_text);
  324. static const struct soc_enum pcm512x_vedf =
  325. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
  326. pcm512x_ramp_rate_text);
  327. static const char * const pcm512x_ramp_step_text[] = {
  328. "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
  329. };
  330. static const struct soc_enum pcm512x_vnds =
  331. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
  332. pcm512x_ramp_step_text);
  333. static const struct soc_enum pcm512x_vnus =
  334. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
  335. pcm512x_ramp_step_text);
  336. static const struct soc_enum pcm512x_veds =
  337. SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
  338. pcm512x_ramp_step_text);
  339. static int pcm512x_update_mute(struct pcm512x_priv *pcm512x)
  340. {
  341. return regmap_update_bits(
  342. pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR,
  343. (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT)
  344. | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT));
  345. }
  346. static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol,
  347. struct snd_ctl_elem_value *ucontrol)
  348. {
  349. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  350. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  351. mutex_lock(&pcm512x->mutex);
  352. ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4);
  353. ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2);
  354. mutex_unlock(&pcm512x->mutex);
  355. return 0;
  356. }
  357. static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol,
  358. struct snd_ctl_elem_value *ucontrol)
  359. {
  360. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  361. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  362. int ret, changed = 0;
  363. mutex_lock(&pcm512x->mutex);
  364. if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) {
  365. pcm512x->mute ^= 0x4;
  366. changed = 1;
  367. }
  368. if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) {
  369. pcm512x->mute ^= 0x2;
  370. changed = 1;
  371. }
  372. if (changed) {
  373. ret = pcm512x_update_mute(pcm512x);
  374. if (ret != 0) {
  375. dev_err(component->dev,
  376. "Failed to update digital mute: %d\n", ret);
  377. mutex_unlock(&pcm512x->mutex);
  378. return ret;
  379. }
  380. }
  381. mutex_unlock(&pcm512x->mutex);
  382. return changed;
  383. }
  384. static const struct snd_kcontrol_new pcm512x_controls[] = {
  385. SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
  386. PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
  387. SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
  388. PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
  389. SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
  390. PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
  391. {
  392. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  393. .name = "Digital Playback Switch",
  394. .index = 0,
  395. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  396. .info = snd_ctl_boolean_stereo_info,
  397. .get = pcm512x_digital_playback_switch_get,
  398. .put = pcm512x_digital_playback_switch_put
  399. },
  400. SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
  401. SOC_ENUM("DSP Program", pcm512x_dsp_program),
  402. SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
  403. SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
  404. SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
  405. SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
  406. PCM512x_ACTL_SHIFT, 1, 0),
  407. SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
  408. PCM512x_AMRE_SHIFT, 1, 0),
  409. SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
  410. SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
  411. SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
  412. SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
  413. SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
  414. SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
  415. SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
  416. pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
  417. SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
  418. pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
  419. SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
  420. pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
  421. };
  422. static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
  423. SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
  424. SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
  425. SND_SOC_DAPM_OUTPUT("OUTL"),
  426. SND_SOC_DAPM_OUTPUT("OUTR"),
  427. };
  428. static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
  429. { "DACL", NULL, "Playback" },
  430. { "DACR", NULL, "Playback" },
  431. { "OUTL", NULL, "DACL" },
  432. { "OUTR", NULL, "DACR" },
  433. };
  434. static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
  435. {
  436. return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
  437. }
  438. static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
  439. {
  440. return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
  441. }
  442. static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
  443. unsigned long rate)
  444. {
  445. return rate + rate * pcm512x->overclock_dac / 100;
  446. }
  447. static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
  448. {
  449. if (!pcm512x->pll_out)
  450. return 25000000;
  451. return pcm512x_pll_max(pcm512x);
  452. }
  453. static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
  454. unsigned long dac_rate)
  455. {
  456. /*
  457. * If the DAC is not actually overclocked, use the good old
  458. * NCP target rate...
  459. */
  460. if (dac_rate <= 6144000)
  461. return 1536000;
  462. /*
  463. * ...but if the DAC is in fact overclocked, bump the NCP target
  464. * rate to get the recommended dividers even when overclocking.
  465. */
  466. return pcm512x_dac_max(pcm512x, 1536000);
  467. }
  468. static const u32 pcm512x_dai_rates[] = {
  469. 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
  470. 88200, 96000, 176400, 192000, 384000,
  471. };
  472. static const struct snd_pcm_hw_constraint_list constraints_slave = {
  473. .count = ARRAY_SIZE(pcm512x_dai_rates),
  474. .list = pcm512x_dai_rates,
  475. };
  476. static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
  477. struct snd_pcm_hw_rule *rule)
  478. {
  479. struct pcm512x_priv *pcm512x = rule->private;
  480. struct snd_interval ranges[2];
  481. int frame_size;
  482. frame_size = snd_soc_params_to_frame_size(params);
  483. if (frame_size < 0)
  484. return frame_size;
  485. switch (frame_size) {
  486. case 32:
  487. /* No hole when the frame size is 32. */
  488. return 0;
  489. case 48:
  490. case 64:
  491. /* There is only one hole in the range of supported
  492. * rates, but it moves with the frame size.
  493. */
  494. memset(ranges, 0, sizeof(ranges));
  495. ranges[0].min = 8000;
  496. ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
  497. ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
  498. ranges[1].max = 384000;
  499. break;
  500. default:
  501. return -EINVAL;
  502. }
  503. return snd_interval_ranges(hw_param_interval(params, rule->var),
  504. ARRAY_SIZE(ranges), ranges, 0);
  505. }
  506. static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
  507. struct snd_soc_dai *dai)
  508. {
  509. struct snd_soc_component *component = dai->component;
  510. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  511. struct device *dev = dai->dev;
  512. struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
  513. struct snd_ratnum *rats_no_pll;
  514. if (IS_ERR(pcm512x->sclk)) {
  515. dev_err(dev, "Need SCLK for master mode: %ld\n",
  516. PTR_ERR(pcm512x->sclk));
  517. return PTR_ERR(pcm512x->sclk);
  518. }
  519. if (pcm512x->pll_out)
  520. return snd_pcm_hw_rule_add(substream->runtime, 0,
  521. SNDRV_PCM_HW_PARAM_RATE,
  522. pcm512x_hw_rule_rate,
  523. pcm512x,
  524. SNDRV_PCM_HW_PARAM_FRAME_BITS,
  525. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  526. constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
  527. GFP_KERNEL);
  528. if (!constraints_no_pll)
  529. return -ENOMEM;
  530. constraints_no_pll->nrats = 1;
  531. rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
  532. if (!rats_no_pll)
  533. return -ENOMEM;
  534. constraints_no_pll->rats = rats_no_pll;
  535. rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
  536. rats_no_pll->den_min = 1;
  537. rats_no_pll->den_max = 128;
  538. rats_no_pll->den_step = 1;
  539. return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
  540. SNDRV_PCM_HW_PARAM_RATE,
  541. constraints_no_pll);
  542. }
  543. static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
  544. struct snd_soc_dai *dai)
  545. {
  546. struct snd_soc_component *component = dai->component;
  547. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  548. struct device *dev = dai->dev;
  549. struct regmap *regmap = pcm512x->regmap;
  550. if (IS_ERR(pcm512x->sclk)) {
  551. dev_info(dev, "No SCLK, using BCLK: %ld\n",
  552. PTR_ERR(pcm512x->sclk));
  553. /* Disable reporting of missing SCLK as an error */
  554. regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
  555. PCM512x_IDCH, PCM512x_IDCH);
  556. /* Switch PLL input to BCLK */
  557. regmap_update_bits(regmap, PCM512x_PLL_REF,
  558. PCM512x_SREF, PCM512x_SREF_BCK);
  559. }
  560. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  561. SNDRV_PCM_HW_PARAM_RATE,
  562. &constraints_slave);
  563. }
  564. static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
  565. struct snd_soc_dai *dai)
  566. {
  567. struct snd_soc_component *component = dai->component;
  568. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  569. switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  570. case SND_SOC_DAIFMT_CBM_CFM:
  571. case SND_SOC_DAIFMT_CBM_CFS:
  572. return pcm512x_dai_startup_master(substream, dai);
  573. case SND_SOC_DAIFMT_CBS_CFS:
  574. return pcm512x_dai_startup_slave(substream, dai);
  575. default:
  576. return -EINVAL;
  577. }
  578. }
  579. static int pcm512x_set_bias_level(struct snd_soc_component *component,
  580. enum snd_soc_bias_level level)
  581. {
  582. struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
  583. int ret;
  584. switch (level) {
  585. case SND_SOC_BIAS_ON:
  586. case SND_SOC_BIAS_PREPARE:
  587. break;
  588. case SND_SOC_BIAS_STANDBY:
  589. ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
  590. PCM512x_RQST, 0);
  591. if (ret != 0) {
  592. dev_err(component->dev, "Failed to remove standby: %d\n",
  593. ret);
  594. return ret;
  595. }
  596. break;
  597. case SND_SOC_BIAS_OFF:
  598. ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
  599. PCM512x_RQST, PCM512x_RQST);
  600. if (ret != 0) {
  601. dev_err(component->dev, "Failed to request standby: %d\n",
  602. ret);
  603. return ret;
  604. }
  605. break;
  606. }
  607. return 0;
  608. }
  609. static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
  610. unsigned long bclk_rate)
  611. {
  612. struct device *dev = dai->dev;
  613. struct snd_soc_component *component = dai->component;
  614. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  615. unsigned long sck_rate;
  616. int pow2;
  617. /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
  618. /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
  619. /* select sck_rate as a multiple of bclk_rate but still with
  620. * as many factors of 2 as possible, as that makes it easier
  621. * to find a fast DAC rate
  622. */
  623. pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
  624. for (; pow2; pow2 >>= 1) {
  625. sck_rate = rounddown(pcm512x_pll_max(pcm512x),
  626. bclk_rate * pow2);
  627. if (sck_rate >= 16000000)
  628. break;
  629. }
  630. if (!pow2) {
  631. dev_err(dev, "Impossible to generate a suitable SCK\n");
  632. return 0;
  633. }
  634. dev_dbg(dev, "sck_rate %lu\n", sck_rate);
  635. return sck_rate;
  636. }
  637. /* pll_rate = pllin_rate * R * J.D / P
  638. * 1 <= R <= 16
  639. * 1 <= J <= 63
  640. * 0 <= D <= 9999
  641. * 1 <= P <= 15
  642. * 64 MHz <= pll_rate <= 100 MHz
  643. * if D == 0
  644. * 1 MHz <= pllin_rate / P <= 20 MHz
  645. * else if D > 0
  646. * 6.667 MHz <= pllin_rate / P <= 20 MHz
  647. * 4 <= J <= 11
  648. * R = 1
  649. */
  650. static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
  651. unsigned long pllin_rate,
  652. unsigned long pll_rate)
  653. {
  654. struct device *dev = dai->dev;
  655. struct snd_soc_component *component = dai->component;
  656. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  657. unsigned long common;
  658. int R, J, D, P;
  659. unsigned long K; /* 10000 * J.D */
  660. unsigned long num;
  661. unsigned long den;
  662. common = gcd(pll_rate, pllin_rate);
  663. dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
  664. pll_rate, pllin_rate, common);
  665. num = pll_rate / common;
  666. den = pllin_rate / common;
  667. /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
  668. if (pllin_rate / den > 20000000 && num < 8) {
  669. num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
  670. den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
  671. }
  672. dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
  673. P = den;
  674. if (den <= 15 && num <= 16 * 63
  675. && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
  676. /* Try the case with D = 0 */
  677. D = 0;
  678. /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
  679. for (R = 16; R; R--) {
  680. if (num % R)
  681. continue;
  682. J = num / R;
  683. if (J == 0 || J > 63)
  684. continue;
  685. dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
  686. pcm512x->real_pll = pll_rate;
  687. goto done;
  688. }
  689. /* no luck */
  690. }
  691. R = 1;
  692. if (num > 0xffffffffUL / 10000)
  693. goto fallback;
  694. /* Try to find an exact pll_rate using the D > 0 case */
  695. common = gcd(10000 * num, den);
  696. num = 10000 * num / common;
  697. den /= common;
  698. dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
  699. for (P = den; P <= 15; P++) {
  700. if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
  701. continue;
  702. if (num * P % den)
  703. continue;
  704. K = num * P / den;
  705. /* J == 12 is ok if D == 0 */
  706. if (K < 40000 || K > 120000)
  707. continue;
  708. J = K / 10000;
  709. D = K % 10000;
  710. dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
  711. pcm512x->real_pll = pll_rate;
  712. goto done;
  713. }
  714. /* Fall back to an approximate pll_rate */
  715. fallback:
  716. /* find smallest possible P */
  717. P = DIV_ROUND_UP(pllin_rate, 20000000);
  718. if (!P)
  719. P = 1;
  720. else if (P > 15) {
  721. dev_err(dev, "Need a slower clock as pll-input\n");
  722. return -EINVAL;
  723. }
  724. if (pllin_rate / P < 6667000) {
  725. dev_err(dev, "Need a faster clock as pll-input\n");
  726. return -EINVAL;
  727. }
  728. K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
  729. if (K < 40000)
  730. K = 40000;
  731. /* J == 12 is ok if D == 0 */
  732. if (K > 120000)
  733. K = 120000;
  734. J = K / 10000;
  735. D = K % 10000;
  736. dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
  737. pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
  738. done:
  739. pcm512x->pll_r = R;
  740. pcm512x->pll_j = J;
  741. pcm512x->pll_d = D;
  742. pcm512x->pll_p = P;
  743. return 0;
  744. }
  745. static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
  746. unsigned long osr_rate,
  747. unsigned long pllin_rate)
  748. {
  749. struct snd_soc_component *component = dai->component;
  750. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  751. unsigned long dac_rate;
  752. if (!pcm512x->pll_out)
  753. return 0; /* no PLL to bypass, force SCK as DAC input */
  754. if (pllin_rate % osr_rate)
  755. return 0; /* futile, quit early */
  756. /* run DAC no faster than 6144000 Hz */
  757. for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
  758. dac_rate;
  759. dac_rate -= osr_rate) {
  760. if (pllin_rate / dac_rate > 128)
  761. return 0; /* DAC divider would be too big */
  762. if (!(pllin_rate % dac_rate))
  763. return dac_rate;
  764. dac_rate -= osr_rate;
  765. }
  766. return 0;
  767. }
  768. static int pcm512x_set_dividers(struct snd_soc_dai *dai,
  769. struct snd_pcm_hw_params *params)
  770. {
  771. struct device *dev = dai->dev;
  772. struct snd_soc_component *component = dai->component;
  773. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  774. unsigned long pllin_rate = 0;
  775. unsigned long pll_rate;
  776. unsigned long sck_rate;
  777. unsigned long mck_rate;
  778. unsigned long bclk_rate;
  779. unsigned long sample_rate;
  780. unsigned long osr_rate;
  781. unsigned long dacsrc_rate;
  782. int bclk_div;
  783. int lrclk_div;
  784. int dsp_div;
  785. int dac_div;
  786. unsigned long dac_rate;
  787. int ncp_div;
  788. int osr_div;
  789. int ret;
  790. int idac;
  791. int fssp;
  792. int gpio;
  793. if (pcm512x->bclk_ratio > 0) {
  794. lrclk_div = pcm512x->bclk_ratio;
  795. } else {
  796. lrclk_div = snd_soc_params_to_frame_size(params);
  797. if (lrclk_div == 0) {
  798. dev_err(dev, "No LRCLK?\n");
  799. return -EINVAL;
  800. }
  801. }
  802. if (!pcm512x->pll_out) {
  803. sck_rate = clk_get_rate(pcm512x->sclk);
  804. bclk_rate = params_rate(params) * lrclk_div;
  805. bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
  806. mck_rate = sck_rate;
  807. } else {
  808. ret = snd_soc_params_to_bclk(params);
  809. if (ret < 0) {
  810. dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
  811. return ret;
  812. }
  813. if (ret == 0) {
  814. dev_err(dev, "No BCLK?\n");
  815. return -EINVAL;
  816. }
  817. bclk_rate = ret;
  818. pllin_rate = clk_get_rate(pcm512x->sclk);
  819. sck_rate = pcm512x_find_sck(dai, bclk_rate);
  820. if (!sck_rate)
  821. return -EINVAL;
  822. pll_rate = 4 * sck_rate;
  823. ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
  824. if (ret != 0)
  825. return ret;
  826. ret = regmap_write(pcm512x->regmap,
  827. PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
  828. if (ret != 0) {
  829. dev_err(dev, "Failed to write PLL P: %d\n", ret);
  830. return ret;
  831. }
  832. ret = regmap_write(pcm512x->regmap,
  833. PCM512x_PLL_COEFF_1, pcm512x->pll_j);
  834. if (ret != 0) {
  835. dev_err(dev, "Failed to write PLL J: %d\n", ret);
  836. return ret;
  837. }
  838. ret = regmap_write(pcm512x->regmap,
  839. PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
  840. if (ret != 0) {
  841. dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
  842. return ret;
  843. }
  844. ret = regmap_write(pcm512x->regmap,
  845. PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
  846. if (ret != 0) {
  847. dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
  848. return ret;
  849. }
  850. ret = regmap_write(pcm512x->regmap,
  851. PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
  852. if (ret != 0) {
  853. dev_err(dev, "Failed to write PLL R: %d\n", ret);
  854. return ret;
  855. }
  856. mck_rate = pcm512x->real_pll;
  857. bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
  858. }
  859. if (bclk_div > 128) {
  860. dev_err(dev, "Failed to find BCLK divider\n");
  861. return -EINVAL;
  862. }
  863. /* the actual rate */
  864. sample_rate = sck_rate / bclk_div / lrclk_div;
  865. osr_rate = 16 * sample_rate;
  866. /* run DSP no faster than 50 MHz */
  867. dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
  868. dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
  869. if (dac_rate) {
  870. /* the desired clock rate is "compatible" with the pll input
  871. * clock, so use that clock as dac input instead of the pll
  872. * output clock since the pll will introduce jitter and thus
  873. * noise.
  874. */
  875. dev_dbg(dev, "using pll input as dac input\n");
  876. ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
  877. PCM512x_SDAC, PCM512x_SDAC_GPIO);
  878. if (ret != 0) {
  879. dev_err(component->dev,
  880. "Failed to set gpio as dacref: %d\n", ret);
  881. return ret;
  882. }
  883. gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
  884. ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
  885. PCM512x_GREF, gpio);
  886. if (ret != 0) {
  887. dev_err(component->dev,
  888. "Failed to set gpio %d as dacin: %d\n",
  889. pcm512x->pll_in, ret);
  890. return ret;
  891. }
  892. dacsrc_rate = pllin_rate;
  893. } else {
  894. /* run DAC no faster than 6144000 Hz */
  895. unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
  896. / osr_rate;
  897. unsigned long sck_mul = sck_rate / osr_rate;
  898. for (; dac_mul; dac_mul--) {
  899. if (!(sck_mul % dac_mul))
  900. break;
  901. }
  902. if (!dac_mul) {
  903. dev_err(dev, "Failed to find DAC rate\n");
  904. return -EINVAL;
  905. }
  906. dac_rate = dac_mul * osr_rate;
  907. dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
  908. dac_rate, sample_rate);
  909. ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
  910. PCM512x_SDAC, PCM512x_SDAC_SCK);
  911. if (ret != 0) {
  912. dev_err(component->dev,
  913. "Failed to set sck as dacref: %d\n", ret);
  914. return ret;
  915. }
  916. dacsrc_rate = sck_rate;
  917. }
  918. osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
  919. if (osr_div > 128) {
  920. dev_err(dev, "Failed to find OSR divider\n");
  921. return -EINVAL;
  922. }
  923. dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
  924. if (dac_div > 128) {
  925. dev_err(dev, "Failed to find DAC divider\n");
  926. return -EINVAL;
  927. }
  928. dac_rate = dacsrc_rate / dac_div;
  929. ncp_div = DIV_ROUND_CLOSEST(dac_rate,
  930. pcm512x_ncp_target(pcm512x, dac_rate));
  931. if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
  932. /* run NCP no faster than 2048000 Hz, but why? */
  933. ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
  934. if (ncp_div > 128) {
  935. dev_err(dev, "Failed to find NCP divider\n");
  936. return -EINVAL;
  937. }
  938. }
  939. idac = mck_rate / (dsp_div * sample_rate);
  940. ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
  941. if (ret != 0) {
  942. dev_err(dev, "Failed to write DSP divider: %d\n", ret);
  943. return ret;
  944. }
  945. ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
  946. if (ret != 0) {
  947. dev_err(dev, "Failed to write DAC divider: %d\n", ret);
  948. return ret;
  949. }
  950. ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
  951. if (ret != 0) {
  952. dev_err(dev, "Failed to write NCP divider: %d\n", ret);
  953. return ret;
  954. }
  955. ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
  956. if (ret != 0) {
  957. dev_err(dev, "Failed to write OSR divider: %d\n", ret);
  958. return ret;
  959. }
  960. ret = regmap_write(pcm512x->regmap,
  961. PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
  962. if (ret != 0) {
  963. dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
  964. return ret;
  965. }
  966. ret = regmap_write(pcm512x->regmap,
  967. PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
  968. if (ret != 0) {
  969. dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
  970. return ret;
  971. }
  972. ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
  973. if (ret != 0) {
  974. dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
  975. return ret;
  976. }
  977. ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
  978. if (ret != 0) {
  979. dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
  980. return ret;
  981. }
  982. if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
  983. fssp = PCM512x_FSSP_48KHZ;
  984. else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
  985. fssp = PCM512x_FSSP_96KHZ;
  986. else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
  987. fssp = PCM512x_FSSP_192KHZ;
  988. else
  989. fssp = PCM512x_FSSP_384KHZ;
  990. ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
  991. PCM512x_FSSP, fssp);
  992. if (ret != 0) {
  993. dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
  994. return ret;
  995. }
  996. dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
  997. dev_dbg(component->dev, "DAC divider %d\n", dac_div);
  998. dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
  999. dev_dbg(component->dev, "OSR divider %d\n", osr_div);
  1000. dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
  1001. dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
  1002. dev_dbg(component->dev, "IDAC %d\n", idac);
  1003. dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
  1004. return 0;
  1005. }
  1006. static int pcm512x_hw_params(struct snd_pcm_substream *substream,
  1007. struct snd_pcm_hw_params *params,
  1008. struct snd_soc_dai *dai)
  1009. {
  1010. struct snd_soc_component *component = dai->component;
  1011. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  1012. int alen;
  1013. int gpio;
  1014. int clock_output;
  1015. int master_mode;
  1016. int ret;
  1017. dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
  1018. params_rate(params),
  1019. params_channels(params));
  1020. switch (params_width(params)) {
  1021. case 16:
  1022. alen = PCM512x_ALEN_16;
  1023. break;
  1024. case 20:
  1025. alen = PCM512x_ALEN_20;
  1026. break;
  1027. case 24:
  1028. alen = PCM512x_ALEN_24;
  1029. break;
  1030. case 32:
  1031. alen = PCM512x_ALEN_32;
  1032. break;
  1033. default:
  1034. dev_err(component->dev, "Bad frame size: %d\n",
  1035. params_width(params));
  1036. return -EINVAL;
  1037. }
  1038. switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1039. case SND_SOC_DAIFMT_CBS_CFS:
  1040. ret = regmap_update_bits(pcm512x->regmap,
  1041. PCM512x_BCLK_LRCLK_CFG,
  1042. PCM512x_BCKP
  1043. | PCM512x_BCKO | PCM512x_LRKO,
  1044. 0);
  1045. if (ret != 0) {
  1046. dev_err(component->dev,
  1047. "Failed to enable slave mode: %d\n", ret);
  1048. return ret;
  1049. }
  1050. ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
  1051. PCM512x_DCAS, 0);
  1052. if (ret != 0) {
  1053. dev_err(component->dev,
  1054. "Failed to enable clock divider autoset: %d\n",
  1055. ret);
  1056. return ret;
  1057. }
  1058. return 0;
  1059. case SND_SOC_DAIFMT_CBM_CFM:
  1060. clock_output = PCM512x_BCKO | PCM512x_LRKO;
  1061. master_mode = PCM512x_RLRK | PCM512x_RBCK;
  1062. break;
  1063. case SND_SOC_DAIFMT_CBM_CFS:
  1064. clock_output = PCM512x_BCKO;
  1065. master_mode = PCM512x_RBCK;
  1066. break;
  1067. default:
  1068. return -EINVAL;
  1069. }
  1070. ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
  1071. PCM512x_ALEN, alen);
  1072. if (ret != 0) {
  1073. dev_err(component->dev, "Failed to set frame size: %d\n", ret);
  1074. return ret;
  1075. }
  1076. if (pcm512x->pll_out) {
  1077. ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
  1078. if (ret != 0) {
  1079. dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
  1080. return ret;
  1081. }
  1082. ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
  1083. if (ret != 0) {
  1084. dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
  1085. return ret;
  1086. }
  1087. ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
  1088. PCM512x_IDFS | PCM512x_IDBK
  1089. | PCM512x_IDSK | PCM512x_IDCH
  1090. | PCM512x_IDCM | PCM512x_DCAS
  1091. | PCM512x_IPLK,
  1092. PCM512x_IDFS | PCM512x_IDBK
  1093. | PCM512x_IDSK | PCM512x_IDCH
  1094. | PCM512x_DCAS);
  1095. if (ret != 0) {
  1096. dev_err(component->dev,
  1097. "Failed to ignore auto-clock failures: %d\n",
  1098. ret);
  1099. return ret;
  1100. }
  1101. } else {
  1102. ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
  1103. PCM512x_IDFS | PCM512x_IDBK
  1104. | PCM512x_IDSK | PCM512x_IDCH
  1105. | PCM512x_IDCM | PCM512x_DCAS
  1106. | PCM512x_IPLK,
  1107. PCM512x_IDFS | PCM512x_IDBK
  1108. | PCM512x_IDSK | PCM512x_IDCH
  1109. | PCM512x_DCAS | PCM512x_IPLK);
  1110. if (ret != 0) {
  1111. dev_err(component->dev,
  1112. "Failed to ignore auto-clock failures: %d\n",
  1113. ret);
  1114. return ret;
  1115. }
  1116. ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
  1117. PCM512x_PLLE, 0);
  1118. if (ret != 0) {
  1119. dev_err(component->dev, "Failed to disable pll: %d\n", ret);
  1120. return ret;
  1121. }
  1122. }
  1123. ret = pcm512x_set_dividers(dai, params);
  1124. if (ret != 0)
  1125. return ret;
  1126. if (pcm512x->pll_out) {
  1127. ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
  1128. PCM512x_SREF, PCM512x_SREF_GPIO);
  1129. if (ret != 0) {
  1130. dev_err(component->dev,
  1131. "Failed to set gpio as pllref: %d\n", ret);
  1132. return ret;
  1133. }
  1134. gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
  1135. ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
  1136. PCM512x_GREF, gpio);
  1137. if (ret != 0) {
  1138. dev_err(component->dev,
  1139. "Failed to set gpio %d as pllin: %d\n",
  1140. pcm512x->pll_in, ret);
  1141. return ret;
  1142. }
  1143. ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
  1144. PCM512x_PLLE, PCM512x_PLLE);
  1145. if (ret != 0) {
  1146. dev_err(component->dev, "Failed to enable pll: %d\n", ret);
  1147. return ret;
  1148. }
  1149. }
  1150. ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
  1151. PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
  1152. clock_output);
  1153. if (ret != 0) {
  1154. dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
  1155. return ret;
  1156. }
  1157. ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
  1158. PCM512x_RLRK | PCM512x_RBCK,
  1159. master_mode);
  1160. if (ret != 0) {
  1161. dev_err(component->dev, "Failed to enable master mode: %d\n", ret);
  1162. return ret;
  1163. }
  1164. if (pcm512x->pll_out) {
  1165. gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
  1166. ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
  1167. gpio, gpio);
  1168. if (ret != 0) {
  1169. dev_err(component->dev, "Failed to enable gpio %d: %d\n",
  1170. pcm512x->pll_out, ret);
  1171. return ret;
  1172. }
  1173. gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
  1174. ret = regmap_update_bits(pcm512x->regmap, gpio,
  1175. PCM512x_GxSL, PCM512x_GxSL_PLLCK);
  1176. if (ret != 0) {
  1177. dev_err(component->dev, "Failed to output pll on %d: %d\n",
  1178. ret, pcm512x->pll_out);
  1179. return ret;
  1180. }
  1181. }
  1182. ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
  1183. PCM512x_RQSY, PCM512x_RQSY_HALT);
  1184. if (ret != 0) {
  1185. dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
  1186. return ret;
  1187. }
  1188. ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
  1189. PCM512x_RQSY, PCM512x_RQSY_RESUME);
  1190. if (ret != 0) {
  1191. dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
  1192. return ret;
  1193. }
  1194. return 0;
  1195. }
  1196. static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1197. {
  1198. struct snd_soc_component *component = dai->component;
  1199. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  1200. pcm512x->fmt = fmt;
  1201. return 0;
  1202. }
  1203. static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  1204. {
  1205. struct snd_soc_component *component = dai->component;
  1206. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  1207. if (ratio > 256)
  1208. return -EINVAL;
  1209. pcm512x->bclk_ratio = ratio;
  1210. return 0;
  1211. }
  1212. static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction)
  1213. {
  1214. struct snd_soc_component *component = dai->component;
  1215. struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
  1216. int ret;
  1217. unsigned int mute_det;
  1218. mutex_lock(&pcm512x->mutex);
  1219. if (mute) {
  1220. pcm512x->mute |= 0x1;
  1221. ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE,
  1222. PCM512x_RQML | PCM512x_RQMR,
  1223. PCM512x_RQML | PCM512x_RQMR);
  1224. if (ret != 0) {
  1225. dev_err(component->dev,
  1226. "Failed to set digital mute: %d\n", ret);
  1227. goto unlock;
  1228. }
  1229. regmap_read_poll_timeout(pcm512x->regmap,
  1230. PCM512x_ANALOG_MUTE_DET,
  1231. mute_det, (mute_det & 0x3) == 0,
  1232. 200, 10000);
  1233. } else {
  1234. pcm512x->mute &= ~0x1;
  1235. ret = pcm512x_update_mute(pcm512x);
  1236. if (ret != 0) {
  1237. dev_err(component->dev,
  1238. "Failed to update digital mute: %d\n", ret);
  1239. goto unlock;
  1240. }
  1241. regmap_read_poll_timeout(pcm512x->regmap,
  1242. PCM512x_ANALOG_MUTE_DET,
  1243. mute_det,
  1244. (mute_det & 0x3)
  1245. == ((~pcm512x->mute >> 1) & 0x3),
  1246. 200, 10000);
  1247. }
  1248. unlock:
  1249. mutex_unlock(&pcm512x->mutex);
  1250. return ret;
  1251. }
  1252. static const struct snd_soc_dai_ops pcm512x_dai_ops = {
  1253. .startup = pcm512x_dai_startup,
  1254. .hw_params = pcm512x_hw_params,
  1255. .set_fmt = pcm512x_set_fmt,
  1256. .mute_stream = pcm512x_mute,
  1257. .set_bclk_ratio = pcm512x_set_bclk_ratio,
  1258. .no_capture_mute = 1,
  1259. };
  1260. static struct snd_soc_dai_driver pcm512x_dai = {
  1261. .name = "pcm512x-hifi",
  1262. .playback = {
  1263. .stream_name = "Playback",
  1264. .channels_min = 2,
  1265. .channels_max = 2,
  1266. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  1267. .rate_min = 8000,
  1268. .rate_max = 384000,
  1269. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  1270. SNDRV_PCM_FMTBIT_S24_LE |
  1271. SNDRV_PCM_FMTBIT_S32_LE
  1272. },
  1273. .ops = &pcm512x_dai_ops,
  1274. };
  1275. static const struct snd_soc_component_driver pcm512x_component_driver = {
  1276. .set_bias_level = pcm512x_set_bias_level,
  1277. .controls = pcm512x_controls,
  1278. .num_controls = ARRAY_SIZE(pcm512x_controls),
  1279. .dapm_widgets = pcm512x_dapm_widgets,
  1280. .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
  1281. .dapm_routes = pcm512x_dapm_routes,
  1282. .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
  1283. .use_pmdown_time = 1,
  1284. .endianness = 1,
  1285. .non_legacy_dai_naming = 1,
  1286. };
  1287. static const struct regmap_range_cfg pcm512x_range = {
  1288. .name = "Pages", .range_min = PCM512x_VIRT_BASE,
  1289. .range_max = PCM512x_MAX_REGISTER,
  1290. .selector_reg = PCM512x_PAGE,
  1291. .selector_mask = 0xff,
  1292. .window_start = 0, .window_len = 0x100,
  1293. };
  1294. const struct regmap_config pcm512x_regmap = {
  1295. .reg_bits = 8,
  1296. .val_bits = 8,
  1297. .readable_reg = pcm512x_readable,
  1298. .volatile_reg = pcm512x_volatile,
  1299. .ranges = &pcm512x_range,
  1300. .num_ranges = 1,
  1301. .max_register = PCM512x_MAX_REGISTER,
  1302. .reg_defaults = pcm512x_reg_defaults,
  1303. .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
  1304. .cache_type = REGCACHE_RBTREE,
  1305. };
  1306. EXPORT_SYMBOL_GPL(pcm512x_regmap);
  1307. int pcm512x_probe(struct device *dev, struct regmap *regmap)
  1308. {
  1309. struct pcm512x_priv *pcm512x;
  1310. int i, ret;
  1311. pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
  1312. if (!pcm512x)
  1313. return -ENOMEM;
  1314. mutex_init(&pcm512x->mutex);
  1315. dev_set_drvdata(dev, pcm512x);
  1316. pcm512x->regmap = regmap;
  1317. for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
  1318. pcm512x->supplies[i].supply = pcm512x_supply_names[i];
  1319. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
  1320. pcm512x->supplies);
  1321. if (ret != 0) {
  1322. dev_err(dev, "Failed to get supplies: %d\n", ret);
  1323. return ret;
  1324. }
  1325. pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
  1326. pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
  1327. pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
  1328. for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
  1329. ret = devm_regulator_register_notifier(
  1330. pcm512x->supplies[i].consumer,
  1331. &pcm512x->supply_nb[i]);
  1332. if (ret != 0) {
  1333. dev_err(dev,
  1334. "Failed to register regulator notifier: %d\n",
  1335. ret);
  1336. }
  1337. }
  1338. ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
  1339. pcm512x->supplies);
  1340. if (ret != 0) {
  1341. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  1342. return ret;
  1343. }
  1344. /* Reset the device, verifying I/O in the process for I2C */
  1345. ret = regmap_write(regmap, PCM512x_RESET,
  1346. PCM512x_RSTM | PCM512x_RSTR);
  1347. if (ret != 0) {
  1348. dev_err(dev, "Failed to reset device: %d\n", ret);
  1349. goto err;
  1350. }
  1351. ret = regmap_write(regmap, PCM512x_RESET, 0);
  1352. if (ret != 0) {
  1353. dev_err(dev, "Failed to reset device: %d\n", ret);
  1354. goto err;
  1355. }
  1356. pcm512x->sclk = devm_clk_get(dev, NULL);
  1357. if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
  1358. ret = -EPROBE_DEFER;
  1359. goto err;
  1360. }
  1361. if (!IS_ERR(pcm512x->sclk)) {
  1362. ret = clk_prepare_enable(pcm512x->sclk);
  1363. if (ret != 0) {
  1364. dev_err(dev, "Failed to enable SCLK: %d\n", ret);
  1365. goto err;
  1366. }
  1367. }
  1368. /* Default to standby mode */
  1369. ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
  1370. PCM512x_RQST, PCM512x_RQST);
  1371. if (ret != 0) {
  1372. dev_err(dev, "Failed to request standby: %d\n",
  1373. ret);
  1374. goto err_clk;
  1375. }
  1376. pm_runtime_set_active(dev);
  1377. pm_runtime_enable(dev);
  1378. pm_runtime_idle(dev);
  1379. #ifdef CONFIG_OF
  1380. if (dev->of_node) {
  1381. const struct device_node *np = dev->of_node;
  1382. u32 val;
  1383. if (of_property_read_u32(np, "pll-in", &val) >= 0) {
  1384. if (val > 6) {
  1385. dev_err(dev, "Invalid pll-in\n");
  1386. ret = -EINVAL;
  1387. goto err_clk;
  1388. }
  1389. pcm512x->pll_in = val;
  1390. }
  1391. if (of_property_read_u32(np, "pll-out", &val) >= 0) {
  1392. if (val > 6) {
  1393. dev_err(dev, "Invalid pll-out\n");
  1394. ret = -EINVAL;
  1395. goto err_clk;
  1396. }
  1397. pcm512x->pll_out = val;
  1398. }
  1399. if (!pcm512x->pll_in != !pcm512x->pll_out) {
  1400. dev_err(dev,
  1401. "Error: both pll-in and pll-out, or none\n");
  1402. ret = -EINVAL;
  1403. goto err_clk;
  1404. }
  1405. if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
  1406. dev_err(dev, "Error: pll-in == pll-out\n");
  1407. ret = -EINVAL;
  1408. goto err_clk;
  1409. }
  1410. }
  1411. #endif
  1412. ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
  1413. &pcm512x_dai, 1);
  1414. if (ret != 0) {
  1415. dev_err(dev, "Failed to register CODEC: %d\n", ret);
  1416. goto err_pm;
  1417. }
  1418. return 0;
  1419. err_pm:
  1420. pm_runtime_disable(dev);
  1421. err_clk:
  1422. if (!IS_ERR(pcm512x->sclk))
  1423. clk_disable_unprepare(pcm512x->sclk);
  1424. err:
  1425. regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
  1426. pcm512x->supplies);
  1427. return ret;
  1428. }
  1429. EXPORT_SYMBOL_GPL(pcm512x_probe);
  1430. void pcm512x_remove(struct device *dev)
  1431. {
  1432. struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
  1433. pm_runtime_disable(dev);
  1434. if (!IS_ERR(pcm512x->sclk))
  1435. clk_disable_unprepare(pcm512x->sclk);
  1436. regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
  1437. pcm512x->supplies);
  1438. }
  1439. EXPORT_SYMBOL_GPL(pcm512x_remove);
  1440. #ifdef CONFIG_PM
  1441. static int pcm512x_suspend(struct device *dev)
  1442. {
  1443. struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
  1444. int ret;
  1445. ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
  1446. PCM512x_RQPD, PCM512x_RQPD);
  1447. if (ret != 0) {
  1448. dev_err(dev, "Failed to request power down: %d\n", ret);
  1449. return ret;
  1450. }
  1451. ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
  1452. pcm512x->supplies);
  1453. if (ret != 0) {
  1454. dev_err(dev, "Failed to disable supplies: %d\n", ret);
  1455. return ret;
  1456. }
  1457. if (!IS_ERR(pcm512x->sclk))
  1458. clk_disable_unprepare(pcm512x->sclk);
  1459. return 0;
  1460. }
  1461. static int pcm512x_resume(struct device *dev)
  1462. {
  1463. struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
  1464. int ret;
  1465. if (!IS_ERR(pcm512x->sclk)) {
  1466. ret = clk_prepare_enable(pcm512x->sclk);
  1467. if (ret != 0) {
  1468. dev_err(dev, "Failed to enable SCLK: %d\n", ret);
  1469. return ret;
  1470. }
  1471. }
  1472. ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
  1473. pcm512x->supplies);
  1474. if (ret != 0) {
  1475. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  1476. return ret;
  1477. }
  1478. regcache_cache_only(pcm512x->regmap, false);
  1479. ret = regcache_sync(pcm512x->regmap);
  1480. if (ret != 0) {
  1481. dev_err(dev, "Failed to sync cache: %d\n", ret);
  1482. return ret;
  1483. }
  1484. ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
  1485. PCM512x_RQPD, 0);
  1486. if (ret != 0) {
  1487. dev_err(dev, "Failed to remove power down: %d\n", ret);
  1488. return ret;
  1489. }
  1490. return 0;
  1491. }
  1492. #endif
  1493. const struct dev_pm_ops pcm512x_pm_ops = {
  1494. SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
  1495. };
  1496. EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
  1497. MODULE_DESCRIPTION("ASoC PCM512x codec driver");
  1498. MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
  1499. MODULE_LICENSE("GPL v2");