pcm186x.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments PCM186x Universal Audio ADC
  4. *
  5. * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
  6. * Andreas Dannenberg <dannenberg@ti.com>
  7. * Andrew F. Davis <afd@ti.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/jack.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include "pcm186x.h"
  26. static const char * const pcm186x_supply_names[] = {
  27. "avdd", /* Analog power supply. Connect to 3.3-V supply. */
  28. "dvdd", /* Digital power supply. Connect to 3.3-V supply. */
  29. "iovdd", /* I/O power supply. Connect to 3.3-V or 1.8-V. */
  30. };
  31. #define PCM186x_NUM_SUPPLIES ARRAY_SIZE(pcm186x_supply_names)
  32. struct pcm186x_priv {
  33. struct regmap *regmap;
  34. struct regulator_bulk_data supplies[PCM186x_NUM_SUPPLIES];
  35. unsigned int sysclk;
  36. unsigned int tdm_offset;
  37. bool is_tdm_mode;
  38. bool is_master_mode;
  39. };
  40. static const DECLARE_TLV_DB_SCALE(pcm186x_pga_tlv, -1200, 50, 0);
  41. static const struct snd_kcontrol_new pcm1863_snd_controls[] = {
  42. SOC_DOUBLE_R_S_TLV("ADC Capture Volume", PCM186X_PGA_VAL_CH1_L,
  43. PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
  44. pcm186x_pga_tlv),
  45. };
  46. static const struct snd_kcontrol_new pcm1865_snd_controls[] = {
  47. SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", PCM186X_PGA_VAL_CH1_L,
  48. PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
  49. pcm186x_pga_tlv),
  50. SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", PCM186X_PGA_VAL_CH2_L,
  51. PCM186X_PGA_VAL_CH2_R, 0, -24, 80, 7, 0,
  52. pcm186x_pga_tlv),
  53. };
  54. static const unsigned int pcm186x_adc_input_channel_sel_value[] = {
  55. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  56. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  57. 0x10, 0x20, 0x30
  58. };
  59. static const char * const pcm186x_adcl_input_channel_sel_text[] = {
  60. "No Select",
  61. "VINL1[SE]", /* Default for ADC1L */
  62. "VINL2[SE]", /* Default for ADC2L */
  63. "VINL2[SE] + VINL1[SE]",
  64. "VINL3[SE]",
  65. "VINL3[SE] + VINL1[SE]",
  66. "VINL3[SE] + VINL2[SE]",
  67. "VINL3[SE] + VINL2[SE] + VINL1[SE]",
  68. "VINL4[SE]",
  69. "VINL4[SE] + VINL1[SE]",
  70. "VINL4[SE] + VINL2[SE]",
  71. "VINL4[SE] + VINL2[SE] + VINL1[SE]",
  72. "VINL4[SE] + VINL3[SE]",
  73. "VINL4[SE] + VINL3[SE] + VINL1[SE]",
  74. "VINL4[SE] + VINL3[SE] + VINL2[SE]",
  75. "VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]",
  76. "{VIN1P, VIN1M}[DIFF]",
  77. "{VIN4P, VIN4M}[DIFF]",
  78. "{VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]"
  79. };
  80. static const char * const pcm186x_adcr_input_channel_sel_text[] = {
  81. "No Select",
  82. "VINR1[SE]", /* Default for ADC1R */
  83. "VINR2[SE]", /* Default for ADC2R */
  84. "VINR2[SE] + VINR1[SE]",
  85. "VINR3[SE]",
  86. "VINR3[SE] + VINR1[SE]",
  87. "VINR3[SE] + VINR2[SE]",
  88. "VINR3[SE] + VINR2[SE] + VINR1[SE]",
  89. "VINR4[SE]",
  90. "VINR4[SE] + VINR1[SE]",
  91. "VINR4[SE] + VINR2[SE]",
  92. "VINR4[SE] + VINR2[SE] + VINR1[SE]",
  93. "VINR4[SE] + VINR3[SE]",
  94. "VINR4[SE] + VINR3[SE] + VINR1[SE]",
  95. "VINR4[SE] + VINR3[SE] + VINR2[SE]",
  96. "VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]",
  97. "{VIN2P, VIN2M}[DIFF]",
  98. "{VIN3P, VIN3M}[DIFF]",
  99. "{VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]"
  100. };
  101. static const struct soc_enum pcm186x_adc_input_channel_sel[] = {
  102. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_L, 0,
  103. PCM186X_ADC_INPUT_SEL_MASK,
  104. ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
  105. pcm186x_adcl_input_channel_sel_text,
  106. pcm186x_adc_input_channel_sel_value),
  107. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_R, 0,
  108. PCM186X_ADC_INPUT_SEL_MASK,
  109. ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
  110. pcm186x_adcr_input_channel_sel_text,
  111. pcm186x_adc_input_channel_sel_value),
  112. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_L, 0,
  113. PCM186X_ADC_INPUT_SEL_MASK,
  114. ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
  115. pcm186x_adcl_input_channel_sel_text,
  116. pcm186x_adc_input_channel_sel_value),
  117. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_R, 0,
  118. PCM186X_ADC_INPUT_SEL_MASK,
  119. ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
  120. pcm186x_adcr_input_channel_sel_text,
  121. pcm186x_adc_input_channel_sel_value),
  122. };
  123. static const struct snd_kcontrol_new pcm186x_adc_mux_controls[] = {
  124. SOC_DAPM_ENUM("ADC1 Left Input", pcm186x_adc_input_channel_sel[0]),
  125. SOC_DAPM_ENUM("ADC1 Right Input", pcm186x_adc_input_channel_sel[1]),
  126. SOC_DAPM_ENUM("ADC2 Left Input", pcm186x_adc_input_channel_sel[2]),
  127. SOC_DAPM_ENUM("ADC2 Right Input", pcm186x_adc_input_channel_sel[3]),
  128. };
  129. static const struct snd_soc_dapm_widget pcm1863_dapm_widgets[] = {
  130. SND_SOC_DAPM_INPUT("VINL1"),
  131. SND_SOC_DAPM_INPUT("VINR1"),
  132. SND_SOC_DAPM_INPUT("VINL2"),
  133. SND_SOC_DAPM_INPUT("VINR2"),
  134. SND_SOC_DAPM_INPUT("VINL3"),
  135. SND_SOC_DAPM_INPUT("VINR3"),
  136. SND_SOC_DAPM_INPUT("VINL4"),
  137. SND_SOC_DAPM_INPUT("VINR4"),
  138. SND_SOC_DAPM_MUX("ADC Left Capture Source", SND_SOC_NOPM, 0, 0,
  139. &pcm186x_adc_mux_controls[0]),
  140. SND_SOC_DAPM_MUX("ADC Right Capture Source", SND_SOC_NOPM, 0, 0,
  141. &pcm186x_adc_mux_controls[1]),
  142. /*
  143. * Put the codec into SLEEP mode when not in use, allowing the
  144. * Energysense mechanism to operate.
  145. */
  146. SND_SOC_DAPM_ADC("ADC", "HiFi Capture", PCM186X_POWER_CTRL, 1, 1),
  147. };
  148. static const struct snd_soc_dapm_widget pcm1865_dapm_widgets[] = {
  149. SND_SOC_DAPM_INPUT("VINL1"),
  150. SND_SOC_DAPM_INPUT("VINR1"),
  151. SND_SOC_DAPM_INPUT("VINL2"),
  152. SND_SOC_DAPM_INPUT("VINR2"),
  153. SND_SOC_DAPM_INPUT("VINL3"),
  154. SND_SOC_DAPM_INPUT("VINR3"),
  155. SND_SOC_DAPM_INPUT("VINL4"),
  156. SND_SOC_DAPM_INPUT("VINR4"),
  157. SND_SOC_DAPM_MUX("ADC1 Left Capture Source", SND_SOC_NOPM, 0, 0,
  158. &pcm186x_adc_mux_controls[0]),
  159. SND_SOC_DAPM_MUX("ADC1 Right Capture Source", SND_SOC_NOPM, 0, 0,
  160. &pcm186x_adc_mux_controls[1]),
  161. SND_SOC_DAPM_MUX("ADC2 Left Capture Source", SND_SOC_NOPM, 0, 0,
  162. &pcm186x_adc_mux_controls[2]),
  163. SND_SOC_DAPM_MUX("ADC2 Right Capture Source", SND_SOC_NOPM, 0, 0,
  164. &pcm186x_adc_mux_controls[3]),
  165. /*
  166. * Put the codec into SLEEP mode when not in use, allowing the
  167. * Energysense mechanism to operate.
  168. */
  169. SND_SOC_DAPM_ADC("ADC1", "HiFi Capture 1", PCM186X_POWER_CTRL, 1, 1),
  170. SND_SOC_DAPM_ADC("ADC2", "HiFi Capture 2", PCM186X_POWER_CTRL, 1, 1),
  171. };
  172. static const struct snd_soc_dapm_route pcm1863_dapm_routes[] = {
  173. { "ADC Left Capture Source", NULL, "VINL1" },
  174. { "ADC Left Capture Source", NULL, "VINR1" },
  175. { "ADC Left Capture Source", NULL, "VINL2" },
  176. { "ADC Left Capture Source", NULL, "VINR2" },
  177. { "ADC Left Capture Source", NULL, "VINL3" },
  178. { "ADC Left Capture Source", NULL, "VINR3" },
  179. { "ADC Left Capture Source", NULL, "VINL4" },
  180. { "ADC Left Capture Source", NULL, "VINR4" },
  181. { "ADC", NULL, "ADC Left Capture Source" },
  182. { "ADC Right Capture Source", NULL, "VINL1" },
  183. { "ADC Right Capture Source", NULL, "VINR1" },
  184. { "ADC Right Capture Source", NULL, "VINL2" },
  185. { "ADC Right Capture Source", NULL, "VINR2" },
  186. { "ADC Right Capture Source", NULL, "VINL3" },
  187. { "ADC Right Capture Source", NULL, "VINR3" },
  188. { "ADC Right Capture Source", NULL, "VINL4" },
  189. { "ADC Right Capture Source", NULL, "VINR4" },
  190. { "ADC", NULL, "ADC Right Capture Source" },
  191. };
  192. static const struct snd_soc_dapm_route pcm1865_dapm_routes[] = {
  193. { "ADC1 Left Capture Source", NULL, "VINL1" },
  194. { "ADC1 Left Capture Source", NULL, "VINR1" },
  195. { "ADC1 Left Capture Source", NULL, "VINL2" },
  196. { "ADC1 Left Capture Source", NULL, "VINR2" },
  197. { "ADC1 Left Capture Source", NULL, "VINL3" },
  198. { "ADC1 Left Capture Source", NULL, "VINR3" },
  199. { "ADC1 Left Capture Source", NULL, "VINL4" },
  200. { "ADC1 Left Capture Source", NULL, "VINR4" },
  201. { "ADC1", NULL, "ADC1 Left Capture Source" },
  202. { "ADC1 Right Capture Source", NULL, "VINL1" },
  203. { "ADC1 Right Capture Source", NULL, "VINR1" },
  204. { "ADC1 Right Capture Source", NULL, "VINL2" },
  205. { "ADC1 Right Capture Source", NULL, "VINR2" },
  206. { "ADC1 Right Capture Source", NULL, "VINL3" },
  207. { "ADC1 Right Capture Source", NULL, "VINR3" },
  208. { "ADC1 Right Capture Source", NULL, "VINL4" },
  209. { "ADC1 Right Capture Source", NULL, "VINR4" },
  210. { "ADC1", NULL, "ADC1 Right Capture Source" },
  211. { "ADC2 Left Capture Source", NULL, "VINL1" },
  212. { "ADC2 Left Capture Source", NULL, "VINR1" },
  213. { "ADC2 Left Capture Source", NULL, "VINL2" },
  214. { "ADC2 Left Capture Source", NULL, "VINR2" },
  215. { "ADC2 Left Capture Source", NULL, "VINL3" },
  216. { "ADC2 Left Capture Source", NULL, "VINR3" },
  217. { "ADC2 Left Capture Source", NULL, "VINL4" },
  218. { "ADC2 Left Capture Source", NULL, "VINR4" },
  219. { "ADC2", NULL, "ADC2 Left Capture Source" },
  220. { "ADC2 Right Capture Source", NULL, "VINL1" },
  221. { "ADC2 Right Capture Source", NULL, "VINR1" },
  222. { "ADC2 Right Capture Source", NULL, "VINL2" },
  223. { "ADC2 Right Capture Source", NULL, "VINR2" },
  224. { "ADC2 Right Capture Source", NULL, "VINL3" },
  225. { "ADC2 Right Capture Source", NULL, "VINR3" },
  226. { "ADC2 Right Capture Source", NULL, "VINL4" },
  227. { "ADC2 Right Capture Source", NULL, "VINR4" },
  228. { "ADC2", NULL, "ADC2 Right Capture Source" },
  229. };
  230. static int pcm186x_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *params,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct snd_soc_component *component = dai->component;
  235. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  236. unsigned int rate = params_rate(params);
  237. snd_pcm_format_t format = params_format(params);
  238. unsigned int width = params_width(params);
  239. unsigned int channels = params_channels(params);
  240. unsigned int div_lrck;
  241. unsigned int div_bck;
  242. u8 tdm_tx_sel = 0;
  243. u8 pcm_cfg = 0;
  244. dev_dbg(component->dev, "%s() rate=%u format=0x%x width=%u channels=%u\n",
  245. __func__, rate, format, width, channels);
  246. switch (width) {
  247. case 16:
  248. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_16 <<
  249. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  250. PCM186X_PCM_CFG_TX_WLEN_16 <<
  251. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  252. break;
  253. case 20:
  254. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_20 <<
  255. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  256. PCM186X_PCM_CFG_TX_WLEN_20 <<
  257. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  258. break;
  259. case 24:
  260. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_24 <<
  261. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  262. PCM186X_PCM_CFG_TX_WLEN_24 <<
  263. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  264. break;
  265. case 32:
  266. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_32 <<
  267. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  268. PCM186X_PCM_CFG_TX_WLEN_32 <<
  269. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  270. break;
  271. default:
  272. return -EINVAL;
  273. }
  274. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  275. PCM186X_PCM_CFG_RX_WLEN_MASK |
  276. PCM186X_PCM_CFG_TX_WLEN_MASK,
  277. pcm_cfg);
  278. div_lrck = width * channels;
  279. if (priv->is_tdm_mode) {
  280. /* Select TDM transmission data */
  281. switch (channels) {
  282. case 2:
  283. tdm_tx_sel = PCM186X_TDM_TX_SEL_2CH;
  284. break;
  285. case 4:
  286. tdm_tx_sel = PCM186X_TDM_TX_SEL_4CH;
  287. break;
  288. case 6:
  289. tdm_tx_sel = PCM186X_TDM_TX_SEL_6CH;
  290. break;
  291. default:
  292. return -EINVAL;
  293. }
  294. snd_soc_component_update_bits(component, PCM186X_TDM_TX_SEL,
  295. PCM186X_TDM_TX_SEL_MASK, tdm_tx_sel);
  296. /* In DSP/TDM mode, the LRCLK divider must be 256 */
  297. div_lrck = 256;
  298. /* Configure 1/256 duty cycle for LRCK */
  299. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  300. PCM186X_PCM_CFG_TDM_LRCK_MODE,
  301. PCM186X_PCM_CFG_TDM_LRCK_MODE);
  302. }
  303. /* Only configure clock dividers in master mode. */
  304. if (priv->is_master_mode) {
  305. div_bck = priv->sysclk / (div_lrck * rate);
  306. dev_dbg(component->dev,
  307. "%s() master_clk=%u div_bck=%u div_lrck=%u\n",
  308. __func__, priv->sysclk, div_bck, div_lrck);
  309. snd_soc_component_write(component, PCM186X_BCK_DIV, div_bck - 1);
  310. snd_soc_component_write(component, PCM186X_LRK_DIV, div_lrck - 1);
  311. }
  312. return 0;
  313. }
  314. static int pcm186x_set_fmt(struct snd_soc_dai *dai, unsigned int format)
  315. {
  316. struct snd_soc_component *component = dai->component;
  317. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  318. u8 clk_ctrl = 0;
  319. u8 pcm_cfg = 0;
  320. dev_dbg(component->dev, "%s() format=0x%x\n", __func__, format);
  321. /* set master/slave audio interface */
  322. switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
  323. case SND_SOC_DAIFMT_CBM_CFM:
  324. if (!priv->sysclk) {
  325. dev_err(component->dev, "operating in master mode requires sysclock to be configured\n");
  326. return -EINVAL;
  327. }
  328. clk_ctrl |= PCM186X_CLK_CTRL_MST_MODE;
  329. priv->is_master_mode = true;
  330. break;
  331. case SND_SOC_DAIFMT_CBS_CFS:
  332. priv->is_master_mode = false;
  333. break;
  334. default:
  335. dev_err(component->dev, "Invalid DAI master/slave interface\n");
  336. return -EINVAL;
  337. }
  338. /* set interface polarity */
  339. switch (format & SND_SOC_DAIFMT_INV_MASK) {
  340. case SND_SOC_DAIFMT_NB_NF:
  341. break;
  342. default:
  343. dev_err(component->dev, "Inverted DAI clocks not supported\n");
  344. return -EINVAL;
  345. }
  346. /* set interface format */
  347. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  348. case SND_SOC_DAIFMT_I2S:
  349. pcm_cfg = PCM186X_PCM_CFG_FMT_I2S;
  350. break;
  351. case SND_SOC_DAIFMT_LEFT_J:
  352. pcm_cfg = PCM186X_PCM_CFG_FMT_LEFTJ;
  353. break;
  354. case SND_SOC_DAIFMT_DSP_A:
  355. priv->tdm_offset += 1;
  356. fallthrough;
  357. /* DSP_A uses the same basic config as DSP_B
  358. * except we need to shift the TDM output by one BCK cycle
  359. */
  360. case SND_SOC_DAIFMT_DSP_B:
  361. priv->is_tdm_mode = true;
  362. pcm_cfg = PCM186X_PCM_CFG_FMT_TDM;
  363. break;
  364. default:
  365. dev_err(component->dev, "Invalid DAI format\n");
  366. return -EINVAL;
  367. }
  368. snd_soc_component_update_bits(component, PCM186X_CLK_CTRL,
  369. PCM186X_CLK_CTRL_MST_MODE, clk_ctrl);
  370. snd_soc_component_write(component, PCM186X_TDM_TX_OFFSET, priv->tdm_offset);
  371. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  372. PCM186X_PCM_CFG_FMT_MASK, pcm_cfg);
  373. return 0;
  374. }
  375. static int pcm186x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  376. unsigned int rx_mask, int slots, int slot_width)
  377. {
  378. struct snd_soc_component *component = dai->component;
  379. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  380. unsigned int first_slot, last_slot, tdm_offset;
  381. dev_dbg(component->dev,
  382. "%s() tx_mask=0x%x rx_mask=0x%x slots=%d slot_width=%d\n",
  383. __func__, tx_mask, rx_mask, slots, slot_width);
  384. if (!tx_mask) {
  385. dev_err(component->dev, "tdm tx mask must not be 0\n");
  386. return -EINVAL;
  387. }
  388. first_slot = __ffs(tx_mask);
  389. last_slot = __fls(tx_mask);
  390. if (last_slot - first_slot != hweight32(tx_mask) - 1) {
  391. dev_err(component->dev, "tdm tx mask must be contiguous\n");
  392. return -EINVAL;
  393. }
  394. tdm_offset = first_slot * slot_width;
  395. if (tdm_offset > 255) {
  396. dev_err(component->dev, "tdm tx slot selection out of bounds\n");
  397. return -EINVAL;
  398. }
  399. priv->tdm_offset = tdm_offset;
  400. return 0;
  401. }
  402. static int pcm186x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  403. unsigned int freq, int dir)
  404. {
  405. struct snd_soc_component *component = dai->component;
  406. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  407. dev_dbg(component->dev, "%s() clk_id=%d freq=%u dir=%d\n",
  408. __func__, clk_id, freq, dir);
  409. priv->sysclk = freq;
  410. return 0;
  411. }
  412. static const struct snd_soc_dai_ops pcm186x_dai_ops = {
  413. .set_sysclk = pcm186x_set_dai_sysclk,
  414. .set_tdm_slot = pcm186x_set_tdm_slot,
  415. .set_fmt = pcm186x_set_fmt,
  416. .hw_params = pcm186x_hw_params,
  417. };
  418. static struct snd_soc_dai_driver pcm1863_dai = {
  419. .name = "pcm1863-aif",
  420. .capture = {
  421. .stream_name = "Capture",
  422. .channels_min = 1,
  423. .channels_max = 2,
  424. .rates = PCM186X_RATES,
  425. .formats = PCM186X_FORMATS,
  426. },
  427. .ops = &pcm186x_dai_ops,
  428. };
  429. static struct snd_soc_dai_driver pcm1865_dai = {
  430. .name = "pcm1865-aif",
  431. .capture = {
  432. .stream_name = "Capture",
  433. .channels_min = 1,
  434. .channels_max = 4,
  435. .rates = PCM186X_RATES,
  436. .formats = PCM186X_FORMATS,
  437. },
  438. .ops = &pcm186x_dai_ops,
  439. };
  440. static int pcm186x_power_on(struct snd_soc_component *component)
  441. {
  442. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  443. int ret = 0;
  444. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  445. priv->supplies);
  446. if (ret)
  447. return ret;
  448. regcache_cache_only(priv->regmap, false);
  449. ret = regcache_sync(priv->regmap);
  450. if (ret) {
  451. dev_err(component->dev, "Failed to restore cache\n");
  452. regcache_cache_only(priv->regmap, true);
  453. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  454. priv->supplies);
  455. return ret;
  456. }
  457. snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
  458. PCM186X_PWR_CTRL_PWRDN, 0);
  459. return 0;
  460. }
  461. static int pcm186x_power_off(struct snd_soc_component *component)
  462. {
  463. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  464. int ret;
  465. snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
  466. PCM186X_PWR_CTRL_PWRDN, PCM186X_PWR_CTRL_PWRDN);
  467. regcache_cache_only(priv->regmap, true);
  468. ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  469. priv->supplies);
  470. if (ret)
  471. return ret;
  472. return 0;
  473. }
  474. static int pcm186x_set_bias_level(struct snd_soc_component *component,
  475. enum snd_soc_bias_level level)
  476. {
  477. dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
  478. snd_soc_component_get_bias_level(component), level);
  479. switch (level) {
  480. case SND_SOC_BIAS_ON:
  481. break;
  482. case SND_SOC_BIAS_PREPARE:
  483. break;
  484. case SND_SOC_BIAS_STANDBY:
  485. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  486. pcm186x_power_on(component);
  487. break;
  488. case SND_SOC_BIAS_OFF:
  489. pcm186x_power_off(component);
  490. break;
  491. }
  492. return 0;
  493. }
  494. static struct snd_soc_component_driver soc_codec_dev_pcm1863 = {
  495. .set_bias_level = pcm186x_set_bias_level,
  496. .controls = pcm1863_snd_controls,
  497. .num_controls = ARRAY_SIZE(pcm1863_snd_controls),
  498. .dapm_widgets = pcm1863_dapm_widgets,
  499. .num_dapm_widgets = ARRAY_SIZE(pcm1863_dapm_widgets),
  500. .dapm_routes = pcm1863_dapm_routes,
  501. .num_dapm_routes = ARRAY_SIZE(pcm1863_dapm_routes),
  502. .idle_bias_on = 1,
  503. .use_pmdown_time = 1,
  504. .endianness = 1,
  505. .non_legacy_dai_naming = 1,
  506. };
  507. static struct snd_soc_component_driver soc_codec_dev_pcm1865 = {
  508. .set_bias_level = pcm186x_set_bias_level,
  509. .controls = pcm1865_snd_controls,
  510. .num_controls = ARRAY_SIZE(pcm1865_snd_controls),
  511. .dapm_widgets = pcm1865_dapm_widgets,
  512. .num_dapm_widgets = ARRAY_SIZE(pcm1865_dapm_widgets),
  513. .dapm_routes = pcm1865_dapm_routes,
  514. .num_dapm_routes = ARRAY_SIZE(pcm1865_dapm_routes),
  515. .suspend_bias_off = 1,
  516. .idle_bias_on = 1,
  517. .use_pmdown_time = 1,
  518. .endianness = 1,
  519. .non_legacy_dai_naming = 1,
  520. };
  521. static bool pcm186x_volatile(struct device *dev, unsigned int reg)
  522. {
  523. switch (reg) {
  524. case PCM186X_PAGE:
  525. case PCM186X_DEVICE_STATUS:
  526. case PCM186X_FSAMPLE_STATUS:
  527. case PCM186X_DIV_STATUS:
  528. case PCM186X_CLK_STATUS:
  529. case PCM186X_SUPPLY_STATUS:
  530. case PCM186X_MMAP_STAT_CTRL:
  531. case PCM186X_MMAP_ADDRESS:
  532. return true;
  533. }
  534. return false;
  535. }
  536. static const struct regmap_range_cfg pcm186x_range = {
  537. .name = "Pages",
  538. .range_max = PCM186X_MAX_REGISTER,
  539. .selector_reg = PCM186X_PAGE,
  540. .selector_mask = 0xff,
  541. .window_len = PCM186X_PAGE_LEN,
  542. };
  543. const struct regmap_config pcm186x_regmap = {
  544. .reg_bits = 8,
  545. .val_bits = 8,
  546. .volatile_reg = pcm186x_volatile,
  547. .ranges = &pcm186x_range,
  548. .num_ranges = 1,
  549. .max_register = PCM186X_MAX_REGISTER,
  550. .cache_type = REGCACHE_RBTREE,
  551. };
  552. EXPORT_SYMBOL_GPL(pcm186x_regmap);
  553. int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq,
  554. struct regmap *regmap)
  555. {
  556. struct pcm186x_priv *priv;
  557. int i, ret;
  558. priv = devm_kzalloc(dev, sizeof(struct pcm186x_priv), GFP_KERNEL);
  559. if (!priv)
  560. return -ENOMEM;
  561. dev_set_drvdata(dev, priv);
  562. priv->regmap = regmap;
  563. for (i = 0; i < ARRAY_SIZE(priv->supplies); i++)
  564. priv->supplies[i].supply = pcm186x_supply_names[i];
  565. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
  566. priv->supplies);
  567. if (ret) {
  568. dev_err(dev, "failed to request supplies: %d\n", ret);
  569. return ret;
  570. }
  571. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  572. priv->supplies);
  573. if (ret) {
  574. dev_err(dev, "failed enable supplies: %d\n", ret);
  575. return ret;
  576. }
  577. /* Reset device registers for a consistent power-on like state */
  578. ret = regmap_write(regmap, PCM186X_PAGE, PCM186X_RESET);
  579. if (ret) {
  580. dev_err(dev, "failed to write device: %d\n", ret);
  581. return ret;
  582. }
  583. ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  584. priv->supplies);
  585. if (ret) {
  586. dev_err(dev, "failed disable supplies: %d\n", ret);
  587. return ret;
  588. }
  589. switch (type) {
  590. case PCM1865:
  591. case PCM1864:
  592. ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1865,
  593. &pcm1865_dai, 1);
  594. break;
  595. case PCM1863:
  596. case PCM1862:
  597. default:
  598. ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1863,
  599. &pcm1863_dai, 1);
  600. }
  601. if (ret) {
  602. dev_err(dev, "failed to register CODEC: %d\n", ret);
  603. return ret;
  604. }
  605. return 0;
  606. }
  607. EXPORT_SYMBOL_GPL(pcm186x_probe);
  608. MODULE_AUTHOR("Andreas Dannenberg <dannenberg@ti.com>");
  609. MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
  610. MODULE_DESCRIPTION("PCM186x Universal Audio ADC driver");
  611. MODULE_LICENSE("GPL v2");