nau8825.c 87 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Nuvoton NAU8825 audio codec driver
  4. *
  5. * Copyright 2015 Google Chromium project.
  6. * Author: Anatol Pomozov <anatol@chromium.org>
  7. * Copyright 2015 Nuvoton Technology Corp.
  8. * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/i2c.h>
  14. #include <linux/regmap.h>
  15. #include <linux/slab.h>
  16. #include <linux/clk.h>
  17. #include <linux/acpi.h>
  18. #include <linux/math64.h>
  19. #include <linux/semaphore.h>
  20. #include <sound/initval.h>
  21. #include <sound/tlv.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/jack.h>
  27. #include "nau8825.h"
  28. #define NUVOTON_CODEC_DAI "nau8825-hifi"
  29. #define NAU_FREF_MAX 13500000
  30. #define NAU_FVCO_MAX 124000000
  31. #define NAU_FVCO_MIN 90000000
  32. /* cross talk suppression detection */
  33. #define LOG10_MAGIC 646456993
  34. #define GAIN_AUGMENT 22500
  35. #define SIDETONE_BASE 207000
  36. /* the maximum frequency of CLK_ADC and CLK_DAC */
  37. #define CLK_DA_AD_MAX 6144000
  38. static int nau8825_configure_sysclk(struct nau8825 *nau8825,
  39. int clk_id, unsigned int freq);
  40. struct nau8825_fll {
  41. int mclk_src;
  42. int ratio;
  43. int fll_frac;
  44. int fll_int;
  45. int clk_ref_div;
  46. };
  47. struct nau8825_fll_attr {
  48. unsigned int param;
  49. unsigned int val;
  50. };
  51. /* scaling for mclk from sysclk_src output */
  52. static const struct nau8825_fll_attr mclk_src_scaling[] = {
  53. { 1, 0x0 },
  54. { 2, 0x2 },
  55. { 4, 0x3 },
  56. { 8, 0x4 },
  57. { 16, 0x5 },
  58. { 32, 0x6 },
  59. { 3, 0x7 },
  60. { 6, 0xa },
  61. { 12, 0xb },
  62. { 24, 0xc },
  63. { 48, 0xd },
  64. { 96, 0xe },
  65. { 5, 0xf },
  66. };
  67. /* ratio for input clk freq */
  68. static const struct nau8825_fll_attr fll_ratio[] = {
  69. { 512000, 0x01 },
  70. { 256000, 0x02 },
  71. { 128000, 0x04 },
  72. { 64000, 0x08 },
  73. { 32000, 0x10 },
  74. { 8000, 0x20 },
  75. { 4000, 0x40 },
  76. };
  77. static const struct nau8825_fll_attr fll_pre_scalar[] = {
  78. { 1, 0x0 },
  79. { 2, 0x1 },
  80. { 4, 0x2 },
  81. { 8, 0x3 },
  82. };
  83. /* over sampling rate */
  84. struct nau8825_osr_attr {
  85. unsigned int osr;
  86. unsigned int clk_src;
  87. };
  88. static const struct nau8825_osr_attr osr_dac_sel[] = {
  89. { 64, 2 }, /* OSR 64, SRC 1/4 */
  90. { 256, 0 }, /* OSR 256, SRC 1 */
  91. { 128, 1 }, /* OSR 128, SRC 1/2 */
  92. { 0, 0 },
  93. { 32, 3 }, /* OSR 32, SRC 1/8 */
  94. };
  95. static const struct nau8825_osr_attr osr_adc_sel[] = {
  96. { 32, 3 }, /* OSR 32, SRC 1/8 */
  97. { 64, 2 }, /* OSR 64, SRC 1/4 */
  98. { 128, 1 }, /* OSR 128, SRC 1/2 */
  99. { 256, 0 }, /* OSR 256, SRC 1 */
  100. };
  101. static const struct reg_default nau8825_reg_defaults[] = {
  102. { NAU8825_REG_ENA_CTRL, 0x00ff },
  103. { NAU8825_REG_IIC_ADDR_SET, 0x0 },
  104. { NAU8825_REG_CLK_DIVIDER, 0x0050 },
  105. { NAU8825_REG_FLL1, 0x0 },
  106. { NAU8825_REG_FLL2, 0x3126 },
  107. { NAU8825_REG_FLL3, 0x0008 },
  108. { NAU8825_REG_FLL4, 0x0010 },
  109. { NAU8825_REG_FLL5, 0x0 },
  110. { NAU8825_REG_FLL6, 0x6000 },
  111. { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
  112. { NAU8825_REG_HSD_CTRL, 0x000c },
  113. { NAU8825_REG_JACK_DET_CTRL, 0x0 },
  114. { NAU8825_REG_INTERRUPT_MASK, 0x0 },
  115. { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
  116. { NAU8825_REG_SAR_CTRL, 0x0015 },
  117. { NAU8825_REG_KEYDET_CTRL, 0x0110 },
  118. { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
  119. { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
  120. { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
  121. { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
  122. { NAU8825_REG_GPIO34_CTRL, 0x0 },
  123. { NAU8825_REG_GPIO12_CTRL, 0x0 },
  124. { NAU8825_REG_TDM_CTRL, 0x0 },
  125. { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
  126. { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
  127. { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
  128. { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
  129. { NAU8825_REG_BIQ_CTRL, 0x0 },
  130. { NAU8825_REG_BIQ_COF1, 0x0 },
  131. { NAU8825_REG_BIQ_COF2, 0x0 },
  132. { NAU8825_REG_BIQ_COF3, 0x0 },
  133. { NAU8825_REG_BIQ_COF4, 0x0 },
  134. { NAU8825_REG_BIQ_COF5, 0x0 },
  135. { NAU8825_REG_BIQ_COF6, 0x0 },
  136. { NAU8825_REG_BIQ_COF7, 0x0 },
  137. { NAU8825_REG_BIQ_COF8, 0x0 },
  138. { NAU8825_REG_BIQ_COF9, 0x0 },
  139. { NAU8825_REG_BIQ_COF10, 0x0 },
  140. { NAU8825_REG_ADC_RATE, 0x0010 },
  141. { NAU8825_REG_DAC_CTRL1, 0x0001 },
  142. { NAU8825_REG_DAC_CTRL2, 0x0 },
  143. { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
  144. { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
  145. { NAU8825_REG_MUTE_CTRL, 0x0 },
  146. { NAU8825_REG_HSVOL_CTRL, 0x0 },
  147. { NAU8825_REG_DACL_CTRL, 0x02cf },
  148. { NAU8825_REG_DACR_CTRL, 0x00cf },
  149. { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
  150. { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
  151. { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
  152. { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
  153. { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
  154. { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
  155. { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
  156. { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
  157. { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
  158. { NAU8825_REG_CLASSG_CTRL, 0x0 },
  159. { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
  160. { NAU8825_REG_MISC_CTRL, 0x0 },
  161. { NAU8825_REG_BIAS_ADJ, 0x0 },
  162. { NAU8825_REG_TRIM_SETTINGS, 0x0 },
  163. { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
  164. { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
  165. { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
  166. { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
  167. { NAU8825_REG_RDAC, 0x0008 },
  168. { NAU8825_REG_MIC_BIAS, 0x0006 },
  169. { NAU8825_REG_BOOST, 0x0 },
  170. { NAU8825_REG_FEPGA, 0x0 },
  171. { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
  172. { NAU8825_REG_CHARGE_PUMP, 0x0 },
  173. };
  174. /* register backup table when cross talk detection */
  175. static struct reg_default nau8825_xtalk_baktab[] = {
  176. { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
  177. { NAU8825_REG_HSVOL_CTRL, 0 },
  178. { NAU8825_REG_DACL_CTRL, 0x00cf },
  179. { NAU8825_REG_DACR_CTRL, 0x02cf },
  180. };
  181. static const unsigned short logtable[256] = {
  182. 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
  183. 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
  184. 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
  185. 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
  186. 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
  187. 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
  188. 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
  189. 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
  190. 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
  191. 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
  192. 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
  193. 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
  194. 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
  195. 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
  196. 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
  197. 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
  198. 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
  199. 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
  200. 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
  201. 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
  202. 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
  203. 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
  204. 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
  205. 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
  206. 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
  207. 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
  208. 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
  209. 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
  210. 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
  211. 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
  212. 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
  213. 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
  214. };
  215. /**
  216. * nau8825_sema_acquire - acquire the semaphore of nau88l25
  217. * @nau8825: component to register the codec private data with
  218. * @timeout: how long in jiffies to wait before failure or zero to wait
  219. * until release
  220. *
  221. * Attempts to acquire the semaphore with number of jiffies. If no more
  222. * tasks are allowed to acquire the semaphore, calling this function will
  223. * put the task to sleep. If the semaphore is not released within the
  224. * specified number of jiffies, this function returns.
  225. * If the semaphore is not released within the specified number of jiffies,
  226. * this function returns -ETIME. If the sleep is interrupted by a signal,
  227. * this function will return -EINTR. It returns 0 if the semaphore was
  228. * acquired successfully.
  229. *
  230. * Acquires the semaphore without jiffies. Try to acquire the semaphore
  231. * atomically. Returns 0 if the semaphore has been acquired successfully
  232. * or 1 if it cannot be acquired.
  233. */
  234. static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
  235. {
  236. int ret;
  237. if (timeout) {
  238. ret = down_timeout(&nau8825->xtalk_sem, timeout);
  239. if (ret < 0)
  240. dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
  241. } else {
  242. ret = down_trylock(&nau8825->xtalk_sem);
  243. if (ret)
  244. dev_warn(nau8825->dev, "Acquire semaphore fail\n");
  245. }
  246. return ret;
  247. }
  248. /**
  249. * nau8825_sema_release - release the semaphore of nau88l25
  250. * @nau8825: component to register the codec private data with
  251. *
  252. * Release the semaphore which may be called from any context and
  253. * even by tasks which have never called down().
  254. */
  255. static inline void nau8825_sema_release(struct nau8825 *nau8825)
  256. {
  257. up(&nau8825->xtalk_sem);
  258. }
  259. /**
  260. * nau8825_sema_reset - reset the semaphore for nau88l25
  261. * @nau8825: component to register the codec private data with
  262. *
  263. * Reset the counter of the semaphore. Call this function to restart
  264. * a new round task management.
  265. */
  266. static inline void nau8825_sema_reset(struct nau8825 *nau8825)
  267. {
  268. nau8825->xtalk_sem.count = 1;
  269. }
  270. /**
  271. * Ramp up the headphone volume change gradually to target level.
  272. *
  273. * @nau8825: component to register the codec private data with
  274. * @vol_from: the volume to start up
  275. * @vol_to: the target volume
  276. * @step: the volume span to move on
  277. *
  278. * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
  279. * If the volume changes sharp, there is a pop noise heard in headphone. We
  280. * provide the function to ramp up the volume up or down by delaying 10ms
  281. * per step.
  282. */
  283. static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
  284. unsigned int vol_from, unsigned int vol_to, unsigned int step)
  285. {
  286. unsigned int value, volume, ramp_up, from, to;
  287. if (vol_from == vol_to || step == 0) {
  288. return;
  289. } else if (vol_from < vol_to) {
  290. ramp_up = true;
  291. from = vol_from;
  292. to = vol_to;
  293. } else {
  294. ramp_up = false;
  295. from = vol_to;
  296. to = vol_from;
  297. }
  298. /* only handle volume from 0dB to minimum -54dB */
  299. if (to > NAU8825_HP_VOL_MIN)
  300. to = NAU8825_HP_VOL_MIN;
  301. for (volume = from; volume < to; volume += step) {
  302. if (ramp_up)
  303. value = volume;
  304. else
  305. value = to - volume + from;
  306. regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
  307. NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
  308. (value << NAU8825_HPL_VOL_SFT) | value);
  309. usleep_range(10000, 10500);
  310. }
  311. if (ramp_up)
  312. value = to;
  313. else
  314. value = from;
  315. regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
  316. NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
  317. (value << NAU8825_HPL_VOL_SFT) | value);
  318. }
  319. /**
  320. * Computes log10 of a value; the result is round off to 3 decimal. This func-
  321. * tion takes reference to dvb-math. The source code locates as the following.
  322. * Linux/drivers/media/dvb-core/dvb_math.c
  323. * @value: input for log10
  324. *
  325. * return log10(value) * 1000
  326. */
  327. static u32 nau8825_intlog10_dec3(u32 value)
  328. {
  329. u32 msb, logentry, significand, interpolation, log10val;
  330. u64 log2val;
  331. /* first detect the msb (count begins at 0) */
  332. msb = fls(value) - 1;
  333. /**
  334. * now we use a logtable after the following method:
  335. *
  336. * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
  337. * where x = msb and therefore 1 <= y < 2
  338. * first y is determined by shifting the value left
  339. * so that msb is bit 31
  340. * 0x00231f56 -> 0x8C7D5800
  341. * the result is y * 2^31 -> "significand"
  342. * then the highest 9 bits are used for a table lookup
  343. * the highest bit is discarded because it's always set
  344. * the highest nine bits in our example are 100011000
  345. * so we would use the entry 0x18
  346. */
  347. significand = value << (31 - msb);
  348. logentry = (significand >> 23) & 0xff;
  349. /**
  350. * last step we do is interpolation because of the
  351. * limitations of the log table the error is that part of
  352. * the significand which isn't used for lookup then we
  353. * compute the ratio between the error and the next table entry
  354. * and interpolate it between the log table entry used and the
  355. * next one the biggest error possible is 0x7fffff
  356. * (in our example it's 0x7D5800)
  357. * needed value for next table entry is 0x800000
  358. * so the interpolation is
  359. * (error / 0x800000) * (logtable_next - logtable_current)
  360. * in the implementation the division is moved to the end for
  361. * better accuracy there is also an overflow correction if
  362. * logtable_next is 256
  363. */
  364. interpolation = ((significand & 0x7fffff) *
  365. ((logtable[(logentry + 1) & 0xff] -
  366. logtable[logentry]) & 0xffff)) >> 15;
  367. log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
  368. /**
  369. * log10(x) = log2(x) * log10(2)
  370. */
  371. log10val = (log2val * LOG10_MAGIC) >> 31;
  372. /**
  373. * the result is round off to 3 decimal
  374. */
  375. return log10val / ((1 << 24) / 1000);
  376. }
  377. /**
  378. * computes cross talk suppression sidetone gain.
  379. *
  380. * @sig_org: orignal signal level
  381. * @sig_cros: cross talk signal level
  382. *
  383. * The orignal and cross talk signal vlues need to be characterized.
  384. * Once these values have been characterized, this sidetone value
  385. * can be converted to decibel with the equation below.
  386. * sidetone = 20 * log (original signal level / crosstalk signal level)
  387. *
  388. * return cross talk sidetone gain
  389. */
  390. static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
  391. {
  392. u32 gain, sidetone;
  393. if (WARN_ON(sig_org == 0 || sig_cros == 0))
  394. return 0;
  395. sig_org = nau8825_intlog10_dec3(sig_org);
  396. sig_cros = nau8825_intlog10_dec3(sig_cros);
  397. if (sig_org >= sig_cros)
  398. gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
  399. else
  400. gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
  401. sidetone = SIDETONE_BASE - gain * 2;
  402. sidetone /= 1000;
  403. return sidetone;
  404. }
  405. static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
  406. {
  407. int index;
  408. for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
  409. if (nau8825_xtalk_baktab[index].reg == reg)
  410. return index;
  411. return -EINVAL;
  412. }
  413. static void nau8825_xtalk_backup(struct nau8825 *nau8825)
  414. {
  415. int i;
  416. if (nau8825->xtalk_baktab_initialized)
  417. return;
  418. /* Backup some register values to backup table */
  419. for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
  420. regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
  421. &nau8825_xtalk_baktab[i].def);
  422. nau8825->xtalk_baktab_initialized = true;
  423. }
  424. static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
  425. {
  426. int i, volume;
  427. if (!nau8825->xtalk_baktab_initialized)
  428. return;
  429. /* Restore register values from backup table; When the driver restores
  430. * the headphone volume in XTALK_DONE state, it needs recover to
  431. * original level gradually with 3dB per step for less pop noise.
  432. * Otherwise, the restore should do ASAP.
  433. */
  434. for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
  435. if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
  436. NAU8825_REG_HSVOL_CTRL) {
  437. /* Ramping up the volume change to reduce pop noise */
  438. volume = nau8825_xtalk_baktab[i].def &
  439. NAU8825_HPR_VOL_MASK;
  440. nau8825_hpvol_ramp(nau8825, 0, volume, 3);
  441. continue;
  442. }
  443. regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
  444. nau8825_xtalk_baktab[i].def);
  445. }
  446. nau8825->xtalk_baktab_initialized = false;
  447. }
  448. static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
  449. {
  450. /* Enable power of DAC path */
  451. regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
  452. NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
  453. NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
  454. NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
  455. NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
  456. NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
  457. /* Prevent startup click by letting charge pump to ramp up and
  458. * change bump enable
  459. */
  460. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  461. NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
  462. NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
  463. /* Enable clock sync of DAC and DAC clock */
  464. regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
  465. NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
  466. NAU8825_RDAC_FS_BCLK_ENB,
  467. NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
  468. /* Power up output driver with 2 stage */
  469. regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
  470. NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
  471. NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
  472. NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
  473. NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
  474. regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
  475. NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
  476. NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
  477. /* HP outputs not shouted to ground */
  478. regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
  479. NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
  480. /* Enable HP boost driver */
  481. regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
  482. NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
  483. /* Enable class G compare path to supply 1.8V or 0.9V. */
  484. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
  485. NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
  486. NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
  487. }
  488. static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
  489. {
  490. /* Power up left ADC and raise 5dB than Vmid for Vref */
  491. regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
  492. NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
  493. NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
  494. }
  495. static void nau8825_xtalk_clock(struct nau8825 *nau8825)
  496. {
  497. /* Recover FLL default value */
  498. regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
  499. regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
  500. regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
  501. regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
  502. regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
  503. regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
  504. /* Enable internal VCO clock for detection signal generated */
  505. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  506. NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
  507. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
  508. NAU8825_DCO_EN);
  509. /* Given specific clock frequency of internal clock to
  510. * generate signal.
  511. */
  512. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  513. NAU8825_CLK_MCLK_SRC_MASK, 0xf);
  514. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
  515. NAU8825_FLL_RATIO_MASK, 0x10);
  516. }
  517. static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
  518. {
  519. int volume, index;
  520. /* Backup those registers changed by cross talk detection */
  521. nau8825_xtalk_backup(nau8825);
  522. /* Config IIS as master to output signal by codec */
  523. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
  524. NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
  525. NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
  526. (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
  527. /* Ramp up headphone volume to 0dB to get better performance and
  528. * avoid pop noise in headphone.
  529. */
  530. index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
  531. if (index != -EINVAL) {
  532. volume = nau8825_xtalk_baktab[index].def &
  533. NAU8825_HPR_VOL_MASK;
  534. nau8825_hpvol_ramp(nau8825, volume, 0, 3);
  535. }
  536. nau8825_xtalk_clock(nau8825);
  537. nau8825_xtalk_prepare_dac(nau8825);
  538. nau8825_xtalk_prepare_adc(nau8825);
  539. /* Config channel path and digital gain */
  540. regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
  541. NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
  542. NAU8825_DACL_CH_SEL_L | 0xab);
  543. regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
  544. NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
  545. NAU8825_DACR_CH_SEL_R | 0xab);
  546. /* Config cross talk parameters and generate the 23Hz sine wave with
  547. * 1/16 full scale of signal level for impedance measurement.
  548. */
  549. regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
  550. NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
  551. NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
  552. (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
  553. NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
  554. /* RMS intrruption enable */
  555. regmap_update_bits(nau8825->regmap,
  556. NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
  557. /* Power up left and right DAC */
  558. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  559. NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
  560. }
  561. static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
  562. {
  563. /* Disable HP boost driver */
  564. regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
  565. NAU8825_HP_BOOST_DIS, 0);
  566. /* HP outputs shouted to ground */
  567. regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
  568. NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
  569. NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
  570. /* Power down left and right DAC */
  571. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  572. NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
  573. NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
  574. /* Enable the TESTDAC and disable L/R HP impedance */
  575. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  576. NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
  577. NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
  578. /* Power down output driver with 2 stage */
  579. regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
  580. NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
  581. regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
  582. NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
  583. NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
  584. /* Disable clock sync of DAC and DAC clock */
  585. regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
  586. NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
  587. /* Disable charge pump ramp up function and change bump */
  588. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  589. NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
  590. /* Disable power of DAC path */
  591. regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
  592. NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
  593. NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
  594. if (!nau8825->irq)
  595. regmap_update_bits(nau8825->regmap,
  596. NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
  597. }
  598. static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
  599. {
  600. /* Power down left ADC and restore voltage to Vmid */
  601. regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
  602. NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
  603. }
  604. static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
  605. {
  606. /* Enable internal VCO needed for interruptions */
  607. nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
  608. nau8825_xtalk_clean_dac(nau8825);
  609. nau8825_xtalk_clean_adc(nau8825);
  610. /* Clear cross talk parameters and disable */
  611. regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
  612. /* RMS intrruption disable */
  613. regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
  614. NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
  615. /* Recover default value for IIS */
  616. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
  617. NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
  618. NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
  619. /* Restore value of specific register for cross talk */
  620. nau8825_xtalk_restore(nau8825, cause_cancel);
  621. }
  622. static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
  623. {
  624. /* Apply ADC volume for better cross talk performance */
  625. regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
  626. NAU8825_ADC_DIG_VOL_MASK, vol);
  627. /* Disables JKTIP(HPL) DAC channel for right to left measurement.
  628. * Do it before sending signal in order to erase pop noise.
  629. */
  630. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  631. NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
  632. NAU8825_BIAS_TESTDACL_EN);
  633. switch (nau8825->xtalk_state) {
  634. case NAU8825_XTALK_HPR_R2L:
  635. /* Enable right headphone impedance */
  636. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  637. NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
  638. NAU8825_BIAS_HPR_IMP);
  639. break;
  640. case NAU8825_XTALK_HPL_R2L:
  641. /* Enable left headphone impedance */
  642. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  643. NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
  644. NAU8825_BIAS_HPL_IMP);
  645. break;
  646. default:
  647. break;
  648. }
  649. msleep(100);
  650. /* Impedance measurement mode enable */
  651. regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
  652. NAU8825_IMM_EN, NAU8825_IMM_EN);
  653. }
  654. static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
  655. {
  656. /* Impedance measurement mode disable */
  657. regmap_update_bits(nau8825->regmap,
  658. NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
  659. }
  660. /* The cross talk measurement function can reduce cross talk across the
  661. * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
  662. * level to determine what cross talk reduction gain is. This system works by
  663. * sending a 23Hz -24dBV sine wave into the headset output DAC and through
  664. * the PGA. The output of the PGA is then connected to an internal current
  665. * sense which measures the attenuated 23Hz signal and passing the output to
  666. * an ADC which converts the measurement to a binary code. With two separated
  667. * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
  668. * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
  669. * Thus, the measurement function has four states to complete whole sequence.
  670. * 1. Prepare state : Prepare the resource for detection and transfer to HPR
  671. * IMM stat to make JKR1(HPR) impedance measure.
  672. * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
  673. * to HPL IMM state to make JKTIP(HPL) impedance measure.
  674. * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
  675. * transfer to IMM state to determine suppression sidetone gain.
  676. * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
  677. * and cross talk signal level. Apply this gain and then restore codec
  678. * configuration. Then transfer to Done state for ending.
  679. */
  680. static void nau8825_xtalk_measure(struct nau8825 *nau8825)
  681. {
  682. u32 sidetone;
  683. switch (nau8825->xtalk_state) {
  684. case NAU8825_XTALK_PREPARE:
  685. /* In prepare state, set up clock, intrruption, DAC path, ADC
  686. * path and cross talk detection parameters for preparation.
  687. */
  688. nau8825_xtalk_prepare(nau8825);
  689. msleep(280);
  690. /* Trigger right headphone impedance detection */
  691. nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
  692. nau8825_xtalk_imm_start(nau8825, 0x00d2);
  693. break;
  694. case NAU8825_XTALK_HPR_R2L:
  695. /* In right headphone IMM state, read out right headphone
  696. * impedance measure result, and then start up left side.
  697. */
  698. regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
  699. &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
  700. dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
  701. nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
  702. /* Disable then re-enable IMM mode to update */
  703. nau8825_xtalk_imm_stop(nau8825);
  704. /* Trigger left headphone impedance detection */
  705. nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
  706. nau8825_xtalk_imm_start(nau8825, 0x00ff);
  707. break;
  708. case NAU8825_XTALK_HPL_R2L:
  709. /* In left headphone IMM state, read out left headphone
  710. * impedance measure result, and delay some time to wait
  711. * detection sine wave output finish. Then, we can calculate
  712. * the cross talk suppresstion side tone according to the L/R
  713. * headphone imedance.
  714. */
  715. regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
  716. &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
  717. dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
  718. nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
  719. nau8825_xtalk_imm_stop(nau8825);
  720. msleep(150);
  721. nau8825->xtalk_state = NAU8825_XTALK_IMM;
  722. break;
  723. case NAU8825_XTALK_IMM:
  724. /* In impedance measure state, the orignal and cross talk
  725. * signal level vlues are ready. The side tone gain is deter-
  726. * mined with these signal level. After all, restore codec
  727. * configuration.
  728. */
  729. sidetone = nau8825_xtalk_sidetone(
  730. nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
  731. nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
  732. dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
  733. regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
  734. (sidetone << 8) | sidetone);
  735. nau8825_xtalk_clean(nau8825, false);
  736. nau8825->xtalk_state = NAU8825_XTALK_DONE;
  737. break;
  738. default:
  739. break;
  740. }
  741. }
  742. static void nau8825_xtalk_work(struct work_struct *work)
  743. {
  744. struct nau8825 *nau8825 = container_of(
  745. work, struct nau8825, xtalk_work);
  746. nau8825_xtalk_measure(nau8825);
  747. /* To determine the cross talk side tone gain when reach
  748. * the impedance measure state.
  749. */
  750. if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
  751. nau8825_xtalk_measure(nau8825);
  752. /* Delay jack report until cross talk detection process
  753. * completed. It can avoid application to do playback
  754. * preparation before cross talk detection is still working.
  755. * Meanwhile, the protection of the cross talk detection
  756. * is released.
  757. */
  758. if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
  759. snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
  760. nau8825->xtalk_event_mask);
  761. nau8825_sema_release(nau8825);
  762. nau8825->xtalk_protect = false;
  763. }
  764. }
  765. static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
  766. {
  767. /* If the crosstalk is eanbled and the process is on going,
  768. * the driver forces to cancel the crosstalk task and
  769. * restores the configuration to original status.
  770. */
  771. if (nau8825->xtalk_enable && nau8825->xtalk_state !=
  772. NAU8825_XTALK_DONE) {
  773. cancel_work_sync(&nau8825->xtalk_work);
  774. nau8825_xtalk_clean(nau8825, true);
  775. }
  776. /* Reset parameters for cross talk suppression function */
  777. nau8825_sema_reset(nau8825);
  778. nau8825->xtalk_state = NAU8825_XTALK_DONE;
  779. nau8825->xtalk_protect = false;
  780. }
  781. static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
  782. {
  783. switch (reg) {
  784. case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
  785. case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
  786. case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
  787. case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
  788. case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
  789. case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
  790. case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
  791. case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
  792. case NAU8825_REG_MISC_CTRL:
  793. case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
  794. case NAU8825_REG_BIAS_ADJ:
  795. case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
  796. case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
  797. case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
  798. case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
  799. return true;
  800. default:
  801. return false;
  802. }
  803. }
  804. static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
  805. {
  806. switch (reg) {
  807. case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
  808. case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
  809. case NAU8825_REG_INTERRUPT_MASK:
  810. case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
  811. case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
  812. case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
  813. case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
  814. case NAU8825_REG_IMM_MODE_CTRL:
  815. case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
  816. case NAU8825_REG_MISC_CTRL:
  817. case NAU8825_REG_BIAS_ADJ:
  818. case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
  819. case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
  820. case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
  821. case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
  822. return true;
  823. default:
  824. return false;
  825. }
  826. }
  827. static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
  828. {
  829. switch (reg) {
  830. case NAU8825_REG_RESET:
  831. case NAU8825_REG_IRQ_STATUS:
  832. case NAU8825_REG_INT_CLR_KEY_STATUS:
  833. case NAU8825_REG_IMM_RMS_L:
  834. case NAU8825_REG_IMM_RMS_R:
  835. case NAU8825_REG_I2C_DEVICE_ID:
  836. case NAU8825_REG_SARDOUT_RAM_STATUS:
  837. case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
  838. case NAU8825_REG_GENERAL_STATUS:
  839. case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
  840. return true;
  841. default:
  842. return false;
  843. }
  844. }
  845. static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
  846. struct snd_kcontrol *kcontrol, int event)
  847. {
  848. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  849. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  850. switch (event) {
  851. case SND_SOC_DAPM_POST_PMU:
  852. msleep(125);
  853. regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
  854. NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
  855. break;
  856. case SND_SOC_DAPM_POST_PMD:
  857. if (!nau8825->irq)
  858. regmap_update_bits(nau8825->regmap,
  859. NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
  860. break;
  861. default:
  862. return -EINVAL;
  863. }
  864. return 0;
  865. }
  866. static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
  867. struct snd_kcontrol *kcontrol, int event)
  868. {
  869. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  870. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  871. switch (event) {
  872. case SND_SOC_DAPM_POST_PMU:
  873. /* Prevent startup click by letting charge pump to ramp up */
  874. msleep(10);
  875. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  876. NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
  877. break;
  878. case SND_SOC_DAPM_PRE_PMD:
  879. regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
  880. NAU8825_JAMNODCLOW, 0);
  881. break;
  882. default:
  883. return -EINVAL;
  884. }
  885. return 0;
  886. }
  887. static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
  888. struct snd_kcontrol *kcontrol, int event)
  889. {
  890. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  891. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  892. switch (event) {
  893. case SND_SOC_DAPM_PRE_PMU:
  894. /* Disables the TESTDAC to let DAC signal pass through. */
  895. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  896. NAU8825_BIAS_TESTDAC_EN, 0);
  897. break;
  898. case SND_SOC_DAPM_POST_PMD:
  899. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  900. NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
  901. break;
  902. default:
  903. return -EINVAL;
  904. }
  905. return 0;
  906. }
  907. static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
  908. struct snd_ctl_elem_value *ucontrol)
  909. {
  910. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  911. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  912. if (!component->regmap)
  913. return -EINVAL;
  914. regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
  915. ucontrol->value.bytes.data, params->max);
  916. return 0;
  917. }
  918. static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
  919. struct snd_ctl_elem_value *ucontrol)
  920. {
  921. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  922. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  923. void *data;
  924. if (!component->regmap)
  925. return -EINVAL;
  926. data = kmemdup(ucontrol->value.bytes.data,
  927. params->max, GFP_KERNEL | GFP_DMA);
  928. if (!data)
  929. return -ENOMEM;
  930. regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
  931. NAU8825_BIQ_WRT_EN, 0);
  932. regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
  933. data, params->max);
  934. regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
  935. NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
  936. kfree(data);
  937. return 0;
  938. }
  939. static const char * const nau8825_biq_path[] = {
  940. "ADC", "DAC"
  941. };
  942. static const struct soc_enum nau8825_biq_path_enum =
  943. SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
  944. ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
  945. static const char * const nau8825_adc_decimation[] = {
  946. "32", "64", "128", "256"
  947. };
  948. static const struct soc_enum nau8825_adc_decimation_enum =
  949. SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
  950. ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
  951. static const char * const nau8825_dac_oversampl[] = {
  952. "64", "256", "128", "", "32"
  953. };
  954. static const struct soc_enum nau8825_dac_oversampl_enum =
  955. SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
  956. ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
  957. static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
  958. static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
  959. static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
  960. static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
  961. static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
  962. static const struct snd_kcontrol_new nau8825_controls[] = {
  963. SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
  964. 0, 0xff, 0, adc_vol_tlv),
  965. SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
  966. 12, 8, 0x0f, 0, sidetone_vol_tlv),
  967. SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
  968. 6, 0, 0x3f, 1, dac_vol_tlv),
  969. SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
  970. 8, 37, 0, fepga_gain_tlv),
  971. SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
  972. 0, 8, 0xff, 0, crosstalk_vol_tlv),
  973. SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
  974. SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
  975. /* programmable biquad filter */
  976. SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
  977. SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
  978. nau8825_biq_coeff_get, nau8825_biq_coeff_put),
  979. };
  980. /* DAC Mux 0x33[9] and 0x34[9] */
  981. static const char * const nau8825_dac_src[] = {
  982. "DACL", "DACR",
  983. };
  984. static SOC_ENUM_SINGLE_DECL(
  985. nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
  986. NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
  987. static SOC_ENUM_SINGLE_DECL(
  988. nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
  989. NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
  990. static const struct snd_kcontrol_new nau8825_dacl_mux =
  991. SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
  992. static const struct snd_kcontrol_new nau8825_dacr_mux =
  993. SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
  994. static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
  995. SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
  996. 15, 1),
  997. SND_SOC_DAPM_INPUT("MIC"),
  998. SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
  999. SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
  1000. NULL, 0),
  1001. SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
  1002. nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
  1003. SND_SOC_DAPM_POST_PMD),
  1004. SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
  1005. SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
  1006. 0),
  1007. /* ADC for button press detection. A dapm supply widget is used to
  1008. * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
  1009. * during suspend.
  1010. */
  1011. SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
  1012. NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
  1013. SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
  1014. SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
  1015. SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
  1016. SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
  1017. SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
  1018. NAU8825_ENABLE_DACR_SFT, 0),
  1019. SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
  1020. NAU8825_ENABLE_DACL_SFT, 0),
  1021. SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
  1022. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
  1023. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
  1024. SND_SOC_DAPM_PGA_S("HP amp L", 0,
  1025. NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
  1026. SND_SOC_DAPM_PGA_S("HP amp R", 0,
  1027. NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
  1028. SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
  1029. nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
  1030. SND_SOC_DAPM_PRE_PMD),
  1031. SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
  1032. NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
  1033. SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
  1034. NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
  1035. SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
  1036. NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
  1037. SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
  1038. NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
  1039. SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
  1040. NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
  1041. SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
  1042. NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
  1043. SND_SOC_DAPM_PGA_S("Output DACL", 7,
  1044. NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
  1045. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1046. SND_SOC_DAPM_PGA_S("Output DACR", 7,
  1047. NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
  1048. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1049. /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
  1050. SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
  1051. NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
  1052. SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
  1053. NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
  1054. /* High current HPOL/R boost driver */
  1055. SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
  1056. NAU8825_REG_BOOST, 9, 1, NULL, 0),
  1057. /* Class G operation control*/
  1058. SND_SOC_DAPM_PGA_S("Class G", 10,
  1059. NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
  1060. SND_SOC_DAPM_OUTPUT("HPOL"),
  1061. SND_SOC_DAPM_OUTPUT("HPOR"),
  1062. };
  1063. static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
  1064. {"Frontend PGA", NULL, "MIC"},
  1065. {"ADC", NULL, "Frontend PGA"},
  1066. {"ADC", NULL, "ADC Clock"},
  1067. {"ADC", NULL, "ADC Power"},
  1068. {"AIFTX", NULL, "ADC"},
  1069. {"DDACL", NULL, "Playback"},
  1070. {"DDACR", NULL, "Playback"},
  1071. {"DDACL", NULL, "DDAC Clock"},
  1072. {"DDACR", NULL, "DDAC Clock"},
  1073. {"DACL Mux", "DACL", "DDACL"},
  1074. {"DACL Mux", "DACR", "DDACR"},
  1075. {"DACR Mux", "DACL", "DDACL"},
  1076. {"DACR Mux", "DACR", "DDACR"},
  1077. {"HP amp L", NULL, "DACL Mux"},
  1078. {"HP amp R", NULL, "DACR Mux"},
  1079. {"Charge Pump", NULL, "HP amp L"},
  1080. {"Charge Pump", NULL, "HP amp R"},
  1081. {"ADACL", NULL, "Charge Pump"},
  1082. {"ADACR", NULL, "Charge Pump"},
  1083. {"ADACL Clock", NULL, "ADACL"},
  1084. {"ADACR Clock", NULL, "ADACR"},
  1085. {"Output Driver L Stage 1", NULL, "ADACL Clock"},
  1086. {"Output Driver R Stage 1", NULL, "ADACR Clock"},
  1087. {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
  1088. {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
  1089. {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
  1090. {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
  1091. {"Output DACL", NULL, "Output Driver L Stage 3"},
  1092. {"Output DACR", NULL, "Output Driver R Stage 3"},
  1093. {"HPOL Pulldown", NULL, "Output DACL"},
  1094. {"HPOR Pulldown", NULL, "Output DACR"},
  1095. {"HP Boost Driver", NULL, "HPOL Pulldown"},
  1096. {"HP Boost Driver", NULL, "HPOR Pulldown"},
  1097. {"Class G", NULL, "HP Boost Driver"},
  1098. {"HPOL", NULL, "Class G"},
  1099. {"HPOR", NULL, "Class G"},
  1100. };
  1101. static int nau8825_clock_check(struct nau8825 *nau8825,
  1102. int stream, int rate, int osr)
  1103. {
  1104. int osrate;
  1105. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1106. if (osr >= ARRAY_SIZE(osr_dac_sel))
  1107. return -EINVAL;
  1108. osrate = osr_dac_sel[osr].osr;
  1109. } else {
  1110. if (osr >= ARRAY_SIZE(osr_adc_sel))
  1111. return -EINVAL;
  1112. osrate = osr_adc_sel[osr].osr;
  1113. }
  1114. if (!osrate || rate * osr > CLK_DA_AD_MAX) {
  1115. dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
  1116. return -EINVAL;
  1117. }
  1118. return 0;
  1119. }
  1120. static int nau8825_hw_params(struct snd_pcm_substream *substream,
  1121. struct snd_pcm_hw_params *params,
  1122. struct snd_soc_dai *dai)
  1123. {
  1124. struct snd_soc_component *component = dai->component;
  1125. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1126. unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
  1127. nau8825_sema_acquire(nau8825, 3 * HZ);
  1128. /* CLK_DAC or CLK_ADC = OSR * FS
  1129. * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
  1130. * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
  1131. * values must be selected such that the maximum frequency is less
  1132. * than 6.144 MHz.
  1133. */
  1134. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1135. regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
  1136. osr &= NAU8825_DAC_OVERSAMPLE_MASK;
  1137. if (nau8825_clock_check(nau8825, substream->stream,
  1138. params_rate(params), osr)) {
  1139. nau8825_sema_release(nau8825);
  1140. return -EINVAL;
  1141. }
  1142. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  1143. NAU8825_CLK_DAC_SRC_MASK,
  1144. osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
  1145. } else {
  1146. regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
  1147. osr &= NAU8825_ADC_SYNC_DOWN_MASK;
  1148. if (nau8825_clock_check(nau8825, substream->stream,
  1149. params_rate(params), osr)) {
  1150. nau8825_sema_release(nau8825);
  1151. return -EINVAL;
  1152. }
  1153. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  1154. NAU8825_CLK_ADC_SRC_MASK,
  1155. osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
  1156. }
  1157. /* make BCLK and LRC divde configuration if the codec as master. */
  1158. regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
  1159. if (ctrl_val & NAU8825_I2S_MS_MASTER) {
  1160. /* get the bclk and fs ratio */
  1161. bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
  1162. if (bclk_fs <= 32)
  1163. bclk_div = 2;
  1164. else if (bclk_fs <= 64)
  1165. bclk_div = 1;
  1166. else if (bclk_fs <= 128)
  1167. bclk_div = 0;
  1168. else {
  1169. nau8825_sema_release(nau8825);
  1170. return -EINVAL;
  1171. }
  1172. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
  1173. NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
  1174. ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
  1175. }
  1176. switch (params_width(params)) {
  1177. case 16:
  1178. val_len |= NAU8825_I2S_DL_16;
  1179. break;
  1180. case 20:
  1181. val_len |= NAU8825_I2S_DL_20;
  1182. break;
  1183. case 24:
  1184. val_len |= NAU8825_I2S_DL_24;
  1185. break;
  1186. case 32:
  1187. val_len |= NAU8825_I2S_DL_32;
  1188. break;
  1189. default:
  1190. nau8825_sema_release(nau8825);
  1191. return -EINVAL;
  1192. }
  1193. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
  1194. NAU8825_I2S_DL_MASK, val_len);
  1195. /* Release the semaphore. */
  1196. nau8825_sema_release(nau8825);
  1197. return 0;
  1198. }
  1199. static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  1200. {
  1201. struct snd_soc_component *component = codec_dai->component;
  1202. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1203. unsigned int ctrl1_val = 0, ctrl2_val = 0;
  1204. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1205. case SND_SOC_DAIFMT_CBM_CFM:
  1206. ctrl2_val |= NAU8825_I2S_MS_MASTER;
  1207. break;
  1208. case SND_SOC_DAIFMT_CBS_CFS:
  1209. break;
  1210. default:
  1211. return -EINVAL;
  1212. }
  1213. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1214. case SND_SOC_DAIFMT_NB_NF:
  1215. break;
  1216. case SND_SOC_DAIFMT_IB_NF:
  1217. ctrl1_val |= NAU8825_I2S_BP_INV;
  1218. break;
  1219. default:
  1220. return -EINVAL;
  1221. }
  1222. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1223. case SND_SOC_DAIFMT_I2S:
  1224. ctrl1_val |= NAU8825_I2S_DF_I2S;
  1225. break;
  1226. case SND_SOC_DAIFMT_LEFT_J:
  1227. ctrl1_val |= NAU8825_I2S_DF_LEFT;
  1228. break;
  1229. case SND_SOC_DAIFMT_RIGHT_J:
  1230. ctrl1_val |= NAU8825_I2S_DF_RIGTH;
  1231. break;
  1232. case SND_SOC_DAIFMT_DSP_A:
  1233. ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
  1234. break;
  1235. case SND_SOC_DAIFMT_DSP_B:
  1236. ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
  1237. ctrl1_val |= NAU8825_I2S_PCMB_EN;
  1238. break;
  1239. default:
  1240. return -EINVAL;
  1241. }
  1242. nau8825_sema_acquire(nau8825, 3 * HZ);
  1243. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
  1244. NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
  1245. NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
  1246. ctrl1_val);
  1247. regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
  1248. NAU8825_I2S_MS_MASK, ctrl2_val);
  1249. /* Release the semaphore. */
  1250. nau8825_sema_release(nau8825);
  1251. return 0;
  1252. }
  1253. static const struct snd_soc_dai_ops nau8825_dai_ops = {
  1254. .hw_params = nau8825_hw_params,
  1255. .set_fmt = nau8825_set_dai_fmt,
  1256. };
  1257. #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
  1258. #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
  1259. | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  1260. static struct snd_soc_dai_driver nau8825_dai = {
  1261. .name = "nau8825-hifi",
  1262. .playback = {
  1263. .stream_name = "Playback",
  1264. .channels_min = 1,
  1265. .channels_max = 2,
  1266. .rates = NAU8825_RATES,
  1267. .formats = NAU8825_FORMATS,
  1268. },
  1269. .capture = {
  1270. .stream_name = "Capture",
  1271. .channels_min = 1,
  1272. .channels_max = 1,
  1273. .rates = NAU8825_RATES,
  1274. .formats = NAU8825_FORMATS,
  1275. },
  1276. .ops = &nau8825_dai_ops,
  1277. };
  1278. /**
  1279. * nau8825_enable_jack_detect - Specify a jack for event reporting
  1280. *
  1281. * @component: component to register the jack with
  1282. * @jack: jack to use to report headset and button events on
  1283. *
  1284. * After this function has been called the headset insert/remove and button
  1285. * events will be routed to the given jack. Jack can be null to stop
  1286. * reporting.
  1287. */
  1288. int nau8825_enable_jack_detect(struct snd_soc_component *component,
  1289. struct snd_soc_jack *jack)
  1290. {
  1291. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1292. struct regmap *regmap = nau8825->regmap;
  1293. nau8825->jack = jack;
  1294. /* Ground HP Outputs[1:0], needed for headset auto detection
  1295. * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
  1296. */
  1297. regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
  1298. NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
  1299. NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
  1300. return 0;
  1301. }
  1302. EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
  1303. static bool nau8825_is_jack_inserted(struct regmap *regmap)
  1304. {
  1305. bool active_high, is_high;
  1306. int status, jkdet;
  1307. regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
  1308. active_high = jkdet & NAU8825_JACK_POLARITY;
  1309. regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
  1310. is_high = status & NAU8825_GPIO2JD1;
  1311. /* return jack connection status according to jack insertion logic
  1312. * active high or active low.
  1313. */
  1314. return active_high == is_high;
  1315. }
  1316. static void nau8825_restart_jack_detection(struct regmap *regmap)
  1317. {
  1318. /* this will restart the entire jack detection process including MIC/GND
  1319. * switching and create interrupts. We have to go from 0 to 1 and back
  1320. * to 0 to restart.
  1321. */
  1322. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1323. NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
  1324. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1325. NAU8825_JACK_DET_RESTART, 0);
  1326. }
  1327. static void nau8825_int_status_clear_all(struct regmap *regmap)
  1328. {
  1329. int active_irq, clear_irq, i;
  1330. /* Reset the intrruption status from rightmost bit if the corres-
  1331. * ponding irq event occurs.
  1332. */
  1333. regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
  1334. for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
  1335. clear_irq = (0x1 << i);
  1336. if (active_irq & clear_irq)
  1337. regmap_write(regmap,
  1338. NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
  1339. }
  1340. }
  1341. static void nau8825_eject_jack(struct nau8825 *nau8825)
  1342. {
  1343. struct snd_soc_dapm_context *dapm = nau8825->dapm;
  1344. struct regmap *regmap = nau8825->regmap;
  1345. /* Force to cancel the cross talk detection process */
  1346. nau8825_xtalk_cancel(nau8825);
  1347. snd_soc_dapm_disable_pin(dapm, "SAR");
  1348. snd_soc_dapm_disable_pin(dapm, "MICBIAS");
  1349. /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
  1350. regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
  1351. NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
  1352. /* ground HPL/HPR, MICGRND1/2 */
  1353. regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
  1354. snd_soc_dapm_sync(dapm);
  1355. /* Clear all interruption status */
  1356. nau8825_int_status_clear_all(regmap);
  1357. /* Enable the insertion interruption, disable the ejection inter-
  1358. * ruption, and then bypass de-bounce circuit.
  1359. */
  1360. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
  1361. NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
  1362. NAU8825_IRQ_EJECT_DIS);
  1363. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  1364. NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
  1365. NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
  1366. NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
  1367. NAU8825_IRQ_HEADSET_COMPLETE_EN);
  1368. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1369. NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
  1370. /* Disable ADC needed for interruptions at audo mode */
  1371. regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
  1372. NAU8825_ENABLE_ADC, 0);
  1373. /* Close clock for jack type detection at manual mode */
  1374. nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
  1375. }
  1376. /* Enable audo mode interruptions with internal clock. */
  1377. static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
  1378. {
  1379. struct regmap *regmap = nau8825->regmap;
  1380. /* Enable headset jack type detection complete interruption and
  1381. * jack ejection interruption.
  1382. */
  1383. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  1384. NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
  1385. /* Enable internal VCO needed for interruptions */
  1386. nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
  1387. /* Enable ADC needed for interruptions */
  1388. regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
  1389. NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
  1390. /* Chip needs one FSCLK cycle in order to generate interruptions,
  1391. * as we cannot guarantee one will be provided by the system. Turning
  1392. * master mode on then off enables us to generate that FSCLK cycle
  1393. * with a minimum of contention on the clock bus.
  1394. */
  1395. regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
  1396. NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
  1397. regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
  1398. NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
  1399. /* Not bypass de-bounce circuit */
  1400. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1401. NAU8825_JACK_DET_DB_BYPASS, 0);
  1402. /* Unmask all interruptions */
  1403. regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
  1404. /* Restart the jack detection process at auto mode */
  1405. nau8825_restart_jack_detection(regmap);
  1406. }
  1407. static int nau8825_button_decode(int value)
  1408. {
  1409. int buttons = 0;
  1410. /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
  1411. if (value & BIT(0))
  1412. buttons |= SND_JACK_BTN_0;
  1413. if (value & BIT(1))
  1414. buttons |= SND_JACK_BTN_1;
  1415. if (value & BIT(2))
  1416. buttons |= SND_JACK_BTN_2;
  1417. if (value & BIT(3))
  1418. buttons |= SND_JACK_BTN_3;
  1419. if (value & BIT(4))
  1420. buttons |= SND_JACK_BTN_4;
  1421. if (value & BIT(5))
  1422. buttons |= SND_JACK_BTN_5;
  1423. return buttons;
  1424. }
  1425. static int nau8825_jack_insert(struct nau8825 *nau8825)
  1426. {
  1427. struct regmap *regmap = nau8825->regmap;
  1428. struct snd_soc_dapm_context *dapm = nau8825->dapm;
  1429. int jack_status_reg, mic_detected;
  1430. int type = 0;
  1431. regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
  1432. mic_detected = (jack_status_reg >> 10) & 3;
  1433. /* The JKSLV and JKR2 all detected in high impedance headset */
  1434. if (mic_detected == 0x3)
  1435. nau8825->high_imped = true;
  1436. else
  1437. nau8825->high_imped = false;
  1438. switch (mic_detected) {
  1439. case 0:
  1440. /* no mic */
  1441. type = SND_JACK_HEADPHONE;
  1442. break;
  1443. case 1:
  1444. dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
  1445. type = SND_JACK_HEADSET;
  1446. /* Unground MICGND1 */
  1447. regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
  1448. 1 << 2);
  1449. /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
  1450. regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
  1451. NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
  1452. NAU8825_MICBIAS_JKR2);
  1453. /* Attach SARADC to MICGND1 */
  1454. regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
  1455. NAU8825_SAR_INPUT_MASK,
  1456. NAU8825_SAR_INPUT_JKR2);
  1457. snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
  1458. snd_soc_dapm_force_enable_pin(dapm, "SAR");
  1459. snd_soc_dapm_sync(dapm);
  1460. break;
  1461. case 2:
  1462. dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
  1463. type = SND_JACK_HEADSET;
  1464. /* Unground MICGND2 */
  1465. regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
  1466. 2 << 2);
  1467. /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
  1468. regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
  1469. NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
  1470. NAU8825_MICBIAS_JKSLV);
  1471. /* Attach SARADC to MICGND2 */
  1472. regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
  1473. NAU8825_SAR_INPUT_MASK,
  1474. NAU8825_SAR_INPUT_JKSLV);
  1475. snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
  1476. snd_soc_dapm_force_enable_pin(dapm, "SAR");
  1477. snd_soc_dapm_sync(dapm);
  1478. break;
  1479. case 3:
  1480. /* detect error case */
  1481. dev_err(nau8825->dev, "detection error; disable mic function\n");
  1482. type = SND_JACK_HEADPHONE;
  1483. break;
  1484. }
  1485. /* Leaving HPOL/R grounded after jack insert by default. They will be
  1486. * ungrounded as part of the widget power up sequence at the beginning
  1487. * of playback to reduce pop.
  1488. */
  1489. return type;
  1490. }
  1491. #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
  1492. SND_JACK_BTN_2 | SND_JACK_BTN_3)
  1493. static irqreturn_t nau8825_interrupt(int irq, void *data)
  1494. {
  1495. struct nau8825 *nau8825 = (struct nau8825 *)data;
  1496. struct regmap *regmap = nau8825->regmap;
  1497. int active_irq, clear_irq = 0, event = 0, event_mask = 0;
  1498. if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
  1499. dev_err(nau8825->dev, "failed to read irq status\n");
  1500. return IRQ_NONE;
  1501. }
  1502. if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
  1503. NAU8825_JACK_EJECTION_DETECTED) {
  1504. nau8825_eject_jack(nau8825);
  1505. event_mask |= SND_JACK_HEADSET;
  1506. clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
  1507. } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
  1508. int key_status;
  1509. regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
  1510. &key_status);
  1511. /* upper 8 bits of the register are for short pressed keys,
  1512. * lower 8 bits - for long pressed buttons
  1513. */
  1514. nau8825->button_pressed = nau8825_button_decode(
  1515. key_status >> 8);
  1516. event |= nau8825->button_pressed;
  1517. event_mask |= NAU8825_BUTTONS;
  1518. clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
  1519. } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
  1520. event_mask = NAU8825_BUTTONS;
  1521. clear_irq = NAU8825_KEY_RELEASE_IRQ;
  1522. } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
  1523. if (nau8825_is_jack_inserted(regmap)) {
  1524. event |= nau8825_jack_insert(nau8825);
  1525. if (nau8825->xtalk_enable && !nau8825->high_imped) {
  1526. /* Apply the cross talk suppression in the
  1527. * headset without high impedance.
  1528. */
  1529. if (!nau8825->xtalk_protect) {
  1530. /* Raise protection for cross talk de-
  1531. * tection if no protection before.
  1532. * The driver has to cancel the pro-
  1533. * cess and restore changes if process
  1534. * is ongoing when ejection.
  1535. */
  1536. int ret;
  1537. nau8825->xtalk_protect = true;
  1538. ret = nau8825_sema_acquire(nau8825, 0);
  1539. if (ret)
  1540. nau8825->xtalk_protect = false;
  1541. }
  1542. /* Startup cross talk detection process */
  1543. if (nau8825->xtalk_protect) {
  1544. nau8825->xtalk_state =
  1545. NAU8825_XTALK_PREPARE;
  1546. schedule_work(&nau8825->xtalk_work);
  1547. }
  1548. } else {
  1549. /* The cross talk suppression shouldn't apply
  1550. * in the headset with high impedance. Thus,
  1551. * relieve the protection raised before.
  1552. */
  1553. if (nau8825->xtalk_protect) {
  1554. nau8825_sema_release(nau8825);
  1555. nau8825->xtalk_protect = false;
  1556. }
  1557. }
  1558. } else {
  1559. dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
  1560. nau8825_eject_jack(nau8825);
  1561. }
  1562. event_mask |= SND_JACK_HEADSET;
  1563. clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
  1564. /* Record the interruption report event for driver to report
  1565. * the event later. The jack report will delay until cross
  1566. * talk detection process is done.
  1567. */
  1568. if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
  1569. nau8825->xtalk_event = event;
  1570. nau8825->xtalk_event_mask = event_mask;
  1571. }
  1572. } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
  1573. /* crosstalk detection enable and process on going */
  1574. if (nau8825->xtalk_enable && nau8825->xtalk_protect)
  1575. schedule_work(&nau8825->xtalk_work);
  1576. clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
  1577. } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
  1578. NAU8825_JACK_INSERTION_DETECTED) {
  1579. /* One more step to check GPIO status directly. Thus, the
  1580. * driver can confirm the real insertion interruption because
  1581. * the intrruption at manual mode has bypassed debounce
  1582. * circuit which can get rid of unstable status.
  1583. */
  1584. if (nau8825_is_jack_inserted(regmap)) {
  1585. /* Turn off insertion interruption at manual mode */
  1586. regmap_update_bits(regmap,
  1587. NAU8825_REG_INTERRUPT_DIS_CTRL,
  1588. NAU8825_IRQ_INSERT_DIS,
  1589. NAU8825_IRQ_INSERT_DIS);
  1590. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  1591. NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
  1592. /* Enable interruption for jack type detection at audo
  1593. * mode which can detect microphone and jack type.
  1594. */
  1595. nau8825_setup_auto_irq(nau8825);
  1596. }
  1597. }
  1598. if (!clear_irq)
  1599. clear_irq = active_irq;
  1600. /* clears the rightmost interruption */
  1601. regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
  1602. /* Delay jack report until cross talk detection is done. It can avoid
  1603. * application to do playback preparation when cross talk detection
  1604. * process is still working. Otherwise, the resource like clock and
  1605. * power will be issued by them at the same time and conflict happens.
  1606. */
  1607. if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
  1608. snd_soc_jack_report(nau8825->jack, event, event_mask);
  1609. return IRQ_HANDLED;
  1610. }
  1611. static void nau8825_setup_buttons(struct nau8825 *nau8825)
  1612. {
  1613. struct regmap *regmap = nau8825->regmap;
  1614. regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
  1615. NAU8825_SAR_TRACKING_GAIN_MASK,
  1616. nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
  1617. regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
  1618. NAU8825_SAR_COMPARE_TIME_MASK,
  1619. nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
  1620. regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
  1621. NAU8825_SAR_SAMPLING_TIME_MASK,
  1622. nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
  1623. regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
  1624. NAU8825_KEYDET_LEVELS_NR_MASK,
  1625. (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
  1626. regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
  1627. NAU8825_KEYDET_HYSTERESIS_MASK,
  1628. nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
  1629. regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
  1630. NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
  1631. nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
  1632. regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
  1633. (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
  1634. regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
  1635. (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
  1636. regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
  1637. (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
  1638. regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
  1639. (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
  1640. /* Enable short press and release interruptions */
  1641. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  1642. NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
  1643. 0);
  1644. }
  1645. static void nau8825_init_regs(struct nau8825 *nau8825)
  1646. {
  1647. struct regmap *regmap = nau8825->regmap;
  1648. /* Latch IIC LSB value */
  1649. regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
  1650. /* Enable Bias/Vmid */
  1651. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  1652. NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
  1653. regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
  1654. NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
  1655. /* VMID Tieoff */
  1656. regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
  1657. NAU8825_BIAS_VMID_SEL_MASK,
  1658. nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
  1659. /* Disable Boost Driver, Automatic Short circuit protection enable */
  1660. regmap_update_bits(regmap, NAU8825_REG_BOOST,
  1661. NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
  1662. NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
  1663. NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
  1664. NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
  1665. regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
  1666. NAU8825_JKDET_OUTPUT_EN,
  1667. nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
  1668. regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
  1669. NAU8825_JKDET_PULL_EN,
  1670. nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
  1671. regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
  1672. NAU8825_JKDET_PULL_UP,
  1673. nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
  1674. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1675. NAU8825_JACK_POLARITY,
  1676. /* jkdet_polarity - 1 is for active-low */
  1677. nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
  1678. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1679. NAU8825_JACK_INSERT_DEBOUNCE_MASK,
  1680. nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
  1681. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  1682. NAU8825_JACK_EJECT_DEBOUNCE_MASK,
  1683. nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
  1684. /* Pull up IRQ pin */
  1685. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  1686. NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN,
  1687. NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN);
  1688. /* Mask unneeded IRQs: 1 - disable, 0 - enable */
  1689. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
  1690. regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
  1691. NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
  1692. if (nau8825->sar_threshold_num)
  1693. nau8825_setup_buttons(nau8825);
  1694. /* Default oversampling/decimations settings are unusable
  1695. * (audible hiss). Set it to something better.
  1696. */
  1697. regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
  1698. NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
  1699. NAU8825_ADC_SYNC_DOWN_64);
  1700. regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
  1701. NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
  1702. /* Disable DACR/L power */
  1703. regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
  1704. NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
  1705. NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
  1706. /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
  1707. * signal to avoid any glitches due to power up transients in both
  1708. * the analog and digital DAC circuit.
  1709. */
  1710. regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
  1711. NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
  1712. /* CICCLP off */
  1713. regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
  1714. NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
  1715. /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
  1716. regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
  1717. NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
  1718. NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
  1719. NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
  1720. NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
  1721. /* Class G timer 64ms */
  1722. regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
  1723. NAU8825_CLASSG_TIMER_MASK,
  1724. 0x20 << NAU8825_CLASSG_TIMER_SFT);
  1725. /* DAC clock delay 2ns, VREF */
  1726. regmap_update_bits(regmap, NAU8825_REG_RDAC,
  1727. NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
  1728. (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
  1729. (0x3 << NAU8825_RDAC_VREF_SFT));
  1730. /* Config L/R channel */
  1731. regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
  1732. NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
  1733. regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
  1734. NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
  1735. /* Disable short Frame Sync detection logic */
  1736. regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
  1737. NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
  1738. }
  1739. static const struct regmap_config nau8825_regmap_config = {
  1740. .val_bits = NAU8825_REG_DATA_LEN,
  1741. .reg_bits = NAU8825_REG_ADDR_LEN,
  1742. .max_register = NAU8825_REG_MAX,
  1743. .readable_reg = nau8825_readable_reg,
  1744. .writeable_reg = nau8825_writeable_reg,
  1745. .volatile_reg = nau8825_volatile_reg,
  1746. .cache_type = REGCACHE_RBTREE,
  1747. .reg_defaults = nau8825_reg_defaults,
  1748. .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
  1749. };
  1750. static int nau8825_component_probe(struct snd_soc_component *component)
  1751. {
  1752. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1753. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1754. nau8825->dapm = dapm;
  1755. return 0;
  1756. }
  1757. static void nau8825_component_remove(struct snd_soc_component *component)
  1758. {
  1759. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1760. /* Cancel and reset cross tak suppresstion detection funciton */
  1761. nau8825_xtalk_cancel(nau8825);
  1762. }
  1763. /**
  1764. * nau8825_calc_fll_param - Calculate FLL parameters.
  1765. * @fll_in: external clock provided to codec.
  1766. * @fs: sampling rate.
  1767. * @fll_param: Pointer to structure of FLL parameters.
  1768. *
  1769. * Calculate FLL parameters to configure codec.
  1770. *
  1771. * Returns 0 for success or negative error code.
  1772. */
  1773. static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
  1774. struct nau8825_fll *fll_param)
  1775. {
  1776. u64 fvco, fvco_max;
  1777. unsigned int fref, i, fvco_sel;
  1778. /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
  1779. * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
  1780. * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
  1781. */
  1782. for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
  1783. fref = fll_in / fll_pre_scalar[i].param;
  1784. if (fref <= NAU_FREF_MAX)
  1785. break;
  1786. }
  1787. if (i == ARRAY_SIZE(fll_pre_scalar))
  1788. return -EINVAL;
  1789. fll_param->clk_ref_div = fll_pre_scalar[i].val;
  1790. /* Choose the FLL ratio based on FREF */
  1791. for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
  1792. if (fref >= fll_ratio[i].param)
  1793. break;
  1794. }
  1795. if (i == ARRAY_SIZE(fll_ratio))
  1796. return -EINVAL;
  1797. fll_param->ratio = fll_ratio[i].val;
  1798. /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
  1799. * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
  1800. * guaranteed across the full range of operation.
  1801. * FDCO = freq_out * 2 * mclk_src_scaling
  1802. */
  1803. fvco_max = 0;
  1804. fvco_sel = ARRAY_SIZE(mclk_src_scaling);
  1805. for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
  1806. fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
  1807. if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
  1808. fvco_max < fvco) {
  1809. fvco_max = fvco;
  1810. fvco_sel = i;
  1811. }
  1812. }
  1813. if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
  1814. return -EINVAL;
  1815. fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
  1816. /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
  1817. * input based on FDCO, FREF and FLL ratio.
  1818. */
  1819. fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
  1820. fll_param->fll_int = (fvco >> 16) & 0x3FF;
  1821. fll_param->fll_frac = fvco & 0xFFFF;
  1822. return 0;
  1823. }
  1824. static void nau8825_fll_apply(struct nau8825 *nau8825,
  1825. struct nau8825_fll *fll_param)
  1826. {
  1827. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  1828. NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
  1829. NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
  1830. /* Make DSP operate at high speed for better performance. */
  1831. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
  1832. NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
  1833. fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
  1834. /* FLL 16-bit fractional input */
  1835. regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
  1836. /* FLL 10-bit integer input */
  1837. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
  1838. NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
  1839. /* FLL pre-scaler */
  1840. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
  1841. NAU8825_FLL_REF_DIV_MASK,
  1842. fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
  1843. /* select divided VCO input */
  1844. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
  1845. NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
  1846. /* Disable free-running mode */
  1847. regmap_update_bits(nau8825->regmap,
  1848. NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
  1849. if (fll_param->fll_frac) {
  1850. /* set FLL loop filter enable and cutoff frequency at 500Khz */
  1851. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
  1852. NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
  1853. NAU8825_FLL_FTR_SW_MASK,
  1854. NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
  1855. NAU8825_FLL_FTR_SW_FILTER);
  1856. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
  1857. NAU8825_SDM_EN | NAU8825_CUTOFF500,
  1858. NAU8825_SDM_EN | NAU8825_CUTOFF500);
  1859. } else {
  1860. /* disable FLL loop filter and cutoff frequency */
  1861. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
  1862. NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
  1863. NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
  1864. regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
  1865. NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
  1866. }
  1867. }
  1868. /* freq_out must be 256*Fs in order to achieve the best performance */
  1869. static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source,
  1870. unsigned int freq_in, unsigned int freq_out)
  1871. {
  1872. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  1873. struct nau8825_fll fll_param;
  1874. int ret, fs;
  1875. fs = freq_out / 256;
  1876. ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
  1877. if (ret < 0) {
  1878. dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
  1879. return ret;
  1880. }
  1881. dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
  1882. fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
  1883. fll_param.fll_int, fll_param.clk_ref_div);
  1884. nau8825_fll_apply(nau8825, &fll_param);
  1885. mdelay(2);
  1886. regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
  1887. NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
  1888. return 0;
  1889. }
  1890. static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
  1891. {
  1892. int ret = 0;
  1893. nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
  1894. if (IS_ERR(nau8825->mclk)) {
  1895. dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
  1896. return 0;
  1897. }
  1898. if (!nau8825->mclk_freq) {
  1899. ret = clk_prepare_enable(nau8825->mclk);
  1900. if (ret) {
  1901. dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
  1902. return ret;
  1903. }
  1904. }
  1905. if (nau8825->mclk_freq != freq) {
  1906. freq = clk_round_rate(nau8825->mclk, freq);
  1907. ret = clk_set_rate(nau8825->mclk, freq);
  1908. if (ret) {
  1909. dev_err(nau8825->dev, "Unable to set mclk rate\n");
  1910. return ret;
  1911. }
  1912. nau8825->mclk_freq = freq;
  1913. }
  1914. return 0;
  1915. }
  1916. static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
  1917. {
  1918. regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
  1919. NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
  1920. regmap_update_bits(regmap, NAU8825_REG_FLL6,
  1921. NAU8825_DCO_EN, 0);
  1922. /* Make DSP operate as default setting for power saving. */
  1923. regmap_update_bits(regmap, NAU8825_REG_FLL1,
  1924. NAU8825_ICTRL_LATCH_MASK, 0);
  1925. }
  1926. static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
  1927. unsigned int freq)
  1928. {
  1929. struct regmap *regmap = nau8825->regmap;
  1930. int ret;
  1931. switch (clk_id) {
  1932. case NAU8825_CLK_DIS:
  1933. /* Clock provided externally and disable internal VCO clock */
  1934. nau8825_configure_mclk_as_sysclk(regmap);
  1935. if (nau8825->mclk_freq) {
  1936. clk_disable_unprepare(nau8825->mclk);
  1937. nau8825->mclk_freq = 0;
  1938. }
  1939. break;
  1940. case NAU8825_CLK_MCLK:
  1941. /* Acquire the semaphore to synchronize the playback and
  1942. * interrupt handler. In order to avoid the playback inter-
  1943. * fered by cross talk process, the driver make the playback
  1944. * preparation halted until cross talk process finish.
  1945. */
  1946. nau8825_sema_acquire(nau8825, 3 * HZ);
  1947. nau8825_configure_mclk_as_sysclk(regmap);
  1948. /* MCLK not changed by clock tree */
  1949. regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
  1950. NAU8825_CLK_MCLK_SRC_MASK, 0);
  1951. /* Release the semaphore. */
  1952. nau8825_sema_release(nau8825);
  1953. ret = nau8825_mclk_prepare(nau8825, freq);
  1954. if (ret)
  1955. return ret;
  1956. break;
  1957. case NAU8825_CLK_INTERNAL:
  1958. if (nau8825_is_jack_inserted(nau8825->regmap)) {
  1959. regmap_update_bits(regmap, NAU8825_REG_FLL6,
  1960. NAU8825_DCO_EN, NAU8825_DCO_EN);
  1961. regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
  1962. NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
  1963. /* Decrease the VCO frequency and make DSP operate
  1964. * as default setting for power saving.
  1965. */
  1966. regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
  1967. NAU8825_CLK_MCLK_SRC_MASK, 0xf);
  1968. regmap_update_bits(regmap, NAU8825_REG_FLL1,
  1969. NAU8825_ICTRL_LATCH_MASK |
  1970. NAU8825_FLL_RATIO_MASK, 0x10);
  1971. regmap_update_bits(regmap, NAU8825_REG_FLL6,
  1972. NAU8825_SDM_EN, NAU8825_SDM_EN);
  1973. } else {
  1974. /* The clock turns off intentionally for power saving
  1975. * when no headset connected.
  1976. */
  1977. nau8825_configure_mclk_as_sysclk(regmap);
  1978. dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
  1979. }
  1980. if (nau8825->mclk_freq) {
  1981. clk_disable_unprepare(nau8825->mclk);
  1982. nau8825->mclk_freq = 0;
  1983. }
  1984. break;
  1985. case NAU8825_CLK_FLL_MCLK:
  1986. /* Acquire the semaphore to synchronize the playback and
  1987. * interrupt handler. In order to avoid the playback inter-
  1988. * fered by cross talk process, the driver make the playback
  1989. * preparation halted until cross talk process finish.
  1990. */
  1991. nau8825_sema_acquire(nau8825, 3 * HZ);
  1992. /* Higher FLL reference input frequency can only set lower
  1993. * gain error, such as 0000 for input reference from MCLK
  1994. * 12.288Mhz.
  1995. */
  1996. regmap_update_bits(regmap, NAU8825_REG_FLL3,
  1997. NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
  1998. NAU8825_FLL_CLK_SRC_MCLK | 0);
  1999. /* Release the semaphore. */
  2000. nau8825_sema_release(nau8825);
  2001. ret = nau8825_mclk_prepare(nau8825, freq);
  2002. if (ret)
  2003. return ret;
  2004. break;
  2005. case NAU8825_CLK_FLL_BLK:
  2006. /* Acquire the semaphore to synchronize the playback and
  2007. * interrupt handler. In order to avoid the playback inter-
  2008. * fered by cross talk process, the driver make the playback
  2009. * preparation halted until cross talk process finish.
  2010. */
  2011. nau8825_sema_acquire(nau8825, 3 * HZ);
  2012. /* If FLL reference input is from low frequency source,
  2013. * higher error gain can apply such as 0xf which has
  2014. * the most sensitive gain error correction threshold,
  2015. * Therefore, FLL has the most accurate DCO to
  2016. * target frequency.
  2017. */
  2018. regmap_update_bits(regmap, NAU8825_REG_FLL3,
  2019. NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
  2020. NAU8825_FLL_CLK_SRC_BLK |
  2021. (0xf << NAU8825_GAIN_ERR_SFT));
  2022. /* Release the semaphore. */
  2023. nau8825_sema_release(nau8825);
  2024. if (nau8825->mclk_freq) {
  2025. clk_disable_unprepare(nau8825->mclk);
  2026. nau8825->mclk_freq = 0;
  2027. }
  2028. break;
  2029. case NAU8825_CLK_FLL_FS:
  2030. /* Acquire the semaphore to synchronize the playback and
  2031. * interrupt handler. In order to avoid the playback inter-
  2032. * fered by cross talk process, the driver make the playback
  2033. * preparation halted until cross talk process finish.
  2034. */
  2035. nau8825_sema_acquire(nau8825, 3 * HZ);
  2036. /* If FLL reference input is from low frequency source,
  2037. * higher error gain can apply such as 0xf which has
  2038. * the most sensitive gain error correction threshold,
  2039. * Therefore, FLL has the most accurate DCO to
  2040. * target frequency.
  2041. */
  2042. regmap_update_bits(regmap, NAU8825_REG_FLL3,
  2043. NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
  2044. NAU8825_FLL_CLK_SRC_FS |
  2045. (0xf << NAU8825_GAIN_ERR_SFT));
  2046. /* Release the semaphore. */
  2047. nau8825_sema_release(nau8825);
  2048. if (nau8825->mclk_freq) {
  2049. clk_disable_unprepare(nau8825->mclk);
  2050. nau8825->mclk_freq = 0;
  2051. }
  2052. break;
  2053. default:
  2054. dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
  2055. return -EINVAL;
  2056. }
  2057. dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
  2058. clk_id);
  2059. return 0;
  2060. }
  2061. static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id,
  2062. int source, unsigned int freq, int dir)
  2063. {
  2064. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  2065. return nau8825_configure_sysclk(nau8825, clk_id, freq);
  2066. }
  2067. static int nau8825_resume_setup(struct nau8825 *nau8825)
  2068. {
  2069. struct regmap *regmap = nau8825->regmap;
  2070. /* Close clock when jack type detection at manual mode */
  2071. nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
  2072. /* Clear all interruption status */
  2073. nau8825_int_status_clear_all(regmap);
  2074. /* Enable both insertion and ejection interruptions, and then
  2075. * bypass de-bounce circuit.
  2076. */
  2077. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
  2078. NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
  2079. NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
  2080. NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
  2081. regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
  2082. NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
  2083. regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
  2084. NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
  2085. return 0;
  2086. }
  2087. static int nau8825_set_bias_level(struct snd_soc_component *component,
  2088. enum snd_soc_bias_level level)
  2089. {
  2090. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  2091. int ret;
  2092. switch (level) {
  2093. case SND_SOC_BIAS_ON:
  2094. break;
  2095. case SND_SOC_BIAS_PREPARE:
  2096. break;
  2097. case SND_SOC_BIAS_STANDBY:
  2098. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  2099. if (nau8825->mclk_freq) {
  2100. ret = clk_prepare_enable(nau8825->mclk);
  2101. if (ret) {
  2102. dev_err(nau8825->dev, "Unable to prepare component mclk\n");
  2103. return ret;
  2104. }
  2105. }
  2106. /* Setup codec configuration after resume */
  2107. nau8825_resume_setup(nau8825);
  2108. }
  2109. break;
  2110. case SND_SOC_BIAS_OFF:
  2111. /* Reset the configuration of jack type for detection */
  2112. /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
  2113. regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
  2114. NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
  2115. /* ground HPL/HPR, MICGRND1/2 */
  2116. regmap_update_bits(nau8825->regmap,
  2117. NAU8825_REG_HSD_CTRL, 0xf, 0xf);
  2118. /* Cancel and reset cross talk detection funciton */
  2119. nau8825_xtalk_cancel(nau8825);
  2120. /* Turn off all interruptions before system shutdown. Keep the
  2121. * interruption quiet before resume setup completes.
  2122. */
  2123. regmap_write(nau8825->regmap,
  2124. NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
  2125. /* Disable ADC needed for interruptions at audo mode */
  2126. regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
  2127. NAU8825_ENABLE_ADC, 0);
  2128. if (nau8825->mclk_freq)
  2129. clk_disable_unprepare(nau8825->mclk);
  2130. break;
  2131. }
  2132. return 0;
  2133. }
  2134. static int __maybe_unused nau8825_suspend(struct snd_soc_component *component)
  2135. {
  2136. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  2137. disable_irq(nau8825->irq);
  2138. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  2139. /* Power down codec power; don't suppoet button wakeup */
  2140. snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
  2141. snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
  2142. snd_soc_dapm_sync(nau8825->dapm);
  2143. regcache_cache_only(nau8825->regmap, true);
  2144. regcache_mark_dirty(nau8825->regmap);
  2145. return 0;
  2146. }
  2147. static int __maybe_unused nau8825_resume(struct snd_soc_component *component)
  2148. {
  2149. struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
  2150. int ret;
  2151. regcache_cache_only(nau8825->regmap, false);
  2152. regcache_sync(nau8825->regmap);
  2153. nau8825->xtalk_protect = true;
  2154. ret = nau8825_sema_acquire(nau8825, 0);
  2155. if (ret)
  2156. nau8825->xtalk_protect = false;
  2157. enable_irq(nau8825->irq);
  2158. return 0;
  2159. }
  2160. static const struct snd_soc_component_driver nau8825_component_driver = {
  2161. .probe = nau8825_component_probe,
  2162. .remove = nau8825_component_remove,
  2163. .set_sysclk = nau8825_set_sysclk,
  2164. .set_pll = nau8825_set_pll,
  2165. .set_bias_level = nau8825_set_bias_level,
  2166. .suspend = nau8825_suspend,
  2167. .resume = nau8825_resume,
  2168. .controls = nau8825_controls,
  2169. .num_controls = ARRAY_SIZE(nau8825_controls),
  2170. .dapm_widgets = nau8825_dapm_widgets,
  2171. .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
  2172. .dapm_routes = nau8825_dapm_routes,
  2173. .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
  2174. .suspend_bias_off = 1,
  2175. .idle_bias_on = 1,
  2176. .use_pmdown_time = 1,
  2177. .endianness = 1,
  2178. .non_legacy_dai_naming = 1,
  2179. };
  2180. static void nau8825_reset_chip(struct regmap *regmap)
  2181. {
  2182. regmap_write(regmap, NAU8825_REG_RESET, 0x00);
  2183. regmap_write(regmap, NAU8825_REG_RESET, 0x00);
  2184. }
  2185. static void nau8825_print_device_properties(struct nau8825 *nau8825)
  2186. {
  2187. int i;
  2188. struct device *dev = nau8825->dev;
  2189. dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
  2190. dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
  2191. dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
  2192. dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
  2193. dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
  2194. dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
  2195. dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
  2196. for (i = 0; i < nau8825->sar_threshold_num; i++)
  2197. dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
  2198. nau8825->sar_threshold[i]);
  2199. dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
  2200. dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
  2201. dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
  2202. dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
  2203. dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
  2204. dev_dbg(dev, "jack-insert-debounce: %d\n",
  2205. nau8825->jack_insert_debounce);
  2206. dev_dbg(dev, "jack-eject-debounce: %d\n",
  2207. nau8825->jack_eject_debounce);
  2208. dev_dbg(dev, "crosstalk-enable: %d\n",
  2209. nau8825->xtalk_enable);
  2210. }
  2211. static int nau8825_read_device_properties(struct device *dev,
  2212. struct nau8825 *nau8825) {
  2213. int ret;
  2214. nau8825->jkdet_enable = device_property_read_bool(dev,
  2215. "nuvoton,jkdet-enable");
  2216. nau8825->jkdet_pull_enable = device_property_read_bool(dev,
  2217. "nuvoton,jkdet-pull-enable");
  2218. nau8825->jkdet_pull_up = device_property_read_bool(dev,
  2219. "nuvoton,jkdet-pull-up");
  2220. ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
  2221. &nau8825->jkdet_polarity);
  2222. if (ret)
  2223. nau8825->jkdet_polarity = 1;
  2224. ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
  2225. &nau8825->micbias_voltage);
  2226. if (ret)
  2227. nau8825->micbias_voltage = 6;
  2228. ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
  2229. &nau8825->vref_impedance);
  2230. if (ret)
  2231. nau8825->vref_impedance = 2;
  2232. ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
  2233. &nau8825->sar_threshold_num);
  2234. if (ret)
  2235. nau8825->sar_threshold_num = 4;
  2236. ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
  2237. nau8825->sar_threshold, nau8825->sar_threshold_num);
  2238. if (ret) {
  2239. nau8825->sar_threshold[0] = 0x08;
  2240. nau8825->sar_threshold[1] = 0x12;
  2241. nau8825->sar_threshold[2] = 0x26;
  2242. nau8825->sar_threshold[3] = 0x73;
  2243. }
  2244. ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
  2245. &nau8825->sar_hysteresis);
  2246. if (ret)
  2247. nau8825->sar_hysteresis = 0;
  2248. ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
  2249. &nau8825->sar_voltage);
  2250. if (ret)
  2251. nau8825->sar_voltage = 6;
  2252. ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
  2253. &nau8825->sar_compare_time);
  2254. if (ret)
  2255. nau8825->sar_compare_time = 1;
  2256. ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
  2257. &nau8825->sar_sampling_time);
  2258. if (ret)
  2259. nau8825->sar_sampling_time = 1;
  2260. ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
  2261. &nau8825->key_debounce);
  2262. if (ret)
  2263. nau8825->key_debounce = 3;
  2264. ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
  2265. &nau8825->jack_insert_debounce);
  2266. if (ret)
  2267. nau8825->jack_insert_debounce = 7;
  2268. ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
  2269. &nau8825->jack_eject_debounce);
  2270. if (ret)
  2271. nau8825->jack_eject_debounce = 0;
  2272. nau8825->xtalk_enable = device_property_read_bool(dev,
  2273. "nuvoton,crosstalk-enable");
  2274. nau8825->mclk = devm_clk_get(dev, "mclk");
  2275. if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
  2276. return -EPROBE_DEFER;
  2277. } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
  2278. /* The MCLK is managed externally or not used at all */
  2279. nau8825->mclk = NULL;
  2280. dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
  2281. } else if (IS_ERR(nau8825->mclk)) {
  2282. return -EINVAL;
  2283. }
  2284. return 0;
  2285. }
  2286. static int nau8825_setup_irq(struct nau8825 *nau8825)
  2287. {
  2288. int ret;
  2289. ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
  2290. nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  2291. "nau8825", nau8825);
  2292. if (ret) {
  2293. dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
  2294. nau8825->irq, ret);
  2295. return ret;
  2296. }
  2297. return 0;
  2298. }
  2299. static int nau8825_i2c_probe(struct i2c_client *i2c,
  2300. const struct i2c_device_id *id)
  2301. {
  2302. struct device *dev = &i2c->dev;
  2303. struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
  2304. int ret, value;
  2305. if (!nau8825) {
  2306. nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
  2307. if (!nau8825)
  2308. return -ENOMEM;
  2309. ret = nau8825_read_device_properties(dev, nau8825);
  2310. if (ret)
  2311. return ret;
  2312. }
  2313. i2c_set_clientdata(i2c, nau8825);
  2314. nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
  2315. if (IS_ERR(nau8825->regmap))
  2316. return PTR_ERR(nau8825->regmap);
  2317. nau8825->dev = dev;
  2318. nau8825->irq = i2c->irq;
  2319. /* Initiate parameters, semaphore and work queue which are needed in
  2320. * cross talk suppression measurment function.
  2321. */
  2322. nau8825->xtalk_state = NAU8825_XTALK_DONE;
  2323. nau8825->xtalk_protect = false;
  2324. nau8825->xtalk_baktab_initialized = false;
  2325. sema_init(&nau8825->xtalk_sem, 1);
  2326. INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
  2327. nau8825_print_device_properties(nau8825);
  2328. nau8825_reset_chip(nau8825->regmap);
  2329. ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
  2330. if (ret < 0) {
  2331. dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
  2332. ret);
  2333. return ret;
  2334. }
  2335. if ((value & NAU8825_SOFTWARE_ID_MASK) !=
  2336. NAU8825_SOFTWARE_ID_NAU8825) {
  2337. dev_err(dev, "Not a NAU8825 chip\n");
  2338. return -ENODEV;
  2339. }
  2340. nau8825_init_regs(nau8825);
  2341. if (i2c->irq)
  2342. nau8825_setup_irq(nau8825);
  2343. return devm_snd_soc_register_component(&i2c->dev,
  2344. &nau8825_component_driver,
  2345. &nau8825_dai, 1);
  2346. }
  2347. static int nau8825_i2c_remove(struct i2c_client *client)
  2348. {
  2349. return 0;
  2350. }
  2351. static const struct i2c_device_id nau8825_i2c_ids[] = {
  2352. { "nau8825", 0 },
  2353. { }
  2354. };
  2355. MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
  2356. #ifdef CONFIG_OF
  2357. static const struct of_device_id nau8825_of_ids[] = {
  2358. { .compatible = "nuvoton,nau8825", },
  2359. {}
  2360. };
  2361. MODULE_DEVICE_TABLE(of, nau8825_of_ids);
  2362. #endif
  2363. #ifdef CONFIG_ACPI
  2364. static const struct acpi_device_id nau8825_acpi_match[] = {
  2365. { "10508825", 0 },
  2366. {},
  2367. };
  2368. MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
  2369. #endif
  2370. static struct i2c_driver nau8825_driver = {
  2371. .driver = {
  2372. .name = "nau8825",
  2373. .of_match_table = of_match_ptr(nau8825_of_ids),
  2374. .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
  2375. },
  2376. .probe = nau8825_i2c_probe,
  2377. .remove = nau8825_i2c_remove,
  2378. .id_table = nau8825_i2c_ids,
  2379. };
  2380. module_i2c_driver(nau8825_driver);
  2381. MODULE_DESCRIPTION("ASoC nau8825 driver");
  2382. MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
  2383. MODULE_LICENSE("GPL");