nau8824.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * NAU88L24 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Nuvoton Technology Corp.
  6. * Author: John Hsu <KCHSU0@nuvoton.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmi.h>
  11. #include <linux/init.h>
  12. #include <linux/i2c.h>
  13. #include <linux/regmap.h>
  14. #include <linux/slab.h>
  15. #include <linux/clk.h>
  16. #include <linux/acpi.h>
  17. #include <linux/math64.h>
  18. #include <linux/semaphore.h>
  19. #include <sound/initval.h>
  20. #include <sound/tlv.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/jack.h>
  26. #include "nau8824.h"
  27. #define NAU8824_JD_ACTIVE_HIGH BIT(0)
  28. static int nau8824_quirk;
  29. static int quirk_override = -1;
  30. module_param_named(quirk, quirk_override, uint, 0444);
  31. MODULE_PARM_DESC(quirk, "Board-specific quirk override");
  32. static int nau8824_config_sysclk(struct nau8824 *nau8824,
  33. int clk_id, unsigned int freq);
  34. static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
  35. /* the ADC threshold of headset */
  36. #define DMIC_CLK 3072000
  37. /* the ADC threshold of headset */
  38. #define HEADSET_SARADC_THD 0x80
  39. /* the parameter threshold of FLL */
  40. #define NAU_FREF_MAX 13500000
  41. #define NAU_FVCO_MAX 100000000
  42. #define NAU_FVCO_MIN 90000000
  43. /* scaling for mclk from sysclk_src output */
  44. static const struct nau8824_fll_attr mclk_src_scaling[] = {
  45. { 1, 0x0 },
  46. { 2, 0x2 },
  47. { 4, 0x3 },
  48. { 8, 0x4 },
  49. { 16, 0x5 },
  50. { 32, 0x6 },
  51. { 3, 0x7 },
  52. { 6, 0xa },
  53. { 12, 0xb },
  54. { 24, 0xc },
  55. };
  56. /* ratio for input clk freq */
  57. static const struct nau8824_fll_attr fll_ratio[] = {
  58. { 512000, 0x01 },
  59. { 256000, 0x02 },
  60. { 128000, 0x04 },
  61. { 64000, 0x08 },
  62. { 32000, 0x10 },
  63. { 8000, 0x20 },
  64. { 4000, 0x40 },
  65. };
  66. static const struct nau8824_fll_attr fll_pre_scalar[] = {
  67. { 1, 0x0 },
  68. { 2, 0x1 },
  69. { 4, 0x2 },
  70. { 8, 0x3 },
  71. };
  72. /* the maximum frequency of CLK_ADC and CLK_DAC */
  73. #define CLK_DA_AD_MAX 6144000
  74. /* over sampling rate */
  75. static const struct nau8824_osr_attr osr_dac_sel[] = {
  76. { 64, 2 }, /* OSR 64, SRC 1/4 */
  77. { 256, 0 }, /* OSR 256, SRC 1 */
  78. { 128, 1 }, /* OSR 128, SRC 1/2 */
  79. { 0, 0 },
  80. { 32, 3 }, /* OSR 32, SRC 1/8 */
  81. };
  82. static const struct nau8824_osr_attr osr_adc_sel[] = {
  83. { 32, 3 }, /* OSR 32, SRC 1/8 */
  84. { 64, 2 }, /* OSR 64, SRC 1/4 */
  85. { 128, 1 }, /* OSR 128, SRC 1/2 */
  86. { 256, 0 }, /* OSR 256, SRC 1 */
  87. };
  88. static const struct reg_default nau8824_reg_defaults[] = {
  89. { NAU8824_REG_ENA_CTRL, 0x0000 },
  90. { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
  91. { NAU8824_REG_CLK_DIVIDER, 0x0000 },
  92. { NAU8824_REG_FLL1, 0x0000 },
  93. { NAU8824_REG_FLL2, 0x3126 },
  94. { NAU8824_REG_FLL3, 0x0008 },
  95. { NAU8824_REG_FLL4, 0x0010 },
  96. { NAU8824_REG_FLL5, 0xC000 },
  97. { NAU8824_REG_FLL6, 0x6000 },
  98. { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
  99. { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
  100. { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
  101. { NAU8824_REG_IRQ, 0x0000 },
  102. { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
  103. { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
  104. { NAU8824_REG_SAR_ADC, 0x0015 },
  105. { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
  106. { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
  107. { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
  108. { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
  109. { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
  110. { NAU8824_REG_GPIO_SEL, 0x0000 },
  111. { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
  112. { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
  113. { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
  114. { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
  115. { NAU8824_REG_TDM_CTRL, 0x0000 },
  116. { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
  117. { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
  118. { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
  119. { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
  120. { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
  121. { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
  122. { NAU8824_REG_EQ1_LOW, 0x112C },
  123. { NAU8824_REG_EQ2_EQ3, 0x2C2C },
  124. { NAU8824_REG_EQ4_EQ5, 0x2C2C },
  125. { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
  126. { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
  127. { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
  128. { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
  129. { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
  130. { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
  131. { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
  132. { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
  133. { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
  134. { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
  135. { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
  136. { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
  137. { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
  138. { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
  139. { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
  140. { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
  141. { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
  142. { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
  143. { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
  144. { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
  145. { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
  146. { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
  147. { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
  148. { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
  149. { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
  150. { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
  151. { NAU8824_REG_MODE, 0x0000 },
  152. { NAU8824_REG_MODE1, 0x0000 },
  153. { NAU8824_REG_MODE2, 0x0000 },
  154. { NAU8824_REG_CLASSG, 0x0000 },
  155. { NAU8824_REG_OTP_EFUSE, 0x0000 },
  156. { NAU8824_REG_OTPDOUT_1, 0x0000 },
  157. { NAU8824_REG_OTPDOUT_2, 0x0000 },
  158. { NAU8824_REG_MISC_CTRL, 0x0000 },
  159. { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
  160. { NAU8824_REG_TEST_MODE, 0x0000 },
  161. { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
  162. { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
  163. { NAU8824_REG_BIAS_ADJ, 0x0000 },
  164. { NAU8824_REG_PGA_GAIN, 0x0000 },
  165. { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
  166. { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
  167. { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
  168. { NAU8824_REG_ENABLE_LO, 0x0000 },
  169. { NAU8824_REG_GAIN_LO, 0x0000 },
  170. { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
  171. { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
  172. { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
  173. { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
  174. { NAU8824_REG_RDAC, 0x0008 },
  175. { NAU8824_REG_MIC_BIAS, 0x0006 },
  176. { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
  177. { NAU8824_REG_BOOST, 0x0000 },
  178. { NAU8824_REG_FEPGA, 0x0000 },
  179. { NAU8824_REG_FEPGA_II, 0x0000 },
  180. { NAU8824_REG_FEPGA_SE, 0x0000 },
  181. { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
  182. { NAU8824_REG_ATT_PORT0, 0x0000 },
  183. { NAU8824_REG_ATT_PORT1, 0x0000 },
  184. { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
  185. { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
  186. { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
  187. };
  188. static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
  189. {
  190. int ret;
  191. if (timeout) {
  192. ret = down_timeout(&nau8824->jd_sem, timeout);
  193. if (ret < 0)
  194. dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
  195. } else {
  196. ret = down_interruptible(&nau8824->jd_sem);
  197. if (ret < 0)
  198. dev_warn(nau8824->dev, "Acquire semaphore fail\n");
  199. }
  200. return ret;
  201. }
  202. static inline void nau8824_sema_release(struct nau8824 *nau8824)
  203. {
  204. up(&nau8824->jd_sem);
  205. }
  206. static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
  207. {
  208. switch (reg) {
  209. case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
  210. case NAU8824_REG_JACK_DET_CTRL:
  211. case NAU8824_REG_INTERRUPT_SETTING_1:
  212. case NAU8824_REG_IRQ:
  213. case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
  214. case NAU8824_REG_GPIO_SEL:
  215. case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
  216. case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
  217. case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
  218. case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
  219. case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
  220. case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
  221. case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
  222. case NAU8824_REG_I2C_TIMEOUT:
  223. case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
  224. case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
  225. case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
  226. case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
  227. return true;
  228. default:
  229. return false;
  230. }
  231. }
  232. static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
  233. {
  234. switch (reg) {
  235. case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
  236. case NAU8824_REG_JACK_DET_CTRL:
  237. case NAU8824_REG_INTERRUPT_SETTING_1:
  238. case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
  239. case NAU8824_REG_GPIO_SEL:
  240. case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
  241. case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
  242. case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
  243. case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
  244. case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
  245. case NAU8824_REG_DRC_SLOPE_ADC_CH01:
  246. case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
  247. case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
  248. case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
  249. case NAU8824_REG_DRC_SLOPE_ADC_CH23:
  250. case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
  251. case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
  252. case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
  253. case NAU8824_REG_I2C_TIMEOUT:
  254. case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
  255. case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
  256. case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
  257. return true;
  258. default:
  259. return false;
  260. }
  261. }
  262. static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
  263. {
  264. switch (reg) {
  265. case NAU8824_REG_RESET:
  266. case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
  267. case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
  268. case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
  269. case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
  270. case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
  271. case NAU8824_REG_CHARGE_PUMP_INPUT:
  272. return true;
  273. default:
  274. return false;
  275. }
  276. }
  277. static const char * const nau8824_companding[] = {
  278. "Off", "NC", "u-law", "A-law" };
  279. static const struct soc_enum nau8824_companding_adc_enum =
  280. SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
  281. ARRAY_SIZE(nau8824_companding), nau8824_companding);
  282. static const struct soc_enum nau8824_companding_dac_enum =
  283. SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
  284. ARRAY_SIZE(nau8824_companding), nau8824_companding);
  285. static const char * const nau8824_adc_decimation[] = {
  286. "32", "64", "128", "256" };
  287. static const struct soc_enum nau8824_adc_decimation_enum =
  288. SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
  289. ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
  290. static const char * const nau8824_dac_oversampl[] = {
  291. "64", "256", "128", "", "32" };
  292. static const struct soc_enum nau8824_dac_oversampl_enum =
  293. SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
  294. ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
  295. static const char * const nau8824_input_channel[] = {
  296. "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
  297. static const struct soc_enum nau8824_adc_ch0_enum =
  298. SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
  299. ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
  300. static const struct soc_enum nau8824_adc_ch1_enum =
  301. SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
  302. ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
  303. static const struct soc_enum nau8824_adc_ch2_enum =
  304. SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
  305. ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
  306. static const struct soc_enum nau8824_adc_ch3_enum =
  307. SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
  308. ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
  309. static const char * const nau8824_tdm_slot[] = {
  310. "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
  311. static const struct soc_enum nau8824_dac_left_sel_enum =
  312. SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
  313. ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
  314. static const struct soc_enum nau8824_dac_right_sel_enum =
  315. SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
  316. ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
  317. static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
  318. static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
  319. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
  320. static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
  321. static const struct snd_kcontrol_new nau8824_snd_controls[] = {
  322. SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
  323. SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
  324. SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
  325. SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
  326. SOC_SINGLE_TLV("Speaker Right DACR Volume",
  327. NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
  328. SOC_SINGLE_TLV("Speaker Left DACL Volume",
  329. NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
  330. SOC_SINGLE_TLV("Speaker Left DACR Volume",
  331. NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
  332. SOC_SINGLE_TLV("Speaker Right DACL Volume",
  333. NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
  334. SOC_SINGLE_TLV("Headphone Right DACR Volume",
  335. NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
  336. SOC_SINGLE_TLV("Headphone Left DACL Volume",
  337. NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
  338. SOC_SINGLE_TLV("Headphone Right DACL Volume",
  339. NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
  340. SOC_SINGLE_TLV("Headphone Left DACR Volume",
  341. NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
  342. SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
  343. NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
  344. SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
  345. NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
  346. SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
  347. 0, 0x164, 0, dmic_vol_tlv),
  348. SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
  349. 0, 0x164, 0, dmic_vol_tlv),
  350. SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
  351. 0, 0x164, 0, dmic_vol_tlv),
  352. SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
  353. 0, 0x164, 0, dmic_vol_tlv),
  354. SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
  355. SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
  356. SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
  357. SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
  358. SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
  359. SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
  360. SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
  361. SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
  362. SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
  363. SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
  364. SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
  365. SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
  366. SOC_SINGLE("THD for key media",
  367. NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
  368. SOC_SINGLE("THD for key voice command",
  369. NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
  370. SOC_SINGLE("THD for key volume up",
  371. NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
  372. SOC_SINGLE("THD for key volume down",
  373. NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
  374. };
  375. static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
  376. struct snd_kcontrol *kcontrol, int event)
  377. {
  378. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  379. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  380. switch (event) {
  381. case SND_SOC_DAPM_PRE_PMU:
  382. /* Disables the TESTDAC to let DAC signal pass through. */
  383. regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
  384. NAU8824_TEST_DAC_EN, 0);
  385. break;
  386. case SND_SOC_DAPM_POST_PMD:
  387. regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
  388. NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
  389. break;
  390. default:
  391. return -EINVAL;
  392. }
  393. return 0;
  394. }
  395. static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
  396. struct snd_kcontrol *kcontrol, int event)
  397. {
  398. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  399. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  400. switch (event) {
  401. case SND_SOC_DAPM_PRE_PMU:
  402. regmap_update_bits(nau8824->regmap,
  403. NAU8824_REG_ANALOG_CONTROL_2,
  404. NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
  405. break;
  406. case SND_SOC_DAPM_POST_PMD:
  407. regmap_update_bits(nau8824->regmap,
  408. NAU8824_REG_ANALOG_CONTROL_2,
  409. NAU8824_CLASSD_CLAMP_DIS, 0);
  410. break;
  411. default:
  412. return -EINVAL;
  413. }
  414. return 0;
  415. }
  416. static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol, int event)
  418. {
  419. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  420. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  421. switch (event) {
  422. case SND_SOC_DAPM_POST_PMU:
  423. /* Prevent startup click by letting charge pump to ramp up */
  424. msleep(10);
  425. regmap_update_bits(nau8824->regmap,
  426. NAU8824_REG_CHARGE_PUMP_CONTROL,
  427. NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
  428. break;
  429. case SND_SOC_DAPM_PRE_PMD:
  430. regmap_update_bits(nau8824->regmap,
  431. NAU8824_REG_CHARGE_PUMP_CONTROL,
  432. NAU8824_JAMNODCLOW, 0);
  433. break;
  434. default:
  435. return -EINVAL;
  436. }
  437. return 0;
  438. }
  439. static int system_clock_control(struct snd_soc_dapm_widget *w,
  440. struct snd_kcontrol *k, int event)
  441. {
  442. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  443. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  444. struct regmap *regmap = nau8824->regmap;
  445. unsigned int value;
  446. bool clk_fll, error;
  447. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  448. dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
  449. /* Set clock source to disable or internal clock before the
  450. * playback or capture end. Codec needs clock for Jack
  451. * detection and button press if jack inserted; otherwise,
  452. * the clock should be closed.
  453. */
  454. if (nau8824_is_jack_inserted(nau8824)) {
  455. nau8824_config_sysclk(nau8824,
  456. NAU8824_CLK_INTERNAL, 0);
  457. } else {
  458. nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
  459. }
  460. } else {
  461. dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
  462. /* Check the clock source setting is proper or not
  463. * no matter the source is from FLL or MCLK.
  464. */
  465. regmap_read(regmap, NAU8824_REG_FLL1, &value);
  466. clk_fll = value & NAU8824_FLL_RATIO_MASK;
  467. /* It's error to use internal clock when playback */
  468. regmap_read(regmap, NAU8824_REG_FLL6, &value);
  469. error = value & NAU8824_DCO_EN;
  470. if (!error) {
  471. /* Check error depending on source is FLL or MCLK. */
  472. regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
  473. if (clk_fll)
  474. error = !(value & NAU8824_CLK_SRC_VCO);
  475. else
  476. error = value & NAU8824_CLK_SRC_VCO;
  477. }
  478. /* Recover the clock source setting if error. */
  479. if (error) {
  480. if (clk_fll) {
  481. regmap_update_bits(regmap,
  482. NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
  483. regmap_update_bits(regmap,
  484. NAU8824_REG_CLK_DIVIDER,
  485. NAU8824_CLK_SRC_MASK,
  486. NAU8824_CLK_SRC_VCO);
  487. } else {
  488. nau8824_config_sysclk(nau8824,
  489. NAU8824_CLK_MCLK, 0);
  490. }
  491. }
  492. }
  493. return 0;
  494. }
  495. static int dmic_clock_control(struct snd_soc_dapm_widget *w,
  496. struct snd_kcontrol *k, int event)
  497. {
  498. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  499. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  500. int src;
  501. /* The DMIC clock is gotten from system clock (256fs) divided by
  502. * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
  503. * less than 3.072 MHz.
  504. */
  505. for (src = 0; src < 5; src++) {
  506. if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
  507. break;
  508. }
  509. dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
  510. regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
  511. NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
  512. return 0;
  513. }
  514. static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
  515. SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
  516. NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
  517. static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
  518. SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
  519. NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
  520. static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
  521. SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
  522. NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
  523. static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
  524. SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
  525. NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
  526. static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
  527. SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
  528. NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
  529. SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
  530. NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
  531. };
  532. static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
  533. SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
  534. NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
  535. SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
  536. NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
  537. };
  538. static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
  539. SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
  540. NAU8824_DACR_HPL_EN_SFT, 1, 0),
  541. SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
  542. NAU8824_DACL_HPL_EN_SFT, 1, 0),
  543. };
  544. static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
  545. SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
  546. NAU8824_DACL_HPR_EN_SFT, 1, 0),
  547. SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
  548. NAU8824_DACR_HPR_EN_SFT, 1, 0),
  549. };
  550. static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
  551. static SOC_ENUM_SINGLE_DECL(
  552. nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
  553. NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
  554. static SOC_ENUM_SINGLE_DECL(
  555. nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
  556. NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
  557. static const struct snd_kcontrol_new nau8824_dacl_mux =
  558. SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
  559. static const struct snd_kcontrol_new nau8824_dacr_mux =
  560. SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
  561. static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
  562. SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
  563. system_clock_control, SND_SOC_DAPM_POST_PMD |
  564. SND_SOC_DAPM_POST_PMU),
  565. SND_SOC_DAPM_INPUT("HSMIC1"),
  566. SND_SOC_DAPM_INPUT("HSMIC2"),
  567. SND_SOC_DAPM_INPUT("MIC1"),
  568. SND_SOC_DAPM_INPUT("MIC2"),
  569. SND_SOC_DAPM_INPUT("DMIC1"),
  570. SND_SOC_DAPM_INPUT("DMIC2"),
  571. SND_SOC_DAPM_INPUT("DMIC3"),
  572. SND_SOC_DAPM_INPUT("DMIC4"),
  573. SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
  574. NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
  575. SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
  576. NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
  577. SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
  578. NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
  579. SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
  580. NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
  581. SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
  582. dmic_clock_control, SND_SOC_DAPM_POST_PMU),
  583. SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
  584. 0, 0, &nau8824_adc_ch0_dmic),
  585. SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
  586. 0, 0, &nau8824_adc_ch1_dmic),
  587. SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
  588. 0, 0, &nau8824_adc_ch2_dmic),
  589. SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
  590. 0, 0, &nau8824_adc_ch3_dmic),
  591. SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
  592. 12, 0, nau8824_adc_left_mixer,
  593. ARRAY_SIZE(nau8824_adc_left_mixer)),
  594. SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
  595. 13, 0, nau8824_adc_right_mixer,
  596. ARRAY_SIZE(nau8824_adc_right_mixer)),
  597. SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
  598. NAU8824_ADCL_EN_SFT, 0),
  599. SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
  600. NAU8824_ADCR_EN_SFT, 0),
  601. SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
  602. SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
  603. SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
  604. NAU8824_DACL_EN_SFT, 0),
  605. SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
  606. NAU8824_DACL_CLK_SFT, 0, NULL, 0),
  607. SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
  608. NAU8824_DACR_EN_SFT, 0),
  609. SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
  610. NAU8824_DACR_CLK_SFT, 0, NULL, 0),
  611. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
  612. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
  613. SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
  614. 8, 1, nau8824_output_dac_event,
  615. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  616. SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
  617. 9, 1, nau8824_output_dac_event,
  618. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  619. SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
  620. NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
  621. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  622. SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
  623. NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
  624. ARRAY_SIZE(nau8824_hp_left_mixer)),
  625. SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
  626. NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
  627. ARRAY_SIZE(nau8824_hp_right_mixer)),
  628. SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
  629. NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
  630. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  631. SND_SOC_DAPM_PGA("Output Driver L",
  632. NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
  633. SND_SOC_DAPM_PGA("Output Driver R",
  634. NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
  635. SND_SOC_DAPM_PGA("Main Driver L",
  636. NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
  637. SND_SOC_DAPM_PGA("Main Driver R",
  638. NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
  639. SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
  640. NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
  641. SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
  642. NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
  643. SND_SOC_DAPM_OUTPUT("SPKOUTL"),
  644. SND_SOC_DAPM_OUTPUT("SPKOUTR"),
  645. SND_SOC_DAPM_OUTPUT("HPOL"),
  646. SND_SOC_DAPM_OUTPUT("HPOR"),
  647. };
  648. static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
  649. {"DMIC1 Enable", "Switch", "DMIC1"},
  650. {"DMIC2 Enable", "Switch", "DMIC2"},
  651. {"DMIC3 Enable", "Switch", "DMIC3"},
  652. {"DMIC4 Enable", "Switch", "DMIC4"},
  653. {"DMIC1", NULL, "DMIC12 Power"},
  654. {"DMIC2", NULL, "DMIC12 Power"},
  655. {"DMIC3", NULL, "DMIC34 Power"},
  656. {"DMIC4", NULL, "DMIC34 Power"},
  657. {"DMIC12 Power", NULL, "DMIC Clock"},
  658. {"DMIC34 Power", NULL, "DMIC Clock"},
  659. {"Left ADC", "MIC Switch", "MIC1"},
  660. {"Left ADC", "HSMIC Switch", "HSMIC1"},
  661. {"Right ADC", "MIC Switch", "MIC2"},
  662. {"Right ADC", "HSMIC Switch", "HSMIC2"},
  663. {"ADCL", NULL, "Left ADC"},
  664. {"ADCR", NULL, "Right ADC"},
  665. {"AIFTX", NULL, "MICBIAS"},
  666. {"AIFTX", NULL, "ADCL"},
  667. {"AIFTX", NULL, "ADCR"},
  668. {"AIFTX", NULL, "DMIC1 Enable"},
  669. {"AIFTX", NULL, "DMIC2 Enable"},
  670. {"AIFTX", NULL, "DMIC3 Enable"},
  671. {"AIFTX", NULL, "DMIC4 Enable"},
  672. {"AIFTX", NULL, "System Clock"},
  673. {"AIFRX", NULL, "System Clock"},
  674. {"DACL", NULL, "AIFRX"},
  675. {"DACL", NULL, "DACL Clock"},
  676. {"DACR", NULL, "AIFRX"},
  677. {"DACR", NULL, "DACR Clock"},
  678. {"DACL Mux", "DACL", "DACL"},
  679. {"DACL Mux", "DACR", "DACR"},
  680. {"DACR Mux", "DACL", "DACL"},
  681. {"DACR Mux", "DACR", "DACR"},
  682. {"Output DACL", NULL, "DACL Mux"},
  683. {"Output DACR", NULL, "DACR Mux"},
  684. {"ClassD", NULL, "Output DACL"},
  685. {"ClassD", NULL, "Output DACR"},
  686. {"Left Headphone", "DAC Left Switch", "Output DACL"},
  687. {"Left Headphone", "DAC Right Switch", "Output DACR"},
  688. {"Right Headphone", "DAC Left Switch", "Output DACL"},
  689. {"Right Headphone", "DAC Right Switch", "Output DACR"},
  690. {"Charge Pump", NULL, "Left Headphone"},
  691. {"Charge Pump", NULL, "Right Headphone"},
  692. {"Output Driver L", NULL, "Charge Pump"},
  693. {"Output Driver R", NULL, "Charge Pump"},
  694. {"Main Driver L", NULL, "Output Driver L"},
  695. {"Main Driver R", NULL, "Output Driver R"},
  696. {"Class G", NULL, "Main Driver L"},
  697. {"Class G", NULL, "Main Driver R"},
  698. {"HP Boost Driver", NULL, "Class G"},
  699. {"SPKOUTL", NULL, "ClassD"},
  700. {"SPKOUTR", NULL, "ClassD"},
  701. {"HPOL", NULL, "HP Boost Driver"},
  702. {"HPOR", NULL, "HP Boost Driver"},
  703. };
  704. static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
  705. {
  706. struct snd_soc_jack *jack = nau8824->jack;
  707. bool insert = false;
  708. if (nau8824->irq && jack)
  709. insert = jack->status & SND_JACK_HEADPHONE;
  710. return insert;
  711. }
  712. static void nau8824_int_status_clear_all(struct regmap *regmap)
  713. {
  714. int active_irq, clear_irq, i;
  715. /* Reset the intrruption status from rightmost bit if the corres-
  716. * ponding irq event occurs.
  717. */
  718. regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
  719. for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
  720. clear_irq = (0x1 << i);
  721. if (active_irq & clear_irq)
  722. regmap_write(regmap,
  723. NAU8824_REG_CLEAR_INT_REG, clear_irq);
  724. }
  725. }
  726. static void nau8824_dapm_disable_pin(struct nau8824 *nau8824, const char *pin)
  727. {
  728. struct snd_soc_dapm_context *dapm = nau8824->dapm;
  729. const char *prefix = dapm->component->name_prefix;
  730. char prefixed_pin[80];
  731. if (prefix) {
  732. snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
  733. prefix, pin);
  734. snd_soc_dapm_disable_pin(dapm, prefixed_pin);
  735. } else {
  736. snd_soc_dapm_disable_pin(dapm, pin);
  737. }
  738. }
  739. static void nau8824_dapm_enable_pin(struct nau8824 *nau8824, const char *pin)
  740. {
  741. struct snd_soc_dapm_context *dapm = nau8824->dapm;
  742. const char *prefix = dapm->component->name_prefix;
  743. char prefixed_pin[80];
  744. if (prefix) {
  745. snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s",
  746. prefix, pin);
  747. snd_soc_dapm_force_enable_pin(dapm, prefixed_pin);
  748. } else {
  749. snd_soc_dapm_force_enable_pin(dapm, pin);
  750. }
  751. }
  752. static void nau8824_eject_jack(struct nau8824 *nau8824)
  753. {
  754. struct snd_soc_dapm_context *dapm = nau8824->dapm;
  755. struct regmap *regmap = nau8824->regmap;
  756. /* Clear all interruption status */
  757. nau8824_int_status_clear_all(regmap);
  758. nau8824_dapm_disable_pin(nau8824, "SAR");
  759. nau8824_dapm_disable_pin(nau8824, "MICBIAS");
  760. snd_soc_dapm_sync(dapm);
  761. /* Enable the insertion interruption, disable the ejection
  762. * interruption, and then bypass de-bounce circuit.
  763. */
  764. regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
  765. NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
  766. NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
  767. NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
  768. NAU8824_IRQ_EJECT_DIS);
  769. regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
  770. NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
  771. NAU8824_IRQ_INSERT_EN);
  772. regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
  773. NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
  774. /* Close clock for jack type detection at manual mode */
  775. if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
  776. nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
  777. }
  778. static void nau8824_jdet_work(struct work_struct *work)
  779. {
  780. struct nau8824 *nau8824 = container_of(
  781. work, struct nau8824, jdet_work);
  782. struct snd_soc_dapm_context *dapm = nau8824->dapm;
  783. struct regmap *regmap = nau8824->regmap;
  784. int adc_value, event = 0, event_mask = 0;
  785. nau8824_dapm_enable_pin(nau8824, "MICBIAS");
  786. nau8824_dapm_enable_pin(nau8824, "SAR");
  787. snd_soc_dapm_sync(dapm);
  788. msleep(100);
  789. regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
  790. adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
  791. dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
  792. if (adc_value < HEADSET_SARADC_THD) {
  793. event |= SND_JACK_HEADPHONE;
  794. nau8824_dapm_disable_pin(nau8824, "SAR");
  795. nau8824_dapm_disable_pin(nau8824, "MICBIAS");
  796. snd_soc_dapm_sync(dapm);
  797. } else {
  798. event |= SND_JACK_HEADSET;
  799. }
  800. event_mask |= SND_JACK_HEADSET;
  801. snd_soc_jack_report(nau8824->jack, event, event_mask);
  802. /* Enable short key press and release interruption. */
  803. regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
  804. NAU8824_IRQ_KEY_RELEASE_DIS |
  805. NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
  806. nau8824_sema_release(nau8824);
  807. }
  808. static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
  809. {
  810. struct regmap *regmap = nau8824->regmap;
  811. /* Enable jack ejection interruption. */
  812. regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
  813. NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
  814. NAU8824_IRQ_EJECT_EN);
  815. regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
  816. NAU8824_IRQ_EJECT_DIS, 0);
  817. /* Enable internal VCO needed for interruptions */
  818. if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
  819. nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
  820. regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
  821. NAU8824_JD_SLEEP_MODE, 0);
  822. }
  823. static int nau8824_button_decode(int value)
  824. {
  825. int buttons = 0;
  826. /* The chip supports up to 8 buttons, but ALSA defines
  827. * only 6 buttons.
  828. */
  829. if (value & BIT(0))
  830. buttons |= SND_JACK_BTN_0;
  831. if (value & BIT(1))
  832. buttons |= SND_JACK_BTN_1;
  833. if (value & BIT(2))
  834. buttons |= SND_JACK_BTN_2;
  835. if (value & BIT(3))
  836. buttons |= SND_JACK_BTN_3;
  837. if (value & BIT(4))
  838. buttons |= SND_JACK_BTN_4;
  839. if (value & BIT(5))
  840. buttons |= SND_JACK_BTN_5;
  841. return buttons;
  842. }
  843. #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
  844. SND_JACK_BTN_2 | SND_JACK_BTN_3)
  845. static irqreturn_t nau8824_interrupt(int irq, void *data)
  846. {
  847. struct nau8824 *nau8824 = (struct nau8824 *)data;
  848. struct regmap *regmap = nau8824->regmap;
  849. int active_irq, clear_irq = 0, event = 0, event_mask = 0;
  850. if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
  851. dev_err(nau8824->dev, "failed to read irq status\n");
  852. return IRQ_NONE;
  853. }
  854. dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
  855. if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
  856. nau8824_eject_jack(nau8824);
  857. event_mask |= SND_JACK_HEADSET;
  858. clear_irq = NAU8824_JACK_EJECTION_DETECTED;
  859. /* release semaphore held after resume,
  860. * and cancel jack detection
  861. */
  862. nau8824_sema_release(nau8824);
  863. cancel_work_sync(&nau8824->jdet_work);
  864. } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
  865. int key_status, button_pressed;
  866. regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
  867. &key_status);
  868. /* lower 8 bits of the register are for pressed keys */
  869. button_pressed = nau8824_button_decode(key_status);
  870. event |= button_pressed;
  871. dev_dbg(nau8824->dev, "button %x pressed\n", event);
  872. event_mask |= NAU8824_BUTTONS;
  873. clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
  874. } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
  875. event_mask = NAU8824_BUTTONS;
  876. clear_irq = NAU8824_KEY_RELEASE_IRQ;
  877. } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
  878. /* Turn off insertion interruption at manual mode */
  879. regmap_update_bits(regmap,
  880. NAU8824_REG_INTERRUPT_SETTING,
  881. NAU8824_IRQ_INSERT_DIS,
  882. NAU8824_IRQ_INSERT_DIS);
  883. regmap_update_bits(regmap,
  884. NAU8824_REG_INTERRUPT_SETTING_1,
  885. NAU8824_IRQ_INSERT_EN, 0);
  886. /* detect microphone and jack type */
  887. cancel_work_sync(&nau8824->jdet_work);
  888. schedule_work(&nau8824->jdet_work);
  889. /* Enable interruption for jack type detection at audo
  890. * mode which can detect microphone and jack type.
  891. */
  892. nau8824_setup_auto_irq(nau8824);
  893. }
  894. if (!clear_irq)
  895. clear_irq = active_irq;
  896. /* clears the rightmost interruption */
  897. regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
  898. if (event_mask)
  899. snd_soc_jack_report(nau8824->jack, event, event_mask);
  900. return IRQ_HANDLED;
  901. }
  902. static int nau8824_clock_check(struct nau8824 *nau8824,
  903. int stream, int rate, int osr)
  904. {
  905. int osrate;
  906. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  907. if (osr >= ARRAY_SIZE(osr_dac_sel))
  908. return -EINVAL;
  909. osrate = osr_dac_sel[osr].osr;
  910. } else {
  911. if (osr >= ARRAY_SIZE(osr_adc_sel))
  912. return -EINVAL;
  913. osrate = osr_adc_sel[osr].osr;
  914. }
  915. if (!osrate || rate * osr > CLK_DA_AD_MAX) {
  916. dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
  917. return -EINVAL;
  918. }
  919. return 0;
  920. }
  921. static int nau8824_hw_params(struct snd_pcm_substream *substream,
  922. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  923. {
  924. struct snd_soc_component *component = dai->component;
  925. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  926. unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
  927. nau8824_sema_acquire(nau8824, HZ);
  928. /* CLK_DAC or CLK_ADC = OSR * FS
  929. * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
  930. * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
  931. * values must be selected such that the maximum frequency is less
  932. * than 6.144 MHz.
  933. */
  934. nau8824->fs = params_rate(params);
  935. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  936. regmap_read(nau8824->regmap,
  937. NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
  938. osr &= NAU8824_DAC_OVERSAMPLE_MASK;
  939. if (nau8824_clock_check(nau8824, substream->stream,
  940. nau8824->fs, osr))
  941. return -EINVAL;
  942. regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
  943. NAU8824_CLK_DAC_SRC_MASK,
  944. osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT);
  945. } else {
  946. regmap_read(nau8824->regmap,
  947. NAU8824_REG_ADC_FILTER_CTRL, &osr);
  948. osr &= NAU8824_ADC_SYNC_DOWN_MASK;
  949. if (nau8824_clock_check(nau8824, substream->stream,
  950. nau8824->fs, osr))
  951. return -EINVAL;
  952. regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
  953. NAU8824_CLK_ADC_SRC_MASK,
  954. osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT);
  955. }
  956. /* make BCLK and LRC divde configuration if the codec as master. */
  957. regmap_read(nau8824->regmap,
  958. NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
  959. if (ctrl_val & NAU8824_I2S_MS_MASTER) {
  960. /* get the bclk and fs ratio */
  961. bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
  962. if (bclk_fs <= 32)
  963. bclk_div = 0x3;
  964. else if (bclk_fs <= 64)
  965. bclk_div = 0x2;
  966. else if (bclk_fs <= 128)
  967. bclk_div = 0x1;
  968. else if (bclk_fs <= 256)
  969. bclk_div = 0;
  970. else
  971. return -EINVAL;
  972. regmap_update_bits(nau8824->regmap,
  973. NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
  974. NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
  975. (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
  976. }
  977. switch (params_width(params)) {
  978. case 16:
  979. val_len |= NAU8824_I2S_DL_16;
  980. break;
  981. case 20:
  982. val_len |= NAU8824_I2S_DL_20;
  983. break;
  984. case 24:
  985. val_len |= NAU8824_I2S_DL_24;
  986. break;
  987. case 32:
  988. val_len |= NAU8824_I2S_DL_32;
  989. break;
  990. default:
  991. return -EINVAL;
  992. }
  993. regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
  994. NAU8824_I2S_DL_MASK, val_len);
  995. nau8824_sema_release(nau8824);
  996. return 0;
  997. }
  998. static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  999. {
  1000. struct snd_soc_component *component = dai->component;
  1001. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1002. unsigned int ctrl1_val = 0, ctrl2_val = 0;
  1003. nau8824_sema_acquire(nau8824, HZ);
  1004. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1005. case SND_SOC_DAIFMT_CBM_CFM:
  1006. ctrl2_val |= NAU8824_I2S_MS_MASTER;
  1007. break;
  1008. case SND_SOC_DAIFMT_CBS_CFS:
  1009. break;
  1010. default:
  1011. return -EINVAL;
  1012. }
  1013. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1014. case SND_SOC_DAIFMT_NB_NF:
  1015. break;
  1016. case SND_SOC_DAIFMT_IB_NF:
  1017. ctrl1_val |= NAU8824_I2S_BP_INV;
  1018. break;
  1019. default:
  1020. return -EINVAL;
  1021. }
  1022. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1023. case SND_SOC_DAIFMT_I2S:
  1024. ctrl1_val |= NAU8824_I2S_DF_I2S;
  1025. break;
  1026. case SND_SOC_DAIFMT_LEFT_J:
  1027. ctrl1_val |= NAU8824_I2S_DF_LEFT;
  1028. break;
  1029. case SND_SOC_DAIFMT_RIGHT_J:
  1030. ctrl1_val |= NAU8824_I2S_DF_RIGTH;
  1031. break;
  1032. case SND_SOC_DAIFMT_DSP_A:
  1033. ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
  1034. break;
  1035. case SND_SOC_DAIFMT_DSP_B:
  1036. ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
  1037. ctrl1_val |= NAU8824_I2S_PCMB_EN;
  1038. break;
  1039. default:
  1040. return -EINVAL;
  1041. }
  1042. regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
  1043. NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
  1044. NAU8824_I2S_PCMB_EN, ctrl1_val);
  1045. regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
  1046. NAU8824_I2S_MS_MASK, ctrl2_val);
  1047. nau8824_sema_release(nau8824);
  1048. return 0;
  1049. }
  1050. /**
  1051. * nau8824_set_tdm_slot - configure DAI TDM.
  1052. * @dai: DAI
  1053. * @tx_mask: Bitmask representing active TX slots. Ex.
  1054. * 0xf for normal 4 channel TDM.
  1055. * 0xf0 for shifted 4 channel TDM
  1056. * @rx_mask: Bitmask [0:1] representing active DACR RX slots.
  1057. * Bitmask [2:3] representing active DACL RX slots.
  1058. * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
  1059. * 0xf for DACL/R selecting TDM CH3.
  1060. * 0xf0 for DACL/R selecting shifted TDM CH3.
  1061. * @slots: Number of slots in use.
  1062. * @slot_width: Width in bits for each slot.
  1063. *
  1064. * Configures a DAI for TDM operation. Only support 4 slots TDM.
  1065. */
  1066. static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
  1067. unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
  1068. {
  1069. struct snd_soc_component *component = dai->component;
  1070. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1071. unsigned int tslot_l = 0, ctrl_val = 0;
  1072. if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
  1073. ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
  1074. ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
  1075. ((rx_mask & 0xf) && (tx_mask & 0xf0)))
  1076. return -EINVAL;
  1077. ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
  1078. if (tx_mask & 0xf0) {
  1079. tslot_l = 4 * slot_width;
  1080. ctrl_val |= (tx_mask >> 4);
  1081. } else {
  1082. ctrl_val |= tx_mask;
  1083. }
  1084. if (rx_mask & 0xf0)
  1085. ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
  1086. else
  1087. ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
  1088. regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
  1089. NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
  1090. NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
  1091. NAU8824_TDM_TX_MASK, ctrl_val);
  1092. regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
  1093. NAU8824_TSLOT_L_MASK, tslot_l);
  1094. return 0;
  1095. }
  1096. /**
  1097. * nau8824_calc_fll_param - Calculate FLL parameters.
  1098. * @fll_in: external clock provided to codec.
  1099. * @fs: sampling rate.
  1100. * @fll_param: Pointer to structure of FLL parameters.
  1101. *
  1102. * Calculate FLL parameters to configure codec.
  1103. *
  1104. * Returns 0 for success or negative error code.
  1105. */
  1106. static int nau8824_calc_fll_param(unsigned int fll_in,
  1107. unsigned int fs, struct nau8824_fll *fll_param)
  1108. {
  1109. u64 fvco, fvco_max;
  1110. unsigned int fref, i, fvco_sel;
  1111. /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
  1112. * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
  1113. * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
  1114. */
  1115. for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
  1116. fref = fll_in / fll_pre_scalar[i].param;
  1117. if (fref <= NAU_FREF_MAX)
  1118. break;
  1119. }
  1120. if (i == ARRAY_SIZE(fll_pre_scalar))
  1121. return -EINVAL;
  1122. fll_param->clk_ref_div = fll_pre_scalar[i].val;
  1123. /* Choose the FLL ratio based on FREF */
  1124. for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
  1125. if (fref >= fll_ratio[i].param)
  1126. break;
  1127. }
  1128. if (i == ARRAY_SIZE(fll_ratio))
  1129. return -EINVAL;
  1130. fll_param->ratio = fll_ratio[i].val;
  1131. /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
  1132. * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
  1133. * guaranteed across the full range of operation.
  1134. * FDCO = freq_out * 2 * mclk_src_scaling
  1135. */
  1136. fvco_max = 0;
  1137. fvco_sel = ARRAY_SIZE(mclk_src_scaling);
  1138. for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
  1139. fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
  1140. if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
  1141. fvco_max < fvco) {
  1142. fvco_max = fvco;
  1143. fvco_sel = i;
  1144. }
  1145. }
  1146. if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
  1147. return -EINVAL;
  1148. fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
  1149. /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
  1150. * input based on FDCO, FREF and FLL ratio.
  1151. */
  1152. fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
  1153. fll_param->fll_int = (fvco >> 16) & 0x3FF;
  1154. fll_param->fll_frac = fvco & 0xFFFF;
  1155. return 0;
  1156. }
  1157. static void nau8824_fll_apply(struct regmap *regmap,
  1158. struct nau8824_fll *fll_param)
  1159. {
  1160. regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
  1161. NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
  1162. NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
  1163. regmap_update_bits(regmap, NAU8824_REG_FLL1,
  1164. NAU8824_FLL_RATIO_MASK, fll_param->ratio);
  1165. /* FLL 16-bit fractional input */
  1166. regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
  1167. /* FLL 10-bit integer input */
  1168. regmap_update_bits(regmap, NAU8824_REG_FLL3,
  1169. NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
  1170. /* FLL pre-scaler */
  1171. regmap_update_bits(regmap, NAU8824_REG_FLL4,
  1172. NAU8824_FLL_REF_DIV_MASK,
  1173. fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
  1174. /* select divided VCO input */
  1175. regmap_update_bits(regmap, NAU8824_REG_FLL5,
  1176. NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
  1177. /* Disable free-running mode */
  1178. regmap_update_bits(regmap,
  1179. NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
  1180. if (fll_param->fll_frac) {
  1181. regmap_update_bits(regmap, NAU8824_REG_FLL5,
  1182. NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
  1183. NAU8824_FLL_FTR_SW_MASK,
  1184. NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
  1185. NAU8824_FLL_FTR_SW_FILTER);
  1186. regmap_update_bits(regmap, NAU8824_REG_FLL6,
  1187. NAU8824_SDM_EN, NAU8824_SDM_EN);
  1188. } else {
  1189. regmap_update_bits(regmap, NAU8824_REG_FLL5,
  1190. NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
  1191. NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
  1192. regmap_update_bits(regmap,
  1193. NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
  1194. }
  1195. }
  1196. /* freq_out must be 256*Fs in order to achieve the best performance */
  1197. static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
  1198. unsigned int freq_in, unsigned int freq_out)
  1199. {
  1200. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1201. struct nau8824_fll fll_param;
  1202. int ret, fs;
  1203. fs = freq_out / 256;
  1204. ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
  1205. if (ret < 0) {
  1206. dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
  1207. return ret;
  1208. }
  1209. dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
  1210. fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
  1211. fll_param.fll_int, fll_param.clk_ref_div);
  1212. nau8824_fll_apply(nau8824->regmap, &fll_param);
  1213. mdelay(2);
  1214. regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
  1215. NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
  1216. return 0;
  1217. }
  1218. static int nau8824_config_sysclk(struct nau8824 *nau8824,
  1219. int clk_id, unsigned int freq)
  1220. {
  1221. struct regmap *regmap = nau8824->regmap;
  1222. switch (clk_id) {
  1223. case NAU8824_CLK_DIS:
  1224. regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
  1225. NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
  1226. regmap_update_bits(regmap, NAU8824_REG_FLL6,
  1227. NAU8824_DCO_EN, 0);
  1228. break;
  1229. case NAU8824_CLK_MCLK:
  1230. nau8824_sema_acquire(nau8824, HZ);
  1231. regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
  1232. NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
  1233. regmap_update_bits(regmap, NAU8824_REG_FLL6,
  1234. NAU8824_DCO_EN, 0);
  1235. nau8824_sema_release(nau8824);
  1236. break;
  1237. case NAU8824_CLK_INTERNAL:
  1238. regmap_update_bits(regmap, NAU8824_REG_FLL6,
  1239. NAU8824_DCO_EN, NAU8824_DCO_EN);
  1240. regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
  1241. NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
  1242. break;
  1243. case NAU8824_CLK_FLL_MCLK:
  1244. nau8824_sema_acquire(nau8824, HZ);
  1245. regmap_update_bits(regmap, NAU8824_REG_FLL3,
  1246. NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
  1247. nau8824_sema_release(nau8824);
  1248. break;
  1249. case NAU8824_CLK_FLL_BLK:
  1250. nau8824_sema_acquire(nau8824, HZ);
  1251. regmap_update_bits(regmap, NAU8824_REG_FLL3,
  1252. NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
  1253. nau8824_sema_release(nau8824);
  1254. break;
  1255. case NAU8824_CLK_FLL_FS:
  1256. nau8824_sema_acquire(nau8824, HZ);
  1257. regmap_update_bits(regmap, NAU8824_REG_FLL3,
  1258. NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
  1259. nau8824_sema_release(nau8824);
  1260. break;
  1261. default:
  1262. dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
  1263. return -EINVAL;
  1264. }
  1265. dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
  1266. clk_id);
  1267. return 0;
  1268. }
  1269. static int nau8824_set_sysclk(struct snd_soc_component *component,
  1270. int clk_id, int source, unsigned int freq, int dir)
  1271. {
  1272. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1273. return nau8824_config_sysclk(nau8824, clk_id, freq);
  1274. }
  1275. static void nau8824_resume_setup(struct nau8824 *nau8824)
  1276. {
  1277. nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
  1278. if (nau8824->irq) {
  1279. /* Clear all interruption status */
  1280. nau8824_int_status_clear_all(nau8824->regmap);
  1281. /* Enable jack detection at sleep mode, insertion detection,
  1282. * and ejection detection.
  1283. */
  1284. regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
  1285. NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
  1286. regmap_update_bits(nau8824->regmap,
  1287. NAU8824_REG_INTERRUPT_SETTING_1,
  1288. NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
  1289. NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
  1290. regmap_update_bits(nau8824->regmap,
  1291. NAU8824_REG_INTERRUPT_SETTING,
  1292. NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
  1293. }
  1294. }
  1295. static int nau8824_set_bias_level(struct snd_soc_component *component,
  1296. enum snd_soc_bias_level level)
  1297. {
  1298. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1299. switch (level) {
  1300. case SND_SOC_BIAS_ON:
  1301. break;
  1302. case SND_SOC_BIAS_PREPARE:
  1303. break;
  1304. case SND_SOC_BIAS_STANDBY:
  1305. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1306. /* Setup codec configuration after resume */
  1307. nau8824_resume_setup(nau8824);
  1308. }
  1309. break;
  1310. case SND_SOC_BIAS_OFF:
  1311. regmap_update_bits(nau8824->regmap,
  1312. NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
  1313. regmap_update_bits(nau8824->regmap,
  1314. NAU8824_REG_INTERRUPT_SETTING_1,
  1315. NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
  1316. break;
  1317. }
  1318. return 0;
  1319. }
  1320. static int nau8824_component_probe(struct snd_soc_component *component)
  1321. {
  1322. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1323. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1324. nau8824->dapm = dapm;
  1325. return 0;
  1326. }
  1327. static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
  1328. {
  1329. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1330. if (nau8824->irq) {
  1331. disable_irq(nau8824->irq);
  1332. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  1333. }
  1334. regcache_cache_only(nau8824->regmap, true);
  1335. regcache_mark_dirty(nau8824->regmap);
  1336. return 0;
  1337. }
  1338. static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
  1339. {
  1340. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1341. regcache_cache_only(nau8824->regmap, false);
  1342. regcache_sync(nau8824->regmap);
  1343. if (nau8824->irq) {
  1344. /* Hold semaphore to postpone playback happening
  1345. * until jack detection done.
  1346. */
  1347. nau8824_sema_acquire(nau8824, 0);
  1348. enable_irq(nau8824->irq);
  1349. }
  1350. return 0;
  1351. }
  1352. static const struct snd_soc_component_driver nau8824_component_driver = {
  1353. .probe = nau8824_component_probe,
  1354. .set_sysclk = nau8824_set_sysclk,
  1355. .set_pll = nau8824_set_pll,
  1356. .set_bias_level = nau8824_set_bias_level,
  1357. .suspend = nau8824_suspend,
  1358. .resume = nau8824_resume,
  1359. .controls = nau8824_snd_controls,
  1360. .num_controls = ARRAY_SIZE(nau8824_snd_controls),
  1361. .dapm_widgets = nau8824_dapm_widgets,
  1362. .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
  1363. .dapm_routes = nau8824_dapm_routes,
  1364. .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
  1365. .suspend_bias_off = 1,
  1366. .idle_bias_on = 1,
  1367. .use_pmdown_time = 1,
  1368. .endianness = 1,
  1369. .non_legacy_dai_naming = 1,
  1370. };
  1371. static const struct snd_soc_dai_ops nau8824_dai_ops = {
  1372. .hw_params = nau8824_hw_params,
  1373. .set_fmt = nau8824_set_fmt,
  1374. .set_tdm_slot = nau8824_set_tdm_slot,
  1375. };
  1376. #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
  1377. #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
  1378. | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  1379. static struct snd_soc_dai_driver nau8824_dai = {
  1380. .name = NAU8824_CODEC_DAI,
  1381. .playback = {
  1382. .stream_name = "Playback",
  1383. .channels_min = 1,
  1384. .channels_max = 2,
  1385. .rates = NAU8824_RATES,
  1386. .formats = NAU8824_FORMATS,
  1387. },
  1388. .capture = {
  1389. .stream_name = "Capture",
  1390. .channels_min = 1,
  1391. .channels_max = 2,
  1392. .rates = NAU8824_RATES,
  1393. .formats = NAU8824_FORMATS,
  1394. },
  1395. .ops = &nau8824_dai_ops,
  1396. };
  1397. static const struct regmap_config nau8824_regmap_config = {
  1398. .val_bits = NAU8824_REG_ADDR_LEN,
  1399. .reg_bits = NAU8824_REG_DATA_LEN,
  1400. .max_register = NAU8824_REG_MAX,
  1401. .readable_reg = nau8824_readable_reg,
  1402. .writeable_reg = nau8824_writeable_reg,
  1403. .volatile_reg = nau8824_volatile_reg,
  1404. .cache_type = REGCACHE_RBTREE,
  1405. .reg_defaults = nau8824_reg_defaults,
  1406. .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
  1407. };
  1408. /**
  1409. * nau8824_enable_jack_detect - Specify a jack for event reporting
  1410. *
  1411. * @component: component to register the jack with
  1412. * @jack: jack to use to report headset and button events on
  1413. *
  1414. * After this function has been called the headset insert/remove and button
  1415. * events will be routed to the given jack. Jack can be null to stop
  1416. * reporting.
  1417. */
  1418. int nau8824_enable_jack_detect(struct snd_soc_component *component,
  1419. struct snd_soc_jack *jack)
  1420. {
  1421. struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
  1422. int ret;
  1423. nau8824->jack = jack;
  1424. /* Initiate jack detection work queue */
  1425. INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
  1426. ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
  1427. nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  1428. "nau8824", nau8824);
  1429. if (ret) {
  1430. dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
  1431. nau8824->irq, ret);
  1432. }
  1433. return ret;
  1434. }
  1435. EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
  1436. static void nau8824_reset_chip(struct regmap *regmap)
  1437. {
  1438. regmap_write(regmap, NAU8824_REG_RESET, 0x00);
  1439. regmap_write(regmap, NAU8824_REG_RESET, 0x00);
  1440. }
  1441. static void nau8824_setup_buttons(struct nau8824 *nau8824)
  1442. {
  1443. struct regmap *regmap = nau8824->regmap;
  1444. regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
  1445. NAU8824_SAR_TRACKING_GAIN_MASK,
  1446. nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
  1447. regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
  1448. NAU8824_SAR_COMPARE_TIME_MASK,
  1449. nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
  1450. regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
  1451. NAU8824_SAR_SAMPLING_TIME_MASK,
  1452. nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
  1453. regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
  1454. NAU8824_LEVELS_NR_MASK,
  1455. (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
  1456. regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
  1457. NAU8824_HYSTERESIS_MASK,
  1458. nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
  1459. regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
  1460. NAU8824_SHORTKEY_DEBOUNCE_MASK,
  1461. nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
  1462. regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
  1463. (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
  1464. regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
  1465. (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
  1466. regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
  1467. (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
  1468. regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
  1469. (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
  1470. }
  1471. static void nau8824_init_regs(struct nau8824 *nau8824)
  1472. {
  1473. struct regmap *regmap = nau8824->regmap;
  1474. /* Enable Bias/VMID/VMID Tieoff */
  1475. regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
  1476. NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
  1477. (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
  1478. regmap_update_bits(regmap, NAU8824_REG_BOOST,
  1479. NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
  1480. mdelay(2);
  1481. regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
  1482. NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
  1483. /* Disable Boost Driver, Automatic Short circuit protection enable */
  1484. regmap_update_bits(regmap, NAU8824_REG_BOOST,
  1485. NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
  1486. NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
  1487. NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
  1488. NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
  1489. /* Scaling for ADC and DAC clock */
  1490. regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
  1491. NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
  1492. (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
  1493. (0x1 << NAU8824_CLK_DAC_SRC_SFT));
  1494. regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
  1495. NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
  1496. regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
  1497. NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
  1498. NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
  1499. NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
  1500. NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
  1501. NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
  1502. NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
  1503. regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
  1504. NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
  1505. NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
  1506. NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
  1507. NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
  1508. NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
  1509. NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
  1510. NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
  1511. NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
  1512. /* Class G timer 64ms */
  1513. regmap_update_bits(regmap, NAU8824_REG_CLASSG,
  1514. NAU8824_CLASSG_TIMER_MASK,
  1515. 0x20 << NAU8824_CLASSG_TIMER_SFT);
  1516. regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
  1517. NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
  1518. /* Disable DACR/L power */
  1519. regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
  1520. NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
  1521. NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
  1522. NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
  1523. NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
  1524. /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
  1525. * signal to avoid any glitches due to power up transients in both
  1526. * the analog and digital DAC circuit.
  1527. */
  1528. regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
  1529. NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
  1530. /* Config L/R channel */
  1531. regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
  1532. NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
  1533. regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
  1534. NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
  1535. regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
  1536. NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
  1537. NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
  1538. /* Default oversampling/decimations settings are unusable
  1539. * (audible hiss). Set it to something better.
  1540. */
  1541. regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
  1542. NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
  1543. regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
  1544. NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
  1545. NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
  1546. /* DAC clock delay 2ns, VREF */
  1547. regmap_update_bits(regmap, NAU8824_REG_RDAC,
  1548. NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
  1549. (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
  1550. (0x3 << NAU8824_RDAC_VREF_SFT));
  1551. /* PGA input mode selection */
  1552. regmap_update_bits(regmap, NAU8824_REG_FEPGA,
  1553. NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
  1554. NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
  1555. /* Digital microphone control */
  1556. regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
  1557. NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
  1558. NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
  1559. regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
  1560. NAU8824_JACK_LOGIC,
  1561. /* jkdet_polarity - 1 is for active-low */
  1562. nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
  1563. regmap_update_bits(regmap,
  1564. NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
  1565. (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
  1566. if (nau8824->sar_threshold_num)
  1567. nau8824_setup_buttons(nau8824);
  1568. }
  1569. static int nau8824_setup_irq(struct nau8824 *nau8824)
  1570. {
  1571. /* Disable interruption before codec initiation done */
  1572. regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
  1573. NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
  1574. regmap_update_bits(nau8824->regmap,
  1575. NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
  1576. regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
  1577. NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
  1578. return 0;
  1579. }
  1580. static void nau8824_print_device_properties(struct nau8824 *nau8824)
  1581. {
  1582. struct device *dev = nau8824->dev;
  1583. int i;
  1584. dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
  1585. dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
  1586. dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
  1587. dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
  1588. for (i = 0; i < nau8824->sar_threshold_num; i++)
  1589. dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
  1590. nau8824->sar_threshold[i]);
  1591. dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
  1592. dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
  1593. dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
  1594. dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
  1595. dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
  1596. dev_dbg(dev, "jack-eject-debounce: %d\n",
  1597. nau8824->jack_eject_debounce);
  1598. }
  1599. static int nau8824_read_device_properties(struct device *dev,
  1600. struct nau8824 *nau8824) {
  1601. int ret;
  1602. ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
  1603. &nau8824->jkdet_polarity);
  1604. if (ret)
  1605. nau8824->jkdet_polarity = 1;
  1606. ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
  1607. &nau8824->micbias_voltage);
  1608. if (ret)
  1609. nau8824->micbias_voltage = 6;
  1610. ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
  1611. &nau8824->vref_impedance);
  1612. if (ret)
  1613. nau8824->vref_impedance = 2;
  1614. ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
  1615. &nau8824->sar_threshold_num);
  1616. if (ret)
  1617. nau8824->sar_threshold_num = 4;
  1618. ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
  1619. nau8824->sar_threshold, nau8824->sar_threshold_num);
  1620. if (ret) {
  1621. nau8824->sar_threshold[0] = 0x0a;
  1622. nau8824->sar_threshold[1] = 0x14;
  1623. nau8824->sar_threshold[2] = 0x26;
  1624. nau8824->sar_threshold[3] = 0x73;
  1625. }
  1626. ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
  1627. &nau8824->sar_hysteresis);
  1628. if (ret)
  1629. nau8824->sar_hysteresis = 0;
  1630. ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
  1631. &nau8824->sar_voltage);
  1632. if (ret)
  1633. nau8824->sar_voltage = 6;
  1634. ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
  1635. &nau8824->sar_compare_time);
  1636. if (ret)
  1637. nau8824->sar_compare_time = 1;
  1638. ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
  1639. &nau8824->sar_sampling_time);
  1640. if (ret)
  1641. nau8824->sar_sampling_time = 1;
  1642. ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
  1643. &nau8824->key_debounce);
  1644. if (ret)
  1645. nau8824->key_debounce = 0;
  1646. ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
  1647. &nau8824->jack_eject_debounce);
  1648. if (ret)
  1649. nau8824->jack_eject_debounce = 1;
  1650. return 0;
  1651. }
  1652. /* Please keep this list alphabetically sorted */
  1653. static const struct dmi_system_id nau8824_quirk_table[] = {
  1654. {
  1655. /* Cyberbook T116 rugged tablet */
  1656. .matches = {
  1657. DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
  1658. DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
  1659. DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
  1660. },
  1661. .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
  1662. },
  1663. {}
  1664. };
  1665. static void nau8824_check_quirks(void)
  1666. {
  1667. const struct dmi_system_id *dmi_id;
  1668. if (quirk_override != -1) {
  1669. nau8824_quirk = quirk_override;
  1670. return;
  1671. }
  1672. dmi_id = dmi_first_match(nau8824_quirk_table);
  1673. if (dmi_id)
  1674. nau8824_quirk = (unsigned long)dmi_id->driver_data;
  1675. }
  1676. static int nau8824_i2c_probe(struct i2c_client *i2c,
  1677. const struct i2c_device_id *id)
  1678. {
  1679. struct device *dev = &i2c->dev;
  1680. struct nau8824 *nau8824 = dev_get_platdata(dev);
  1681. int ret, value;
  1682. if (!nau8824) {
  1683. nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
  1684. if (!nau8824)
  1685. return -ENOMEM;
  1686. ret = nau8824_read_device_properties(dev, nau8824);
  1687. if (ret)
  1688. return ret;
  1689. }
  1690. i2c_set_clientdata(i2c, nau8824);
  1691. nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
  1692. if (IS_ERR(nau8824->regmap))
  1693. return PTR_ERR(nau8824->regmap);
  1694. nau8824->dev = dev;
  1695. nau8824->irq = i2c->irq;
  1696. sema_init(&nau8824->jd_sem, 1);
  1697. nau8824_check_quirks();
  1698. if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
  1699. nau8824->jkdet_polarity = 0;
  1700. nau8824_print_device_properties(nau8824);
  1701. ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
  1702. if (ret < 0) {
  1703. dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
  1704. ret);
  1705. return ret;
  1706. }
  1707. nau8824_reset_chip(nau8824->regmap);
  1708. nau8824_init_regs(nau8824);
  1709. if (i2c->irq)
  1710. nau8824_setup_irq(nau8824);
  1711. return devm_snd_soc_register_component(dev,
  1712. &nau8824_component_driver, &nau8824_dai, 1);
  1713. }
  1714. static const struct i2c_device_id nau8824_i2c_ids[] = {
  1715. { "nau8824", 0 },
  1716. { }
  1717. };
  1718. MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
  1719. #ifdef CONFIG_OF
  1720. static const struct of_device_id nau8824_of_ids[] = {
  1721. { .compatible = "nuvoton,nau8824", },
  1722. {}
  1723. };
  1724. MODULE_DEVICE_TABLE(of, nau8824_of_ids);
  1725. #endif
  1726. #ifdef CONFIG_ACPI
  1727. static const struct acpi_device_id nau8824_acpi_match[] = {
  1728. { "10508824", 0 },
  1729. {},
  1730. };
  1731. MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
  1732. #endif
  1733. static struct i2c_driver nau8824_i2c_driver = {
  1734. .driver = {
  1735. .name = "nau8824",
  1736. .of_match_table = of_match_ptr(nau8824_of_ids),
  1737. .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
  1738. },
  1739. .probe = nau8824_i2c_probe,
  1740. .id_table = nau8824_i2c_ids,
  1741. };
  1742. module_i2c_driver(nau8824_i2c_driver);
  1743. MODULE_DESCRIPTION("ASoC NAU88L24 driver");
  1744. MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
  1745. MODULE_LICENSE("GPL v2");