nau8822.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * nau8822.h -- NAU8822 ALSA SoC Audio driver
  4. *
  5. * Copyright 2017 Nuvoton Technology Crop.
  6. *
  7. * Author: David Lin <ctlin0@nuvoton.com>
  8. * Co-author: John Hsu <kchsu0@nuvoton.com>
  9. * Co-author: Seven Li <wtli@nuvoton.com>
  10. */
  11. #ifndef __NAU8822_H__
  12. #define __NAU8822_H__
  13. #define NAU8822_REG_RESET 0x00
  14. #define NAU8822_REG_POWER_MANAGEMENT_1 0x01
  15. #define NAU8822_REG_POWER_MANAGEMENT_2 0x02
  16. #define NAU8822_REG_POWER_MANAGEMENT_3 0x03
  17. #define NAU8822_REG_AUDIO_INTERFACE 0x04
  18. #define NAU8822_REG_COMPANDING_CONTROL 0x05
  19. #define NAU8822_REG_CLOCKING 0x06
  20. #define NAU8822_REG_ADDITIONAL_CONTROL 0x07
  21. #define NAU8822_REG_GPIO_CONTROL 0x08
  22. #define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09
  23. #define NAU8822_REG_DAC_CONTROL 0x0A
  24. #define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B
  25. #define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C
  26. #define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D
  27. #define NAU8822_REG_ADC_CONTROL 0x0E
  28. #define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F
  29. #define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x10
  30. #define NAU8822_REG_EQ1 0x12
  31. #define NAU8822_REG_EQ2 0x13
  32. #define NAU8822_REG_EQ3 0x14
  33. #define NAU8822_REG_EQ4 0x15
  34. #define NAU8822_REG_EQ5 0x16
  35. #define NAU8822_REG_DAC_LIMITER_1 0x18
  36. #define NAU8822_REG_DAC_LIMITER_2 0x19
  37. #define NAU8822_REG_NOTCH_FILTER_1 0x1B
  38. #define NAU8822_REG_NOTCH_FILTER_2 0x1C
  39. #define NAU8822_REG_NOTCH_FILTER_3 0x1D
  40. #define NAU8822_REG_NOTCH_FILTER_4 0x1E
  41. #define NAU8822_REG_ALC_CONTROL_1 0x20
  42. #define NAU8822_REG_ALC_CONTROL_2 0x21
  43. #define NAU8822_REG_ALC_CONTROL_3 0x22
  44. #define NAU8822_REG_NOISE_GATE 0x23
  45. #define NAU8822_REG_PLL_N 0x24
  46. #define NAU8822_REG_PLL_K1 0x25
  47. #define NAU8822_REG_PLL_K2 0x26
  48. #define NAU8822_REG_PLL_K3 0x27
  49. #define NAU8822_REG_3D_CONTROL 0x29
  50. #define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B
  51. #define NAU8822_REG_INPUT_CONTROL 0x2C
  52. #define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D
  53. #define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E
  54. #define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F
  55. #define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30
  56. #define NAU8822_REG_OUTPUT_CONTROL 0x31
  57. #define NAU8822_REG_LEFT_MIXER_CONTROL 0x32
  58. #define NAU8822_REG_RIGHT_MIXER_CONTROL 0x33
  59. #define NAU8822_REG_LHP_VOLUME 0x34
  60. #define NAU8822_REG_RHP_VOLUME 0x35
  61. #define NAU8822_REG_LSPKOUT_VOLUME 0x36
  62. #define NAU8822_REG_RSPKOUT_VOLUME 0x37
  63. #define NAU8822_REG_AUX2_MIXER 0x38
  64. #define NAU8822_REG_AUX1_MIXER 0x39
  65. #define NAU8822_REG_POWER_MANAGEMENT_4 0x3A
  66. #define NAU8822_REG_LEFT_TIME_SLOT 0x3B
  67. #define NAU8822_REG_MISC 0x3C
  68. #define NAU8822_REG_RIGHT_TIME_SLOT 0x3D
  69. #define NAU8822_REG_DEVICE_REVISION 0x3E
  70. #define NAU8822_REG_DEVICE_ID 0x3F
  71. #define NAU8822_REG_DAC_DITHER 0x41
  72. #define NAU8822_REG_ALC_ENHANCE_1 0x46
  73. #define NAU8822_REG_ALC_ENHANCE_2 0x47
  74. #define NAU8822_REG_192KHZ_SAMPLING 0x48
  75. #define NAU8822_REG_MISC_CONTROL 0x49
  76. #define NAU8822_REG_INPUT_TIEOFF 0x4A
  77. #define NAU8822_REG_POWER_REDUCTION 0x4B
  78. #define NAU8822_REG_AGC_PEAK2PEAK 0x4C
  79. #define NAU8822_REG_AGC_PEAK_DETECT 0x4D
  80. #define NAU8822_REG_AUTOMUTE_CONTROL 0x4E
  81. #define NAU8822_REG_OUTPUT_TIEOFF 0x4F
  82. #define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF
  83. /* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
  84. #define NAU8822_REFIMP_MASK 0x3
  85. #define NAU8822_REFIMP_80K 0x1
  86. #define NAU8822_REFIMP_300K 0x2
  87. #define NAU8822_REFIMP_3K 0x3
  88. #define NAU8822_IOBUF_EN (0x1 << 2)
  89. #define NAU8822_ABIAS_EN (0x1 << 3)
  90. /* NAU8822_REG_AUDIO_INTERFACE (0x4) */
  91. #define NAU8822_AIFMT_MASK (0x3 << 3)
  92. #define NAU8822_WLEN_MASK (0x3 << 5)
  93. #define NAU8822_WLEN_20 (0x1 << 5)
  94. #define NAU8822_WLEN_24 (0x2 << 5)
  95. #define NAU8822_WLEN_32 (0x3 << 5)
  96. #define NAU8822_LRP_MASK (0x1 << 7)
  97. #define NAU8822_BCLKP_MASK (0x1 << 8)
  98. /* NAU8822_REG_COMPANDING_CONTROL (0x5) */
  99. #define NAU8822_ADDAP_SFT 0
  100. #define NAU8822_ADCCM_SFT 1
  101. #define NAU8822_DACCM_SFT 3
  102. /* NAU8822_REG_CLOCKING (0x6) */
  103. #define NAU8822_CLKIOEN_MASK 0x1
  104. #define NAU8822_CLK_MASTER 0x1
  105. #define NAU8822_CLK_SLAVE 0x0
  106. #define NAU8822_MCLKSEL_SFT 5
  107. #define NAU8822_MCLKSEL_MASK (0x7 << 5)
  108. #define NAU8822_BCLKSEL_SFT 2
  109. #define NAU8822_BCLKSEL_MASK (0x7 << 2)
  110. #define NAU8822_BCLKDIV_1 (0x0 << 2)
  111. #define NAU8822_BCLKDIV_2 (0x1 << 2)
  112. #define NAU8822_BCLKDIV_4 (0x2 << 2)
  113. #define NAU8822_BCLKDIV_8 (0x3 << 2)
  114. #define NAU8822_BCLKDIV_16 (0x4 << 2)
  115. #define NAU8822_CLKM_MASK (0x1 << 8)
  116. #define NAU8822_CLKM_MCLK (0x0 << 8)
  117. #define NAU8822_CLKM_PLL (0x1 << 8)
  118. /* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
  119. #define NAU8822_SMPLR_SFT 1
  120. #define NAU8822_SMPLR_MASK (0x7 << 1)
  121. #define NAU8822_SMPLR_48K (0x0 << 1)
  122. #define NAU8822_SMPLR_32K (0x1 << 1)
  123. #define NAU8822_SMPLR_24K (0x2 << 1)
  124. #define NAU8822_SMPLR_16K (0x3 << 1)
  125. #define NAU8822_SMPLR_12K (0x4 << 1)
  126. #define NAU8822_SMPLR_8K (0x5 << 1)
  127. /* NAU8822_REG_EQ1 (0x12) */
  128. #define NAU8822_EQ1GC_SFT 0
  129. #define NAU8822_EQ1CF_SFT 5
  130. #define NAU8822_EQM_SFT 8
  131. /* NAU8822_REG_EQ2 (0x13) */
  132. #define NAU8822_EQ2GC_SFT 0
  133. #define NAU8822_EQ2CF_SFT 5
  134. #define NAU8822_EQ2BW_SFT 8
  135. /* NAU8822_REG_EQ3 (0x14) */
  136. #define NAU8822_EQ3GC_SFT 0
  137. #define NAU8822_EQ3CF_SFT 5
  138. #define NAU8822_EQ3BW_SFT 8
  139. /* NAU8822_REG_EQ4 (0x15) */
  140. #define NAU8822_EQ4GC_SFT 0
  141. #define NAU8822_EQ4CF_SFT 5
  142. #define NAU8822_EQ4BW_SFT 8
  143. /* NAU8822_REG_EQ5 (0x16) */
  144. #define NAU8822_EQ5GC_SFT 0
  145. #define NAU8822_EQ5CF_SFT 5
  146. /* NAU8822_REG_ALC_CONTROL_1 (0x20) */
  147. #define NAU8822_ALCMINGAIN_SFT 0
  148. #define NAU8822_ALCMXGAIN_SFT 3
  149. #define NAU8822_ALCEN_SFT 7
  150. /* NAU8822_REG_ALC_CONTROL_2 (0x21) */
  151. #define NAU8822_ALCSL_SFT 0
  152. #define NAU8822_ALCHT_SFT 4
  153. /* NAU8822_REG_ALC_CONTROL_3 (0x22) */
  154. #define NAU8822_ALCATK_SFT 0
  155. #define NAU8822_ALCDCY_SFT 4
  156. #define NAU8822_ALCM_SFT 8
  157. /* NAU8822_REG_PLL_N (0x24) */
  158. #define NAU8822_PLLMCLK_DIV2 (0x1 << 4)
  159. #define NAU8822_PLLN_MASK 0xF
  160. #define NAU8822_PLLK1_SFT 18
  161. #define NAU8822_PLLK1_MASK 0x3F
  162. /* NAU8822_REG_PLL_K2 (0x26) */
  163. #define NAU8822_PLLK2_SFT 9
  164. #define NAU8822_PLLK2_MASK 0x1FF
  165. /* NAU8822_REG_PLL_K3 (0x27) */
  166. #define NAU8822_PLLK3_MASK 0x1FF
  167. /* System Clock Source */
  168. enum {
  169. NAU8822_CLK_MCLK,
  170. NAU8822_CLK_PLL,
  171. };
  172. struct nau8822_pll {
  173. int pre_factor;
  174. int mclk_scaler;
  175. int pll_frac;
  176. int pll_int;
  177. };
  178. /* Codec Private Data */
  179. struct nau8822 {
  180. struct device *dev;
  181. struct regmap *regmap;
  182. int mclk_idx;
  183. struct nau8822_pll pll;
  184. int sysclk;
  185. int div_id;
  186. };
  187. #endif /* __NAU8822_H__ */