nau8822.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // nau8822.c -- NAU8822 ALSA Soc Audio driver
  4. //
  5. // Copyright 2017 Nuvoton Technology Crop.
  6. //
  7. // Author: David Lin <ctlin0@nuvoton.com>
  8. // Co-author: John Hsu <kchsu0@nuvoton.com>
  9. // Co-author: Seven Li <wtli@nuvoton.com>
  10. //
  11. // Based on WM8974.c
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include <asm/div64.h>
  28. #include "nau8822.h"
  29. #define NAU_PLL_FREQ_MAX 100000000
  30. #define NAU_PLL_FREQ_MIN 90000000
  31. #define NAU_PLL_REF_MAX 33000000
  32. #define NAU_PLL_REF_MIN 8000000
  33. #define NAU_PLL_OPTOP_MIN 6
  34. static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
  35. static const struct reg_default nau8822_reg_defaults[] = {
  36. { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
  37. { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
  38. { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
  39. { NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
  40. { NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
  41. { NAU8822_REG_CLOCKING, 0x0140 },
  42. { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
  43. { NAU8822_REG_GPIO_CONTROL, 0x0000 },
  44. { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
  45. { NAU8822_REG_DAC_CONTROL, 0x0000 },
  46. { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
  47. { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
  48. { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
  49. { NAU8822_REG_ADC_CONTROL, 0x0100 },
  50. { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
  51. { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
  52. { NAU8822_REG_EQ1, 0x012c },
  53. { NAU8822_REG_EQ2, 0x002c },
  54. { NAU8822_REG_EQ3, 0x002c },
  55. { NAU8822_REG_EQ4, 0x002c },
  56. { NAU8822_REG_EQ5, 0x002c },
  57. { NAU8822_REG_DAC_LIMITER_1, 0x0032 },
  58. { NAU8822_REG_DAC_LIMITER_2, 0x0000 },
  59. { NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
  60. { NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
  61. { NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
  62. { NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
  63. { NAU8822_REG_ALC_CONTROL_1, 0x0038 },
  64. { NAU8822_REG_ALC_CONTROL_2, 0x000b },
  65. { NAU8822_REG_ALC_CONTROL_3, 0x0032 },
  66. { NAU8822_REG_NOISE_GATE, 0x0010 },
  67. { NAU8822_REG_PLL_N, 0x0008 },
  68. { NAU8822_REG_PLL_K1, 0x000c },
  69. { NAU8822_REG_PLL_K2, 0x0093 },
  70. { NAU8822_REG_PLL_K3, 0x00e9 },
  71. { NAU8822_REG_3D_CONTROL, 0x0000 },
  72. { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
  73. { NAU8822_REG_INPUT_CONTROL, 0x0033 },
  74. { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
  75. { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
  76. { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
  77. { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
  78. { NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
  79. { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
  80. { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
  81. { NAU8822_REG_LHP_VOLUME, 0x0039 },
  82. { NAU8822_REG_RHP_VOLUME, 0x0039 },
  83. { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
  84. { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
  85. { NAU8822_REG_AUX2_MIXER, 0x0001 },
  86. { NAU8822_REG_AUX1_MIXER, 0x0001 },
  87. { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
  88. { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
  89. { NAU8822_REG_MISC, 0x0020 },
  90. { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
  91. { NAU8822_REG_DEVICE_REVISION, 0x007f },
  92. { NAU8822_REG_DEVICE_ID, 0x001a },
  93. { NAU8822_REG_DAC_DITHER, 0x0114 },
  94. { NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
  95. { NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
  96. { NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
  97. { NAU8822_REG_MISC_CONTROL, 0x0000 },
  98. { NAU8822_REG_INPUT_TIEOFF, 0x0000 },
  99. { NAU8822_REG_POWER_REDUCTION, 0x0000 },
  100. { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
  101. { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
  102. { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
  103. { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
  104. };
  105. static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
  106. {
  107. switch (reg) {
  108. case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
  109. case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
  110. case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
  111. case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
  112. case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
  113. case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
  114. case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
  115. case NAU8822_REG_3D_CONTROL:
  116. case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
  117. case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
  118. case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
  119. case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
  120. case NAU8822_REG_DAC_DITHER:
  121. case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
  122. case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
  123. return true;
  124. default:
  125. return false;
  126. }
  127. }
  128. static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
  129. {
  130. switch (reg) {
  131. case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
  132. case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
  133. case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
  134. case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
  135. case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
  136. case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
  137. case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
  138. case NAU8822_REG_3D_CONTROL:
  139. case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
  140. case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
  141. case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
  142. case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
  143. case NAU8822_REG_DAC_DITHER:
  144. case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
  145. case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
  146. return true;
  147. default:
  148. return false;
  149. }
  150. }
  151. static bool nau8822_volatile(struct device *dev, unsigned int reg)
  152. {
  153. switch (reg) {
  154. case NAU8822_REG_RESET:
  155. case NAU8822_REG_DEVICE_REVISION:
  156. case NAU8822_REG_DEVICE_ID:
  157. case NAU8822_REG_AGC_PEAK2PEAK:
  158. case NAU8822_REG_AGC_PEAK_DETECT:
  159. case NAU8822_REG_AUTOMUTE_CONTROL:
  160. return true;
  161. default:
  162. return false;
  163. }
  164. }
  165. /* The EQ parameters get function is to get the 5 band equalizer control.
  166. * The regmap raw read can't work here because regmap doesn't provide
  167. * value format for value width of 9 bits. Therefore, the driver reads data
  168. * from cache and makes value format according to the endianness of
  169. * bytes type control element.
  170. */
  171. static int nau8822_eq_get(struct snd_kcontrol *kcontrol,
  172. struct snd_ctl_elem_value *ucontrol)
  173. {
  174. struct snd_soc_component *component =
  175. snd_soc_kcontrol_component(kcontrol);
  176. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  177. int i, reg;
  178. u16 reg_val, *val;
  179. val = (u16 *)ucontrol->value.bytes.data;
  180. reg = NAU8822_REG_EQ1;
  181. for (i = 0; i < params->max / sizeof(u16); i++) {
  182. reg_val = snd_soc_component_read(component, reg + i);
  183. /* conversion of 16-bit integers between native CPU format
  184. * and big endian format
  185. */
  186. reg_val = cpu_to_be16(reg_val);
  187. memcpy(val + i, &reg_val, sizeof(reg_val));
  188. }
  189. return 0;
  190. }
  191. /* The EQ parameters put function is to make configuration of 5 band equalizer
  192. * control. These configuration includes central frequency, equalizer gain,
  193. * cut-off frequency, bandwidth control, and equalizer path.
  194. * The regmap raw write can't work here because regmap doesn't provide
  195. * register and value format for register with address 7 bits and value 9 bits.
  196. * Therefore, the driver makes value format according to the endianness of
  197. * bytes type control element and writes data to codec.
  198. */
  199. static int nau8822_eq_put(struct snd_kcontrol *kcontrol,
  200. struct snd_ctl_elem_value *ucontrol)
  201. {
  202. struct snd_soc_component *component =
  203. snd_soc_kcontrol_component(kcontrol);
  204. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  205. void *data;
  206. u16 *val, value;
  207. int i, reg, ret;
  208. data = kmemdup(ucontrol->value.bytes.data,
  209. params->max, GFP_KERNEL | GFP_DMA);
  210. if (!data)
  211. return -ENOMEM;
  212. val = (u16 *)data;
  213. reg = NAU8822_REG_EQ1;
  214. for (i = 0; i < params->max / sizeof(u16); i++) {
  215. /* conversion of 16-bit integers between native CPU format
  216. * and big endian format
  217. */
  218. value = be16_to_cpu(*(val + i));
  219. ret = snd_soc_component_write(component, reg + i, value);
  220. if (ret) {
  221. dev_err(component->dev,
  222. "EQ configuration fail, register: %x ret: %d\n",
  223. reg + i, ret);
  224. kfree(data);
  225. return ret;
  226. }
  227. }
  228. kfree(data);
  229. return 0;
  230. }
  231. static const char * const nau8822_companding[] = {
  232. "Off", "NC", "u-law", "A-law"};
  233. static const struct soc_enum nau8822_companding_adc_enum =
  234. SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT,
  235. ARRAY_SIZE(nau8822_companding), nau8822_companding);
  236. static const struct soc_enum nau8822_companding_dac_enum =
  237. SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT,
  238. ARRAY_SIZE(nau8822_companding), nau8822_companding);
  239. static const char * const nau8822_eqmode[] = {"Capture", "Playback"};
  240. static const struct soc_enum nau8822_eqmode_enum =
  241. SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT,
  242. ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode);
  243. static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
  244. static const char * const nau8822_alc3[] = {"Normal", "Limiter"};
  245. static const struct soc_enum nau8822_alc_enable_enum =
  246. SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT,
  247. ARRAY_SIZE(nau8822_alc1), nau8822_alc1);
  248. static const struct soc_enum nau8822_alc_mode_enum =
  249. SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT,
  250. ARRAY_SIZE(nau8822_alc3), nau8822_alc3);
  251. static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  252. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
  253. static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
  254. static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
  255. static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
  256. static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
  257. static const struct snd_kcontrol_new nau8822_snd_controls[] = {
  258. SOC_ENUM("ADC Companding", nau8822_companding_adc_enum),
  259. SOC_ENUM("DAC Companding", nau8822_companding_dac_enum),
  260. SOC_ENUM("EQ Function", nau8822_eqmode_enum),
  261. SND_SOC_BYTES_EXT("EQ Parameters", 10,
  262. nau8822_eq_get, nau8822_eq_put),
  263. SOC_DOUBLE("DAC Inversion Switch",
  264. NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
  265. SOC_DOUBLE_R_TLV("PCM Volume",
  266. NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
  267. NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
  268. SOC_SINGLE("High Pass Filter Switch",
  269. NAU8822_REG_ADC_CONTROL, 8, 1, 0),
  270. SOC_SINGLE("High Pass Cut Off",
  271. NAU8822_REG_ADC_CONTROL, 4, 7, 0),
  272. SOC_DOUBLE("ADC Inversion Switch",
  273. NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
  274. SOC_DOUBLE_R_TLV("ADC Volume",
  275. NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
  276. NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
  277. SOC_SINGLE("DAC Limiter Switch",
  278. NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
  279. SOC_SINGLE("DAC Limiter Decay",
  280. NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
  281. SOC_SINGLE("DAC Limiter Attack",
  282. NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
  283. SOC_SINGLE("DAC Limiter Threshold",
  284. NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
  285. SOC_SINGLE_TLV("DAC Limiter Volume",
  286. NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
  287. SOC_ENUM("ALC Mode", nau8822_alc_mode_enum),
  288. SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum),
  289. SOC_SINGLE("ALC Min Gain",
  290. NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
  291. SOC_SINGLE("ALC Max Gain",
  292. NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
  293. SOC_SINGLE("ALC Hold",
  294. NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
  295. SOC_SINGLE("ALC Target",
  296. NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
  297. SOC_SINGLE("ALC Decay",
  298. NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
  299. SOC_SINGLE("ALC Attack",
  300. NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
  301. SOC_SINGLE("ALC Noise Gate Switch",
  302. NAU8822_REG_NOISE_GATE, 3, 1, 0),
  303. SOC_SINGLE("ALC Noise Gate Threshold",
  304. NAU8822_REG_NOISE_GATE, 0, 7, 0),
  305. SOC_DOUBLE_R("PGA ZC Switch",
  306. NAU8822_REG_LEFT_INP_PGA_CONTROL,
  307. NAU8822_REG_RIGHT_INP_PGA_CONTROL,
  308. 7, 1, 0),
  309. SOC_DOUBLE_R_TLV("PGA Volume",
  310. NAU8822_REG_LEFT_INP_PGA_CONTROL,
  311. NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv),
  312. SOC_DOUBLE_R("Headphone ZC Switch",
  313. NAU8822_REG_LHP_VOLUME,
  314. NAU8822_REG_RHP_VOLUME, 7, 1, 0),
  315. SOC_DOUBLE_R("Headphone Playback Switch",
  316. NAU8822_REG_LHP_VOLUME,
  317. NAU8822_REG_RHP_VOLUME, 6, 1, 1),
  318. SOC_DOUBLE_R_TLV("Headphone Volume",
  319. NAU8822_REG_LHP_VOLUME,
  320. NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv),
  321. SOC_DOUBLE_R("Speaker ZC Switch",
  322. NAU8822_REG_LSPKOUT_VOLUME,
  323. NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
  324. SOC_DOUBLE_R("Speaker Playback Switch",
  325. NAU8822_REG_LSPKOUT_VOLUME,
  326. NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
  327. SOC_DOUBLE_R_TLV("Speaker Volume",
  328. NAU8822_REG_LSPKOUT_VOLUME,
  329. NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv),
  330. SOC_DOUBLE_R("AUXOUT Playback Switch",
  331. NAU8822_REG_AUX2_MIXER,
  332. NAU8822_REG_AUX1_MIXER, 6, 1, 1),
  333. SOC_DOUBLE_R_TLV("PGA Boost Volume",
  334. NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
  335. NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv),
  336. SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
  337. NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
  338. NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv),
  339. SOC_DOUBLE_R_TLV("Aux Boost Volume",
  340. NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
  341. NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv),
  342. SOC_SINGLE("DAC 128x Oversampling Switch",
  343. NAU8822_REG_DAC_CONTROL, 5, 1, 0),
  344. SOC_SINGLE("ADC 128x Oversampling Switch",
  345. NAU8822_REG_ADC_CONTROL, 5, 1, 0),
  346. };
  347. /* LMAIN and RMAIN Mixer */
  348. static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
  349. SOC_DAPM_SINGLE("LINMIX Switch",
  350. NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
  351. SOC_DAPM_SINGLE("LAUX Switch",
  352. NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
  353. SOC_DAPM_SINGLE("LDAC Switch",
  354. NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
  355. SOC_DAPM_SINGLE("RDAC Switch",
  356. NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
  357. };
  358. static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
  359. SOC_DAPM_SINGLE("RINMIX Switch",
  360. NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
  361. SOC_DAPM_SINGLE("RAUX Switch",
  362. NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
  363. SOC_DAPM_SINGLE("RDAC Switch",
  364. NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
  365. SOC_DAPM_SINGLE("LDAC Switch",
  366. NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
  367. };
  368. /* AUX1 and AUX2 Mixer */
  369. static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
  370. SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
  371. SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
  372. SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
  373. SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
  374. SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
  375. };
  376. static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
  377. SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
  378. SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
  379. SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
  380. SOC_DAPM_SINGLE("AUX1MIX Output Switch",
  381. NAU8822_REG_AUX2_MIXER, 3, 1, 0),
  382. };
  383. /* Input PGA */
  384. static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
  385. SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
  386. SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
  387. SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
  388. };
  389. static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
  390. SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
  391. SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
  392. SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
  393. };
  394. /* Loopback Switch */
  395. static const struct snd_kcontrol_new nau8822_loopback =
  396. SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL,
  397. NAU8822_ADDAP_SFT, 1, 0);
  398. static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
  399. struct snd_soc_dapm_widget *sink)
  400. {
  401. struct snd_soc_component *component =
  402. snd_soc_dapm_to_component(source->dapm);
  403. unsigned int value;
  404. value = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
  405. return (value & NAU8822_CLKM_MASK);
  406. }
  407. static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
  408. SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
  409. NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
  410. SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
  411. NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
  412. SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
  413. NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
  414. SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
  415. NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
  416. SOC_MIXER_ARRAY("Left Output Mixer",
  417. NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer),
  418. SOC_MIXER_ARRAY("Right Output Mixer",
  419. NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer),
  420. SOC_MIXER_ARRAY("AUX1 Output Mixer",
  421. NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer),
  422. SOC_MIXER_ARRAY("AUX2 Output Mixer",
  423. NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer),
  424. SOC_MIXER_ARRAY("Left Input Mixer",
  425. NAU8822_REG_POWER_MANAGEMENT_2,
  426. 2, 0, nau8822_left_input_mixer),
  427. SOC_MIXER_ARRAY("Right Input Mixer",
  428. NAU8822_REG_POWER_MANAGEMENT_2,
  429. 3, 0, nau8822_right_input_mixer),
  430. SND_SOC_DAPM_PGA("Left Boost Mixer",
  431. NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
  432. SND_SOC_DAPM_PGA("Right Boost Mixer",
  433. NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
  434. SND_SOC_DAPM_PGA("Left Capture PGA",
  435. NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0),
  436. SND_SOC_DAPM_PGA("Right Capture PGA",
  437. NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0),
  438. SND_SOC_DAPM_PGA("Left Headphone Out",
  439. NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
  440. SND_SOC_DAPM_PGA("Right Headphone Out",
  441. NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0),
  442. SND_SOC_DAPM_PGA("Left Speaker Out",
  443. NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
  444. SND_SOC_DAPM_PGA("Right Speaker Out",
  445. NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0),
  446. SND_SOC_DAPM_PGA("AUX1 Out",
  447. NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
  448. SND_SOC_DAPM_PGA("AUX2 Out",
  449. NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
  450. SND_SOC_DAPM_SUPPLY("Mic Bias",
  451. NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
  452. SND_SOC_DAPM_SUPPLY("PLL",
  453. NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
  454. SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
  455. &nau8822_loopback),
  456. SND_SOC_DAPM_INPUT("LMICN"),
  457. SND_SOC_DAPM_INPUT("LMICP"),
  458. SND_SOC_DAPM_INPUT("RMICN"),
  459. SND_SOC_DAPM_INPUT("RMICP"),
  460. SND_SOC_DAPM_INPUT("LAUX"),
  461. SND_SOC_DAPM_INPUT("RAUX"),
  462. SND_SOC_DAPM_INPUT("L2"),
  463. SND_SOC_DAPM_INPUT("R2"),
  464. SND_SOC_DAPM_OUTPUT("LHP"),
  465. SND_SOC_DAPM_OUTPUT("RHP"),
  466. SND_SOC_DAPM_OUTPUT("LSPK"),
  467. SND_SOC_DAPM_OUTPUT("RSPK"),
  468. SND_SOC_DAPM_OUTPUT("AUXOUT1"),
  469. SND_SOC_DAPM_OUTPUT("AUXOUT2"),
  470. };
  471. static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
  472. {"Right DAC", NULL, "PLL", check_mclk_select_pll},
  473. {"Left DAC", NULL, "PLL", check_mclk_select_pll},
  474. /* LMAIN and RMAIN Mixer */
  475. {"Right Output Mixer", "LDAC Switch", "Left DAC"},
  476. {"Right Output Mixer", "RDAC Switch", "Right DAC"},
  477. {"Right Output Mixer", "RAUX Switch", "RAUX"},
  478. {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
  479. {"Left Output Mixer", "LDAC Switch", "Left DAC"},
  480. {"Left Output Mixer", "RDAC Switch", "Right DAC"},
  481. {"Left Output Mixer", "LAUX Switch", "LAUX"},
  482. {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
  483. /* AUX1 and AUX2 Mixer */
  484. {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
  485. {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
  486. {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
  487. {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
  488. {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
  489. {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
  490. {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
  491. {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
  492. {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
  493. /* Outputs */
  494. {"Right Headphone Out", NULL, "Right Output Mixer"},
  495. {"RHP", NULL, "Right Headphone Out"},
  496. {"Left Headphone Out", NULL, "Left Output Mixer"},
  497. {"LHP", NULL, "Left Headphone Out"},
  498. {"Right Speaker Out", NULL, "Right Output Mixer"},
  499. {"RSPK", NULL, "Right Speaker Out"},
  500. {"Left Speaker Out", NULL, "Left Output Mixer"},
  501. {"LSPK", NULL, "Left Speaker Out"},
  502. {"AUX1 Out", NULL, "AUX1 Output Mixer"},
  503. {"AUX2 Out", NULL, "AUX2 Output Mixer"},
  504. {"AUXOUT1", NULL, "AUX1 Out"},
  505. {"AUXOUT2", NULL, "AUX2 Out"},
  506. /* Boost Mixer */
  507. {"Right ADC", NULL, "PLL", check_mclk_select_pll},
  508. {"Left ADC", NULL, "PLL", check_mclk_select_pll},
  509. {"Right ADC", NULL, "Right Boost Mixer"},
  510. {"Right Boost Mixer", NULL, "RAUX"},
  511. {"Right Boost Mixer", NULL, "Right Capture PGA"},
  512. {"Right Boost Mixer", NULL, "R2"},
  513. {"Left ADC", NULL, "Left Boost Mixer"},
  514. {"Left Boost Mixer", NULL, "LAUX"},
  515. {"Left Boost Mixer", NULL, "Left Capture PGA"},
  516. {"Left Boost Mixer", NULL, "L2"},
  517. /* Input PGA */
  518. {"Right Capture PGA", NULL, "Right Input Mixer"},
  519. {"Left Capture PGA", NULL, "Left Input Mixer"},
  520. /* Enable Microphone Power */
  521. {"Right Capture PGA", NULL, "Mic Bias"},
  522. {"Left Capture PGA", NULL, "Mic Bias"},
  523. {"Right Input Mixer", "R2 Switch", "R2"},
  524. {"Right Input Mixer", "MicN Switch", "RMICN"},
  525. {"Right Input Mixer", "MicP Switch", "RMICP"},
  526. {"Left Input Mixer", "L2 Switch", "L2"},
  527. {"Left Input Mixer", "MicN Switch", "LMICN"},
  528. {"Left Input Mixer", "MicP Switch", "LMICP"},
  529. /* Digital Loopback */
  530. {"Digital Loopback", "Switch", "Left ADC"},
  531. {"Digital Loopback", "Switch", "Right ADC"},
  532. {"Left DAC", NULL, "Digital Loopback"},
  533. {"Right DAC", NULL, "Digital Loopback"},
  534. };
  535. static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  536. unsigned int freq, int dir)
  537. {
  538. struct snd_soc_component *component = dai->component;
  539. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  540. nau8822->div_id = clk_id;
  541. nau8822->sysclk = freq;
  542. dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
  543. clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
  544. return 0;
  545. }
  546. static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
  547. struct nau8822_pll *pll_param)
  548. {
  549. u64 f2, f2_max, pll_ratio;
  550. int i, scal_sel;
  551. if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
  552. return -EINVAL;
  553. f2_max = 0;
  554. scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
  555. for (i = 0; i < scal_sel; i++) {
  556. f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
  557. if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
  558. f2_max < f2) {
  559. f2_max = f2;
  560. scal_sel = i;
  561. }
  562. }
  563. if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel)
  564. return -EINVAL;
  565. pll_param->mclk_scaler = scal_sel;
  566. f2 = f2_max;
  567. /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
  568. * input; round up the 24+4bit.
  569. */
  570. pll_ratio = div_u64(f2 << 28, pll_in);
  571. pll_param->pre_factor = 0;
  572. if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
  573. pll_ratio <<= 1;
  574. pll_param->pre_factor = 1;
  575. }
  576. pll_param->pll_int = (pll_ratio >> 28) & 0xF;
  577. pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
  578. return 0;
  579. }
  580. static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate)
  581. {
  582. struct snd_soc_component *component = dai->component;
  583. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  584. struct nau8822_pll *pll = &nau8822->pll;
  585. int i, sclk, imclk;
  586. switch (nau8822->div_id) {
  587. case NAU8822_CLK_MCLK:
  588. /* Configure the master clock prescaler div to make system
  589. * clock to approximate the internal master clock (IMCLK);
  590. * and large or equal to IMCLK.
  591. */
  592. div = 0;
  593. imclk = rate * 256;
  594. for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
  595. sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
  596. if (sclk < imclk)
  597. break;
  598. div = i;
  599. }
  600. dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
  601. div, rate);
  602. /* master clock from MCLK and disable PLL */
  603. snd_soc_component_update_bits(component,
  604. NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
  605. (div << NAU8822_MCLKSEL_SFT));
  606. snd_soc_component_update_bits(component,
  607. NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
  608. NAU8822_CLKM_MCLK);
  609. break;
  610. case NAU8822_CLK_PLL:
  611. /* master clock from PLL and enable PLL */
  612. if (pll->mclk_scaler != div) {
  613. dev_err(component->dev,
  614. "master clock prescaler not meet PLL parameters\n");
  615. return -EINVAL;
  616. }
  617. snd_soc_component_update_bits(component,
  618. NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
  619. (div << NAU8822_MCLKSEL_SFT));
  620. snd_soc_component_update_bits(component,
  621. NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
  622. NAU8822_CLKM_PLL);
  623. break;
  624. default:
  625. return -EINVAL;
  626. }
  627. return 0;
  628. }
  629. static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
  630. unsigned int freq_in, unsigned int freq_out)
  631. {
  632. struct snd_soc_component *component = dai->component;
  633. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  634. struct nau8822_pll *pll_param = &nau8822->pll;
  635. int ret, fs;
  636. fs = freq_out / 256;
  637. ret = nau8822_calc_pll(freq_in, fs, pll_param);
  638. if (ret < 0) {
  639. dev_err(component->dev, "Unsupported input clock %d\n",
  640. freq_in);
  641. return ret;
  642. }
  643. dev_info(component->dev,
  644. "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
  645. pll_param->pll_int, pll_param->pll_frac,
  646. pll_param->mclk_scaler, pll_param->pre_factor);
  647. snd_soc_component_update_bits(component,
  648. NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK,
  649. (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
  650. pll_param->pll_int);
  651. snd_soc_component_write(component,
  652. NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
  653. NAU8822_PLLK1_MASK);
  654. snd_soc_component_write(component,
  655. NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
  656. NAU8822_PLLK2_MASK);
  657. snd_soc_component_write(component,
  658. NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
  659. snd_soc_component_update_bits(component,
  660. NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
  661. pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
  662. snd_soc_component_update_bits(component,
  663. NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL);
  664. return 0;
  665. }
  666. static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  667. {
  668. struct snd_soc_component *component = dai->component;
  669. u16 ctrl1_val = 0, ctrl2_val = 0;
  670. dev_dbg(component->dev, "%s\n", __func__);
  671. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  672. case SND_SOC_DAIFMT_CBM_CFM:
  673. ctrl2_val |= 1;
  674. break;
  675. case SND_SOC_DAIFMT_CBS_CFS:
  676. ctrl2_val &= ~1;
  677. break;
  678. default:
  679. return -EINVAL;
  680. }
  681. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  682. case SND_SOC_DAIFMT_I2S:
  683. ctrl1_val |= 0x10;
  684. break;
  685. case SND_SOC_DAIFMT_RIGHT_J:
  686. break;
  687. case SND_SOC_DAIFMT_LEFT_J:
  688. ctrl1_val |= 0x8;
  689. break;
  690. case SND_SOC_DAIFMT_DSP_A:
  691. ctrl1_val |= 0x18;
  692. break;
  693. default:
  694. return -EINVAL;
  695. }
  696. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  697. case SND_SOC_DAIFMT_NB_NF:
  698. break;
  699. case SND_SOC_DAIFMT_IB_IF:
  700. ctrl1_val |= 0x180;
  701. break;
  702. case SND_SOC_DAIFMT_IB_NF:
  703. ctrl1_val |= 0x100;
  704. break;
  705. case SND_SOC_DAIFMT_NB_IF:
  706. ctrl1_val |= 0x80;
  707. break;
  708. default:
  709. return -EINVAL;
  710. }
  711. snd_soc_component_update_bits(component,
  712. NAU8822_REG_AUDIO_INTERFACE,
  713. NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK,
  714. ctrl1_val);
  715. snd_soc_component_update_bits(component,
  716. NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val);
  717. return 0;
  718. }
  719. static int nau8822_hw_params(struct snd_pcm_substream *substream,
  720. struct snd_pcm_hw_params *params,
  721. struct snd_soc_dai *dai)
  722. {
  723. struct snd_soc_component *component = dai->component;
  724. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  725. int val_len = 0, val_rate = 0;
  726. unsigned int ctrl_val, bclk_fs, bclk_div;
  727. /* make BCLK and LRC divide configuration if the codec as master. */
  728. ctrl_val = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
  729. if (ctrl_val & NAU8822_CLK_MASTER) {
  730. /* get the bclk and fs ratio */
  731. bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
  732. if (bclk_fs <= 32)
  733. bclk_div = NAU8822_BCLKDIV_8;
  734. else if (bclk_fs <= 64)
  735. bclk_div = NAU8822_BCLKDIV_4;
  736. else if (bclk_fs <= 128)
  737. bclk_div = NAU8822_BCLKDIV_2;
  738. else
  739. return -EINVAL;
  740. snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING,
  741. NAU8822_BCLKSEL_MASK, bclk_div);
  742. }
  743. switch (params_format(params)) {
  744. case SNDRV_PCM_FORMAT_S16_LE:
  745. break;
  746. case SNDRV_PCM_FORMAT_S20_3LE:
  747. val_len |= NAU8822_WLEN_20;
  748. break;
  749. case SNDRV_PCM_FORMAT_S24_LE:
  750. val_len |= NAU8822_WLEN_24;
  751. break;
  752. case SNDRV_PCM_FORMAT_S32_LE:
  753. val_len |= NAU8822_WLEN_32;
  754. break;
  755. default:
  756. return -EINVAL;
  757. }
  758. switch (params_rate(params)) {
  759. case 8000:
  760. val_rate |= NAU8822_SMPLR_8K;
  761. break;
  762. case 11025:
  763. val_rate |= NAU8822_SMPLR_12K;
  764. break;
  765. case 16000:
  766. val_rate |= NAU8822_SMPLR_16K;
  767. break;
  768. case 22050:
  769. val_rate |= NAU8822_SMPLR_24K;
  770. break;
  771. case 32000:
  772. val_rate |= NAU8822_SMPLR_32K;
  773. break;
  774. case 44100:
  775. case 48000:
  776. break;
  777. default:
  778. return -EINVAL;
  779. }
  780. snd_soc_component_update_bits(component,
  781. NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len);
  782. snd_soc_component_update_bits(component,
  783. NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate);
  784. /* If the master clock is from MCLK, provide the runtime FS for driver
  785. * to get the master clock prescaler configuration.
  786. */
  787. if (nau8822->div_id == NAU8822_CLK_MCLK)
  788. nau8822_config_clkdiv(dai, 0, params_rate(params));
  789. return 0;
  790. }
  791. static int nau8822_mute(struct snd_soc_dai *dai, int mute, int direction)
  792. {
  793. struct snd_soc_component *component = dai->component;
  794. dev_dbg(component->dev, "%s: %d\n", __func__, mute);
  795. if (mute)
  796. snd_soc_component_update_bits(component,
  797. NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
  798. else
  799. snd_soc_component_update_bits(component,
  800. NAU8822_REG_DAC_CONTROL, 0x40, 0);
  801. return 0;
  802. }
  803. static int nau8822_set_bias_level(struct snd_soc_component *component,
  804. enum snd_soc_bias_level level)
  805. {
  806. switch (level) {
  807. case SND_SOC_BIAS_ON:
  808. case SND_SOC_BIAS_PREPARE:
  809. snd_soc_component_update_bits(component,
  810. NAU8822_REG_POWER_MANAGEMENT_1,
  811. NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
  812. break;
  813. case SND_SOC_BIAS_STANDBY:
  814. snd_soc_component_update_bits(component,
  815. NAU8822_REG_POWER_MANAGEMENT_1,
  816. NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
  817. NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
  818. if (snd_soc_component_get_bias_level(component) ==
  819. SND_SOC_BIAS_OFF) {
  820. snd_soc_component_update_bits(component,
  821. NAU8822_REG_POWER_MANAGEMENT_1,
  822. NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
  823. mdelay(100);
  824. }
  825. snd_soc_component_update_bits(component,
  826. NAU8822_REG_POWER_MANAGEMENT_1,
  827. NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
  828. break;
  829. case SND_SOC_BIAS_OFF:
  830. snd_soc_component_write(component,
  831. NAU8822_REG_POWER_MANAGEMENT_1, 0);
  832. snd_soc_component_write(component,
  833. NAU8822_REG_POWER_MANAGEMENT_2, 0);
  834. snd_soc_component_write(component,
  835. NAU8822_REG_POWER_MANAGEMENT_3, 0);
  836. break;
  837. }
  838. dev_dbg(component->dev, "%s: %d\n", __func__, level);
  839. return 0;
  840. }
  841. #define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
  842. #define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  843. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  844. static const struct snd_soc_dai_ops nau8822_dai_ops = {
  845. .hw_params = nau8822_hw_params,
  846. .mute_stream = nau8822_mute,
  847. .set_fmt = nau8822_set_dai_fmt,
  848. .set_sysclk = nau8822_set_dai_sysclk,
  849. .set_pll = nau8822_set_pll,
  850. .no_capture_mute = 1,
  851. };
  852. static struct snd_soc_dai_driver nau8822_dai = {
  853. .name = "nau8822-hifi",
  854. .playback = {
  855. .stream_name = "Playback",
  856. .channels_min = 1,
  857. .channels_max = 2,
  858. .rates = NAU8822_RATES,
  859. .formats = NAU8822_FORMATS,
  860. },
  861. .capture = {
  862. .stream_name = "Capture",
  863. .channels_min = 1,
  864. .channels_max = 2,
  865. .rates = NAU8822_RATES,
  866. .formats = NAU8822_FORMATS,
  867. },
  868. .ops = &nau8822_dai_ops,
  869. .symmetric_rates = 1,
  870. };
  871. static int nau8822_suspend(struct snd_soc_component *component)
  872. {
  873. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  874. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  875. regcache_mark_dirty(nau8822->regmap);
  876. return 0;
  877. }
  878. static int nau8822_resume(struct snd_soc_component *component)
  879. {
  880. struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
  881. regcache_sync(nau8822->regmap);
  882. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  883. return 0;
  884. }
  885. /*
  886. * These registers contain an "update" bit - bit 8. This means, for example,
  887. * that one can write new DAC digital volume for both channels, but only when
  888. * the update bit is set, will also the volume be updated - simultaneously for
  889. * both channels.
  890. */
  891. static const int update_reg[] = {
  892. NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
  893. NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
  894. NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
  895. NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
  896. NAU8822_REG_LEFT_INP_PGA_CONTROL,
  897. NAU8822_REG_RIGHT_INP_PGA_CONTROL,
  898. NAU8822_REG_LHP_VOLUME,
  899. NAU8822_REG_RHP_VOLUME,
  900. NAU8822_REG_LSPKOUT_VOLUME,
  901. NAU8822_REG_RSPKOUT_VOLUME,
  902. };
  903. static int nau8822_probe(struct snd_soc_component *component)
  904. {
  905. int i;
  906. /*
  907. * Set the update bit in all registers, that have one. This way all
  908. * writes to those registers will also cause the update bit to be
  909. * written.
  910. */
  911. for (i = 0; i < ARRAY_SIZE(update_reg); i++)
  912. snd_soc_component_update_bits(component,
  913. update_reg[i], 0x100, 0x100);
  914. return 0;
  915. }
  916. static const struct snd_soc_component_driver soc_component_dev_nau8822 = {
  917. .probe = nau8822_probe,
  918. .suspend = nau8822_suspend,
  919. .resume = nau8822_resume,
  920. .set_bias_level = nau8822_set_bias_level,
  921. .controls = nau8822_snd_controls,
  922. .num_controls = ARRAY_SIZE(nau8822_snd_controls),
  923. .dapm_widgets = nau8822_dapm_widgets,
  924. .num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets),
  925. .dapm_routes = nau8822_dapm_routes,
  926. .num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes),
  927. .idle_bias_on = 1,
  928. .use_pmdown_time = 1,
  929. .endianness = 1,
  930. .non_legacy_dai_naming = 1,
  931. };
  932. static const struct regmap_config nau8822_regmap_config = {
  933. .reg_bits = 7,
  934. .val_bits = 9,
  935. .max_register = NAU8822_REG_MAX_REGISTER,
  936. .volatile_reg = nau8822_volatile,
  937. .readable_reg = nau8822_readable_reg,
  938. .writeable_reg = nau8822_writeable_reg,
  939. .cache_type = REGCACHE_RBTREE,
  940. .reg_defaults = nau8822_reg_defaults,
  941. .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
  942. };
  943. static int nau8822_i2c_probe(struct i2c_client *i2c,
  944. const struct i2c_device_id *id)
  945. {
  946. struct device *dev = &i2c->dev;
  947. struct nau8822 *nau8822 = dev_get_platdata(dev);
  948. int ret;
  949. if (!nau8822) {
  950. nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL);
  951. if (nau8822 == NULL)
  952. return -ENOMEM;
  953. }
  954. i2c_set_clientdata(i2c, nau8822);
  955. nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
  956. if (IS_ERR(nau8822->regmap)) {
  957. ret = PTR_ERR(nau8822->regmap);
  958. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  959. return ret;
  960. }
  961. nau8822->dev = dev;
  962. /* Reset the codec */
  963. ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
  964. if (ret != 0) {
  965. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  966. return ret;
  967. }
  968. ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822,
  969. &nau8822_dai, 1);
  970. if (ret != 0) {
  971. dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
  972. return ret;
  973. }
  974. return 0;
  975. }
  976. static const struct i2c_device_id nau8822_i2c_id[] = {
  977. { "nau8822", 0 },
  978. { }
  979. };
  980. MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
  981. #ifdef CONFIG_OF
  982. static const struct of_device_id nau8822_of_match[] = {
  983. { .compatible = "nuvoton,nau8822", },
  984. { }
  985. };
  986. MODULE_DEVICE_TABLE(of, nau8822_of_match);
  987. #endif
  988. static struct i2c_driver nau8822_i2c_driver = {
  989. .driver = {
  990. .name = "nau8822",
  991. .of_match_table = of_match_ptr(nau8822_of_match),
  992. },
  993. .probe = nau8822_i2c_probe,
  994. .id_table = nau8822_i2c_id,
  995. };
  996. module_i2c_driver(nau8822_i2c_driver);
  997. MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
  998. MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
  999. MODULE_LICENSE("GPL v2");