nau8810.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * nau8810.c -- NAU8810 ALSA Soc Audio driver
  4. *
  5. * Copyright 2016 Nuvoton Technology Corp.
  6. *
  7. * Author: David Lin <ctlin0@nuvoton.com>
  8. *
  9. * Based on WM8974.c
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include "nau8810.h"
  27. #define NAU_PLL_FREQ_MAX 100000000
  28. #define NAU_PLL_FREQ_MIN 90000000
  29. #define NAU_PLL_REF_MAX 33000000
  30. #define NAU_PLL_REF_MIN 8000000
  31. #define NAU_PLL_OPTOP_MIN 6
  32. static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
  33. static const struct reg_default nau8810_reg_defaults[] = {
  34. { NAU8810_REG_POWER1, 0x0000 },
  35. { NAU8810_REG_POWER2, 0x0000 },
  36. { NAU8810_REG_POWER3, 0x0000 },
  37. { NAU8810_REG_IFACE, 0x0050 },
  38. { NAU8810_REG_COMP, 0x0000 },
  39. { NAU8810_REG_CLOCK, 0x0140 },
  40. { NAU8810_REG_SMPLR, 0x0000 },
  41. { NAU8810_REG_DAC, 0x0000 },
  42. { NAU8810_REG_DACGAIN, 0x00FF },
  43. { NAU8810_REG_ADC, 0x0100 },
  44. { NAU8810_REG_ADCGAIN, 0x00FF },
  45. { NAU8810_REG_EQ1, 0x012C },
  46. { NAU8810_REG_EQ2, 0x002C },
  47. { NAU8810_REG_EQ3, 0x002C },
  48. { NAU8810_REG_EQ4, 0x002C },
  49. { NAU8810_REG_EQ5, 0x002C },
  50. { NAU8810_REG_DACLIM1, 0x0032 },
  51. { NAU8810_REG_DACLIM2, 0x0000 },
  52. { NAU8810_REG_NOTCH1, 0x0000 },
  53. { NAU8810_REG_NOTCH2, 0x0000 },
  54. { NAU8810_REG_NOTCH3, 0x0000 },
  55. { NAU8810_REG_NOTCH4, 0x0000 },
  56. { NAU8810_REG_ALC1, 0x0038 },
  57. { NAU8810_REG_ALC2, 0x000B },
  58. { NAU8810_REG_ALC3, 0x0032 },
  59. { NAU8810_REG_NOISEGATE, 0x0000 },
  60. { NAU8810_REG_PLLN, 0x0008 },
  61. { NAU8810_REG_PLLK1, 0x000C },
  62. { NAU8810_REG_PLLK2, 0x0093 },
  63. { NAU8810_REG_PLLK3, 0x00E9 },
  64. { NAU8810_REG_ATTEN, 0x0000 },
  65. { NAU8810_REG_INPUT_SIGNAL, 0x0003 },
  66. { NAU8810_REG_PGAGAIN, 0x0010 },
  67. { NAU8810_REG_ADCBOOST, 0x0100 },
  68. { NAU8810_REG_OUTPUT, 0x0002 },
  69. { NAU8810_REG_SPKMIX, 0x0001 },
  70. { NAU8810_REG_SPKGAIN, 0x0039 },
  71. { NAU8810_REG_MONOMIX, 0x0001 },
  72. { NAU8810_REG_POWER4, 0x0000 },
  73. { NAU8810_REG_TSLOTCTL1, 0x0000 },
  74. { NAU8810_REG_TSLOTCTL2, 0x0020 },
  75. { NAU8810_REG_DEVICE_REVID, 0x0000 },
  76. { NAU8810_REG_I2C_DEVICEID, 0x001A },
  77. { NAU8810_REG_ADDITIONID, 0x00CA },
  78. { NAU8810_REG_RESERVE, 0x0124 },
  79. { NAU8810_REG_OUTCTL, 0x0001 },
  80. { NAU8810_REG_ALC1ENHAN1, 0x0010 },
  81. { NAU8810_REG_ALC1ENHAN2, 0x0000 },
  82. { NAU8810_REG_MISCCTL, 0x0000 },
  83. { NAU8810_REG_OUTTIEOFF, 0x0000 },
  84. { NAU8810_REG_AGCP2POUT, 0x0000 },
  85. { NAU8810_REG_AGCPOUT, 0x0000 },
  86. { NAU8810_REG_AMTCTL, 0x0000 },
  87. { NAU8810_REG_OUTTIEOFFMAN, 0x0000 },
  88. };
  89. static bool nau8810_readable_reg(struct device *dev, unsigned int reg)
  90. {
  91. switch (reg) {
  92. case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
  93. case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
  94. case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
  95. case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
  96. case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
  97. case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
  98. case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
  99. case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
  100. case NAU8810_REG_ADCBOOST:
  101. case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
  102. case NAU8810_REG_SPKGAIN:
  103. case NAU8810_REG_MONOMIX:
  104. case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
  105. case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
  106. case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
  107. case NAU8810_REG_MISCCTL:
  108. case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
  109. return true;
  110. default:
  111. return false;
  112. }
  113. }
  114. static bool nau8810_writeable_reg(struct device *dev, unsigned int reg)
  115. {
  116. switch (reg) {
  117. case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
  118. case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
  119. case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
  120. case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
  121. case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
  122. case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
  123. case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
  124. case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
  125. case NAU8810_REG_ADCBOOST:
  126. case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
  127. case NAU8810_REG_SPKGAIN:
  128. case NAU8810_REG_MONOMIX:
  129. case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
  130. case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
  131. case NAU8810_REG_MISCCTL:
  132. case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
  133. return true;
  134. default:
  135. return false;
  136. }
  137. }
  138. static bool nau8810_volatile_reg(struct device *dev, unsigned int reg)
  139. {
  140. switch (reg) {
  141. case NAU8810_REG_RESET:
  142. case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
  143. return true;
  144. default:
  145. return false;
  146. }
  147. }
  148. /* The EQ parameters get function is to get the 5 band equalizer control.
  149. * The regmap raw read can't work here because regmap doesn't provide
  150. * value format for value width of 9 bits. Therefore, the driver reads data
  151. * from cache and makes value format according to the endianness of
  152. * bytes type control element.
  153. */
  154. static int nau8810_eq_get(struct snd_kcontrol *kcontrol,
  155. struct snd_ctl_elem_value *ucontrol)
  156. {
  157. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  158. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  159. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  160. int i, reg, reg_val;
  161. u16 *val;
  162. val = (u16 *)ucontrol->value.bytes.data;
  163. reg = NAU8810_REG_EQ1;
  164. for (i = 0; i < params->max / sizeof(u16); i++) {
  165. regmap_read(nau8810->regmap, reg + i, &reg_val);
  166. /* conversion of 16-bit integers between native CPU format
  167. * and big endian format
  168. */
  169. reg_val = cpu_to_be16(reg_val);
  170. memcpy(val + i, &reg_val, sizeof(reg_val));
  171. }
  172. return 0;
  173. }
  174. /* The EQ parameters put function is to make configuration of 5 band equalizer
  175. * control. These configuration includes central frequency, equalizer gain,
  176. * cut-off frequency, bandwidth control, and equalizer path.
  177. * The regmap raw write can't work here because regmap doesn't provide
  178. * register and value format for register with address 7 bits and value 9 bits.
  179. * Therefore, the driver makes value format according to the endianness of
  180. * bytes type control element and writes data to codec.
  181. */
  182. static int nau8810_eq_put(struct snd_kcontrol *kcontrol,
  183. struct snd_ctl_elem_value *ucontrol)
  184. {
  185. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  186. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  187. struct soc_bytes_ext *params = (void *)kcontrol->private_value;
  188. void *data;
  189. u16 *val, value;
  190. int i, reg, ret;
  191. data = kmemdup(ucontrol->value.bytes.data,
  192. params->max, GFP_KERNEL | GFP_DMA);
  193. if (!data)
  194. return -ENOMEM;
  195. val = (u16 *)data;
  196. reg = NAU8810_REG_EQ1;
  197. for (i = 0; i < params->max / sizeof(u16); i++) {
  198. /* conversion of 16-bit integers between native CPU format
  199. * and big endian format
  200. */
  201. value = be16_to_cpu(*(val + i));
  202. ret = regmap_write(nau8810->regmap, reg + i, value);
  203. if (ret) {
  204. dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n",
  205. reg + i, ret);
  206. kfree(data);
  207. return ret;
  208. }
  209. }
  210. kfree(data);
  211. return 0;
  212. }
  213. static const char * const nau8810_companding[] = {
  214. "Off", "NC", "u-law", "A-law" };
  215. static const struct soc_enum nau8810_companding_adc_enum =
  216. SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT,
  217. ARRAY_SIZE(nau8810_companding), nau8810_companding);
  218. static const struct soc_enum nau8810_companding_dac_enum =
  219. SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT,
  220. ARRAY_SIZE(nau8810_companding), nau8810_companding);
  221. static const char * const nau8810_deemp[] = {
  222. "None", "32kHz", "44.1kHz", "48kHz" };
  223. static const struct soc_enum nau8810_deemp_enum =
  224. SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT,
  225. ARRAY_SIZE(nau8810_deemp), nau8810_deemp);
  226. static const char * const nau8810_eqmode[] = {"Capture", "Playback" };
  227. static const struct soc_enum nau8810_eqmode_enum =
  228. SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT,
  229. ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode);
  230. static const char * const nau8810_alc[] = {"Normal", "Limiter" };
  231. static const struct soc_enum nau8810_alc_enum =
  232. SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT,
  233. ARRAY_SIZE(nau8810_alc), nau8810_alc);
  234. static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  235. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  236. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
  237. static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
  238. static const struct snd_kcontrol_new nau8810_snd_controls[] = {
  239. SOC_ENUM("ADC Companding", nau8810_companding_adc_enum),
  240. SOC_ENUM("DAC Companding", nau8810_companding_dac_enum),
  241. SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum),
  242. SOC_ENUM("EQ Function", nau8810_eqmode_enum),
  243. SND_SOC_BYTES_EXT("EQ Parameters", 10,
  244. nau8810_eq_get, nau8810_eq_put),
  245. SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC,
  246. NAU8810_DACPL_SFT, 1, 0),
  247. SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN,
  248. NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv),
  249. SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC,
  250. NAU8810_HPFEN_SFT, 1, 0),
  251. SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC,
  252. NAU8810_HPF_SFT, 0x7, 0),
  253. SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC,
  254. NAU8810_ADCPL_SFT, 1, 0),
  255. SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN,
  256. NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv),
  257. SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1,
  258. NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv),
  259. SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2,
  260. NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv),
  261. SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3,
  262. NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv),
  263. SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4,
  264. NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv),
  265. SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5,
  266. NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv),
  267. SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1,
  268. NAU8810_DACLIMEN_SFT, 1, 0),
  269. SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1,
  270. NAU8810_DACLIMDCY_SFT, 0xf, 0),
  271. SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1,
  272. NAU8810_DACLIMATK_SFT, 0xf, 0),
  273. SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2,
  274. NAU8810_DACLIMTHL_SFT, 0x7, 0),
  275. SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2,
  276. NAU8810_DACLIMBST_SFT, 0xf, 0),
  277. SOC_ENUM("ALC Mode", nau8810_alc_enum),
  278. SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1,
  279. NAU8810_ALCEN_SFT, 1, 0),
  280. SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1,
  281. NAU8810_ALCMXGAIN_SFT, 0x7, 0),
  282. SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1,
  283. NAU8810_ALCMINGAIN_SFT, 0x7, 0),
  284. SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2,
  285. NAU8810_ALCZC_SFT, 1, 0),
  286. SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2,
  287. NAU8810_ALCHT_SFT, 0xf, 0),
  288. SOC_SINGLE("ALC Target", NAU8810_REG_ALC2,
  289. NAU8810_ALCSL_SFT, 0xf, 0),
  290. SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3,
  291. NAU8810_ALCDCY_SFT, 0xf, 0),
  292. SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3,
  293. NAU8810_ALCATK_SFT, 0xf, 0),
  294. SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE,
  295. NAU8810_ALCNEN_SFT, 1, 0),
  296. SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE,
  297. NAU8810_ALCNTH_SFT, 0x7, 0),
  298. SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN,
  299. NAU8810_PGAZC_SFT, 1, 0),
  300. SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN,
  301. NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv),
  302. SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN,
  303. NAU8810_SPKZC_SFT, 1, 0),
  304. SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN,
  305. NAU8810_SPKMT_SFT, 1, 0),
  306. SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN,
  307. NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv),
  308. SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST,
  309. NAU8810_PGABST_SFT, 1, 0),
  310. SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX,
  311. NAU8810_MOUTMXMT_SFT, 1, 0),
  312. SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC,
  313. NAU8810_DACOS_SFT, 1, 0),
  314. SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC,
  315. NAU8810_ADCOS_SFT, 1, 0),
  316. };
  317. /* Speaker Output Mixer */
  318. static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = {
  319. SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_SPKMIX,
  320. NAU8810_AUXSPK_SFT, 1, 0),
  321. SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX,
  322. NAU8810_BYPSPK_SFT, 1, 0),
  323. SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX,
  324. NAU8810_DACSPK_SFT, 1, 0),
  325. };
  326. /* Mono Output Mixer */
  327. static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = {
  328. SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_MONOMIX,
  329. NAU8810_AUXMOUT_SFT, 1, 0),
  330. SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX,
  331. NAU8810_BYPMOUT_SFT, 1, 0),
  332. SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX,
  333. NAU8810_DACMOUT_SFT, 1, 0),
  334. };
  335. /* PGA Mute */
  336. static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = {
  337. SOC_DAPM_SINGLE("AUX PGA Switch", NAU8810_REG_ADCBOOST,
  338. NAU8810_AUXBSTGAIN_SFT, 0x7, 0),
  339. SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN,
  340. NAU8810_PGAMT_SFT, 1, 1),
  341. SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST,
  342. NAU8810_PMICBSTGAIN_SFT, 0x7, 0),
  343. };
  344. /* Input PGA */
  345. static const struct snd_kcontrol_new nau8810_inpga[] = {
  346. SOC_DAPM_SINGLE("AUX Switch", NAU8810_REG_INPUT_SIGNAL,
  347. NAU8810_AUXPGA_SFT, 1, 0),
  348. SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL,
  349. NAU8810_NMICPGA_SFT, 1, 0),
  350. SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL,
  351. NAU8810_PMICPGA_SFT, 1, 0),
  352. };
  353. /* Loopback Switch */
  354. static const struct snd_kcontrol_new nau8810_loopback =
  355. SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP,
  356. NAU8810_ADDAP_SFT, 1, 0);
  357. static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
  358. struct snd_soc_dapm_widget *sink)
  359. {
  360. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  361. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  362. unsigned int value;
  363. regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value);
  364. return (value & NAU8810_CLKM_MASK);
  365. }
  366. static int check_mic_enabled(struct snd_soc_dapm_widget *source,
  367. struct snd_soc_dapm_widget *sink)
  368. {
  369. struct snd_soc_component *component =
  370. snd_soc_dapm_to_component(source->dapm);
  371. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  372. unsigned int value;
  373. regmap_read(nau8810->regmap, NAU8810_REG_INPUT_SIGNAL, &value);
  374. if (value & NAU8810_PMICPGA_EN || value & NAU8810_NMICPGA_EN)
  375. return 1;
  376. regmap_read(nau8810->regmap, NAU8810_REG_ADCBOOST, &value);
  377. if (value & NAU8810_PMICBSTGAIN_MASK)
  378. return 1;
  379. return 0;
  380. }
  381. static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = {
  382. SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3,
  383. NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0],
  384. ARRAY_SIZE(nau8810_speaker_mixer_controls)),
  385. SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3,
  386. NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0],
  387. ARRAY_SIZE(nau8810_mono_mixer_controls)),
  388. SND_SOC_DAPM_DAC("DAC", "Playback", NAU8810_REG_POWER3,
  389. NAU8810_DAC_EN_SFT, 0),
  390. SND_SOC_DAPM_ADC("ADC", "Capture", NAU8810_REG_POWER2,
  391. NAU8810_ADC_EN_SFT, 0),
  392. SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3,
  393. NAU8810_NSPK_EN_SFT, 0, NULL, 0),
  394. SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3,
  395. NAU8810_PSPK_EN_SFT, 0, NULL, 0),
  396. SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3,
  397. NAU8810_MOUT_EN_SFT, 0, NULL, 0),
  398. SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2,
  399. NAU8810_PGA_EN_SFT, 0, nau8810_inpga,
  400. ARRAY_SIZE(nau8810_inpga)),
  401. SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2,
  402. NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls,
  403. ARRAY_SIZE(nau8810_pgaboost_mixer_controls)),
  404. SND_SOC_DAPM_PGA("AUX Input", NAU8810_REG_POWER1,
  405. NAU8810_AUX_EN_SFT, 0, NULL, 0),
  406. SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1,
  407. NAU8810_MICBIAS_EN_SFT, 0, NULL, 0),
  408. SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1,
  409. NAU8810_PLL_EN_SFT, 0, NULL, 0),
  410. SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
  411. &nau8810_loopback),
  412. SND_SOC_DAPM_INPUT("AUX"),
  413. SND_SOC_DAPM_INPUT("MICN"),
  414. SND_SOC_DAPM_INPUT("MICP"),
  415. SND_SOC_DAPM_OUTPUT("MONOOUT"),
  416. SND_SOC_DAPM_OUTPUT("SPKOUTP"),
  417. SND_SOC_DAPM_OUTPUT("SPKOUTN"),
  418. };
  419. static const struct snd_soc_dapm_route nau8810_dapm_routes[] = {
  420. {"DAC", NULL, "PLL", check_mclk_select_pll},
  421. /* Mono output mixer */
  422. {"Mono Mixer", "AUX Bypass Switch", "AUX Input"},
  423. {"Mono Mixer", "PCM Playback Switch", "DAC"},
  424. {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"},
  425. /* Speaker output mixer */
  426. {"Speaker Mixer", "AUX Bypass Switch", "AUX Input"},
  427. {"Speaker Mixer", "PCM Playback Switch", "DAC"},
  428. {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"},
  429. /* Outputs */
  430. {"Mono Out", NULL, "Mono Mixer"},
  431. {"MONOOUT", NULL, "Mono Out"},
  432. {"SpkN Out", NULL, "Speaker Mixer"},
  433. {"SpkP Out", NULL, "Speaker Mixer"},
  434. {"SPKOUTN", NULL, "SpkN Out"},
  435. {"SPKOUTP", NULL, "SpkP Out"},
  436. /* Input Boost Stage */
  437. {"ADC", NULL, "Input Boost Stage"},
  438. {"ADC", NULL, "PLL", check_mclk_select_pll},
  439. {"Input Boost Stage", "AUX PGA Switch", "AUX Input"},
  440. {"Input Boost Stage", "PGA Mute Switch", "Input PGA"},
  441. {"Input Boost Stage", "PMIC PGA Switch", "MICP"},
  442. /* Input PGA */
  443. {"Input PGA", NULL, "Mic Bias", check_mic_enabled},
  444. {"Input PGA", "AUX Switch", "AUX Input"},
  445. {"Input PGA", "MicN Switch", "MICN"},
  446. {"Input PGA", "MicP Switch", "MICP"},
  447. {"AUX Input", NULL, "AUX"},
  448. /* Digital Looptack */
  449. {"Digital Loopback", "Switch", "ADC"},
  450. {"DAC", NULL, "Digital Loopback"},
  451. };
  452. static int nau8810_set_sysclk(struct snd_soc_dai *dai,
  453. int clk_id, unsigned int freq, int dir)
  454. {
  455. struct snd_soc_component *component = dai->component;
  456. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  457. nau8810->clk_id = clk_id;
  458. nau8810->sysclk = freq;
  459. dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n",
  460. freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK");
  461. return 0;
  462. }
  463. static int nau8810_calc_pll(unsigned int pll_in,
  464. unsigned int fs, struct nau8810_pll *pll_param)
  465. {
  466. u64 f2, f2_max, pll_ratio;
  467. int i, scal_sel;
  468. if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
  469. return -EINVAL;
  470. f2_max = 0;
  471. scal_sel = ARRAY_SIZE(nau8810_mclk_scaler);
  472. for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
  473. f2 = 256ULL * fs * 4 * nau8810_mclk_scaler[i];
  474. f2 = div_u64(f2, 10);
  475. if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
  476. f2_max < f2) {
  477. f2_max = f2;
  478. scal_sel = i;
  479. }
  480. }
  481. if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel)
  482. return -EINVAL;
  483. pll_param->mclk_scaler = scal_sel;
  484. f2 = f2_max;
  485. /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
  486. * input; round up the 24+4bit.
  487. */
  488. pll_ratio = div_u64(f2 << 28, pll_in);
  489. pll_param->pre_factor = 0;
  490. if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
  491. pll_ratio <<= 1;
  492. pll_param->pre_factor = 1;
  493. }
  494. pll_param->pll_int = (pll_ratio >> 28) & 0xF;
  495. pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
  496. return 0;
  497. }
  498. static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
  499. int source, unsigned int freq_in, unsigned int freq_out)
  500. {
  501. struct snd_soc_component *component = codec_dai->component;
  502. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  503. struct regmap *map = nau8810->regmap;
  504. struct nau8810_pll *pll_param = &nau8810->pll;
  505. int ret, fs;
  506. fs = freq_out / 256;
  507. ret = nau8810_calc_pll(freq_in, fs, pll_param);
  508. if (ret < 0) {
  509. dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in);
  510. return ret;
  511. }
  512. dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
  513. pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler,
  514. pll_param->pre_factor);
  515. regmap_update_bits(map, NAU8810_REG_PLLN,
  516. NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK,
  517. (pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) |
  518. pll_param->pll_int);
  519. regmap_write(map, NAU8810_REG_PLLK1,
  520. (pll_param->pll_frac >> NAU8810_PLLK1_SFT) &
  521. NAU8810_PLLK1_MASK);
  522. regmap_write(map, NAU8810_REG_PLLK2,
  523. (pll_param->pll_frac >> NAU8810_PLLK2_SFT) &
  524. NAU8810_PLLK2_MASK);
  525. regmap_write(map, NAU8810_REG_PLLK3,
  526. pll_param->pll_frac & NAU8810_PLLK3_MASK);
  527. regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK,
  528. pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT);
  529. regmap_update_bits(map, NAU8810_REG_CLOCK,
  530. NAU8810_CLKM_MASK, NAU8810_CLKM_PLL);
  531. return 0;
  532. }
  533. static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai,
  534. unsigned int fmt)
  535. {
  536. struct snd_soc_component *component = codec_dai->component;
  537. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  538. u16 ctrl1_val = 0, ctrl2_val = 0;
  539. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  540. case SND_SOC_DAIFMT_CBM_CFM:
  541. ctrl2_val |= NAU8810_CLKIO_MASTER;
  542. break;
  543. case SND_SOC_DAIFMT_CBS_CFS:
  544. break;
  545. default:
  546. return -EINVAL;
  547. }
  548. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  549. case SND_SOC_DAIFMT_I2S:
  550. ctrl1_val |= NAU8810_AIFMT_I2S;
  551. break;
  552. case SND_SOC_DAIFMT_RIGHT_J:
  553. break;
  554. case SND_SOC_DAIFMT_LEFT_J:
  555. ctrl1_val |= NAU8810_AIFMT_LEFT;
  556. break;
  557. case SND_SOC_DAIFMT_DSP_A:
  558. ctrl1_val |= NAU8810_AIFMT_PCM_A;
  559. break;
  560. default:
  561. return -EINVAL;
  562. }
  563. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  564. case SND_SOC_DAIFMT_NB_NF:
  565. break;
  566. case SND_SOC_DAIFMT_IB_IF:
  567. ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF;
  568. break;
  569. case SND_SOC_DAIFMT_IB_NF:
  570. ctrl1_val |= NAU8810_BCLKP_IB;
  571. break;
  572. case SND_SOC_DAIFMT_NB_IF:
  573. ctrl1_val |= NAU8810_FSP_IF;
  574. break;
  575. default:
  576. return -EINVAL;
  577. }
  578. regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
  579. NAU8810_AIFMT_MASK | NAU8810_FSP_IF |
  580. NAU8810_BCLKP_IB, ctrl1_val);
  581. regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
  582. NAU8810_CLKIO_MASK, ctrl2_val);
  583. return 0;
  584. }
  585. static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate)
  586. {
  587. int i, sclk, imclk = rate * 256, div = 0;
  588. if (!nau8810->sysclk) {
  589. dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n");
  590. return -EINVAL;
  591. }
  592. /* Configure the master clock prescaler div to make system
  593. * clock to approximate the internal master clock (IMCLK);
  594. * and large or equal to IMCLK.
  595. */
  596. for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
  597. sclk = (nau8810->sysclk * 10) /
  598. nau8810_mclk_scaler[i];
  599. if (sclk < imclk)
  600. break;
  601. div = i;
  602. }
  603. dev_dbg(nau8810->dev,
  604. "master clock prescaler %x for fs %d\n", div, rate);
  605. /* master clock from MCLK and disable PLL */
  606. regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
  607. NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT));
  608. regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
  609. NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK);
  610. return 0;
  611. }
  612. static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream,
  613. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  614. {
  615. struct snd_soc_component *component = dai->component;
  616. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  617. int val_len = 0, val_rate = 0, ret = 0;
  618. unsigned int ctrl_val, bclk_fs, bclk_div;
  619. /* Select BCLK configuration if the codec as master. */
  620. regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &ctrl_val);
  621. if (ctrl_val & NAU8810_CLKIO_MASTER) {
  622. /* get the bclk and fs ratio */
  623. bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
  624. if (bclk_fs <= 32)
  625. bclk_div = NAU8810_BCLKDIV_8;
  626. else if (bclk_fs <= 64)
  627. bclk_div = NAU8810_BCLKDIV_4;
  628. else if (bclk_fs <= 128)
  629. bclk_div = NAU8810_BCLKDIV_2;
  630. else
  631. return -EINVAL;
  632. regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
  633. NAU8810_BCLKSEL_MASK, bclk_div);
  634. }
  635. switch (params_width(params)) {
  636. case 16:
  637. break;
  638. case 20:
  639. val_len |= NAU8810_WLEN_20;
  640. break;
  641. case 24:
  642. val_len |= NAU8810_WLEN_24;
  643. break;
  644. case 32:
  645. val_len |= NAU8810_WLEN_32;
  646. break;
  647. }
  648. switch (params_rate(params)) {
  649. case 8000:
  650. val_rate |= NAU8810_SMPLR_8K;
  651. break;
  652. case 11025:
  653. val_rate |= NAU8810_SMPLR_12K;
  654. break;
  655. case 16000:
  656. val_rate |= NAU8810_SMPLR_16K;
  657. break;
  658. case 22050:
  659. val_rate |= NAU8810_SMPLR_24K;
  660. break;
  661. case 32000:
  662. val_rate |= NAU8810_SMPLR_32K;
  663. break;
  664. case 44100:
  665. case 48000:
  666. break;
  667. }
  668. regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
  669. NAU8810_WLEN_MASK, val_len);
  670. regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR,
  671. NAU8810_SMPLR_MASK, val_rate);
  672. /* If the master clock is from MCLK, provide the runtime FS for driver
  673. * to get the master clock prescaler configuration.
  674. */
  675. if (nau8810->clk_id == NAU8810_SCLK_MCLK) {
  676. ret = nau8810_mclk_clkdiv(nau8810, params_rate(params));
  677. if (ret < 0)
  678. dev_err(nau8810->dev, "MCLK div configuration fail\n");
  679. }
  680. return ret;
  681. }
  682. static int nau8810_set_bias_level(struct snd_soc_component *component,
  683. enum snd_soc_bias_level level)
  684. {
  685. struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
  686. struct regmap *map = nau8810->regmap;
  687. switch (level) {
  688. case SND_SOC_BIAS_ON:
  689. case SND_SOC_BIAS_PREPARE:
  690. regmap_update_bits(map, NAU8810_REG_POWER1,
  691. NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K);
  692. break;
  693. case SND_SOC_BIAS_STANDBY:
  694. regmap_update_bits(map, NAU8810_REG_POWER1,
  695. NAU8810_IOBUF_EN | NAU8810_ABIAS_EN,
  696. NAU8810_IOBUF_EN | NAU8810_ABIAS_EN);
  697. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  698. regcache_sync(map);
  699. regmap_update_bits(map, NAU8810_REG_POWER1,
  700. NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K);
  701. mdelay(100);
  702. }
  703. regmap_update_bits(map, NAU8810_REG_POWER1,
  704. NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K);
  705. break;
  706. case SND_SOC_BIAS_OFF:
  707. regmap_write(map, NAU8810_REG_POWER1, 0);
  708. regmap_write(map, NAU8810_REG_POWER2, 0);
  709. regmap_write(map, NAU8810_REG_POWER3, 0);
  710. break;
  711. }
  712. return 0;
  713. }
  714. #define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000)
  715. #define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  716. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  717. static const struct snd_soc_dai_ops nau8810_ops = {
  718. .hw_params = nau8810_pcm_hw_params,
  719. .set_fmt = nau8810_set_dai_fmt,
  720. .set_sysclk = nau8810_set_sysclk,
  721. .set_pll = nau8810_set_pll,
  722. };
  723. static struct snd_soc_dai_driver nau8810_dai = {
  724. .name = "nau8810-hifi",
  725. .playback = {
  726. .stream_name = "Playback",
  727. .channels_min = 1,
  728. .channels_max = 2, /* Only 1 channel of data */
  729. .rates = NAU8810_RATES,
  730. .formats = NAU8810_FORMATS,
  731. },
  732. .capture = {
  733. .stream_name = "Capture",
  734. .channels_min = 1,
  735. .channels_max = 2, /* Only 1 channel of data */
  736. .rates = NAU8810_RATES,
  737. .formats = NAU8810_FORMATS,
  738. },
  739. .ops = &nau8810_ops,
  740. .symmetric_rates = 1,
  741. };
  742. static const struct regmap_config nau8810_regmap_config = {
  743. .reg_bits = 7,
  744. .val_bits = 9,
  745. .max_register = NAU8810_REG_MAX,
  746. .readable_reg = nau8810_readable_reg,
  747. .writeable_reg = nau8810_writeable_reg,
  748. .volatile_reg = nau8810_volatile_reg,
  749. .cache_type = REGCACHE_RBTREE,
  750. .reg_defaults = nau8810_reg_defaults,
  751. .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults),
  752. };
  753. static const struct snd_soc_component_driver nau8810_component_driver = {
  754. .set_bias_level = nau8810_set_bias_level,
  755. .controls = nau8810_snd_controls,
  756. .num_controls = ARRAY_SIZE(nau8810_snd_controls),
  757. .dapm_widgets = nau8810_dapm_widgets,
  758. .num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets),
  759. .dapm_routes = nau8810_dapm_routes,
  760. .num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes),
  761. .suspend_bias_off = 1,
  762. .idle_bias_on = 1,
  763. .use_pmdown_time = 1,
  764. .endianness = 1,
  765. .non_legacy_dai_naming = 1,
  766. };
  767. static int nau8810_i2c_probe(struct i2c_client *i2c,
  768. const struct i2c_device_id *id)
  769. {
  770. struct device *dev = &i2c->dev;
  771. struct nau8810 *nau8810 = dev_get_platdata(dev);
  772. if (!nau8810) {
  773. nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL);
  774. if (!nau8810)
  775. return -ENOMEM;
  776. }
  777. i2c_set_clientdata(i2c, nau8810);
  778. nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config);
  779. if (IS_ERR(nau8810->regmap))
  780. return PTR_ERR(nau8810->regmap);
  781. nau8810->dev = dev;
  782. regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00);
  783. return devm_snd_soc_register_component(dev,
  784. &nau8810_component_driver, &nau8810_dai, 1);
  785. }
  786. static const struct i2c_device_id nau8810_i2c_id[] = {
  787. { "nau8810", 0 },
  788. { "nau8812", 0 },
  789. { "nau8814", 0 },
  790. { }
  791. };
  792. MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id);
  793. #ifdef CONFIG_OF
  794. static const struct of_device_id nau8810_of_match[] = {
  795. { .compatible = "nuvoton,nau8810", },
  796. { .compatible = "nuvoton,nau8812", },
  797. { .compatible = "nuvoton,nau8814", },
  798. { }
  799. };
  800. MODULE_DEVICE_TABLE(of, nau8810_of_match);
  801. #endif
  802. static struct i2c_driver nau8810_i2c_driver = {
  803. .driver = {
  804. .name = "nau8810",
  805. .of_match_table = of_match_ptr(nau8810_of_match),
  806. },
  807. .probe = nau8810_i2c_probe,
  808. .id_table = nau8810_i2c_id,
  809. };
  810. module_i2c_driver(nau8810_i2c_driver);
  811. MODULE_DESCRIPTION("ASoC NAU8810 driver");
  812. MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
  813. MODULE_LICENSE("GPL v2");