nau8540.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * NAU85L40 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Nuvoton Technology Corp.
  6. * Author: John Hsu <KCHSU0@nuvoton.com>
  7. */
  8. #ifndef __NAU8540_H__
  9. #define __NAU8540_H__
  10. #define NAU8540_REG_SW_RESET 0x00
  11. #define NAU8540_REG_POWER_MANAGEMENT 0x01
  12. #define NAU8540_REG_CLOCK_CTRL 0x02
  13. #define NAU8540_REG_CLOCK_SRC 0x03
  14. #define NAU8540_REG_FLL1 0x04
  15. #define NAU8540_REG_FLL2 0x05
  16. #define NAU8540_REG_FLL3 0x06
  17. #define NAU8540_REG_FLL4 0x07
  18. #define NAU8540_REG_FLL5 0x08
  19. #define NAU8540_REG_FLL6 0x09
  20. #define NAU8540_REG_FLL_VCO_RSV 0x0A
  21. #define NAU8540_REG_PCM_CTRL0 0x10
  22. #define NAU8540_REG_PCM_CTRL1 0x11
  23. #define NAU8540_REG_PCM_CTRL2 0x12
  24. #define NAU8540_REG_PCM_CTRL3 0x13
  25. #define NAU8540_REG_PCM_CTRL4 0x14
  26. #define NAU8540_REG_ALC_CONTROL_1 0x20
  27. #define NAU8540_REG_ALC_CONTROL_2 0x21
  28. #define NAU8540_REG_ALC_CONTROL_3 0x22
  29. #define NAU8540_REG_ALC_CONTROL_4 0x23
  30. #define NAU8540_REG_ALC_CONTROL_5 0x24
  31. #define NAU8540_REG_ALC_GAIN_CH12 0x2D
  32. #define NAU8540_REG_ALC_GAIN_CH34 0x2E
  33. #define NAU8540_REG_ALC_STATUS 0x2F
  34. #define NAU8540_REG_NOTCH_FIL1_CH1 0x30
  35. #define NAU8540_REG_NOTCH_FIL2_CH1 0x31
  36. #define NAU8540_REG_NOTCH_FIL1_CH2 0x32
  37. #define NAU8540_REG_NOTCH_FIL2_CH2 0x33
  38. #define NAU8540_REG_NOTCH_FIL1_CH3 0x34
  39. #define NAU8540_REG_NOTCH_FIL2_CH3 0x35
  40. #define NAU8540_REG_NOTCH_FIL1_CH4 0x36
  41. #define NAU8540_REG_NOTCH_FIL2_CH4 0x37
  42. #define NAU8540_REG_HPF_FILTER_CH12 0x38
  43. #define NAU8540_REG_HPF_FILTER_CH34 0x39
  44. #define NAU8540_REG_ADC_SAMPLE_RATE 0x3A
  45. #define NAU8540_REG_DIGITAL_GAIN_CH1 0x40
  46. #define NAU8540_REG_DIGITAL_GAIN_CH2 0x41
  47. #define NAU8540_REG_DIGITAL_GAIN_CH3 0x42
  48. #define NAU8540_REG_DIGITAL_GAIN_CH4 0x43
  49. #define NAU8540_REG_DIGITAL_MUX 0x44
  50. #define NAU8540_REG_P2P_CH1 0x48
  51. #define NAU8540_REG_P2P_CH2 0x49
  52. #define NAU8540_REG_P2P_CH3 0x4A
  53. #define NAU8540_REG_P2P_CH4 0x4B
  54. #define NAU8540_REG_PEAK_CH1 0x4C
  55. #define NAU8540_REG_PEAK_CH2 0x4D
  56. #define NAU8540_REG_PEAK_CH3 0x4E
  57. #define NAU8540_REG_PEAK_CH4 0x4F
  58. #define NAU8540_REG_GPIO_CTRL 0x50
  59. #define NAU8540_REG_MISC_CTRL 0x51
  60. #define NAU8540_REG_I2C_CTRL 0x52
  61. #define NAU8540_REG_I2C_DEVICE_ID 0x58
  62. #define NAU8540_REG_RST 0x5A
  63. #define NAU8540_REG_VMID_CTRL 0x60
  64. #define NAU8540_REG_MUTE 0x61
  65. #define NAU8540_REG_ANALOG_ADC1 0x64
  66. #define NAU8540_REG_ANALOG_ADC2 0x65
  67. #define NAU8540_REG_ANALOG_PWR 0x66
  68. #define NAU8540_REG_MIC_BIAS 0x67
  69. #define NAU8540_REG_REFERENCE 0x68
  70. #define NAU8540_REG_FEPGA1 0x69
  71. #define NAU8540_REG_FEPGA2 0x6A
  72. #define NAU8540_REG_FEPGA3 0x6B
  73. #define NAU8540_REG_FEPGA4 0x6C
  74. #define NAU8540_REG_PWR 0x6D
  75. #define NAU8540_REG_MAX NAU8540_REG_PWR
  76. /* POWER_MANAGEMENT (0x01) */
  77. #define NAU8540_ADC4_EN (0x1 << 3)
  78. #define NAU8540_ADC3_EN (0x1 << 2)
  79. #define NAU8540_ADC2_EN (0x1 << 1)
  80. #define NAU8540_ADC1_EN 0x1
  81. /* CLOCK_CTRL (0x02) */
  82. #define NAU8540_CLK_ADC_EN (0x1 << 15)
  83. #define NAU8540_CLK_I2S_EN (0x1 << 1)
  84. /* CLOCK_SRC (0x03) */
  85. #define NAU8540_CLK_SRC_SFT 15
  86. #define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT)
  87. #define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT)
  88. #define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT)
  89. #define NAU8540_CLK_ADC_SRC_SFT 6
  90. #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)
  91. #define NAU8540_CLK_MCLK_SRC_MASK 0xf
  92. /* FLL1 (0x04) */
  93. #define NAU8540_ICTRL_LATCH_SFT 10
  94. #define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT)
  95. #define NAU8540_FLL_RATIO_MASK 0x7f
  96. /* FLL3 (0x06) */
  97. #define NAU8540_GAIN_ERR_SFT 12
  98. #define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT)
  99. #define NAU8540_FLL_CLK_SRC_SFT 10
  100. #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
  101. #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
  102. #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
  103. #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)
  104. #define NAU8540_FLL_INTEGER_MASK 0x3ff
  105. /* FLL4 (0x07) */
  106. #define NAU8540_FLL_REF_DIV_SFT 10
  107. #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)
  108. /* FLL5 (0x08) */
  109. #define NAU8540_FLL_PDB_DAC_EN (0x1 << 15)
  110. #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
  111. #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
  112. #define NAU8540_FLL_CLK_SW_N2 (0x1 << 13)
  113. #define NAU8540_FLL_CLK_SW_REF (0x0 << 13)
  114. #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
  115. #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
  116. #define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12)
  117. /* FLL6 (0x9) */
  118. #define NAU8540_DCO_EN (0x1 << 15)
  119. #define NAU8540_SDM_EN (0x1 << 14)
  120. #define NAU8540_CUTOFF500 (0x1 << 13)
  121. /* PCM_CTRL0 (0x10) */
  122. #define NAU8540_I2S_BP_SFT 7
  123. #define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT)
  124. #define NAU8540_I2S_PCMB_SFT 6
  125. #define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT)
  126. #define NAU8540_I2S_DL_SFT 2
  127. #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)
  128. #define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT)
  129. #define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT)
  130. #define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT)
  131. #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)
  132. #define NAU8540_I2S_DF_MASK 0x3
  133. #define NAU8540_I2S_DF_RIGTH 0
  134. #define NAU8540_I2S_DF_LEFT 0x1
  135. #define NAU8540_I2S_DF_I2S 0x2
  136. #define NAU8540_I2S_DF_PCM_AB 0x3
  137. /* PCM_CTRL1 (0x11) */
  138. #define NAU8540_I2S_DO12_TRI (0x1 << 15)
  139. #define NAU8540_I2S_LRC_DIV_SFT 12
  140. #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
  141. #define NAU8540_I2S_DO12_OE (0x1 << 4)
  142. #define NAU8540_I2S_MS_SFT 3
  143. #define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT)
  144. #define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT)
  145. #define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT)
  146. #define NAU8540_I2S_BLK_DIV_MASK 0x7
  147. /* PCM_CTRL1 (0x12) */
  148. #define NAU8540_I2S_DO34_TRI (0x1 << 15)
  149. #define NAU8540_I2S_DO34_OE (0x1 << 11)
  150. #define NAU8540_I2S_TSLOT_L_MASK 0x3ff
  151. /* PCM_CTRL4 (0x14) */
  152. #define NAU8540_TDM_MODE (0x1 << 15)
  153. #define NAU8540_TDM_OFFSET_EN (0x1 << 14)
  154. #define NAU8540_TDM_TX_MASK 0xf
  155. /* ADC_SAMPLE_RATE (0x3A) */
  156. #define NAU8540_CH_SYNC (0x1 << 14)
  157. #define NAU8540_ADC_OSR_MASK 0x3
  158. #define NAU8540_ADC_OSR_256 0x3
  159. #define NAU8540_ADC_OSR_128 0x2
  160. #define NAU8540_ADC_OSR_64 0x1
  161. #define NAU8540_ADC_OSR_32 0x0
  162. /* VMID_CTRL (0x60) */
  163. #define NAU8540_VMID_EN (1 << 6)
  164. #define NAU8540_VMID_SEL_SFT 4
  165. #define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT)
  166. /* MIC_BIAS (0x67) */
  167. #define NAU8540_PU_PRE (0x1 << 8)
  168. /* REFERENCE (0x68) */
  169. #define NAU8540_PRECHARGE_DIS (0x1 << 13)
  170. #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
  171. /* FEPGA1 (0x69) */
  172. #define NAU8540_FEPGA1_MODCH2_SHT_SFT 7
  173. #define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
  174. #define NAU8540_FEPGA1_MODCH1_SHT_SFT 3
  175. #define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
  176. /* FEPGA2 (0x6A) */
  177. #define NAU8540_FEPGA2_MODCH4_SHT_SFT 7
  178. #define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
  179. #define NAU8540_FEPGA2_MODCH3_SHT_SFT 3
  180. #define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
  181. /* System Clock Source */
  182. enum {
  183. NAU8540_CLK_DIS,
  184. NAU8540_CLK_MCLK,
  185. NAU8540_CLK_INTERNAL,
  186. NAU8540_CLK_FLL_MCLK,
  187. NAU8540_CLK_FLL_BLK,
  188. NAU8540_CLK_FLL_FS,
  189. };
  190. struct nau8540 {
  191. struct device *dev;
  192. struct regmap *regmap;
  193. };
  194. struct nau8540_fll {
  195. int mclk_src;
  196. int ratio;
  197. int fll_frac;
  198. int fll_int;
  199. int clk_ref_div;
  200. };
  201. struct nau8540_fll_attr {
  202. unsigned int param;
  203. unsigned int val;
  204. };
  205. /* over sampling rate */
  206. struct nau8540_osr_attr {
  207. unsigned int osr;
  208. unsigned int clk_src;
  209. };
  210. #endif /* __NAU8540_H__ */