mt6359.h 97 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. * Author: Argus Lin <argus.lin@mediatek.com>
  5. */
  6. #ifndef _MT6359_H_
  7. #define _MT6359_H_
  8. /*************Register Bit Define*************/
  9. #define PMIC_ACCDET_IRQ_SHIFT 0
  10. #define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
  11. #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
  12. #define PMIC_ACCDET_IRQ_CLR_SHIFT 8
  13. #define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT 10
  14. #define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT 11
  15. #define PMIC_RG_INT_STATUS_ACCDET_SHIFT 5
  16. #define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6
  17. #define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7
  18. #define PMIC_RG_EINT0CONFIGACCDET_SHIFT 11
  19. #define PMIC_RG_EINT1CONFIGACCDET_SHIFT 0
  20. #define PMIC_ACCDET_EINT0_INVERTER_SW_EN_SHIFT 6
  21. #define PMIC_ACCDET_EINT1_INVERTER_SW_EN_SHIFT 8
  22. #define PMIC_RG_MTEST_EN_SHIFT 8
  23. #define PMIC_RG_MTEST_SEL_SHIFT 9
  24. #define PMIC_ACCDET_EINT0_M_SW_EN_SHIFT 10
  25. #define PMIC_ACCDET_EINT1_M_SW_EN_SHIFT 11
  26. #define PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT 5
  27. #define PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT 10
  28. #define PMIC_ACCDET_DA_STABLE_SHIFT 0
  29. #define PMIC_ACCDET_EINT0_EN_STABLE_SHIFT 1
  30. #define PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT 2
  31. #define PMIC_ACCDET_EINT1_EN_STABLE_SHIFT 6
  32. #define PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT 7
  33. #define PMIC_ACCDET_EINT_CTURBO_SEL_SHIFT 7
  34. #define PMIC_ACCDET_EINT0_CTURBO_SW_SHIFT 7
  35. #define PMIC_RG_EINTCOMPVTH_SHIFT 4
  36. #define PMIC_RG_EINT0HIRENB_SHIFT 12
  37. #define PMIC_RG_EINT0NOHYS_SHIFT 10
  38. #define PMIC_ACCDET_SW_EN_SHIFT 0
  39. #define PMIC_ACCDET_EINT0_MEM_IN_SHIFT 6
  40. #define PMIC_ACCDET_MEM_IN_SHIFT 6
  41. #define PMIC_ACCDET_EINT_DEBOUNCE0_SHIFT 0
  42. #define PMIC_ACCDET_EINT_DEBOUNCE1_SHIFT 4
  43. #define PMIC_ACCDET_EINT_DEBOUNCE2_SHIFT 8
  44. #define PMIC_ACCDET_EINT_DEBOUNCE3_SHIFT 12
  45. #define PMIC_RG_ACCDET2AUXSWEN_SHIFT 14
  46. #define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 9
  47. #define PMIC_AUDACCDETAUXADCSWCTRL_SW_SHIFT 10
  48. #define PMIC_RG_EINT0CTURBO_SHIFT 5
  49. #define PMIC_RG_EINT1CTURBO_SHIFT 13
  50. #define PMIC_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT 12
  51. #define PMIC_ACCDET_EINT_M_DETECT_EN_SHIFT 12
  52. #define PMIC_ACCDET_EINT0_SW_EN_SHIFT 2
  53. #define PMIC_ACCDET_EINT1_SW_EN_SHIFT 4
  54. #define PMIC_ACCDET_EINT_CMPMOUT_SEL_SHIFT 12
  55. #define PMIC_ACCDET_EINT_CMPMEN_SEL_SHIFT 6
  56. #define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT 0
  57. #define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT 4
  58. #define PMIC_RG_EINT0EN_SHIFT 2
  59. #define PMIC_RG_EINT1EN_SHIFT 10
  60. #define PMIC_RG_NCP_PDDIS_EN_SHIFT 0
  61. #define PMIC_RG_ACCDETSPARE_SHIFT 0
  62. #define PMIC_RG_ACCDET_RST_SHIFT 1
  63. #define PMIC_RG_AUDMICBIAS1HVEN_SHIFT 12
  64. #define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4
  65. #define PMIC_RG_ANALOGFDEN_SHIFT 12
  66. #define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT 8
  67. #define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2
  68. #define PMIC_ACCDET_SEQ_INIT_SHIFT 1
  69. #define PMIC_RG_EINTCOMPVTH_MASK 0xf
  70. #define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x3
  71. #define PMIC_ACCDET_EINT_DEBOUNCE0_MASK 0xf
  72. #define PMIC_ACCDET_EINT_DEBOUNCE1_MASK 0xf
  73. #define PMIC_ACCDET_EINT_DEBOUNCE2_MASK 0xf
  74. #define PMIC_ACCDET_EINT_DEBOUNCE3_MASK 0xf
  75. #define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
  76. #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
  77. /* AUDENC_ANA_CON16: */
  78. #define RG_AUD_MICBIAS1_LOWP_EN BIT(PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT)
  79. /* AUDENC_ANA_CON18: */
  80. #define RG_ACCDET_MODE_ANA11_MODE1 (0x000f)
  81. #define RG_ACCDET_MODE_ANA11_MODE2 (0x008f)
  82. #define RG_ACCDET_MODE_ANA11_MODE6 (0x008f)
  83. /* AUXADC_ADC5: Auxadc CH5 read data */
  84. #define AUXADC_DATA_RDY_CH5 BIT(15)
  85. #define AUXADC_DATA_PROCEED_CH5 BIT(15)
  86. #define AUXADC_DATA_MASK (0x0fff)
  87. /* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
  88. #define AUXADC_RQST_CH5_SET BIT(5)
  89. /* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
  90. #define AUXADC_RQST_CH5_CLR BIT(5)
  91. #define ACCDET_CALI_MASK0 (0xff)
  92. #define ACCDET_CALI_MASK1 (0xff << 8)
  93. #define ACCDET_CALI_MASK2 (0xff)
  94. #define ACCDET_CALI_MASK3 (0xff << 8)
  95. #define ACCDET_CALI_MASK4 (0xff)
  96. #define ACCDET_EINT1_IRQ_CLR_B11 BIT(PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT)
  97. #define ACCDET_EINT0_IRQ_CLR_B10 BIT(PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
  98. #define ACCDET_EINT_IRQ_CLR_B10_11 (0x03 << \
  99. PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
  100. #define ACCDET_IRQ_CLR_B8 BIT(PMIC_ACCDET_IRQ_CLR_SHIFT)
  101. #define ACCDET_EINT1_IRQ_B3 BIT(PMIC_ACCDET_EINT1_IRQ_SHIFT)
  102. #define ACCDET_EINT0_IRQ_B2 BIT(PMIC_ACCDET_EINT0_IRQ_SHIFT)
  103. #define ACCDET_EINT_IRQ_B2_B3 (0x03 << PMIC_ACCDET_EINT0_IRQ_SHIFT)
  104. #define ACCDET_IRQ_B0 BIT(PMIC_ACCDET_IRQ_SHIFT)
  105. /* ACCDET_CON25: RO, accdet FSM state,etc.*/
  106. #define ACCDET_STATE_MEM_IN_OFFSET (PMIC_ACCDET_MEM_IN_SHIFT)
  107. #define ACCDET_STATE_AB_MASK (0x03)
  108. #define ACCDET_STATE_AB_00 (0x00)
  109. #define ACCDET_STATE_AB_01 (0x01)
  110. #define ACCDET_STATE_AB_10 (0x02)
  111. #define ACCDET_STATE_AB_11 (0x03)
  112. /* ACCDET_CON19 */
  113. #define ACCDET_EINT0_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
  114. (1 << PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \
  115. (1 << PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \
  116. (1 << PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT))
  117. #define ACCDET_EINT1_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
  118. (1 << PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \
  119. (1 << PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \
  120. (1 << PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT))
  121. /* The following are used for mt6359.c */
  122. /* MT6359_DCXO_CW12 */
  123. #define RG_XO_AUDIO_EN_M_SFT 13
  124. /* LDO_VAUD18_CON0 */
  125. #define RG_LDO_VAUD18_EN_SFT 0
  126. #define RG_LDO_VAUD18_EN_MASK 0x1
  127. #define RG_LDO_VAUD18_EN_MASK_SFT (0x1 << 0)
  128. /* AUD_TOP_CKPDN_CON0 */
  129. #define RG_VOW13M_CK_PDN_SFT 13
  130. #define RG_VOW13M_CK_PDN_MASK 0x1
  131. #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
  132. #define RG_VOW32K_CK_PDN_SFT 12
  133. #define RG_VOW32K_CK_PDN_MASK 0x1
  134. #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
  135. #define RG_AUD_INTRP_CK_PDN_SFT 8
  136. #define RG_AUD_INTRP_CK_PDN_MASK 0x1
  137. #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
  138. #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT 7
  139. #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
  140. #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
  141. #define RG_AUDNCP_CK_PDN_SFT 6
  142. #define RG_AUDNCP_CK_PDN_MASK 0x1
  143. #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
  144. #define RG_ZCD13M_CK_PDN_SFT 5
  145. #define RG_ZCD13M_CK_PDN_MASK 0x1
  146. #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
  147. #define RG_AUDIF_CK_PDN_SFT 2
  148. #define RG_AUDIF_CK_PDN_MASK 0x1
  149. #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
  150. #define RG_AUD_CK_PDN_SFT 1
  151. #define RG_AUD_CK_PDN_MASK 0x1
  152. #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
  153. #define RG_ACCDET_CK_PDN_SFT 0
  154. #define RG_ACCDET_CK_PDN_MASK 0x1
  155. #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
  156. /* AUD_TOP_CKPDN_CON0_SET */
  157. #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0
  158. #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff
  159. #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)
  160. /* AUD_TOP_CKPDN_CON0_CLR */
  161. #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0
  162. #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff
  163. #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)
  164. /* AUD_TOP_CKSEL_CON0 */
  165. #define RG_AUDIF_CK_CKSEL_SFT 3
  166. #define RG_AUDIF_CK_CKSEL_MASK 0x1
  167. #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
  168. #define RG_AUD_CK_CKSEL_SFT 2
  169. #define RG_AUD_CK_CKSEL_MASK 0x1
  170. #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
  171. /* AUD_TOP_CKSEL_CON0_SET */
  172. #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0
  173. #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf
  174. #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)
  175. /* AUD_TOP_CKSEL_CON0_CLR */
  176. #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0
  177. #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf
  178. #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)
  179. /* AUD_TOP_CKTST_CON0 */
  180. #define RG_VOW13M_CK_TSTSEL_SFT 9
  181. #define RG_VOW13M_CK_TSTSEL_MASK 0x1
  182. #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
  183. #define RG_VOW13M_CK_TST_DIS_SFT 8
  184. #define RG_VOW13M_CK_TST_DIS_MASK 0x1
  185. #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
  186. #define RG_AUD26M_CK_TSTSEL_SFT 4
  187. #define RG_AUD26M_CK_TSTSEL_MASK 0x1
  188. #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
  189. #define RG_AUDIF_CK_TSTSEL_SFT 3
  190. #define RG_AUDIF_CK_TSTSEL_MASK 0x1
  191. #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
  192. #define RG_AUD_CK_TSTSEL_SFT 2
  193. #define RG_AUD_CK_TSTSEL_MASK 0x1
  194. #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
  195. #define RG_AUD26M_CK_TST_DIS_SFT 0
  196. #define RG_AUD26M_CK_TST_DIS_MASK 0x1
  197. #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
  198. /* AUD_TOP_CLK_HWEN_CON0 */
  199. #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0
  200. #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
  201. #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
  202. /* AUD_TOP_CLK_HWEN_CON0_SET */
  203. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0
  204. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff
  205. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)
  206. /* AUD_TOP_CLK_HWEN_CON0_CLR */
  207. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0
  208. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff
  209. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)
  210. /* AUD_TOP_RST_CON0 */
  211. #define RG_AUDNCP_RST_SFT 3
  212. #define RG_AUDNCP_RST_MASK 0x1
  213. #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
  214. #define RG_ZCD_RST_SFT 2
  215. #define RG_ZCD_RST_MASK 0x1
  216. #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
  217. #define RG_ACCDET_RST_SFT 1
  218. #define RG_ACCDET_RST_MASK 0x1
  219. #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
  220. #define RG_AUDIO_RST_SFT 0
  221. #define RG_AUDIO_RST_MASK 0x1
  222. #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
  223. /* AUD_TOP_RST_CON0_SET */
  224. #define RG_AUD_TOP_RST_CON0_SET_SFT 0
  225. #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf
  226. #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)
  227. /* AUD_TOP_RST_CON0_CLR */
  228. #define RG_AUD_TOP_RST_CON0_CLR_SFT 0
  229. #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf
  230. #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)
  231. /* AUD_TOP_RST_BANK_CON0 */
  232. #define BANK_AUDZCD_SWRST_SFT 2
  233. #define BANK_AUDZCD_SWRST_MASK 0x1
  234. #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
  235. #define BANK_AUDIO_SWRST_SFT 1
  236. #define BANK_AUDIO_SWRST_MASK 0x1
  237. #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
  238. #define BANK_ACCDET_SWRST_SFT 0
  239. #define BANK_ACCDET_SWRST_MASK 0x1
  240. #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
  241. /* AFE_UL_DL_CON0 */
  242. #define AFE_UL_LR_SWAP_SFT 15
  243. #define AFE_UL_LR_SWAP_MASK 0x1
  244. #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
  245. #define AFE_DL_LR_SWAP_SFT 14
  246. #define AFE_DL_LR_SWAP_MASK 0x1
  247. #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
  248. #define AFE_ON_SFT 0
  249. #define AFE_ON_MASK 0x1
  250. #define AFE_ON_MASK_SFT (0x1 << 0)
  251. /* AFE_DL_SRC2_CON0_L */
  252. #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
  253. #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
  254. #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
  255. /* AFE_UL_SRC_CON0_H */
  256. #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11
  257. #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
  258. #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
  259. #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8
  260. #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
  261. #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
  262. #define C_TWO_DIGITAL_MIC_CTL_SFT 7
  263. #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
  264. #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
  265. /* AFE_UL_SRC_CON0_L */
  266. #define DMIC_LOW_POWER_MODE_CTL_SFT 14
  267. #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
  268. #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
  269. #define DIGMIC_4P33M_SEL_CTL_SFT 6
  270. #define DIGMIC_4P33M_SEL_CTL_MASK 0x1
  271. #define DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
  272. #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
  273. #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
  274. #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
  275. #define UL_LOOP_BACK_MODE_CTL_SFT 2
  276. #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
  277. #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
  278. #define UL_SDM_3_LEVEL_CTL_SFT 1
  279. #define UL_SDM_3_LEVEL_CTL_MASK 0x1
  280. #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
  281. #define UL_SRC_ON_TMP_CTL_SFT 0
  282. #define UL_SRC_ON_TMP_CTL_MASK 0x1
  283. #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
  284. /* AFE_ADDA6_L_SRC_CON0_H */
  285. #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11
  286. #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
  287. #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
  288. #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8
  289. #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
  290. #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
  291. #define ADDA6_C_TWO_DIGITAL_MIC_CTL_SFT 7
  292. #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
  293. #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
  294. /* AFE_ADDA6_UL_SRC_CON0_L */
  295. #define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT 14
  296. #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
  297. #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
  298. #define ADDA6_DIGMIC_4P33M_SEL_CTL_SFT 6
  299. #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK 0x1
  300. #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
  301. #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
  302. #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
  303. #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
  304. #define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT 2
  305. #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x1
  306. #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
  307. #define ADDA6_UL_SDM_3_LEVEL_CTL_SFT 1
  308. #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x1
  309. #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
  310. #define ADDA6_UL_SRC_ON_TMP_CTL_SFT 0
  311. #define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x1
  312. #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
  313. /* AFE_TOP_CON0 */
  314. #define ADDA6_MTKAIF_SINE_ON_SFT 4
  315. #define ADDA6_MTKAIF_SINE_ON_MASK 0x1
  316. #define ADDA6_MTKAIF_SINE_ON_MASK_SFT (0x1 << 4)
  317. #define ADDA6_UL_SINE_ON_SFT 3
  318. #define ADDA6_UL_SINE_ON_MASK 0x1
  319. #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
  320. #define MTKAIF_SINE_ON_SFT 2
  321. #define MTKAIF_SINE_ON_MASK 0x1
  322. #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
  323. #define UL_SINE_ON_SFT 1
  324. #define UL_SINE_ON_MASK 0x1
  325. #define UL_SINE_ON_MASK_SFT (0x1 << 1)
  326. #define DL_SINE_ON_SFT 0
  327. #define DL_SINE_ON_MASK 0x1
  328. #define DL_SINE_ON_MASK_SFT (0x1 << 0)
  329. /* AUDIO_TOP_CON0 */
  330. #define PDN_AFE_CTL_SFT 7
  331. #define PDN_AFE_CTL_MASK 0x1
  332. #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
  333. #define PDN_DAC_CTL_SFT 6
  334. #define PDN_DAC_CTL_MASK 0x1
  335. #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
  336. #define PDN_ADC_CTL_SFT 5
  337. #define PDN_ADC_CTL_MASK 0x1
  338. #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
  339. #define PDN_ADDA6_ADC_CTL_SFT 4
  340. #define PDN_ADDA6_ADC_CTL_MASK 0x1
  341. #define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4)
  342. #define PDN_I2S_DL_CTL_SFT 3
  343. #define PDN_I2S_DL_CTL_MASK 0x1
  344. #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
  345. #define PWR_CLK_DIS_CTL_SFT 2
  346. #define PWR_CLK_DIS_CTL_MASK 0x1
  347. #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
  348. #define PDN_AFE_TESTMODEL_CTL_SFT 1
  349. #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
  350. #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
  351. #define PDN_RESERVED_SFT 0
  352. #define PDN_RESERVED_MASK 0x1
  353. #define PDN_RESERVED_MASK_SFT (0x1 << 0)
  354. /* AFE_MON_DEBUG0 */
  355. #define AUDIO_SYS_TOP_MON_SWAP_SFT 14
  356. #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
  357. #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
  358. #define AUDIO_SYS_TOP_MON_SEL_SFT 8
  359. #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f
  360. #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)
  361. #define AFE_MON_SEL_SFT 0
  362. #define AFE_MON_SEL_MASK 0xff
  363. #define AFE_MON_SEL_MASK_SFT (0xff << 0)
  364. /* AFUNC_AUD_CON0 */
  365. #define CCI_AUD_ANACK_SEL_SFT 15
  366. #define CCI_AUD_ANACK_SEL_MASK 0x1
  367. #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
  368. #define CCI_AUDIO_FIFO_WPTR_SFT 12
  369. #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
  370. #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
  371. #define CCI_SCRAMBLER_CG_EN_SFT 11
  372. #define CCI_SCRAMBLER_CG_EN_MASK 0x1
  373. #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
  374. #define CCI_LCH_INV_SFT 10
  375. #define CCI_LCH_INV_MASK 0x1
  376. #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
  377. #define CCI_RAND_EN_SFT 9
  378. #define CCI_RAND_EN_MASK 0x1
  379. #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
  380. #define CCI_SPLT_SCRMB_CLK_ON_SFT 8
  381. #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
  382. #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
  383. #define CCI_SPLT_SCRMB_ON_SFT 7
  384. #define CCI_SPLT_SCRMB_ON_MASK 0x1
  385. #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
  386. #define CCI_AUD_IDAC_TEST_EN_SFT 6
  387. #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
  388. #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
  389. #define CCI_ZERO_PAD_DISABLE_SFT 5
  390. #define CCI_ZERO_PAD_DISABLE_MASK 0x1
  391. #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
  392. #define CCI_AUD_SPLIT_TEST_EN_SFT 4
  393. #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
  394. #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
  395. #define CCI_AUD_SDM_MUTEL_SFT 3
  396. #define CCI_AUD_SDM_MUTEL_MASK 0x1
  397. #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
  398. #define CCI_AUD_SDM_MUTER_SFT 2
  399. #define CCI_AUD_SDM_MUTER_MASK 0x1
  400. #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
  401. #define CCI_AUD_SDM_7BIT_SEL_SFT 1
  402. #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
  403. #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
  404. #define CCI_SCRAMBLER_EN_SFT 0
  405. #define CCI_SCRAMBLER_EN_MASK 0x1
  406. #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
  407. /* AFUNC_AUD_CON1 */
  408. #define AUD_SDM_TEST_L_SFT 8
  409. #define AUD_SDM_TEST_L_MASK 0xff
  410. #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)
  411. #define AUD_SDM_TEST_R_SFT 0
  412. #define AUD_SDM_TEST_R_MASK 0xff
  413. #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)
  414. /* AFUNC_AUD_CON2 */
  415. #define CCI_AUD_DAC_ANA_MUTE_SFT 7
  416. #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
  417. #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
  418. #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6
  419. #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
  420. #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
  421. #define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4
  422. #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
  423. #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
  424. #define CCI_AUDIO_FIFO_ENABLE_SFT 3
  425. #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
  426. #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
  427. #define CCI_ACD_MODE_SFT 2
  428. #define CCI_ACD_MODE_MASK 0x1
  429. #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
  430. #define CCI_AFIFO_CLK_PWDB_SFT 1
  431. #define CCI_AFIFO_CLK_PWDB_MASK 0x1
  432. #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
  433. #define CCI_ACD_FUNC_RSTB_SFT 0
  434. #define CCI_ACD_FUNC_RSTB_MASK 0x1
  435. #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
  436. /* AFUNC_AUD_CON3 */
  437. #define SDM_ANA13M_TESTCK_SEL_SFT 15
  438. #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
  439. #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
  440. #define SDM_ANA13M_TESTCK_SRC_SEL_SFT 12
  441. #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
  442. #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
  443. #define SDM_TESTCK_SRC_SEL_SFT 8
  444. #define SDM_TESTCK_SRC_SEL_MASK 0x7
  445. #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
  446. #define DIGMIC_TESTCK_SRC_SEL_SFT 4
  447. #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
  448. #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
  449. #define DIGMIC_TESTCK_SEL_SFT 0
  450. #define DIGMIC_TESTCK_SEL_MASK 0x1
  451. #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
  452. /* AFUNC_AUD_CON4 */
  453. #define UL_FIFO_WCLK_INV_SFT 8
  454. #define UL_FIFO_WCLK_INV_MASK 0x1
  455. #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
  456. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6
  457. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
  458. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
  459. #define UL_FIFO_WDATA_TESTEN_SFT 5
  460. #define UL_FIFO_WDATA_TESTEN_MASK 0x1
  461. #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
  462. #define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4
  463. #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
  464. #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
  465. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
  466. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
  467. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
  468. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
  469. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
  470. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
  471. /* AFUNC_AUD_CON5 */
  472. #define R_AUD_DAC_POS_LARGE_MONO_SFT 8
  473. #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff
  474. #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)
  475. #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0
  476. #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff
  477. #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)
  478. /* AFUNC_AUD_CON6 */
  479. #define R_AUD_DAC_POS_SMALL_MONO_SFT 12
  480. #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf
  481. #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)
  482. #define R_AUD_DAC_NEG_SMALL_MONO_SFT 8
  483. #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf
  484. #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)
  485. #define R_AUD_DAC_POS_TINY_MONO_SFT 6
  486. #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
  487. #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
  488. #define R_AUD_DAC_NEG_TINY_MONO_SFT 4
  489. #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
  490. #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
  491. #define R_AUD_DAC_MONO_SEL_SFT 3
  492. #define R_AUD_DAC_MONO_SEL_MASK 0x1
  493. #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
  494. #define R_AUD_DAC_3TH_SEL_SFT 1
  495. #define R_AUD_DAC_3TH_SEL_MASK 0x1
  496. #define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1)
  497. #define R_AUD_DAC_SW_RSTB_SFT 0
  498. #define R_AUD_DAC_SW_RSTB_MASK 0x1
  499. #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
  500. /* AFUNC_AUD_CON7 */
  501. #define UL2_DIGMIC_TESTCK_SRC_SEL_SFT 10
  502. #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
  503. #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 10)
  504. #define UL2_DIGMIC_TESTCK_SEL_SFT 9
  505. #define UL2_DIGMIC_TESTCK_SEL_MASK 0x1
  506. #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 9)
  507. #define UL2_FIFO_WCLK_INV_SFT 8
  508. #define UL2_FIFO_WCLK_INV_MASK 0x1
  509. #define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
  510. #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6
  511. #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
  512. #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
  513. #define UL2_FIFO_WDATA_TESTEN_SFT 5
  514. #define UL2_FIFO_WDATA_TESTEN_MASK 0x1
  515. #define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
  516. #define UL2_FIFO_WDATA_TESTSRC_SEL_SFT 4
  517. #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
  518. #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
  519. #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
  520. #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
  521. #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
  522. #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
  523. #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
  524. #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
  525. /* AFUNC_AUD_CON8 */
  526. #define SPLITTER2_DITHER_EN_SFT 9
  527. #define SPLITTER2_DITHER_EN_MASK 0x1
  528. #define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
  529. #define SPLITTER1_DITHER_EN_SFT 8
  530. #define SPLITTER1_DITHER_EN_MASK 0x1
  531. #define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
  532. #define SPLITTER2_DITHER_GAIN_SFT 4
  533. #define SPLITTER2_DITHER_GAIN_MASK 0xf
  534. #define SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)
  535. #define SPLITTER1_DITHER_GAIN_SFT 0
  536. #define SPLITTER1_DITHER_GAIN_MASK 0xf
  537. #define SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)
  538. /* AFUNC_AUD_CON9 */
  539. #define CCI_AUD_ANACK_SEL_2ND_SFT 15
  540. #define CCI_AUD_ANACK_SEL_2ND_MASK 0x1
  541. #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 15)
  542. #define CCI_AUDIO_FIFO_WPTR_2ND_SFT 12
  543. #define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x7
  544. #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 12)
  545. #define CCI_SCRAMBLER_CG_EN_2ND_SFT 11
  546. #define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x1
  547. #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 11)
  548. #define CCI_LCH_INV_2ND_SFT 10
  549. #define CCI_LCH_INV_2ND_MASK 0x1
  550. #define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 10)
  551. #define CCI_RAND_EN_2ND_SFT 9
  552. #define CCI_RAND_EN_2ND_MASK 0x1
  553. #define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 9)
  554. #define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT 8
  555. #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x1
  556. #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 8)
  557. #define CCI_SPLT_SCRMB_ON_2ND_SFT 7
  558. #define CCI_SPLT_SCRMB_ON_2ND_MASK 0x1
  559. #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7)
  560. #define CCI_AUD_IDAC_TEST_EN_2ND_SFT 6
  561. #define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x1
  562. #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6)
  563. #define CCI_ZERO_PAD_DISABLE_2ND_SFT 5
  564. #define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x1
  565. #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5)
  566. #define CCI_AUD_SPLIT_TEST_EN_2ND_SFT 4
  567. #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x1
  568. #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4)
  569. #define CCI_AUD_SDM_MUTEL_2ND_SFT 3
  570. #define CCI_AUD_SDM_MUTEL_2ND_MASK 0x1
  571. #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
  572. #define CCI_AUD_SDM_MUTER_2ND_SFT 2
  573. #define CCI_AUD_SDM_MUTER_2ND_MASK 0x1
  574. #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2)
  575. #define CCI_AUD_SDM_7BIT_SEL_2ND_SFT 1
  576. #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x1
  577. #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1)
  578. #define CCI_SCRAMBLER_EN_2ND_SFT 0
  579. #define CCI_SCRAMBLER_EN_2ND_MASK 0x1
  580. #define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0)
  581. /* AFUNC_AUD_CON10 */
  582. #define AUD_SDM_TEST_L_2ND_SFT 8
  583. #define AUD_SDM_TEST_L_2ND_MASK 0xff
  584. #define AUD_SDM_TEST_L_2ND_MASK_SFT (0xff << 8)
  585. #define AUD_SDM_TEST_R_2ND_SFT 0
  586. #define AUD_SDM_TEST_R_2ND_MASK 0xff
  587. #define AUD_SDM_TEST_R_2ND_MASK_SFT (0xff << 0)
  588. /* AFUNC_AUD_CON11 */
  589. #define CCI_AUD_DAC_ANA_MUTE_2ND_SFT 7
  590. #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x1
  591. #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7)
  592. #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT 6
  593. #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x1
  594. #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6)
  595. #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT 4
  596. #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x1
  597. #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4)
  598. #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 3
  599. #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x1
  600. #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
  601. #define CCI_ACD_MODE_2ND_SFT 2
  602. #define CCI_ACD_MODE_2ND_MASK 0x1
  603. #define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2)
  604. #define CCI_AFIFO_CLK_PWDB_2ND_SFT 1
  605. #define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x1
  606. #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1)
  607. #define CCI_ACD_FUNC_RSTB_2ND_SFT 0
  608. #define CCI_ACD_FUNC_RSTB_2ND_MASK 0x1
  609. #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0)
  610. /* AFUNC_AUD_CON12 */
  611. #define SPLITTER2_DITHER_EN_2ND_SFT 9
  612. #define SPLITTER2_DITHER_EN_2ND_MASK 0x1
  613. #define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 9)
  614. #define SPLITTER1_DITHER_EN_2ND_SFT 8
  615. #define SPLITTER1_DITHER_EN_2ND_MASK 0x1
  616. #define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 8)
  617. #define SPLITTER2_DITHER_GAIN_2ND_SFT 4
  618. #define SPLITTER2_DITHER_GAIN_2ND_MASK 0xf
  619. #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT (0xf << 4)
  620. #define SPLITTER1_DITHER_GAIN_2ND_SFT 0
  621. #define SPLITTER1_DITHER_GAIN_2ND_MASK 0xf
  622. #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT (0xf << 0)
  623. /* AFUNC_AUD_MON0 */
  624. #define AUD_SCR_OUT_L_SFT 8
  625. #define AUD_SCR_OUT_L_MASK 0xff
  626. #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)
  627. #define AUD_SCR_OUT_R_SFT 0
  628. #define AUD_SCR_OUT_R_MASK 0xff
  629. #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)
  630. /* AFUNC_AUD_MON1 */
  631. #define AUD_SCR_OUT_L_2ND_SFT 8
  632. #define AUD_SCR_OUT_L_2ND_MASK 0xff
  633. #define AUD_SCR_OUT_L_2ND_MASK_SFT (0xff << 8)
  634. #define AUD_SCR_OUT_R_2ND_SFT 0
  635. #define AUD_SCR_OUT_R_2ND_MASK 0xff
  636. #define AUD_SCR_OUT_R_2ND_MASK_SFT (0xff << 0)
  637. /* AUDRC_TUNE_MON0 */
  638. #define ASYNC_TEST_OUT_BCK_SFT 15
  639. #define ASYNC_TEST_OUT_BCK_MASK 0x1
  640. #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
  641. #define RGS_AUDRCTUNE1READ_SFT 8
  642. #define RGS_AUDRCTUNE1READ_MASK 0x1f
  643. #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)
  644. #define RGS_AUDRCTUNE0READ_SFT 0
  645. #define RGS_AUDRCTUNE0READ_MASK 0x1f
  646. #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)
  647. /* AFE_ADDA_MTKAIF_FIFO_CFG0 */
  648. #define AFE_RESERVED_SFT 1
  649. #define AFE_RESERVED_MASK 0x7fff
  650. #define AFE_RESERVED_MASK_SFT (0x7fff << 1)
  651. #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0
  652. #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
  653. #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
  654. /* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */
  655. #define MTKAIF_RXIF_WR_FULL_STATUS_SFT 1
  656. #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
  657. #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
  658. #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0
  659. #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
  660. #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
  661. /* AFE_ADDA_MTKAIF_MON0 */
  662. #define MTKAIFTX_V3_SYNC_OUT_SFT 15
  663. #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
  664. #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 15)
  665. #define MTKAIFTX_V3_SDATA_OUT3_SFT 14
  666. #define MTKAIFTX_V3_SDATA_OUT3_MASK 0x1
  667. #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT (0x1 << 14)
  668. #define MTKAIFTX_V3_SDATA_OUT2_SFT 13
  669. #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
  670. #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
  671. #define MTKAIFTX_V3_SDATA_OUT1_SFT 12
  672. #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
  673. #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
  674. #define MTKAIF_RXIF_FIFO_STATUS_SFT 0
  675. #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff
  676. #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)
  677. /* AFE_ADDA_MTKAIF_MON1 */
  678. #define MTKAIFRX_V3_SYNC_IN_SFT 15
  679. #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
  680. #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 15)
  681. #define MTKAIFRX_V3_SDATA_IN3_SFT 14
  682. #define MTKAIFRX_V3_SDATA_IN3_MASK 0x1
  683. #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT (0x1 << 14)
  684. #define MTKAIFRX_V3_SDATA_IN2_SFT 13
  685. #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
  686. #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
  687. #define MTKAIFRX_V3_SDATA_IN1_SFT 12
  688. #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
  689. #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
  690. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 11
  691. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
  692. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
  693. #define MTKAIF_RXIF_INVALID_FLAG_SFT 8
  694. #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
  695. #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
  696. #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0
  697. #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff
  698. #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)
  699. /* AFE_ADDA_MTKAIF_MON2 */
  700. #define MTKAIF_TXIF_IN_CH2_SFT 8
  701. #define MTKAIF_TXIF_IN_CH2_MASK 0xff
  702. #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
  703. #define MTKAIF_TXIF_IN_CH1_SFT 0
  704. #define MTKAIF_TXIF_IN_CH1_MASK 0xff
  705. #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
  706. /* AFE_ADDA6_MTKAIF_MON3 */
  707. #define ADDA6_MTKAIF_TXIF_IN_CH2_SFT 8
  708. #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK 0xff
  709. #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
  710. #define ADDA6_MTKAIF_TXIF_IN_CH1_SFT 0
  711. #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK 0xff
  712. #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
  713. /* AFE_ADDA_MTKAIF_MON4 */
  714. #define MTKAIF_RXIF_OUT_CH2_SFT 8
  715. #define MTKAIF_RXIF_OUT_CH2_MASK 0xff
  716. #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
  717. #define MTKAIF_RXIF_OUT_CH1_SFT 0
  718. #define MTKAIF_RXIF_OUT_CH1_MASK 0xff
  719. #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
  720. /* AFE_ADDA_MTKAIF_MON5 */
  721. #define MTKAIF_RXIF_OUT_CH3_SFT 0
  722. #define MTKAIF_RXIF_OUT_CH3_MASK 0xff
  723. #define MTKAIF_RXIF_OUT_CH3_MASK_SFT (0xff << 0)
  724. /* AFE_ADDA_MTKAIF_CFG0 */
  725. #define RG_MTKAIF_RXIF_CLKINV_SFT 15
  726. #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
  727. #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
  728. #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_SFT 9
  729. #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
  730. #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 9)
  731. #define RG_MTKAIF_RXIF_PROTOCOL2_SFT 8
  732. #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
  733. #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
  734. #define RG_MTKAIF_BYPASS_SRC_MODE_SFT 6
  735. #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
  736. #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
  737. #define RG_MTKAIF_BYPASS_SRC_TEST_SFT 5
  738. #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
  739. #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
  740. #define RG_MTKAIF_TXIF_PROTOCOL2_SFT 4
  741. #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
  742. #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
  743. #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT 3
  744. #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
  745. #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
  746. #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 2
  747. #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
  748. #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
  749. #define RG_MTKAIF_LOOPBACK_TEST2_SFT 1
  750. #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
  751. #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
  752. #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0
  753. #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
  754. #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
  755. /* AFE_ADDA_MTKAIF_RX_CFG0 */
  756. #define RG_MTKAIF_RXIF_VOICE_MODE_SFT 12
  757. #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf
  758. #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)
  759. #define RG_MTKAIF_RXIF_DATA_BIT_SFT 8
  760. #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
  761. #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
  762. #define RG_MTKAIF_RXIF_FIFO_RSP_SFT 4
  763. #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
  764. #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
  765. #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3
  766. #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
  767. #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
  768. #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0
  769. #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
  770. #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
  771. /* AFE_ADDA_MTKAIF_RX_CFG1 */
  772. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 12
  773. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
  774. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
  775. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
  776. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
  777. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
  778. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 4
  779. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf
  780. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
  781. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0
  782. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf
  783. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)
  784. /* AFE_ADDA_MTKAIF_RX_CFG2 */
  785. #define RG_MTKAIF_RXIF_P2_INPUT_SEL_SFT 15
  786. #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK 0x1
  787. #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT (0x1 << 15)
  788. #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_SFT 14
  789. #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK 0x1
  790. #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 14)
  791. #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_SFT 13
  792. #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
  793. #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 13)
  794. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 12
  795. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
  796. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
  797. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0
  798. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff
  799. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)
  800. /* AFE_ADDA_MTKAIF_RX_CFG3 */
  801. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT 7
  802. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
  803. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
  804. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4
  805. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
  806. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
  807. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3
  808. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
  809. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
  810. /* AFE_ADDA_MTKAIF_SYNCWORD_CFG0 */
  811. #define RG_MTKAIF_RX_SYNC_WORD2_SFT 4
  812. #define RG_MTKAIF_RX_SYNC_WORD2_MASK 0x7
  813. #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT (0x7 << 4)
  814. #define RG_MTKAIF_RX_SYNC_WORD1_SFT 0
  815. #define RG_MTKAIF_RX_SYNC_WORD1_MASK 0x7
  816. #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT (0x7 << 0)
  817. /* AFE_ADDA_MTKAIF_SYNCWORD_CFG1 */
  818. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_SFT 12
  819. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK 0x7
  820. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 12)
  821. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_SFT 8
  822. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK 0x7
  823. #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 8)
  824. #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_SFT 4
  825. #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK 0x7
  826. #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 4)
  827. #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT 0
  828. #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK 0x7
  829. #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 0)
  830. /* AFE_SGEN_CFG0 */
  831. #define SGEN_AMP_DIV_CH1_CTL_SFT 12
  832. #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf
  833. #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)
  834. #define SGEN_DAC_EN_CTL_SFT 7
  835. #define SGEN_DAC_EN_CTL_MASK 0x1
  836. #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
  837. #define SGEN_MUTE_SW_CTL_SFT 6
  838. #define SGEN_MUTE_SW_CTL_MASK 0x1
  839. #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
  840. #define R_AUD_SDM_MUTE_L_SFT 5
  841. #define R_AUD_SDM_MUTE_L_MASK 0x1
  842. #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
  843. #define R_AUD_SDM_MUTE_R_SFT 4
  844. #define R_AUD_SDM_MUTE_R_MASK 0x1
  845. #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
  846. #define R_AUD_SDM_MUTE_L_2ND_SFT 3
  847. #define R_AUD_SDM_MUTE_L_2ND_MASK 0x1
  848. #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
  849. #define R_AUD_SDM_MUTE_R_2ND_SFT 2
  850. #define R_AUD_SDM_MUTE_R_2ND_MASK 0x1
  851. #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT (0x1 << 2)
  852. /* AFE_SGEN_CFG1 */
  853. #define C_SGEN_RCH_INV_5BIT_SFT 15
  854. #define C_SGEN_RCH_INV_5BIT_MASK 0x1
  855. #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
  856. #define C_SGEN_RCH_INV_8BIT_SFT 14
  857. #define C_SGEN_RCH_INV_8BIT_MASK 0x1
  858. #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
  859. #define SGEN_FREQ_DIV_CH1_CTL_SFT 0
  860. #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f
  861. #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)
  862. /* AFE_ADC_ASYNC_FIFO_CFG */
  863. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5
  864. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
  865. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
  866. #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4
  867. #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
  868. #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
  869. #define RG_AMIC_UL_ADC_CLK_SEL_SFT 1
  870. #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
  871. #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
  872. /* AFE_ADC_ASYNC_FIFO_CFG1 */
  873. #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT 5
  874. #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
  875. #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
  876. #define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT 4
  877. #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x1
  878. #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
  879. /* AFE_DCCLK_CFG0 */
  880. #define DCCLK_DIV_SFT 5
  881. #define DCCLK_DIV_MASK 0x7ff
  882. #define DCCLK_DIV_MASK_SFT (0x7ff << 5)
  883. #define DCCLK_INV_SFT 4
  884. #define DCCLK_INV_MASK 0x1
  885. #define DCCLK_INV_MASK_SFT (0x1 << 4)
  886. #define DCCLK_REF_CK_SEL_SFT 2
  887. #define DCCLK_REF_CK_SEL_MASK 0x3
  888. #define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)
  889. #define DCCLK_PDN_SFT 1
  890. #define DCCLK_PDN_MASK 0x1
  891. #define DCCLK_PDN_MASK_SFT (0x1 << 1)
  892. #define DCCLK_GEN_ON_SFT 0
  893. #define DCCLK_GEN_ON_MASK 0x1
  894. #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
  895. /* AFE_DCCLK_CFG1 */
  896. #define RESYNC_SRC_SEL_SFT 10
  897. #define RESYNC_SRC_SEL_MASK 0x3
  898. #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
  899. #define RESYNC_SRC_CK_INV_SFT 9
  900. #define RESYNC_SRC_CK_INV_MASK 0x1
  901. #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
  902. #define DCCLK_RESYNC_BYPASS_SFT 8
  903. #define DCCLK_RESYNC_BYPASS_MASK 0x1
  904. #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
  905. #define DCCLK_PHASE_SEL_SFT 4
  906. #define DCCLK_PHASE_SEL_MASK 0xf
  907. #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)
  908. /* AUDIO_DIG_CFG */
  909. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 15
  910. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
  911. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
  912. #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 8
  913. #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f
  914. #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)
  915. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7
  916. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
  917. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
  918. #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0
  919. #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f
  920. #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)
  921. /* AUDIO_DIG_CFG1 */
  922. #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT 7
  923. #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1
  924. #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7)
  925. #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT 0
  926. #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7f
  927. #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT (0x7f << 0)
  928. /* AFE_AUD_PAD_TOP */
  929. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 12
  930. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
  931. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
  932. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 11
  933. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
  934. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
  935. #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 8
  936. #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
  937. #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
  938. /* AFE_AUD_PAD_TOP_MON */
  939. #define ADDA_AUD_PAD_TOP_MON_SFT 0
  940. #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff
  941. #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
  942. /* AFE_AUD_PAD_TOP_MON1 */
  943. #define ADDA_AUD_PAD_TOP_MON1_SFT 0
  944. #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff
  945. #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)
  946. /* AFE_AUD_PAD_TOP_MON2 */
  947. #define ADDA_AUD_PAD_TOP_MON2_SFT 0
  948. #define ADDA_AUD_PAD_TOP_MON2_MASK 0xffff
  949. #define ADDA_AUD_PAD_TOP_MON2_MASK_SFT (0xffff << 0)
  950. /* AFE_DL_NLE_CFG */
  951. #define NLE_RCH_HPGAIN_SEL_SFT 10
  952. #define NLE_RCH_HPGAIN_SEL_MASK 0x1
  953. #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
  954. #define NLE_RCH_CH_SEL_SFT 9
  955. #define NLE_RCH_CH_SEL_MASK 0x1
  956. #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
  957. #define NLE_RCH_ON_SFT 8
  958. #define NLE_RCH_ON_MASK 0x1
  959. #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
  960. #define NLE_LCH_HPGAIN_SEL_SFT 2
  961. #define NLE_LCH_HPGAIN_SEL_MASK 0x1
  962. #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
  963. #define NLE_LCH_CH_SEL_SFT 1
  964. #define NLE_LCH_CH_SEL_MASK 0x1
  965. #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
  966. #define NLE_LCH_ON_SFT 0
  967. #define NLE_LCH_ON_MASK 0x1
  968. #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
  969. /* AFE_DL_NLE_MON */
  970. #define NLE_MONITOR_SFT 0
  971. #define NLE_MONITOR_MASK 0x3fff
  972. #define NLE_MONITOR_MASK_SFT (0x3fff << 0)
  973. /* AFE_CG_EN_MON */
  974. #define CK_CG_EN_MON_SFT 0
  975. #define CK_CG_EN_MON_MASK 0x3f
  976. #define CK_CG_EN_MON_MASK_SFT (0x3f << 0)
  977. /* AFE_MIC_ARRAY_CFG */
  978. #define RG_AMIC_ADC1_SOURCE_SEL_SFT 10
  979. #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3
  980. #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)
  981. #define RG_AMIC_ADC2_SOURCE_SEL_SFT 8
  982. #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3
  983. #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)
  984. #define RG_AMIC_ADC3_SOURCE_SEL_SFT 6
  985. #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3
  986. #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)
  987. #define RG_DMIC_ADC1_SOURCE_SEL_SFT 4
  988. #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3
  989. #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)
  990. #define RG_DMIC_ADC2_SOURCE_SEL_SFT 2
  991. #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3
  992. #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)
  993. #define RG_DMIC_ADC3_SOURCE_SEL_SFT 0
  994. #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3
  995. #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)
  996. /* AFE_CHOP_CFG0 */
  997. #define RG_CHOP_DIV_SEL_SFT 4
  998. #define RG_CHOP_DIV_SEL_MASK 0x1f
  999. #define RG_CHOP_DIV_SEL_MASK_SFT (0x1f << 4)
  1000. #define RG_CHOP_DIV_EN_SFT 0
  1001. #define RG_CHOP_DIV_EN_MASK 0x1
  1002. #define RG_CHOP_DIV_EN_MASK_SFT (0x1 << 0)
  1003. /* AFE_MTKAIF_MUX_CFG */
  1004. #define RG_ADDA6_EN_SEL_SFT 12
  1005. #define RG_ADDA6_EN_SEL_MASK 0x1
  1006. #define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 12)
  1007. #define RG_ADDA6_CH2_SEL_SFT 10
  1008. #define RG_ADDA6_CH2_SEL_MASK 0x3
  1009. #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)
  1010. #define RG_ADDA6_CH1_SEL_SFT 8
  1011. #define RG_ADDA6_CH1_SEL_MASK 0x3
  1012. #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)
  1013. #define RG_ADDA_EN_SEL_SFT 4
  1014. #define RG_ADDA_EN_SEL_MASK 0x1
  1015. #define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4)
  1016. #define RG_ADDA_CH2_SEL_SFT 2
  1017. #define RG_ADDA_CH2_SEL_MASK 0x3
  1018. #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)
  1019. #define RG_ADDA_CH1_SEL_SFT 0
  1020. #define RG_ADDA_CH1_SEL_MASK 0x3
  1021. #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)
  1022. /* AFE_PMIC_NEWIF_CFG3 */
  1023. #define RG_UP8X_SYNC_WORD_SFT 0
  1024. #define RG_UP8X_SYNC_WORD_MASK 0xffff
  1025. #define RG_UP8X_SYNC_WORD_MASK_SFT (0xffff << 0)
  1026. /* AFE_NCP_CFG0 */
  1027. #define RG_NCP_CK1_VALID_CNT_SFT 9
  1028. #define RG_NCP_CK1_VALID_CNT_MASK 0x7f
  1029. #define RG_NCP_CK1_VALID_CNT_MASK_SFT (0x7f << 9)
  1030. #define RG_NCP_ADITH_SFT 8
  1031. #define RG_NCP_ADITH_MASK 0x1
  1032. #define RG_NCP_ADITH_MASK_SFT (0x1 << 8)
  1033. #define RG_NCP_DITHER_EN_SFT 7
  1034. #define RG_NCP_DITHER_EN_MASK 0x1
  1035. #define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7)
  1036. #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT 4
  1037. #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x7
  1038. #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4)
  1039. #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT 1
  1040. #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x7
  1041. #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1)
  1042. #define RG_NCP_ON_SFT 0
  1043. #define RG_NCP_ON_MASK 0x1
  1044. #define RG_NCP_ON_MASK_SFT (0x1 << 0)
  1045. /* AFE_NCP_CFG1 */
  1046. #define RG_XY_VAL_CFG_EN_SFT 15
  1047. #define RG_XY_VAL_CFG_EN_MASK 0x1
  1048. #define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 15)
  1049. #define RG_X_VAL_CFG_SFT 8
  1050. #define RG_X_VAL_CFG_MASK 0x7f
  1051. #define RG_X_VAL_CFG_MASK_SFT (0x7f << 8)
  1052. #define RG_Y_VAL_CFG_SFT 0
  1053. #define RG_Y_VAL_CFG_MASK 0x7f
  1054. #define RG_Y_VAL_CFG_MASK_SFT (0x7f << 0)
  1055. /* AFE_NCP_CFG2 */
  1056. #define RG_NCP_NONCLK_SET_SFT 1
  1057. #define RG_NCP_NONCLK_SET_MASK 0x1
  1058. #define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1)
  1059. #define RG_NCP_PDDIS_EN_SFT 0
  1060. #define RG_NCP_PDDIS_EN_MASK 0x1
  1061. #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
  1062. /* AUDENC_ANA_CON0 */
  1063. #define RG_AUDPREAMPLON_SFT 0
  1064. #define RG_AUDPREAMPLON_MASK 0x1
  1065. #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
  1066. #define RG_AUDPREAMPLDCCEN_SFT 1
  1067. #define RG_AUDPREAMPLDCCEN_MASK 0x1
  1068. #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
  1069. #define RG_AUDPREAMPLDCPRECHARGE_SFT 2
  1070. #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
  1071. #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
  1072. #define RG_AUDPREAMPLPGATEST_SFT 3
  1073. #define RG_AUDPREAMPLPGATEST_MASK 0x1
  1074. #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
  1075. #define RG_AUDPREAMPLVSCALE_SFT 4
  1076. #define RG_AUDPREAMPLVSCALE_MASK 0x3
  1077. #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
  1078. #define RG_AUDPREAMPLINPUTSEL_SFT 6
  1079. #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
  1080. #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
  1081. #define RG_AUDPREAMPLGAIN_SFT 8
  1082. #define RG_AUDPREAMPLGAIN_MASK 0x7
  1083. #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
  1084. #define RG_BULKL_VCM_EN_SFT 11
  1085. #define RG_BULKL_VCM_EN_MASK 0x1
  1086. #define RG_BULKL_VCM_EN_MASK_SFT (0x1 << 11)
  1087. #define RG_AUDADCLPWRUP_SFT 12
  1088. #define RG_AUDADCLPWRUP_MASK 0x1
  1089. #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
  1090. #define RG_AUDADCLINPUTSEL_SFT 13
  1091. #define RG_AUDADCLINPUTSEL_MASK 0x3
  1092. #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
  1093. /* AUDENC_ANA_CON1 */
  1094. #define RG_AUDPREAMPRON_SFT 0
  1095. #define RG_AUDPREAMPRON_MASK 0x1
  1096. #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
  1097. #define RG_AUDPREAMPRDCCEN_SFT 1
  1098. #define RG_AUDPREAMPRDCCEN_MASK 0x1
  1099. #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
  1100. #define RG_AUDPREAMPRDCPRECHARGE_SFT 2
  1101. #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
  1102. #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
  1103. #define RG_AUDPREAMPRPGATEST_SFT 3
  1104. #define RG_AUDPREAMPRPGATEST_MASK 0x1
  1105. #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
  1106. #define RG_AUDPREAMPRVSCALE_SFT 4
  1107. #define RG_AUDPREAMPRVSCALE_MASK 0x3
  1108. #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
  1109. #define RG_AUDPREAMPRINPUTSEL_SFT 6
  1110. #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
  1111. #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
  1112. #define RG_AUDPREAMPRGAIN_SFT 8
  1113. #define RG_AUDPREAMPRGAIN_MASK 0x7
  1114. #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
  1115. #define RG_BULKR_VCM_EN_SFT 11
  1116. #define RG_BULKR_VCM_EN_MASK 0x1
  1117. #define RG_BULKR_VCM_EN_MASK_SFT (0x1 << 11)
  1118. #define RG_AUDADCRPWRUP_SFT 12
  1119. #define RG_AUDADCRPWRUP_MASK 0x1
  1120. #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
  1121. #define RG_AUDADCRINPUTSEL_SFT 13
  1122. #define RG_AUDADCRINPUTSEL_MASK 0x3
  1123. #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
  1124. /* AUDENC_ANA_CON2 */
  1125. #define RG_AUDPREAMP3ON_SFT 0
  1126. #define RG_AUDPREAMP3ON_MASK 0x1
  1127. #define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0)
  1128. #define RG_AUDPREAMP3DCCEN_SFT 1
  1129. #define RG_AUDPREAMP3DCCEN_MASK 0x1
  1130. #define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1)
  1131. #define RG_AUDPREAMP3DCPRECHARGE_SFT 2
  1132. #define RG_AUDPREAMP3DCPRECHARGE_MASK 0x1
  1133. #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2)
  1134. #define RG_AUDPREAMP3PGATEST_SFT 3
  1135. #define RG_AUDPREAMP3PGATEST_MASK 0x1
  1136. #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
  1137. #define RG_AUDPREAMP3VSCALE_SFT 4
  1138. #define RG_AUDPREAMP3VSCALE_MASK 0x3
  1139. #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)
  1140. #define RG_AUDPREAMP3INPUTSEL_SFT 6
  1141. #define RG_AUDPREAMP3INPUTSEL_MASK 0x3
  1142. #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)
  1143. #define RG_AUDPREAMP3GAIN_SFT 8
  1144. #define RG_AUDPREAMP3GAIN_MASK 0x7
  1145. #define RG_AUDPREAMP3GAIN_MASK_SFT (0x7 << 8)
  1146. #define RG_BULK3_VCM_EN_SFT 11
  1147. #define RG_BULK3_VCM_EN_MASK 0x1
  1148. #define RG_BULK3_VCM_EN_MASK_SFT (0x1 << 11)
  1149. #define RG_AUDADC3PWRUP_SFT 12
  1150. #define RG_AUDADC3PWRUP_MASK 0x1
  1151. #define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 12)
  1152. #define RG_AUDADC3INPUTSEL_SFT 13
  1153. #define RG_AUDADC3INPUTSEL_MASK 0x3
  1154. #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)
  1155. /* AUDENC_ANA_CON3 */
  1156. #define RG_AUDULHALFBIAS_SFT 0
  1157. #define RG_AUDULHALFBIAS_MASK 0x1
  1158. #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
  1159. #define RG_AUDGLBVOWLPWEN_SFT 1
  1160. #define RG_AUDGLBVOWLPWEN_MASK 0x1
  1161. #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
  1162. #define RG_AUDPREAMPLPEN_SFT 2
  1163. #define RG_AUDPREAMPLPEN_MASK 0x1
  1164. #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
  1165. #define RG_AUDADC1STSTAGELPEN_SFT 3
  1166. #define RG_AUDADC1STSTAGELPEN_MASK 0x1
  1167. #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
  1168. #define RG_AUDADC2NDSTAGELPEN_SFT 4
  1169. #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
  1170. #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
  1171. #define RG_AUDADCFLASHLPEN_SFT 5
  1172. #define RG_AUDADCFLASHLPEN_MASK 0x1
  1173. #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
  1174. #define RG_AUDPREAMPIDDTEST_SFT 6
  1175. #define RG_AUDPREAMPIDDTEST_MASK 0x3
  1176. #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
  1177. #define RG_AUDADC1STSTAGEIDDTEST_SFT 8
  1178. #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
  1179. #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
  1180. #define RG_AUDADC2NDSTAGEIDDTEST_SFT 10
  1181. #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
  1182. #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
  1183. #define RG_AUDADCREFBUFIDDTEST_SFT 12
  1184. #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
  1185. #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
  1186. #define RG_AUDADCFLASHIDDTEST_SFT 14
  1187. #define RG_AUDADCFLASHIDDTEST_MASK 0x3
  1188. #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
  1189. /* AUDENC_ANA_CON4 */
  1190. #define RG_AUDRULHALFBIAS_SFT 0
  1191. #define RG_AUDRULHALFBIAS_MASK 0x1
  1192. #define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0)
  1193. #define RG_AUDGLBRVOWLPWEN_SFT 1
  1194. #define RG_AUDGLBRVOWLPWEN_MASK 0x1
  1195. #define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1)
  1196. #define RG_AUDRPREAMPLPEN_SFT 2
  1197. #define RG_AUDRPREAMPLPEN_MASK 0x1
  1198. #define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2)
  1199. #define RG_AUDRADC1STSTAGELPEN_SFT 3
  1200. #define RG_AUDRADC1STSTAGELPEN_MASK 0x1
  1201. #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
  1202. #define RG_AUDRADC2NDSTAGELPEN_SFT 4
  1203. #define RG_AUDRADC2NDSTAGELPEN_MASK 0x1
  1204. #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
  1205. #define RG_AUDRADCFLASHLPEN_SFT 5
  1206. #define RG_AUDRADCFLASHLPEN_MASK 0x1
  1207. #define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5)
  1208. #define RG_AUDRPREAMPIDDTEST_SFT 6
  1209. #define RG_AUDRPREAMPIDDTEST_MASK 0x3
  1210. #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)
  1211. #define RG_AUDRADC1STSTAGEIDDTEST_SFT 8
  1212. #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3
  1213. #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
  1214. #define RG_AUDRADC2NDSTAGEIDDTEST_SFT 10
  1215. #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3
  1216. #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
  1217. #define RG_AUDRADCREFBUFIDDTEST_SFT 12
  1218. #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3
  1219. #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
  1220. #define RG_AUDRADCFLASHIDDTEST_SFT 14
  1221. #define RG_AUDRADCFLASHIDDTEST_MASK 0x3
  1222. #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
  1223. /* AUDENC_ANA_CON5 */
  1224. #define RG_AUDADCCLKRSTB_SFT 0
  1225. #define RG_AUDADCCLKRSTB_MASK 0x1
  1226. #define RG_AUDADCCLKRSTB_MASK_SFT (0x1 << 0)
  1227. #define RG_AUDADCCLKSEL_SFT 1
  1228. #define RG_AUDADCCLKSEL_MASK 0x3
  1229. #define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)
  1230. #define RG_AUDADCCLKSOURCE_SFT 3
  1231. #define RG_AUDADCCLKSOURCE_MASK 0x3
  1232. #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)
  1233. #define RG_AUDADCCLKGENMODE_SFT 5
  1234. #define RG_AUDADCCLKGENMODE_MASK 0x3
  1235. #define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)
  1236. #define RG_AUDPREAMP_ACCFS_SFT 7
  1237. #define RG_AUDPREAMP_ACCFS_MASK 0x1
  1238. #define RG_AUDPREAMP_ACCFS_MASK_SFT (0x1 << 7)
  1239. #define RG_AUDPREAMPAAFEN_SFT 8
  1240. #define RG_AUDPREAMPAAFEN_MASK 0x1
  1241. #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
  1242. #define RG_DCCVCMBUFLPMODSEL_SFT 9
  1243. #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
  1244. #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
  1245. #define RG_DCCVCMBUFLPSWEN_SFT 10
  1246. #define RG_DCCVCMBUFLPSWEN_MASK 0x1
  1247. #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
  1248. #define RG_AUDSPAREPGA_SFT 11
  1249. #define RG_AUDSPAREPGA_MASK 0x1f
  1250. #define RG_AUDSPAREPGA_MASK_SFT (0x1f << 11)
  1251. /* AUDENC_ANA_CON6 */
  1252. #define RG_AUDADC1STSTAGESDENB_SFT 0
  1253. #define RG_AUDADC1STSTAGESDENB_MASK 0x1
  1254. #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
  1255. #define RG_AUDADC2NDSTAGERESET_SFT 1
  1256. #define RG_AUDADC2NDSTAGERESET_MASK 0x1
  1257. #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
  1258. #define RG_AUDADC3RDSTAGERESET_SFT 2
  1259. #define RG_AUDADC3RDSTAGERESET_MASK 0x1
  1260. #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
  1261. #define RG_AUDADCFSRESET_SFT 3
  1262. #define RG_AUDADCFSRESET_MASK 0x1
  1263. #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
  1264. #define RG_AUDADCWIDECM_SFT 4
  1265. #define RG_AUDADCWIDECM_MASK 0x1
  1266. #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
  1267. #define RG_AUDADCNOPATEST_SFT 5
  1268. #define RG_AUDADCNOPATEST_MASK 0x1
  1269. #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
  1270. #define RG_AUDADCBYPASS_SFT 6
  1271. #define RG_AUDADCBYPASS_MASK 0x1
  1272. #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
  1273. #define RG_AUDADCFFBYPASS_SFT 7
  1274. #define RG_AUDADCFFBYPASS_MASK 0x1
  1275. #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
  1276. #define RG_AUDADCDACFBCURRENT_SFT 8
  1277. #define RG_AUDADCDACFBCURRENT_MASK 0x1
  1278. #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
  1279. #define RG_AUDADCDACIDDTEST_SFT 9
  1280. #define RG_AUDADCDACIDDTEST_MASK 0x3
  1281. #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
  1282. #define RG_AUDADCDACNRZ_SFT 11
  1283. #define RG_AUDADCDACNRZ_MASK 0x1
  1284. #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
  1285. #define RG_AUDADCNODEM_SFT 12
  1286. #define RG_AUDADCNODEM_MASK 0x1
  1287. #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
  1288. #define RG_AUDADCDACTEST_SFT 13
  1289. #define RG_AUDADCDACTEST_MASK 0x1
  1290. #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
  1291. #define RG_AUDADCDAC0P25FS_SFT 14
  1292. #define RG_AUDADCDAC0P25FS_MASK 0x1
  1293. #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 14)
  1294. #define RG_AUDADCRDAC0P25FS_SFT 15
  1295. #define RG_AUDADCRDAC0P25FS_MASK 0x1
  1296. #define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 15)
  1297. /* AUDENC_ANA_CON7 */
  1298. #define RG_AUDADCTESTDATA_SFT 0
  1299. #define RG_AUDADCTESTDATA_MASK 0xffff
  1300. #define RG_AUDADCTESTDATA_MASK_SFT (0xffff << 0)
  1301. /* AUDENC_ANA_CON8 */
  1302. #define RG_AUDRCTUNEL_SFT 0
  1303. #define RG_AUDRCTUNEL_MASK 0x1f
  1304. #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)
  1305. #define RG_AUDRCTUNELSEL_SFT 5
  1306. #define RG_AUDRCTUNELSEL_MASK 0x1
  1307. #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
  1308. #define RG_AUDRCTUNER_SFT 8
  1309. #define RG_AUDRCTUNER_MASK 0x1f
  1310. #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)
  1311. #define RG_AUDRCTUNERSEL_SFT 13
  1312. #define RG_AUDRCTUNERSEL_MASK 0x1
  1313. #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
  1314. /* AUDENC_ANA_CON9 */
  1315. #define RG_AUD3CTUNEL_SFT 0
  1316. #define RG_AUD3CTUNEL_MASK 0x1f
  1317. #define RG_AUD3CTUNEL_MASK_SFT (0x1f << 0)
  1318. #define RG_AUD3CTUNELSEL_SFT 5
  1319. #define RG_AUD3CTUNELSEL_MASK 0x1
  1320. #define RG_AUD3CTUNELSEL_MASK_SFT (0x1 << 5)
  1321. #define RGS_AUDRCTUNE3READ_SFT 6
  1322. #define RGS_AUDRCTUNE3READ_MASK 0x1f
  1323. #define RGS_AUDRCTUNE3READ_MASK_SFT (0x1f << 6)
  1324. #define RG_AUD3SPARE_SFT 11
  1325. #define RG_AUD3SPARE_MASK 0x1f
  1326. #define RG_AUD3SPARE_MASK_SFT (0x1f << 11)
  1327. /* AUDENC_ANA_CON10 */
  1328. #define RGS_AUDRCTUNELREAD_SFT 0
  1329. #define RGS_AUDRCTUNELREAD_MASK 0x1f
  1330. #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)
  1331. #define RGS_AUDRCTUNERREAD_SFT 8
  1332. #define RGS_AUDRCTUNERREAD_MASK 0x1f
  1333. #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)
  1334. /* AUDENC_ANA_CON11 */
  1335. #define RG_AUDSPAREVA30_SFT 0
  1336. #define RG_AUDSPAREVA30_MASK 0xff
  1337. #define RG_AUDSPAREVA30_MASK_SFT (0xff << 0)
  1338. #define RG_AUDSPAREVA18_SFT 8
  1339. #define RG_AUDSPAREVA18_MASK 0xff
  1340. #define RG_AUDSPAREVA18_MASK_SFT (0xff << 8)
  1341. /* AUDENC_ANA_CON12 */
  1342. #define RG_AUDPGA_DECAP_SFT 0
  1343. #define RG_AUDPGA_DECAP_MASK 0x1
  1344. #define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0)
  1345. #define RG_AUDPGA_CAPRA_SFT 1
  1346. #define RG_AUDPGA_CAPRA_MASK 0x1
  1347. #define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1)
  1348. #define RG_AUDPGA_ACCCMP_SFT 2
  1349. #define RG_AUDPGA_ACCCMP_MASK 0x1
  1350. #define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2)
  1351. #define RG_AUDENC_SPARE2_SFT 3
  1352. #define RG_AUDENC_SPARE2_MASK 0x1fff
  1353. #define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)
  1354. /* AUDENC_ANA_CON13 */
  1355. #define RG_AUDDIGMICEN_SFT 0
  1356. #define RG_AUDDIGMICEN_MASK 0x1
  1357. #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
  1358. #define RG_AUDDIGMICBIAS_SFT 1
  1359. #define RG_AUDDIGMICBIAS_MASK 0x3
  1360. #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
  1361. #define RG_DMICHPCLKEN_SFT 3
  1362. #define RG_DMICHPCLKEN_MASK 0x1
  1363. #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
  1364. #define RG_AUDDIGMICPDUTY_SFT 4
  1365. #define RG_AUDDIGMICPDUTY_MASK 0x3
  1366. #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
  1367. #define RG_AUDDIGMICNDUTY_SFT 6
  1368. #define RG_AUDDIGMICNDUTY_MASK 0x3
  1369. #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
  1370. #define RG_DMICMONEN_SFT 8
  1371. #define RG_DMICMONEN_MASK 0x1
  1372. #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
  1373. #define RG_DMICMONSEL_SFT 9
  1374. #define RG_DMICMONSEL_MASK 0x7
  1375. #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
  1376. /* AUDENC_ANA_CON14 */
  1377. #define RG_AUDDIGMIC1EN_SFT 0
  1378. #define RG_AUDDIGMIC1EN_MASK 0x1
  1379. #define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0)
  1380. #define RG_AUDDIGMICBIAS1_SFT 1
  1381. #define RG_AUDDIGMICBIAS1_MASK 0x3
  1382. #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)
  1383. #define RG_DMIC1HPCLKEN_SFT 3
  1384. #define RG_DMIC1HPCLKEN_MASK 0x1
  1385. #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
  1386. #define RG_AUDDIGMIC1PDUTY_SFT 4
  1387. #define RG_AUDDIGMIC1PDUTY_MASK 0x3
  1388. #define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)
  1389. #define RG_AUDDIGMIC1NDUTY_SFT 6
  1390. #define RG_AUDDIGMIC1NDUTY_MASK 0x3
  1391. #define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)
  1392. #define RG_DMIC1MONEN_SFT 8
  1393. #define RG_DMIC1MONEN_MASK 0x1
  1394. #define RG_DMIC1MONEN_MASK_SFT (0x1 << 8)
  1395. #define RG_DMIC1MONSEL_SFT 9
  1396. #define RG_DMIC1MONSEL_MASK 0x7
  1397. #define RG_DMIC1MONSEL_MASK_SFT (0x7 << 9)
  1398. #define RG_AUDSPAREVMIC_SFT 12
  1399. #define RG_AUDSPAREVMIC_MASK 0xf
  1400. #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)
  1401. /* AUDENC_ANA_CON15 */
  1402. #define RG_AUDPWDBMICBIAS0_SFT 0
  1403. #define RG_AUDPWDBMICBIAS0_MASK 0x1
  1404. #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
  1405. #define RG_AUDMICBIAS0BYPASSEN_SFT 1
  1406. #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
  1407. #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
  1408. #define RG_AUDMICBIAS0LOWPEN_SFT 2
  1409. #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
  1410. #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
  1411. #define RG_AUDPWDBMICBIAS3_SFT 3
  1412. #define RG_AUDPWDBMICBIAS3_MASK 0x1
  1413. #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
  1414. #define RG_AUDMICBIAS0VREF_SFT 4
  1415. #define RG_AUDMICBIAS0VREF_MASK 0x7
  1416. #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
  1417. #define RG_AUDMICBIAS0DCSW0P1EN_SFT 8
  1418. #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
  1419. #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
  1420. #define RG_AUDMICBIAS0DCSW0P2EN_SFT 9
  1421. #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
  1422. #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
  1423. #define RG_AUDMICBIAS0DCSW0NEN_SFT 10
  1424. #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
  1425. #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
  1426. #define RG_AUDMICBIAS0DCSW2P1EN_SFT 12
  1427. #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
  1428. #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
  1429. #define RG_AUDMICBIAS0DCSW2P2EN_SFT 13
  1430. #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
  1431. #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
  1432. #define RG_AUDMICBIAS0DCSW2NEN_SFT 14
  1433. #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
  1434. #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
  1435. /* AUDENC_ANA_CON16 */
  1436. #define RG_AUDPWDBMICBIAS1_SFT 0
  1437. #define RG_AUDPWDBMICBIAS1_MASK 0x1
  1438. #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
  1439. #define RG_AUDMICBIAS1BYPASSEN_SFT 1
  1440. #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
  1441. #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
  1442. #define RG_AUDMICBIAS1LOWPEN_SFT 2
  1443. #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
  1444. #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
  1445. #define RG_AUDMICBIAS1VREF_SFT 4
  1446. #define RG_AUDMICBIAS1VREF_MASK 0x7
  1447. #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
  1448. #define RG_AUDMICBIAS1DCSW1PEN_SFT 8
  1449. #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
  1450. #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
  1451. #define RG_AUDMICBIAS1DCSW1NEN_SFT 9
  1452. #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
  1453. #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
  1454. #define RG_BANDGAPGEN_SFT 10
  1455. #define RG_BANDGAPGEN_MASK 0x1
  1456. #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
  1457. #define RG_AUDMICBIAS1HVEN_SFT 12
  1458. #define RG_AUDMICBIAS1HVEN_MASK 0x1
  1459. #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
  1460. #define RG_AUDMICBIAS1HVVREF_SFT 13
  1461. #define RG_AUDMICBIAS1HVVREF_MASK 0x1
  1462. #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
  1463. /* AUDENC_ANA_CON17 */
  1464. #define RG_AUDPWDBMICBIAS2_SFT 0
  1465. #define RG_AUDPWDBMICBIAS2_MASK 0x1
  1466. #define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0)
  1467. #define RG_AUDMICBIAS2BYPASSEN_SFT 1
  1468. #define RG_AUDMICBIAS2BYPASSEN_MASK 0x1
  1469. #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1)
  1470. #define RG_AUDMICBIAS2LOWPEN_SFT 2
  1471. #define RG_AUDMICBIAS2LOWPEN_MASK 0x1
  1472. #define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2)
  1473. #define RG_AUDMICBIAS2VREF_SFT 4
  1474. #define RG_AUDMICBIAS2VREF_MASK 0x7
  1475. #define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4)
  1476. #define RG_AUDMICBIAS2DCSW3P1EN_SFT 8
  1477. #define RG_AUDMICBIAS2DCSW3P1EN_MASK 0x1
  1478. #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT (0x1 << 8)
  1479. #define RG_AUDMICBIAS2DCSW3P2EN_SFT 9
  1480. #define RG_AUDMICBIAS2DCSW3P2EN_MASK 0x1
  1481. #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT (0x1 << 9)
  1482. #define RG_AUDMICBIAS2DCSW3NEN_SFT 10
  1483. #define RG_AUDMICBIAS2DCSW3NEN_MASK 0x1
  1484. #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT (0x1 << 10)
  1485. #define RG_AUDMICBIASSPARE_SFT 12
  1486. #define RG_AUDMICBIASSPARE_MASK 0xf
  1487. #define RG_AUDMICBIASSPARE_MASK_SFT (0xf << 12)
  1488. /* AUDENC_ANA_CON18 */
  1489. #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
  1490. #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
  1491. #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
  1492. #define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1
  1493. #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
  1494. #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
  1495. #define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2
  1496. #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
  1497. #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
  1498. #define RG_AUDACCDETVIN1PULLLOW_SFT 3
  1499. #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
  1500. #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
  1501. #define RG_AUDACCDETVTHACAL_SFT 4
  1502. #define RG_AUDACCDETVTHACAL_MASK 0x1
  1503. #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
  1504. #define RG_AUDACCDETVTHBCAL_SFT 5
  1505. #define RG_AUDACCDETVTHBCAL_MASK 0x1
  1506. #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
  1507. #define RG_AUDACCDETTVDET_SFT 6
  1508. #define RG_AUDACCDETTVDET_MASK 0x1
  1509. #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
  1510. #define RG_ACCDETSEL_SFT 7
  1511. #define RG_ACCDETSEL_MASK 0x1
  1512. #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
  1513. #define RG_SWBUFMODSEL_SFT 8
  1514. #define RG_SWBUFMODSEL_MASK 0x1
  1515. #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
  1516. #define RG_SWBUFSWEN_SFT 9
  1517. #define RG_SWBUFSWEN_MASK 0x1
  1518. #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
  1519. #define RG_EINT0NOHYS_SFT 10
  1520. #define RG_EINT0NOHYS_MASK 0x1
  1521. #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
  1522. #define RG_EINT0CONFIGACCDET_SFT 11
  1523. #define RG_EINT0CONFIGACCDET_MASK 0x1
  1524. #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
  1525. #define RG_EINT0HIRENB_SFT 12
  1526. #define RG_EINT0HIRENB_MASK 0x1
  1527. #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
  1528. #define RG_ACCDET2AUXRESBYPASS_SFT 13
  1529. #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
  1530. #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
  1531. #define RG_ACCDET2AUXSWEN_SFT 14
  1532. #define RG_ACCDET2AUXSWEN_MASK 0x1
  1533. #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
  1534. #define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15
  1535. #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
  1536. #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
  1537. /* AUDENC_ANA_CON19 */
  1538. #define RG_EINT1CONFIGACCDET_SFT 0
  1539. #define RG_EINT1CONFIGACCDET_MASK 0x1
  1540. #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
  1541. #define RG_EINT1HIRENB_SFT 1
  1542. #define RG_EINT1HIRENB_MASK 0x1
  1543. #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
  1544. #define RG_EINT1NOHYS_SFT 2
  1545. #define RG_EINT1NOHYS_MASK 0x1
  1546. #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
  1547. #define RG_EINTCOMPVTH_SFT 4
  1548. #define RG_EINTCOMPVTH_MASK 0xf
  1549. #define RG_EINTCOMPVTH_MASK_SFT (0xf << 4)
  1550. #define RG_MTEST_EN_SFT 8
  1551. #define RG_MTEST_EN_MASK 0x1
  1552. #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
  1553. #define RG_MTEST_SEL_SFT 9
  1554. #define RG_MTEST_SEL_MASK 0x1
  1555. #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
  1556. #define RG_MTEST_CURRENT_SFT 10
  1557. #define RG_MTEST_CURRENT_MASK 0x1
  1558. #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
  1559. #define RG_ANALOGFDEN_SFT 12
  1560. #define RG_ANALOGFDEN_MASK 0x1
  1561. #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
  1562. #define RG_FDVIN1PPULLLOW_SFT 13
  1563. #define RG_FDVIN1PPULLLOW_MASK 0x1
  1564. #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
  1565. #define RG_FDEINT0TYPE_SFT 14
  1566. #define RG_FDEINT0TYPE_MASK 0x1
  1567. #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
  1568. #define RG_FDEINT1TYPE_SFT 15
  1569. #define RG_FDEINT1TYPE_MASK 0x1
  1570. #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
  1571. /* AUDENC_ANA_CON20 */
  1572. #define RG_EINT0CMPEN_SFT 0
  1573. #define RG_EINT0CMPEN_MASK 0x1
  1574. #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
  1575. #define RG_EINT0CMPMEN_SFT 1
  1576. #define RG_EINT0CMPMEN_MASK 0x1
  1577. #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
  1578. #define RG_EINT0EN_SFT 2
  1579. #define RG_EINT0EN_MASK 0x1
  1580. #define RG_EINT0EN_MASK_SFT (0x1 << 2)
  1581. #define RG_EINT0CEN_SFT 3
  1582. #define RG_EINT0CEN_MASK 0x1
  1583. #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
  1584. #define RG_EINT0INVEN_SFT 4
  1585. #define RG_EINT0INVEN_MASK 0x1
  1586. #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
  1587. #define RG_EINT0CTURBO_SFT 5
  1588. #define RG_EINT0CTURBO_MASK 0x7
  1589. #define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
  1590. #define RG_EINT1CMPEN_SFT 8
  1591. #define RG_EINT1CMPEN_MASK 0x1
  1592. #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
  1593. #define RG_EINT1CMPMEN_SFT 9
  1594. #define RG_EINT1CMPMEN_MASK 0x1
  1595. #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
  1596. #define RG_EINT1EN_SFT 10
  1597. #define RG_EINT1EN_MASK 0x1
  1598. #define RG_EINT1EN_MASK_SFT (0x1 << 10)
  1599. #define RG_EINT1CEN_SFT 11
  1600. #define RG_EINT1CEN_MASK 0x1
  1601. #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
  1602. #define RG_EINT1INVEN_SFT 12
  1603. #define RG_EINT1INVEN_MASK 0x1
  1604. #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
  1605. #define RG_EINT1CTURBO_SFT 13
  1606. #define RG_EINT1CTURBO_MASK 0x7
  1607. #define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
  1608. /* AUDENC_ANA_CON21 */
  1609. #define RG_ACCDETSPARE_SFT 0
  1610. #define RG_ACCDETSPARE_MASK 0xffff
  1611. #define RG_ACCDETSPARE_MASK_SFT (0xffff << 0)
  1612. /* AUDENC_ANA_CON22 */
  1613. #define RG_AUDENCSPAREVA30_SFT 0
  1614. #define RG_AUDENCSPAREVA30_MASK 0xff
  1615. #define RG_AUDENCSPAREVA30_MASK_SFT (0xff << 0)
  1616. #define RG_AUDENCSPAREVA18_SFT 8
  1617. #define RG_AUDENCSPAREVA18_MASK 0xff
  1618. #define RG_AUDENCSPAREVA18_MASK_SFT (0xff << 8)
  1619. /* AUDENC_ANA_CON23 */
  1620. #define RG_CLKSQ_EN_SFT 0
  1621. #define RG_CLKSQ_EN_MASK 0x1
  1622. #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
  1623. #define RG_CLKSQ_IN_SEL_TEST_SFT 1
  1624. #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
  1625. #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
  1626. #define RG_CM_REFGENSEL_SFT 2
  1627. #define RG_CM_REFGENSEL_MASK 0x1
  1628. #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
  1629. #define RG_AUDIO_VOW_EN_SFT 3
  1630. #define RG_AUDIO_VOW_EN_MASK 0x1
  1631. #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
  1632. #define RG_CLKSQ_EN_VOW_SFT 4
  1633. #define RG_CLKSQ_EN_VOW_MASK 0x1
  1634. #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 4)
  1635. #define RG_CLKAND_EN_VOW_SFT 5
  1636. #define RG_CLKAND_EN_VOW_MASK 0x1
  1637. #define RG_CLKAND_EN_VOW_MASK_SFT (0x1 << 5)
  1638. #define RG_VOWCLK_SEL_EN_VOW_SFT 6
  1639. #define RG_VOWCLK_SEL_EN_VOW_MASK 0x1
  1640. #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT (0x1 << 6)
  1641. #define RG_SPARE_VOW_SFT 7
  1642. #define RG_SPARE_VOW_MASK 0x7
  1643. #define RG_SPARE_VOW_MASK_SFT (0x7 << 7)
  1644. /* AUDDEC_ANA_CON0 */
  1645. #define RG_AUDDACLPWRUP_VAUDP32_SFT 0
  1646. #define RG_AUDDACLPWRUP_VAUDP32_MASK 0x1
  1647. #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
  1648. #define RG_AUDDACRPWRUP_VAUDP32_SFT 1
  1649. #define RG_AUDDACRPWRUP_VAUDP32_MASK 0x1
  1650. #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
  1651. #define RG_AUD_DAC_PWR_UP_VA32_SFT 2
  1652. #define RG_AUD_DAC_PWR_UP_VA32_MASK 0x1
  1653. #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT (0x1 << 2)
  1654. #define RG_AUD_DAC_PWL_UP_VA32_SFT 3
  1655. #define RG_AUD_DAC_PWL_UP_VA32_MASK 0x1
  1656. #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
  1657. #define RG_AUDHPLPWRUP_VAUDP32_SFT 4
  1658. #define RG_AUDHPLPWRUP_VAUDP32_MASK 0x1
  1659. #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT (0x1 << 4)
  1660. #define RG_AUDHPRPWRUP_VAUDP32_SFT 5
  1661. #define RG_AUDHPRPWRUP_VAUDP32_MASK 0x1
  1662. #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT (0x1 << 5)
  1663. #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_SFT 6
  1664. #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK 0x1
  1665. #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 6)
  1666. #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_SFT 7
  1667. #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK 0x1
  1668. #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 7)
  1669. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT 8
  1670. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x3
  1671. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)
  1672. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT 10
  1673. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x3
  1674. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)
  1675. #define RG_AUDHPLSCDISABLE_VAUDP32_SFT 12
  1676. #define RG_AUDHPLSCDISABLE_VAUDP32_MASK 0x1
  1677. #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 12)
  1678. #define RG_AUDHPRSCDISABLE_VAUDP32_SFT 13
  1679. #define RG_AUDHPRSCDISABLE_VAUDP32_MASK 0x1
  1680. #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT (0x1 << 13)
  1681. #define RG_AUDHPLBSCCURRENT_VAUDP32_SFT 14
  1682. #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK 0x1
  1683. #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 14)
  1684. #define RG_AUDHPRBSCCURRENT_VAUDP32_SFT 15
  1685. #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK 0x1
  1686. #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 15)
  1687. /* AUDDEC_ANA_CON1 */
  1688. #define RG_AUDHPLOUTPWRUP_VAUDP32_SFT 0
  1689. #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK 0x1
  1690. #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
  1691. #define RG_AUDHPROUTPWRUP_VAUDP32_SFT 1
  1692. #define RG_AUDHPROUTPWRUP_VAUDP32_MASK 0x1
  1693. #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
  1694. #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_SFT 2
  1695. #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK 0x1
  1696. #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 2)
  1697. #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT 3
  1698. #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK 0x1
  1699. #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
  1700. #define RG_HPLAUXFBRSW_EN_VAUDP32_SFT 4
  1701. #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK 0x1
  1702. #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 4)
  1703. #define RG_HPRAUXFBRSW_EN_VAUDP32_SFT 5
  1704. #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK 0x1
  1705. #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 5)
  1706. #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_SFT 6
  1707. #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK 0x1
  1708. #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT (0x1 << 6)
  1709. #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_SFT 7
  1710. #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK 0x1
  1711. #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT (0x1 << 7)
  1712. #define RG_HPLOUTSTGCTRL_VAUDP32_SFT 8
  1713. #define RG_HPLOUTSTGCTRL_VAUDP32_MASK 0x7
  1714. #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 8)
  1715. #define RG_HPROUTSTGCTRL_VAUDP32_SFT 12
  1716. #define RG_HPROUTSTGCTRL_VAUDP32_MASK 0x7
  1717. #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 12)
  1718. /* AUDDEC_ANA_CON2 */
  1719. #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0
  1720. #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
  1721. #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
  1722. #define RG_HPROUTPUTSTBENH_VAUDP32_SFT 4
  1723. #define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
  1724. #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
  1725. #define RG_AUDHPSTARTUP_VAUDP32_SFT 7
  1726. #define RG_AUDHPSTARTUP_VAUDP32_MASK 0x1
  1727. #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT (0x1 << 7)
  1728. #define RG_AUDREFN_DERES_EN_VAUDP32_SFT 8
  1729. #define RG_AUDREFN_DERES_EN_VAUDP32_MASK 0x1
  1730. #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT (0x1 << 8)
  1731. #define RG_HPINPUTSTBENH_VAUDP32_SFT 9
  1732. #define RG_HPINPUTSTBENH_VAUDP32_MASK 0x1
  1733. #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 9)
  1734. #define RG_HPINPUTRESET0_VAUDP32_SFT 10
  1735. #define RG_HPINPUTRESET0_VAUDP32_MASK 0x1
  1736. #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
  1737. #define RG_HPOUTPUTRESET0_VAUDP32_SFT 11
  1738. #define RG_HPOUTPUTRESET0_VAUDP32_MASK 0x1
  1739. #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 11)
  1740. #define RG_HPPSHORT2VCM_VAUDP32_SFT 12
  1741. #define RG_HPPSHORT2VCM_VAUDP32_MASK 0x7
  1742. #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT (0x7 << 12)
  1743. #define RG_AUDHPTRIM_EN_VAUDP32_SFT 15
  1744. #define RG_AUDHPTRIM_EN_VAUDP32_MASK 0x1
  1745. #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT (0x1 << 15)
  1746. /* AUDDEC_ANA_CON3 */
  1747. #define RG_AUDHPLTRIM_VAUDP32_SFT 0
  1748. #define RG_AUDHPLTRIM_VAUDP32_MASK 0x1f
  1749. #define RG_AUDHPLTRIM_VAUDP32_MASK_SFT (0x1f << 0)
  1750. #define RG_AUDHPLFINETRIM_VAUDP32_SFT 5
  1751. #define RG_AUDHPLFINETRIM_VAUDP32_MASK 0x7
  1752. #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT (0x7 << 5)
  1753. #define RG_AUDHPRTRIM_VAUDP32_SFT 8
  1754. #define RG_AUDHPRTRIM_VAUDP32_MASK 0x1f
  1755. #define RG_AUDHPRTRIM_VAUDP32_MASK_SFT (0x1f << 8)
  1756. #define RG_AUDHPRFINETRIM_VAUDP32_SFT 13
  1757. #define RG_AUDHPRFINETRIM_VAUDP32_MASK 0x7
  1758. #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT (0x7 << 13)
  1759. /* AUDDEC_ANA_CON4 */
  1760. #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT 0
  1761. #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK 0x7
  1762. #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT (0x7 << 0)
  1763. #define RG_AUDHPLFCOMPRESSEL_VAUDP32_SFT 4
  1764. #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK 0x7
  1765. #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 4)
  1766. #define RG_AUDHPHFCOMPRESSEL_VAUDP32_SFT 8
  1767. #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK 0x7
  1768. #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 8)
  1769. #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT 12
  1770. #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x3
  1771. #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)
  1772. #define RG_AUDHPCOMP_EN_VAUDP32_SFT 15
  1773. #define RG_AUDHPCOMP_EN_VAUDP32_MASK 0x1
  1774. #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT (0x1 << 15)
  1775. /* AUDDEC_ANA_CON5 */
  1776. #define RG_AUDHPDECMGAINADJ_VAUDP32_SFT 0
  1777. #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK 0x7
  1778. #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT (0x7 << 0)
  1779. #define RG_AUDHPDEDMGAINADJ_VAUDP32_SFT 4
  1780. #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK 0x7
  1781. #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT (0x7 << 4)
  1782. /* AUDDEC_ANA_CON6 */
  1783. #define RG_AUDHSPWRUP_VAUDP32_SFT 0
  1784. #define RG_AUDHSPWRUP_VAUDP32_MASK 0x1
  1785. #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
  1786. #define RG_AUDHSPWRUP_IBIAS_VAUDP32_SFT 1
  1787. #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK 0x1
  1788. #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
  1789. #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT 2
  1790. #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x3
  1791. #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
  1792. #define RG_AUDHSSCDISABLE_VAUDP32_SFT 4
  1793. #define RG_AUDHSSCDISABLE_VAUDP32_MASK 0x1
  1794. #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
  1795. #define RG_AUDHSBSCCURRENT_VAUDP32_SFT 5
  1796. #define RG_AUDHSBSCCURRENT_VAUDP32_MASK 0x1
  1797. #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
  1798. #define RG_AUDHSSTARTUP_VAUDP32_SFT 6
  1799. #define RG_AUDHSSTARTUP_VAUDP32_MASK 0x1
  1800. #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
  1801. #define RG_HSOUTPUTSTBENH_VAUDP32_SFT 7
  1802. #define RG_HSOUTPUTSTBENH_VAUDP32_MASK 0x1
  1803. #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
  1804. #define RG_HSINPUTSTBENH_VAUDP32_SFT 8
  1805. #define RG_HSINPUTSTBENH_VAUDP32_MASK 0x1
  1806. #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
  1807. #define RG_HSINPUTRESET0_VAUDP32_SFT 9
  1808. #define RG_HSINPUTRESET0_VAUDP32_MASK 0x1
  1809. #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
  1810. #define RG_HSOUTPUTRESET0_VAUDP32_SFT 10
  1811. #define RG_HSOUTPUTRESET0_VAUDP32_MASK 0x1
  1812. #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
  1813. #define RG_HSOUT_SHORTVCM_VAUDP32_SFT 11
  1814. #define RG_HSOUT_SHORTVCM_VAUDP32_MASK 0x1
  1815. #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
  1816. /* AUDDEC_ANA_CON7 */
  1817. #define RG_AUDLOLPWRUP_VAUDP32_SFT 0
  1818. #define RG_AUDLOLPWRUP_VAUDP32_MASK 0x1
  1819. #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
  1820. #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_SFT 1
  1821. #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK 0x1
  1822. #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
  1823. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT 2
  1824. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x3
  1825. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
  1826. #define RG_AUDLOLSCDISABLE_VAUDP32_SFT 4
  1827. #define RG_AUDLOLSCDISABLE_VAUDP32_MASK 0x1
  1828. #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
  1829. #define RG_AUDLOLBSCCURRENT_VAUDP32_SFT 5
  1830. #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK 0x1
  1831. #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
  1832. #define RG_AUDLOSTARTUP_VAUDP32_SFT 6
  1833. #define RG_AUDLOSTARTUP_VAUDP32_MASK 0x1
  1834. #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
  1835. #define RG_LOINPUTSTBENH_VAUDP32_SFT 7
  1836. #define RG_LOINPUTSTBENH_VAUDP32_MASK 0x1
  1837. #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
  1838. #define RG_LOOUTPUTSTBENH_VAUDP32_SFT 8
  1839. #define RG_LOOUTPUTSTBENH_VAUDP32_MASK 0x1
  1840. #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
  1841. #define RG_LOINPUTRESET0_VAUDP32_SFT 9
  1842. #define RG_LOINPUTRESET0_VAUDP32_MASK 0x1
  1843. #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
  1844. #define RG_LOOUTPUTRESET0_VAUDP32_SFT 10
  1845. #define RG_LOOUTPUTRESET0_VAUDP32_MASK 0x1
  1846. #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
  1847. #define RG_LOOUT_SHORTVCM_VAUDP32_SFT 11
  1848. #define RG_LOOUT_SHORTVCM_VAUDP32_MASK 0x1
  1849. #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
  1850. #define RG_AUDDACTPWRUP_VAUDP32_SFT 12
  1851. #define RG_AUDDACTPWRUP_VAUDP32_MASK 0x1
  1852. #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT (0x1 << 12)
  1853. #define RG_AUD_DAC_PWT_UP_VA32_SFT 13
  1854. #define RG_AUD_DAC_PWT_UP_VA32_MASK 0x1
  1855. #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT (0x1 << 13)
  1856. /* AUDDEC_ANA_CON8 */
  1857. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT 0
  1858. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK 0xf
  1859. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT (0xf << 0)
  1860. #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_SFT 4
  1861. #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x3
  1862. #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)
  1863. #define RG_AUDTRIMBUF_EN_VAUDP32_SFT 6
  1864. #define RG_AUDTRIMBUF_EN_VAUDP32_MASK 0x1
  1865. #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT (0x1 << 6)
  1866. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SFT 8
  1867. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x3
  1868. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)
  1869. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SFT 10
  1870. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x3
  1871. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)
  1872. #define RG_AUDHPSPKDET_EN_VAUDP32_SFT 12
  1873. #define RG_AUDHPSPKDET_EN_VAUDP32_MASK 0x1
  1874. #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT (0x1 << 12)
  1875. /* AUDDEC_ANA_CON9 */
  1876. #define RG_ABIDEC_RSVD0_VA32_SFT 0
  1877. #define RG_ABIDEC_RSVD0_VA32_MASK 0xff
  1878. #define RG_ABIDEC_RSVD0_VA32_MASK_SFT (0xff << 0)
  1879. #define RG_ABIDEC_RSVD0_VAUDP32_SFT 8
  1880. #define RG_ABIDEC_RSVD0_VAUDP32_MASK 0xff
  1881. #define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT (0xff << 8)
  1882. /* AUDDEC_ANA_CON10 */
  1883. #define RG_ABIDEC_RSVD1_VAUDP32_SFT 0
  1884. #define RG_ABIDEC_RSVD1_VAUDP32_MASK 0xff
  1885. #define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT (0xff << 0)
  1886. #define RG_ABIDEC_RSVD2_VAUDP32_SFT 8
  1887. #define RG_ABIDEC_RSVD2_VAUDP32_MASK 0xff
  1888. #define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT (0xff << 8)
  1889. /* AUDDEC_ANA_CON11 */
  1890. #define RG_AUDZCDMUXSEL_VAUDP32_SFT 0
  1891. #define RG_AUDZCDMUXSEL_VAUDP32_MASK 0x7
  1892. #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT (0x7 << 0)
  1893. #define RG_AUDZCDCLKSEL_VAUDP32_SFT 3
  1894. #define RG_AUDZCDCLKSEL_VAUDP32_MASK 0x1
  1895. #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
  1896. #define RG_AUDBIASADJ_0_VAUDP32_SFT 7
  1897. #define RG_AUDBIASADJ_0_VAUDP32_MASK 0x1ff
  1898. #define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT (0x1ff << 7)
  1899. /* AUDDEC_ANA_CON12 */
  1900. #define RG_AUDBIASADJ_1_VAUDP32_SFT 0
  1901. #define RG_AUDBIASADJ_1_VAUDP32_MASK 0xff
  1902. #define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT (0xff << 0)
  1903. #define RG_AUDIBIASPWRDN_VAUDP32_SFT 8
  1904. #define RG_AUDIBIASPWRDN_VAUDP32_MASK 0x1
  1905. #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT (0x1 << 8)
  1906. /* AUDDEC_ANA_CON13 */
  1907. #define RG_RSTB_DECODER_VA32_SFT 0
  1908. #define RG_RSTB_DECODER_VA32_MASK 0x1
  1909. #define RG_RSTB_DECODER_VA32_MASK_SFT (0x1 << 0)
  1910. #define RG_SEL_DECODER_96K_VA32_SFT 1
  1911. #define RG_SEL_DECODER_96K_VA32_MASK 0x1
  1912. #define RG_SEL_DECODER_96K_VA32_MASK_SFT (0x1 << 1)
  1913. #define RG_SEL_DELAY_VCORE_SFT 2
  1914. #define RG_SEL_DELAY_VCORE_MASK 0x1
  1915. #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
  1916. #define RG_AUDGLB_PWRDN_VA32_SFT 4
  1917. #define RG_AUDGLB_PWRDN_VA32_MASK 0x1
  1918. #define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4)
  1919. #define RG_AUDGLB_LP_VOW_EN_VA32_SFT 5
  1920. #define RG_AUDGLB_LP_VOW_EN_VA32_MASK 0x1
  1921. #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT (0x1 << 5)
  1922. #define RG_AUDGLB_LP2_VOW_EN_VA32_SFT 6
  1923. #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK 0x1
  1924. #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT (0x1 << 6)
  1925. /* AUDDEC_ANA_CON14 */
  1926. #define RG_LCLDO_DEC_EN_VA32_SFT 0
  1927. #define RG_LCLDO_DEC_EN_VA32_MASK 0x1
  1928. #define RG_LCLDO_DEC_EN_VA32_MASK_SFT (0x1 << 0)
  1929. #define RG_LCLDO_DEC_PDDIS_EN_VA18_SFT 1
  1930. #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK 0x1
  1931. #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
  1932. #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT 2
  1933. #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK 0x1
  1934. #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
  1935. #define RG_NVREG_EN_VAUDP32_SFT 4
  1936. #define RG_NVREG_EN_VAUDP32_MASK 0x1
  1937. #define RG_NVREG_EN_VAUDP32_MASK_SFT (0x1 << 4)
  1938. #define RG_NVREG_PULL0V_VAUDP32_SFT 5
  1939. #define RG_NVREG_PULL0V_VAUDP32_MASK 0x1
  1940. #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT (0x1 << 5)
  1941. #define RG_AUDPMU_RSVD_VA18_SFT 8
  1942. #define RG_AUDPMU_RSVD_VA18_MASK 0xff
  1943. #define RG_AUDPMU_RSVD_VA18_MASK_SFT (0xff << 8)
  1944. /* MT6359_ZCD_CON0 */
  1945. #define RG_AUDZCDENABLE_SFT 0
  1946. #define RG_AUDZCDENABLE_MASK 0x1
  1947. #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
  1948. #define RG_AUDZCDGAINSTEPTIME_SFT 1
  1949. #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
  1950. #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
  1951. #define RG_AUDZCDGAINSTEPSIZE_SFT 4
  1952. #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
  1953. #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
  1954. #define RG_AUDZCDTIMEOUTMODESEL_SFT 6
  1955. #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
  1956. #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)
  1957. /* MT6359_ZCD_CON1 */
  1958. #define RG_AUDLOLGAIN_SFT 0
  1959. #define RG_AUDLOLGAIN_MASK 0x1f
  1960. #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)
  1961. #define RG_AUDLORGAIN_SFT 7
  1962. #define RG_AUDLORGAIN_MASK 0x1f
  1963. #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)
  1964. /* MT6359_ZCD_CON2 */
  1965. #define RG_AUDHPLGAIN_SFT 0
  1966. #define RG_AUDHPLGAIN_MASK 0x1f
  1967. #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)
  1968. #define RG_AUDHPRGAIN_SFT 7
  1969. #define RG_AUDHPRGAIN_MASK 0x1f
  1970. #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)
  1971. /* MT6359_ZCD_CON3 */
  1972. #define RG_AUDHSGAIN_SFT 0
  1973. #define RG_AUDHSGAIN_MASK 0x1f
  1974. #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)
  1975. /* MT6359_ZCD_CON4 */
  1976. #define RG_AUDIVLGAIN_SFT 0
  1977. #define RG_AUDIVLGAIN_MASK 0x7
  1978. #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
  1979. #define RG_AUDIVRGAIN_SFT 8
  1980. #define RG_AUDIVRGAIN_MASK 0x7
  1981. #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
  1982. /* MT6359_ZCD_CON5 */
  1983. #define RG_AUDINTGAIN1_SFT 0
  1984. #define RG_AUDINTGAIN1_MASK 0x3f
  1985. #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)
  1986. #define RG_AUDINTGAIN2_SFT 8
  1987. #define RG_AUDINTGAIN2_MASK 0x3f
  1988. #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)
  1989. /* audio register */
  1990. #define MT6359_GPIO_DIR0 0x88
  1991. #define MT6359_GPIO_DIR0_SET 0x8a
  1992. #define MT6359_GPIO_DIR0_CLR 0x8c
  1993. #define MT6359_GPIO_DIR1 0x8e
  1994. #define MT6359_GPIO_DIR1_SET 0x90
  1995. #define MT6359_GPIO_DIR1_CLR 0x92
  1996. #define MT6359_DCXO_CW11 0x7a6
  1997. #define MT6359_DCXO_CW12 0x7a8
  1998. #define MT6359_LDO_VAUD18_CON0 0x1c98
  1999. #define MT6359_GPIO_MODE0 0xcc
  2000. #define MT6359_GPIO_MODE0_SET 0xce
  2001. #define MT6359_GPIO_MODE0_CLR 0xd0
  2002. #define MT6359_GPIO_MODE1 0xd2
  2003. #define MT6359_GPIO_MODE1_SET 0xd4
  2004. #define MT6359_GPIO_MODE1_CLR 0xd6
  2005. #define MT6359_GPIO_MODE2 0xd8
  2006. #define MT6359_GPIO_MODE2_SET 0xda
  2007. #define MT6359_GPIO_MODE2_CLR 0xdc
  2008. #define MT6359_GPIO_MODE3 0xde
  2009. #define MT6359_GPIO_MODE3_SET 0xe0
  2010. #define MT6359_GPIO_MODE3_CLR 0xe2
  2011. #define MT6359_GPIO_MODE4 0xe4
  2012. #define MT6359_GPIO_MODE4_SET 0xe6
  2013. #define MT6359_GPIO_MODE4_CLR 0xe8
  2014. #define MT6359_AUD_TOP_ID 0x2300
  2015. #define MT6359_AUD_TOP_REV0 0x2302
  2016. #define MT6359_AUD_TOP_DBI 0x2304
  2017. #define MT6359_AUD_TOP_DXI 0x2306
  2018. #define MT6359_AUD_TOP_CKPDN_TPM0 0x2308
  2019. #define MT6359_AUD_TOP_CKPDN_TPM1 0x230a
  2020. #define MT6359_AUD_TOP_CKPDN_CON0 0x230c
  2021. #define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e
  2022. #define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310
  2023. #define MT6359_AUD_TOP_CKSEL_CON0 0x2312
  2024. #define MT6359_AUD_TOP_CKSEL_CON0_SET 0x2314
  2025. #define MT6359_AUD_TOP_CKSEL_CON0_CLR 0x2316
  2026. #define MT6359_AUD_TOP_CKTST_CON0 0x2318
  2027. #define MT6359_AUD_TOP_CLK_HWEN_CON0 0x231a
  2028. #define MT6359_AUD_TOP_CLK_HWEN_CON0_SET 0x231c
  2029. #define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR 0x231e
  2030. #define MT6359_AUD_TOP_RST_CON0 0x2320
  2031. #define MT6359_AUD_TOP_RST_CON0_SET 0x2322
  2032. #define MT6359_AUD_TOP_RST_CON0_CLR 0x2324
  2033. #define MT6359_AUD_TOP_RST_BANK_CON0 0x2326
  2034. #define MT6359_AUD_TOP_INT_CON0 0x2328
  2035. #define MT6359_AUD_TOP_INT_CON0_SET 0x232a
  2036. #define MT6359_AUD_TOP_INT_CON0_CLR 0x232c
  2037. #define MT6359_AUD_TOP_INT_MASK_CON0 0x232e
  2038. #define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330
  2039. #define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332
  2040. #define MT6359_AUD_TOP_INT_STATUS0 0x2334
  2041. #define MT6359_AUD_TOP_INT_RAW_STATUS0 0x2336
  2042. #define MT6359_AUD_TOP_INT_MISC_CON0 0x2338
  2043. #define MT6359_AUD_TOP_MON_CON0 0x233a
  2044. #define MT6359_AUDIO_DIG_DSN_ID 0x2380
  2045. #define MT6359_AUDIO_DIG_DSN_REV0 0x2382
  2046. #define MT6359_AUDIO_DIG_DSN_DBI 0x2384
  2047. #define MT6359_AUDIO_DIG_DSN_DXI 0x2386
  2048. #define MT6359_AFE_UL_DL_CON0 0x2388
  2049. #define MT6359_AFE_DL_SRC2_CON0_L 0x238a
  2050. #define MT6359_AFE_UL_SRC_CON0_H 0x238c
  2051. #define MT6359_AFE_UL_SRC_CON0_L 0x238e
  2052. #define MT6359_AFE_ADDA6_L_SRC_CON0_H 0x2390
  2053. #define MT6359_AFE_ADDA6_UL_SRC_CON0_L 0x2392
  2054. #define MT6359_AFE_TOP_CON0 0x2394
  2055. #define MT6359_AUDIO_TOP_CON0 0x2396
  2056. #define MT6359_AFE_MON_DEBUG0 0x2398
  2057. #define MT6359_AFUNC_AUD_CON0 0x239a
  2058. #define MT6359_AFUNC_AUD_CON1 0x239c
  2059. #define MT6359_AFUNC_AUD_CON2 0x239e
  2060. #define MT6359_AFUNC_AUD_CON3 0x23a0
  2061. #define MT6359_AFUNC_AUD_CON4 0x23a2
  2062. #define MT6359_AFUNC_AUD_CON5 0x23a4
  2063. #define MT6359_AFUNC_AUD_CON6 0x23a6
  2064. #define MT6359_AFUNC_AUD_CON7 0x23a8
  2065. #define MT6359_AFUNC_AUD_CON8 0x23aa
  2066. #define MT6359_AFUNC_AUD_CON9 0x23ac
  2067. #define MT6359_AFUNC_AUD_CON10 0x23ae
  2068. #define MT6359_AFUNC_AUD_CON11 0x23b0
  2069. #define MT6359_AFUNC_AUD_CON12 0x23b2
  2070. #define MT6359_AFUNC_AUD_MON0 0x23b4
  2071. #define MT6359_AFUNC_AUD_MON1 0x23b6
  2072. #define MT6359_AUDRC_TUNE_MON0 0x23b8
  2073. #define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0 0x23ba
  2074. #define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x23bc
  2075. #define MT6359_AFE_ADDA_MTKAIF_MON0 0x23be
  2076. #define MT6359_AFE_ADDA_MTKAIF_MON1 0x23c0
  2077. #define MT6359_AFE_ADDA_MTKAIF_MON2 0x23c2
  2078. #define MT6359_AFE_ADDA6_MTKAIF_MON3 0x23c4
  2079. #define MT6359_AFE_ADDA_MTKAIF_MON4 0x23c6
  2080. #define MT6359_AFE_ADDA_MTKAIF_MON5 0x23c8
  2081. #define MT6359_AFE_ADDA_MTKAIF_CFG0 0x23ca
  2082. #define MT6359_AFE_ADDA_MTKAIF_RX_CFG0 0x23cc
  2083. #define MT6359_AFE_ADDA_MTKAIF_RX_CFG1 0x23ce
  2084. #define MT6359_AFE_ADDA_MTKAIF_RX_CFG2 0x23d0
  2085. #define MT6359_AFE_ADDA_MTKAIF_RX_CFG3 0x23d2
  2086. #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0 0x23d4
  2087. #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1 0x23d6
  2088. #define MT6359_AFE_SGEN_CFG0 0x23d8
  2089. #define MT6359_AFE_SGEN_CFG1 0x23da
  2090. #define MT6359_AFE_ADC_ASYNC_FIFO_CFG 0x23dc
  2091. #define MT6359_AFE_ADC_ASYNC_FIFO_CFG1 0x23de
  2092. #define MT6359_AFE_DCCLK_CFG0 0x23e0
  2093. #define MT6359_AFE_DCCLK_CFG1 0x23e2
  2094. #define MT6359_AUDIO_DIG_CFG 0x23e4
  2095. #define MT6359_AUDIO_DIG_CFG1 0x23e6
  2096. #define MT6359_AFE_AUD_PAD_TOP 0x23e8
  2097. #define MT6359_AFE_AUD_PAD_TOP_MON 0x23ea
  2098. #define MT6359_AFE_AUD_PAD_TOP_MON1 0x23ec
  2099. #define MT6359_AFE_AUD_PAD_TOP_MON2 0x23ee
  2100. #define MT6359_AFE_DL_NLE_CFG 0x23f0
  2101. #define MT6359_AFE_DL_NLE_MON 0x23f2
  2102. #define MT6359_AFE_CG_EN_MON 0x23f4
  2103. #define MT6359_AFE_MIC_ARRAY_CFG 0x23f6
  2104. #define MT6359_AFE_CHOP_CFG0 0x23f8
  2105. #define MT6359_AFE_MTKAIF_MUX_CFG 0x23fa
  2106. #define MT6359_AUDIO_DIG_2ND_DSN_ID 0x2400
  2107. #define MT6359_AUDIO_DIG_2ND_DSN_REV0 0x2402
  2108. #define MT6359_AUDIO_DIG_2ND_DSN_DBI 0x2404
  2109. #define MT6359_AUDIO_DIG_2ND_DSN_DXI 0x2406
  2110. #define MT6359_AFE_PMIC_NEWIF_CFG3 0x2408
  2111. #define MT6359_AUDIO_DIG_3RD_DSN_ID 0x2480
  2112. #define MT6359_AUDIO_DIG_3RD_DSN_REV0 0x2482
  2113. #define MT6359_AUDIO_DIG_3RD_DSN_DBI 0x2484
  2114. #define MT6359_AUDIO_DIG_3RD_DSN_DXI 0x2486
  2115. #define MT6359_AFE_NCP_CFG0 0x24de
  2116. #define MT6359_AFE_NCP_CFG1 0x24e0
  2117. #define MT6359_AFE_NCP_CFG2 0x24e2
  2118. #define MT6359_AUDENC_DSN_ID 0x2500
  2119. #define MT6359_AUDENC_DSN_REV0 0x2502
  2120. #define MT6359_AUDENC_DSN_DBI 0x2504
  2121. #define MT6359_AUDENC_DSN_FPI 0x2506
  2122. #define MT6359_AUDENC_ANA_CON0 0x2508
  2123. #define MT6359_AUDENC_ANA_CON1 0x250a
  2124. #define MT6359_AUDENC_ANA_CON2 0x250c
  2125. #define MT6359_AUDENC_ANA_CON3 0x250e
  2126. #define MT6359_AUDENC_ANA_CON4 0x2510
  2127. #define MT6359_AUDENC_ANA_CON5 0x2512
  2128. #define MT6359_AUDENC_ANA_CON6 0x2514
  2129. #define MT6359_AUDENC_ANA_CON7 0x2516
  2130. #define MT6359_AUDENC_ANA_CON8 0x2518
  2131. #define MT6359_AUDENC_ANA_CON9 0x251a
  2132. #define MT6359_AUDENC_ANA_CON10 0x251c
  2133. #define MT6359_AUDENC_ANA_CON11 0x251e
  2134. #define MT6359_AUDENC_ANA_CON12 0x2520
  2135. #define MT6359_AUDENC_ANA_CON13 0x2522
  2136. #define MT6359_AUDENC_ANA_CON14 0x2524
  2137. #define MT6359_AUDENC_ANA_CON15 0x2526
  2138. #define MT6359_AUDENC_ANA_CON16 0x2528
  2139. #define MT6359_AUDENC_ANA_CON17 0x252a
  2140. #define MT6359_AUDENC_ANA_CON18 0x252c
  2141. #define MT6359_AUDENC_ANA_CON19 0x252e
  2142. #define MT6359_AUDENC_ANA_CON20 0x2530
  2143. #define MT6359_AUDENC_ANA_CON21 0x2532
  2144. #define MT6359_AUDENC_ANA_CON22 0x2534
  2145. #define MT6359_AUDENC_ANA_CON23 0x2536
  2146. #define MT6359_AUDDEC_DSN_ID 0x2580
  2147. #define MT6359_AUDDEC_DSN_REV0 0x2582
  2148. #define MT6359_AUDDEC_DSN_DBI 0x2584
  2149. #define MT6359_AUDDEC_DSN_FPI 0x2586
  2150. #define MT6359_AUDDEC_ANA_CON0 0x2588
  2151. #define MT6359_AUDDEC_ANA_CON1 0x258a
  2152. #define MT6359_AUDDEC_ANA_CON2 0x258c
  2153. #define MT6359_AUDDEC_ANA_CON3 0x258e
  2154. #define MT6359_AUDDEC_ANA_CON4 0x2590
  2155. #define MT6359_AUDDEC_ANA_CON5 0x2592
  2156. #define MT6359_AUDDEC_ANA_CON6 0x2594
  2157. #define MT6359_AUDDEC_ANA_CON7 0x2596
  2158. #define MT6359_AUDDEC_ANA_CON8 0x2598
  2159. #define MT6359_AUDDEC_ANA_CON9 0x259a
  2160. #define MT6359_AUDDEC_ANA_CON10 0x259c
  2161. #define MT6359_AUDDEC_ANA_CON11 0x259e
  2162. #define MT6359_AUDDEC_ANA_CON12 0x25a0
  2163. #define MT6359_AUDDEC_ANA_CON13 0x25a2
  2164. #define MT6359_AUDDEC_ANA_CON14 0x25a4
  2165. #define MT6359_AUDZCD_DSN_ID 0x2600
  2166. #define MT6359_AUDZCD_DSN_REV0 0x2602
  2167. #define MT6359_AUDZCD_DSN_DBI 0x2604
  2168. #define MT6359_AUDZCD_DSN_FPI 0x2606
  2169. #define MT6359_ZCD_CON0 0x2608
  2170. #define MT6359_ZCD_CON1 0x260a
  2171. #define MT6359_ZCD_CON2 0x260c
  2172. #define MT6359_ZCD_CON3 0x260e
  2173. #define MT6359_ZCD_CON4 0x2610
  2174. #define MT6359_ZCD_CON5 0x2612
  2175. #define MT6359_ACCDET_DSN_DIG_ID 0x2680
  2176. #define MT6359_ACCDET_DSN_DIG_REV0 0x2682
  2177. #define MT6359_ACCDET_DSN_DBI 0x2684
  2178. #define MT6359_ACCDET_DSN_FPI 0x2686
  2179. #define MT6359_ACCDET_CON0 0x2688
  2180. #define MT6359_ACCDET_CON1 0x268a
  2181. #define MT6359_ACCDET_CON2 0x268c
  2182. #define MT6359_ACCDET_CON3 0x268e
  2183. #define MT6359_ACCDET_CON4 0x2690
  2184. #define MT6359_ACCDET_CON5 0x2692
  2185. #define MT6359_ACCDET_CON6 0x2694
  2186. #define MT6359_ACCDET_CON7 0x2696
  2187. #define MT6359_ACCDET_CON8 0x2698
  2188. #define MT6359_ACCDET_CON9 0x269a
  2189. #define MT6359_ACCDET_CON10 0x269c
  2190. #define MT6359_ACCDET_CON11 0x269e
  2191. #define MT6359_ACCDET_CON12 0x26a0
  2192. #define MT6359_ACCDET_CON13 0x26a2
  2193. #define MT6359_ACCDET_CON14 0x26a4
  2194. #define MT6359_ACCDET_CON15 0x26a6
  2195. #define MT6359_ACCDET_CON16 0x26a8
  2196. #define MT6359_ACCDET_CON17 0x26aa
  2197. #define MT6359_ACCDET_CON18 0x26ac
  2198. #define MT6359_ACCDET_CON19 0x26ae
  2199. #define MT6359_ACCDET_CON20 0x26b0
  2200. #define MT6359_ACCDET_CON21 0x26b2
  2201. #define MT6359_ACCDET_CON22 0x26b4
  2202. #define MT6359_ACCDET_CON23 0x26b6
  2203. #define MT6359_ACCDET_CON24 0x26b8
  2204. #define MT6359_ACCDET_CON25 0x26ba
  2205. #define MT6359_ACCDET_CON26 0x26bc
  2206. #define MT6359_ACCDET_CON27 0x26be
  2207. #define MT6359_ACCDET_CON28 0x26c0
  2208. #define MT6359_ACCDET_CON29 0x26c2
  2209. #define MT6359_ACCDET_CON30 0x26c4
  2210. #define MT6359_ACCDET_CON31 0x26c6
  2211. #define MT6359_ACCDET_CON32 0x26c8
  2212. #define MT6359_ACCDET_CON33 0x26ca
  2213. #define MT6359_ACCDET_CON34 0x26cc
  2214. #define MT6359_ACCDET_CON35 0x26ce
  2215. #define MT6359_ACCDET_CON36 0x26d0
  2216. #define MT6359_ACCDET_CON37 0x26d2
  2217. #define MT6359_ACCDET_CON38 0x26d4
  2218. #define MT6359_ACCDET_CON39 0x26d6
  2219. #define MT6359_ACCDET_CON40 0x26d8
  2220. #define MT6359_MAX_REGISTER MT6359_ZCD_CON5
  2221. /* dl bias */
  2222. #define DRBIAS_MASK 0x7
  2223. #define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
  2224. #define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)
  2225. #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
  2226. #define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)
  2227. #define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)
  2228. #define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)
  2229. #define IBIAS_MASK 0x3
  2230. #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
  2231. #define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)
  2232. #define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)
  2233. #define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)
  2234. #define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)
  2235. #define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)
  2236. #define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)
  2237. #define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)
  2238. /* dl gain */
  2239. #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
  2240. #define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)
  2241. #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
  2242. #define DL_GAIN_REG_MASK 0x0f9f
  2243. /* mic type mux */
  2244. #define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
  2245. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
  2246. .info = snd_soc_info_enum_double, \
  2247. .get = xhandler_get, .put = xhandler_put, \
  2248. .private_value = (unsigned long)&(xenum) }
  2249. enum {
  2250. MT6359_MTKAIF_PROTOCOL_1 = 0,
  2251. MT6359_MTKAIF_PROTOCOL_2,
  2252. MT6359_MTKAIF_PROTOCOL_2_CLK_P2,
  2253. };
  2254. enum {
  2255. MT6359_AIF_1 = 0, /* dl: hp, rcv, hp+lo */
  2256. MT6359_AIF_2, /* dl: lo only */
  2257. MT6359_AIF_NUM,
  2258. };
  2259. enum {
  2260. AUDIO_ANALOG_VOLUME_HSOUTL,
  2261. AUDIO_ANALOG_VOLUME_HSOUTR,
  2262. AUDIO_ANALOG_VOLUME_HPOUTL,
  2263. AUDIO_ANALOG_VOLUME_HPOUTR,
  2264. AUDIO_ANALOG_VOLUME_LINEOUTL,
  2265. AUDIO_ANALOG_VOLUME_LINEOUTR,
  2266. AUDIO_ANALOG_VOLUME_MICAMP1,
  2267. AUDIO_ANALOG_VOLUME_MICAMP2,
  2268. AUDIO_ANALOG_VOLUME_MICAMP3,
  2269. AUDIO_ANALOG_VOLUME_TYPE_MAX
  2270. };
  2271. enum {
  2272. MUX_MIC_TYPE_0, /* ain0, micbias 0 */
  2273. MUX_MIC_TYPE_1, /* ain1, micbias 1 */
  2274. MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */
  2275. MUX_PGA_L,
  2276. MUX_PGA_R,
  2277. MUX_PGA_3,
  2278. MUX_HP,
  2279. MUX_NUM,
  2280. };
  2281. enum {
  2282. DEVICE_HP,
  2283. DEVICE_LO,
  2284. DEVICE_RCV,
  2285. DEVICE_MIC1,
  2286. DEVICE_MIC2,
  2287. DEVICE_NUM
  2288. };
  2289. enum {
  2290. HP_GAIN_CTL_ZCD = 0,
  2291. HP_GAIN_CTL_NLE,
  2292. HP_GAIN_CTL_NUM,
  2293. };
  2294. enum {
  2295. HP_MUX_OPEN = 0,
  2296. HP_MUX_HPSPK,
  2297. HP_MUX_HP,
  2298. HP_MUX_TEST_MODE,
  2299. HP_MUX_HP_IMPEDANCE,
  2300. HP_MUX_MASK = 0x7,
  2301. };
  2302. enum {
  2303. RCV_MUX_OPEN = 0,
  2304. RCV_MUX_MUTE,
  2305. RCV_MUX_VOICE_PLAYBACK,
  2306. RCV_MUX_TEST_MODE,
  2307. RCV_MUX_MASK = 0x3,
  2308. };
  2309. enum {
  2310. LO_MUX_OPEN = 0,
  2311. LO_MUX_L_DAC,
  2312. LO_MUX_3RD_DAC,
  2313. LO_MUX_TEST_MODE,
  2314. LO_MUX_MASK = 0x3,
  2315. };
  2316. /* Supply widget subseq */
  2317. enum {
  2318. /* common */
  2319. SUPPLY_SEQ_CLK_BUF,
  2320. SUPPLY_SEQ_LDO_VAUD18,
  2321. SUPPLY_SEQ_AUD_GLB,
  2322. SUPPLY_SEQ_HP_PULL_DOWN,
  2323. SUPPLY_SEQ_CLKSQ,
  2324. SUPPLY_SEQ_ADC_CLKGEN,
  2325. SUPPLY_SEQ_TOP_CK,
  2326. SUPPLY_SEQ_TOP_CK_LAST,
  2327. SUPPLY_SEQ_DCC_CLK,
  2328. SUPPLY_SEQ_MIC_BIAS,
  2329. SUPPLY_SEQ_DMIC,
  2330. SUPPLY_SEQ_AUD_TOP,
  2331. SUPPLY_SEQ_AUD_TOP_LAST,
  2332. SUPPLY_SEQ_DL_SDM_FIFO_CLK,
  2333. SUPPLY_SEQ_DL_SDM,
  2334. SUPPLY_SEQ_DL_NCP,
  2335. SUPPLY_SEQ_AFE,
  2336. /* playback */
  2337. SUPPLY_SEQ_DL_SRC,
  2338. SUPPLY_SEQ_DL_ESD_RESIST,
  2339. SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
  2340. SUPPLY_SEQ_HP_MUTE,
  2341. SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
  2342. SUPPLY_SEQ_DL_LDO,
  2343. SUPPLY_SEQ_DL_NV,
  2344. SUPPLY_SEQ_HP_ANA_TRIM,
  2345. SUPPLY_SEQ_DL_IBIST,
  2346. /* capture */
  2347. SUPPLY_SEQ_UL_PGA,
  2348. SUPPLY_SEQ_UL_ADC,
  2349. SUPPLY_SEQ_UL_MTKAIF,
  2350. SUPPLY_SEQ_UL_SRC_DMIC,
  2351. SUPPLY_SEQ_UL_SRC,
  2352. };
  2353. enum {
  2354. CH_L = 0,
  2355. CH_R,
  2356. NUM_CH,
  2357. };
  2358. enum {
  2359. DRBIAS_4UA = 0,
  2360. DRBIAS_5UA,
  2361. DRBIAS_6UA,
  2362. DRBIAS_7UA,
  2363. DRBIAS_8UA,
  2364. DRBIAS_9UA,
  2365. DRBIAS_10UA,
  2366. DRBIAS_11UA,
  2367. };
  2368. enum {
  2369. IBIAS_4UA = 0,
  2370. IBIAS_5UA,
  2371. IBIAS_6UA,
  2372. IBIAS_7UA,
  2373. };
  2374. enum {
  2375. IBIAS_ZCD_3UA = 0,
  2376. IBIAS_ZCD_4UA,
  2377. IBIAS_ZCD_5UA,
  2378. IBIAS_ZCD_6UA,
  2379. };
  2380. enum {
  2381. MIC_BIAS_1P7 = 0,
  2382. MIC_BIAS_1P8,
  2383. MIC_BIAS_1P9,
  2384. MIC_BIAS_2P0,
  2385. MIC_BIAS_2P1,
  2386. MIC_BIAS_2P5,
  2387. MIC_BIAS_2P6,
  2388. MIC_BIAS_2P7,
  2389. };
  2390. /* dl pga gain */
  2391. enum {
  2392. DL_GAIN_8DB = 0,
  2393. DL_GAIN_0DB = 8,
  2394. DL_GAIN_N_1DB = 9,
  2395. DL_GAIN_N_10DB = 18,
  2396. DL_GAIN_N_22DB = 30,
  2397. DL_GAIN_N_40DB = 0x1f,
  2398. };
  2399. /* Mic Type MUX */
  2400. enum {
  2401. MIC_TYPE_MUX_IDLE = 0,
  2402. MIC_TYPE_MUX_ACC,
  2403. MIC_TYPE_MUX_DMIC,
  2404. MIC_TYPE_MUX_DCC,
  2405. MIC_TYPE_MUX_DCC_ECM_DIFF,
  2406. MIC_TYPE_MUX_DCC_ECM_SINGLE,
  2407. };
  2408. /* UL SRC MUX */
  2409. enum {
  2410. UL_SRC_MUX_AMIC = 0,
  2411. UL_SRC_MUX_DMIC,
  2412. };
  2413. /* MISO MUX */
  2414. enum {
  2415. MISO_MUX_UL1_CH1 = 0,
  2416. MISO_MUX_UL1_CH2,
  2417. MISO_MUX_UL2_CH1,
  2418. MISO_MUX_UL2_CH2,
  2419. };
  2420. /* DMIC MUX */
  2421. enum {
  2422. DMIC_MUX_DMIC_DATA0 = 0,
  2423. DMIC_MUX_DMIC_DATA1_L,
  2424. DMIC_MUX_DMIC_DATA1_L_1,
  2425. DMIC_MUX_DMIC_DATA1_R,
  2426. };
  2427. /* ADC L MUX */
  2428. enum {
  2429. ADC_MUX_IDLE = 0,
  2430. ADC_MUX_AIN0,
  2431. ADC_MUX_PREAMPLIFIER,
  2432. ADC_MUX_IDLE1,
  2433. };
  2434. /* PGA L MUX */
  2435. enum {
  2436. PGA_L_MUX_NONE = 0,
  2437. PGA_L_MUX_AIN0,
  2438. PGA_L_MUX_AIN1,
  2439. };
  2440. /* PGA R MUX */
  2441. enum {
  2442. PGA_R_MUX_NONE = 0,
  2443. PGA_R_MUX_AIN2,
  2444. PGA_R_MUX_AIN3,
  2445. PGA_R_MUX_AIN0,
  2446. };
  2447. /* PGA 3 MUX */
  2448. enum {
  2449. PGA_3_MUX_NONE = 0,
  2450. PGA_3_MUX_AIN3,
  2451. PGA_3_MUX_AIN2,
  2452. };
  2453. struct mt6359_priv {
  2454. struct device *dev;
  2455. struct regmap *regmap;
  2456. unsigned int dl_rate[MT6359_AIF_NUM];
  2457. unsigned int ul_rate[MT6359_AIF_NUM];
  2458. int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  2459. unsigned int mux_select[MUX_NUM];
  2460. unsigned int dmic_one_wire_mode;
  2461. int dev_counter[DEVICE_NUM];
  2462. int hp_gain_ctl;
  2463. int hp_hifi_mode;
  2464. int mtkaif_protocol;
  2465. struct regulator *avdd_reg;
  2466. };
  2467. #define CODEC_MT6359_NAME "mtk-codec-mt6359"
  2468. #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
  2469. (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
  2470. (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
  2471. #endif/* end _MT6359_H_ */