mt6359.c 79 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // mt6359.c -- mt6359 ALSA SoC audio codec driver
  4. //
  5. // Copyright (c) 2020 MediaTek Inc.
  6. // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
  7. #include <linux/delay.h>
  8. #include <linux/kthread.h>
  9. #include <linux/mfd/mt6397/core.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/sched.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include "mt6359.h"
  18. static void mt6359_set_playback_gpio(struct mt6359_priv *priv)
  19. {
  20. /* set gpio mosi mode, clk / data mosi */
  21. regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
  22. regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
  23. /* sync mosi */
  24. regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
  25. regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
  26. }
  27. static void mt6359_reset_playback_gpio(struct mt6359_priv *priv)
  28. {
  29. /* set pad_aud_*_mosi to GPIO mode and dir input
  30. * reason:
  31. * pad_aud_dat_mosi*, because the pin is used as boot strap
  32. * don't clean clk/sync, for mtkaif protocol 2
  33. */
  34. regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
  35. regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0);
  36. }
  37. static void mt6359_set_capture_gpio(struct mt6359_priv *priv)
  38. {
  39. /* set gpio miso mode */
  40. regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
  41. regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
  42. regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
  43. regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
  44. }
  45. static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
  46. {
  47. /* set pad_aud_*_miso to GPIO mode and dir input
  48. * reason:
  49. * pad_aud_clk_miso, because when playback only the miso_clk
  50. * will also have 26m, so will have power leak
  51. * pad_aud_dat_miso*, because the pin is used as boot strap
  52. */
  53. regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
  54. regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
  55. regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
  56. 0x7 << 13, 0x0);
  57. regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
  58. 0x3 << 0, 0x0);
  59. }
  60. static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
  61. {
  62. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
  63. RG_RSTB_DECODER_VA32_MASK_SFT,
  64. (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
  65. }
  66. static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)
  67. {
  68. switch (priv->mtkaif_protocol) {
  69. case MT6359_MTKAIF_PROTOCOL_2_CLK_P2:
  70. /* MTKAIF TX format setting */
  71. regmap_update_bits(priv->regmap,
  72. MT6359_AFE_ADDA_MTKAIF_CFG0,
  73. 0xffff, 0x0210);
  74. /* enable aud_pad TX fifos */
  75. regmap_update_bits(priv->regmap,
  76. MT6359_AFE_AUD_PAD_TOP,
  77. 0xff00, 0x3800);
  78. regmap_update_bits(priv->regmap,
  79. MT6359_AFE_AUD_PAD_TOP,
  80. 0xff00, 0x3900);
  81. break;
  82. case MT6359_MTKAIF_PROTOCOL_2:
  83. /* MTKAIF TX format setting */
  84. regmap_update_bits(priv->regmap,
  85. MT6359_AFE_ADDA_MTKAIF_CFG0,
  86. 0xffff, 0x0210);
  87. /* enable aud_pad TX fifos */
  88. regmap_update_bits(priv->regmap,
  89. MT6359_AFE_AUD_PAD_TOP,
  90. 0xff00, 0x3100);
  91. break;
  92. case MT6359_MTKAIF_PROTOCOL_1:
  93. default:
  94. /* MTKAIF TX format setting */
  95. regmap_update_bits(priv->regmap,
  96. MT6359_AFE_ADDA_MTKAIF_CFG0,
  97. 0xffff, 0x0000);
  98. /* enable aud_pad TX fifos */
  99. regmap_update_bits(priv->regmap,
  100. MT6359_AFE_AUD_PAD_TOP,
  101. 0xff00, 0x3100);
  102. break;
  103. }
  104. }
  105. static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
  106. {
  107. /* disable aud_pad TX fifos */
  108. regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
  109. 0xff00, 0x3000);
  110. }
  111. static void zcd_disable(struct mt6359_priv *priv)
  112. {
  113. regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
  114. }
  115. static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
  116. {
  117. int i = 0, stage = 0;
  118. int target = 7;
  119. /* Enable/Reduce HPL/R main output stage step by step */
  120. for (i = 0; i <= target; i++) {
  121. stage = up ? i : target - i;
  122. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
  123. RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT,
  124. stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT);
  125. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
  126. RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT,
  127. stage << RG_HPROUTSTGCTRL_VAUDP32_SFT);
  128. usleep_range(600, 650);
  129. }
  130. }
  131. static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)
  132. {
  133. int i = 0, stage = 0;
  134. int target = 0xf;
  135. /* Enable/Reduce HP aux feedback loop gain step by step */
  136. for (i = 0; i <= target; i++) {
  137. stage = up ? i : target - i;
  138. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
  139. 0xf << 12, stage << 12);
  140. usleep_range(600, 650);
  141. }
  142. }
  143. static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)
  144. {
  145. int i = 0, stage = 0;
  146. int target = 0x3;
  147. /* Set input diff pair bias select (Hi-Fi mode) */
  148. if (priv->hp_hifi_mode) {
  149. /* Reduce HP aux feedback loop gain step by step */
  150. for (i = 0; i <= target; i++) {
  151. stage = increase ? i : target - i;
  152. regmap_update_bits(priv->regmap,
  153. MT6359_AUDDEC_ANA_CON10,
  154. 0x3 << 3, stage << 3);
  155. usleep_range(100, 150);
  156. }
  157. }
  158. }
  159. static void hp_pull_down(struct mt6359_priv *priv, bool enable)
  160. {
  161. int i;
  162. if (enable) {
  163. for (i = 0x0; i <= 0x7; i++) {
  164. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
  165. RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
  166. i << RG_HPPSHORT2VCM_VAUDP32_SFT);
  167. usleep_range(100, 150);
  168. }
  169. } else {
  170. for (i = 0x7; i >= 0x0; i--) {
  171. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
  172. RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
  173. i << RG_HPPSHORT2VCM_VAUDP32_SFT);
  174. usleep_range(100, 150);
  175. }
  176. }
  177. }
  178. static bool is_valid_hp_pga_idx(int reg_idx)
  179. {
  180. return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) ||
  181. reg_idx == DL_GAIN_N_40DB;
  182. }
  183. static void headset_volume_ramp(struct mt6359_priv *priv,
  184. int from, int to)
  185. {
  186. int offset = 0, count = 1, reg_idx;
  187. if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) {
  188. dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
  189. __func__, from, to);
  190. return;
  191. }
  192. dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to);
  193. if (to > from)
  194. offset = to - from;
  195. else
  196. offset = from - to;
  197. while (offset > 0) {
  198. if (to > from)
  199. reg_idx = from + count;
  200. else
  201. reg_idx = from - count;
  202. if (is_valid_hp_pga_idx(reg_idx)) {
  203. regmap_update_bits(priv->regmap,
  204. MT6359_ZCD_CON2,
  205. DL_GAIN_REG_MASK,
  206. (reg_idx << 7) | reg_idx);
  207. usleep_range(600, 650);
  208. }
  209. offset--;
  210. count++;
  211. }
  212. }
  213. static int mt6359_put_volsw(struct snd_kcontrol *kcontrol,
  214. struct snd_ctl_elem_value *ucontrol)
  215. {
  216. struct snd_soc_component *component =
  217. snd_soc_kcontrol_component(kcontrol);
  218. struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
  219. struct soc_mixer_control *mc =
  220. (struct soc_mixer_control *)kcontrol->private_value;
  221. unsigned int reg;
  222. int index = ucontrol->value.integer.value[0];
  223. int ret;
  224. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  225. if (ret < 0)
  226. return ret;
  227. switch (mc->reg) {
  228. case MT6359_ZCD_CON2:
  229. regmap_read(priv->regmap, MT6359_ZCD_CON2, &reg);
  230. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
  231. (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
  232. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
  233. (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
  234. break;
  235. case MT6359_ZCD_CON1:
  236. regmap_read(priv->regmap, MT6359_ZCD_CON1, &reg);
  237. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
  238. (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
  239. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
  240. (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
  241. break;
  242. case MT6359_ZCD_CON3:
  243. regmap_read(priv->regmap, MT6359_ZCD_CON3, &reg);
  244. priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
  245. (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
  246. break;
  247. case MT6359_AUDENC_ANA_CON0:
  248. regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, &reg);
  249. priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
  250. (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
  251. break;
  252. case MT6359_AUDENC_ANA_CON1:
  253. regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, &reg);
  254. priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
  255. (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
  256. break;
  257. case MT6359_AUDENC_ANA_CON2:
  258. regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, &reg);
  259. priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
  260. (reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK;
  261. break;
  262. }
  263. dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
  264. __func__, kcontrol->id.name, mc->reg, reg, index);
  265. return ret;
  266. }
  267. /* MUX */
  268. /* LOL MUX */
  269. static const char * const lo_in_mux_map[] = {
  270. "Open", "Playback_L_DAC", "Playback", "Test Mode"
  271. };
  272. static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);
  273. static const struct snd_kcontrol_new lo_in_mux_control =
  274. SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum);
  275. /*HP MUX */
  276. static const char * const hp_in_mux_map[] = {
  277. "Open",
  278. "LoudSPK Playback",
  279. "Audio Playback",
  280. "Test Mode",
  281. "HP Impedance",
  282. };
  283. static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum,
  284. SND_SOC_NOPM,
  285. 0,
  286. hp_in_mux_map);
  287. static const struct snd_kcontrol_new hp_in_mux_control =
  288. SOC_DAPM_ENUM("HP Select", hp_in_mux_map_enum);
  289. /* RCV MUX */
  290. static const char * const rcv_in_mux_map[] = {
  291. "Open", "Mute", "Voice Playback", "Test Mode"
  292. };
  293. static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
  294. SND_SOC_NOPM,
  295. 0,
  296. rcv_in_mux_map);
  297. static const struct snd_kcontrol_new rcv_in_mux_control =
  298. SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
  299. /* DAC In MUX */
  300. static const char * const dac_in_mux_map[] = {
  301. "Normal Path", "Sgen"
  302. };
  303. static int dac_in_mux_map_value[] = {
  304. 0x0, 0x1,
  305. };
  306. static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
  307. MT6359_AFE_TOP_CON0,
  308. DL_SINE_ON_SFT,
  309. DL_SINE_ON_MASK,
  310. dac_in_mux_map,
  311. dac_in_mux_map_value);
  312. static const struct snd_kcontrol_new dac_in_mux_control =
  313. SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
  314. /* AIF Out MUX */
  315. static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
  316. MT6359_AFE_TOP_CON0,
  317. UL_SINE_ON_SFT,
  318. UL_SINE_ON_MASK,
  319. dac_in_mux_map,
  320. dac_in_mux_map_value);
  321. static const struct snd_kcontrol_new aif_out_mux_control =
  322. SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
  323. static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum,
  324. MT6359_AFE_TOP_CON0,
  325. ADDA6_UL_SINE_ON_SFT,
  326. ADDA6_UL_SINE_ON_MASK,
  327. dac_in_mux_map,
  328. dac_in_mux_map_value);
  329. static const struct snd_kcontrol_new aif2_out_mux_control =
  330. SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum);
  331. static const char * const ul_src_mux_map[] = {
  332. "AMIC",
  333. "DMIC",
  334. };
  335. static int ul_src_mux_map_value[] = {
  336. UL_SRC_MUX_AMIC,
  337. UL_SRC_MUX_DMIC,
  338. };
  339. static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum,
  340. MT6359_AFE_UL_SRC_CON0_L,
  341. UL_SDM_3_LEVEL_CTL_SFT,
  342. UL_SDM_3_LEVEL_CTL_MASK,
  343. ul_src_mux_map,
  344. ul_src_mux_map_value);
  345. static const struct snd_kcontrol_new ul_src_mux_control =
  346. SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum);
  347. static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum,
  348. MT6359_AFE_ADDA6_UL_SRC_CON0_L,
  349. ADDA6_UL_SDM_3_LEVEL_CTL_SFT,
  350. ADDA6_UL_SDM_3_LEVEL_CTL_MASK,
  351. ul_src_mux_map,
  352. ul_src_mux_map_value);
  353. static const struct snd_kcontrol_new ul2_src_mux_control =
  354. SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum);
  355. static const char * const miso_mux_map[] = {
  356. "UL1_CH1",
  357. "UL1_CH2",
  358. "UL2_CH1",
  359. "UL2_CH2",
  360. };
  361. static int miso_mux_map_value[] = {
  362. MISO_MUX_UL1_CH1,
  363. MISO_MUX_UL1_CH2,
  364. MISO_MUX_UL2_CH1,
  365. MISO_MUX_UL2_CH2,
  366. };
  367. static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum,
  368. MT6359_AFE_MTKAIF_MUX_CFG,
  369. RG_ADDA_CH1_SEL_SFT,
  370. RG_ADDA_CH1_SEL_MASK,
  371. miso_mux_map,
  372. miso_mux_map_value);
  373. static const struct snd_kcontrol_new miso0_mux_control =
  374. SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum);
  375. static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum,
  376. MT6359_AFE_MTKAIF_MUX_CFG,
  377. RG_ADDA_CH2_SEL_SFT,
  378. RG_ADDA_CH2_SEL_MASK,
  379. miso_mux_map,
  380. miso_mux_map_value);
  381. static const struct snd_kcontrol_new miso1_mux_control =
  382. SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum);
  383. static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum,
  384. MT6359_AFE_MTKAIF_MUX_CFG,
  385. RG_ADDA6_CH1_SEL_SFT,
  386. RG_ADDA6_CH1_SEL_MASK,
  387. miso_mux_map,
  388. miso_mux_map_value);
  389. static const struct snd_kcontrol_new miso2_mux_control =
  390. SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum);
  391. static const char * const dmic_mux_map[] = {
  392. "DMIC_DATA0",
  393. "DMIC_DATA1_L",
  394. "DMIC_DATA1_L_1",
  395. "DMIC_DATA1_R",
  396. };
  397. static int dmic_mux_map_value[] = {
  398. DMIC_MUX_DMIC_DATA0,
  399. DMIC_MUX_DMIC_DATA1_L,
  400. DMIC_MUX_DMIC_DATA1_L_1,
  401. DMIC_MUX_DMIC_DATA1_R,
  402. };
  403. static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum,
  404. MT6359_AFE_MIC_ARRAY_CFG,
  405. RG_DMIC_ADC1_SOURCE_SEL_SFT,
  406. RG_DMIC_ADC1_SOURCE_SEL_MASK,
  407. dmic_mux_map,
  408. dmic_mux_map_value);
  409. static const struct snd_kcontrol_new dmic0_mux_control =
  410. SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum);
  411. /* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */
  412. static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum,
  413. MT6359_AFE_MIC_ARRAY_CFG,
  414. RG_DMIC_ADC3_SOURCE_SEL_SFT,
  415. RG_DMIC_ADC3_SOURCE_SEL_MASK,
  416. dmic_mux_map,
  417. dmic_mux_map_value);
  418. static const struct snd_kcontrol_new dmic1_mux_control =
  419. SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum);
  420. /* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */
  421. static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum,
  422. MT6359_AFE_MIC_ARRAY_CFG,
  423. RG_DMIC_ADC2_SOURCE_SEL_SFT,
  424. RG_DMIC_ADC2_SOURCE_SEL_MASK,
  425. dmic_mux_map,
  426. dmic_mux_map_value);
  427. static const struct snd_kcontrol_new dmic2_mux_control =
  428. SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum);
  429. /* ADC L MUX */
  430. static const char * const adc_left_mux_map[] = {
  431. "Idle", "AIN0", "Left Preamplifier", "Idle_1"
  432. };
  433. static int adc_mux_map_value[] = {
  434. ADC_MUX_IDLE,
  435. ADC_MUX_AIN0,
  436. ADC_MUX_PREAMPLIFIER,
  437. ADC_MUX_IDLE1,
  438. };
  439. static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
  440. MT6359_AUDENC_ANA_CON0,
  441. RG_AUDADCLINPUTSEL_SFT,
  442. RG_AUDADCLINPUTSEL_MASK,
  443. adc_left_mux_map,
  444. adc_mux_map_value);
  445. static const struct snd_kcontrol_new adc_left_mux_control =
  446. SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
  447. /* ADC R MUX */
  448. static const char * const adc_right_mux_map[] = {
  449. "Idle", "AIN0", "Right Preamplifier", "Idle_1"
  450. };
  451. static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
  452. MT6359_AUDENC_ANA_CON1,
  453. RG_AUDADCRINPUTSEL_SFT,
  454. RG_AUDADCRINPUTSEL_MASK,
  455. adc_right_mux_map,
  456. adc_mux_map_value);
  457. static const struct snd_kcontrol_new adc_right_mux_control =
  458. SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
  459. /* ADC 3 MUX */
  460. static const char * const adc_3_mux_map[] = {
  461. "Idle", "AIN0", "Preamplifier", "Idle_1"
  462. };
  463. static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum,
  464. MT6359_AUDENC_ANA_CON2,
  465. RG_AUDADC3INPUTSEL_SFT,
  466. RG_AUDADC3INPUTSEL_MASK,
  467. adc_3_mux_map,
  468. adc_mux_map_value);
  469. static const struct snd_kcontrol_new adc_3_mux_control =
  470. SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum);
  471. static const char * const pga_l_mux_map[] = {
  472. "None", "AIN0", "AIN1"
  473. };
  474. static int pga_l_mux_map_value[] = {
  475. PGA_L_MUX_NONE,
  476. PGA_L_MUX_AIN0,
  477. PGA_L_MUX_AIN1
  478. };
  479. static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
  480. MT6359_AUDENC_ANA_CON0,
  481. RG_AUDPREAMPLINPUTSEL_SFT,
  482. RG_AUDPREAMPLINPUTSEL_MASK,
  483. pga_l_mux_map,
  484. pga_l_mux_map_value);
  485. static const struct snd_kcontrol_new pga_left_mux_control =
  486. SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
  487. static const char * const pga_r_mux_map[] = {
  488. "None", "AIN2", "AIN3", "AIN0"
  489. };
  490. static int pga_r_mux_map_value[] = {
  491. PGA_R_MUX_NONE,
  492. PGA_R_MUX_AIN2,
  493. PGA_R_MUX_AIN3,
  494. PGA_R_MUX_AIN0
  495. };
  496. static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
  497. MT6359_AUDENC_ANA_CON1,
  498. RG_AUDPREAMPRINPUTSEL_SFT,
  499. RG_AUDPREAMPRINPUTSEL_MASK,
  500. pga_r_mux_map,
  501. pga_r_mux_map_value);
  502. static const struct snd_kcontrol_new pga_right_mux_control =
  503. SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
  504. static const char * const pga_3_mux_map[] = {
  505. "None", "AIN3", "AIN2"
  506. };
  507. static int pga_3_mux_map_value[] = {
  508. PGA_3_MUX_NONE,
  509. PGA_3_MUX_AIN3,
  510. PGA_3_MUX_AIN2
  511. };
  512. static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum,
  513. MT6359_AUDENC_ANA_CON2,
  514. RG_AUDPREAMP3INPUTSEL_SFT,
  515. RG_AUDPREAMP3INPUTSEL_MASK,
  516. pga_3_mux_map,
  517. pga_3_mux_map_value);
  518. static const struct snd_kcontrol_new pga_3_mux_control =
  519. SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum);
  520. static int mt_sgen_event(struct snd_soc_dapm_widget *w,
  521. struct snd_kcontrol *kcontrol,
  522. int event)
  523. {
  524. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  525. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  526. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  527. switch (event) {
  528. case SND_SOC_DAPM_PRE_PMU:
  529. /* sdm audio fifo clock power on */
  530. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
  531. /* scrambler clock on enable */
  532. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
  533. /* sdm power on */
  534. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
  535. /* sdm fifo enable */
  536. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b);
  537. regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
  538. 0xff3f,
  539. 0x0000);
  540. regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
  541. 0xffff,
  542. 0x0001);
  543. break;
  544. case SND_SOC_DAPM_POST_PMD:
  545. /* DL scrambler disabling sequence */
  546. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
  547. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
  548. break;
  549. default:
  550. break;
  551. }
  552. return 0;
  553. }
  554. static void mtk_hp_enable(struct mt6359_priv *priv)
  555. {
  556. if (priv->hp_hifi_mode) {
  557. /* Set HP DR bias current optimization, 010: 6uA */
  558. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
  559. DRBIAS_HP_MASK_SFT,
  560. DRBIAS_6UA << DRBIAS_HP_SFT);
  561. /* Set HP & ZCD bias current optimization */
  562. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  563. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  564. IBIAS_ZCD_MASK_SFT,
  565. IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
  566. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  567. IBIAS_HP_MASK_SFT,
  568. IBIAS_5UA << IBIAS_HP_SFT);
  569. } else {
  570. /* Set HP DR bias current optimization, 001: 5uA */
  571. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
  572. DRBIAS_HP_MASK_SFT,
  573. DRBIAS_5UA << DRBIAS_HP_SFT);
  574. /* Set HP & ZCD bias current optimization */
  575. /* 00: ZCD: 3uA, HP/HS/LO: 4uA */
  576. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  577. IBIAS_ZCD_MASK_SFT,
  578. IBIAS_ZCD_3UA << IBIAS_ZCD_SFT);
  579. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  580. IBIAS_HP_MASK_SFT,
  581. IBIAS_4UA << IBIAS_HP_SFT);
  582. }
  583. /* HP damp circuit enable */
  584. /* Enable HPRN/HPLN output 4K to VCM */
  585. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
  586. /* HP Feedback Cap select 2'b00: 15pF */
  587. /* for >= 96KHz sampling rate: 2'b01: 10.5pF */
  588. if (priv->dl_rate[MT6359_AIF_1] >= 96000)
  589. regmap_update_bits(priv->regmap,
  590. MT6359_AUDDEC_ANA_CON4,
  591. RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT,
  592. 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT);
  593. else
  594. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
  595. /* Set HPP/N STB enhance circuits */
  596. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
  597. /* Enable HP aux output stage */
  598. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
  599. /* Enable HP aux feedback loop */
  600. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
  601. /* Enable HP aux CMFB loop */
  602. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
  603. /* Enable HP driver bias circuits */
  604. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
  605. /* Enable HP driver core circuits */
  606. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
  607. /* Short HP main output to HP aux output stage */
  608. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
  609. /* Increase HP input pair current to HPM step by step */
  610. hp_in_pair_current(priv, true);
  611. /* Enable HP main CMFB loop */
  612. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
  613. /* Disable HP aux CMFB loop */
  614. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
  615. /* Enable HP main output stage */
  616. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
  617. /* Enable HPR/L main output stage step by step */
  618. hp_main_output_ramp(priv, true);
  619. /* Reduce HP aux feedback loop gain */
  620. hp_aux_feedback_loop_gain_ramp(priv, true);
  621. /* Disable HP aux feedback loop */
  622. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
  623. /* apply volume setting */
  624. headset_volume_ramp(priv,
  625. DL_GAIN_N_22DB,
  626. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
  627. /* Disable HP aux output stage */
  628. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
  629. /* Unshort HP main output to HP aux output stage */
  630. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
  631. usleep_range(100, 120);
  632. /* Enable AUD_CLK */
  633. mt6359_set_decoder_clk(priv, true);
  634. /* Enable Audio DAC */
  635. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
  636. if (priv->hp_hifi_mode) {
  637. /* Enable low-noise mode of DAC */
  638. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
  639. } else {
  640. /* Disable low-noise mode of DAC */
  641. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
  642. }
  643. usleep_range(100, 120);
  644. /* Switch HPL MUX to audio DAC */
  645. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
  646. /* Switch HPR MUX to audio DAC */
  647. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
  648. /* Disable Pull-down HPL/R to AVSS28_AUD */
  649. hp_pull_down(priv, false);
  650. }
  651. static void mtk_hp_disable(struct mt6359_priv *priv)
  652. {
  653. /* Pull-down HPL/R to AVSS28_AUD */
  654. hp_pull_down(priv, true);
  655. /* HPR/HPL mux to open */
  656. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  657. 0x0f00, 0x0000);
  658. /* Disable low-noise mode of DAC */
  659. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
  660. 0x0001, 0x0000);
  661. /* Disable Audio DAC */
  662. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  663. 0x000f, 0x0000);
  664. /* Disable AUD_CLK */
  665. mt6359_set_decoder_clk(priv, false);
  666. /* Short HP main output to HP aux output stage */
  667. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
  668. /* Enable HP aux output stage */
  669. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
  670. /* decrease HPL/R gain to normal gain step by step */
  671. headset_volume_ramp(priv,
  672. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
  673. DL_GAIN_N_22DB);
  674. /* Enable HP aux feedback loop */
  675. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
  676. /* Reduce HP aux feedback loop gain */
  677. hp_aux_feedback_loop_gain_ramp(priv, false);
  678. /* decrease HPR/L main output stage step by step */
  679. hp_main_output_ramp(priv, false);
  680. /* Disable HP main output stage */
  681. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
  682. /* Enable HP aux CMFB loop */
  683. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
  684. /* Disable HP main CMFB loop */
  685. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
  686. /* Decrease HP input pair current to 2'b00 step by step */
  687. hp_in_pair_current(priv, false);
  688. /* Unshort HP main output to HP aux output stage */
  689. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
  690. 0x3 << 6, 0x0);
  691. /* Disable HP driver core circuits */
  692. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  693. 0x3 << 4, 0x0);
  694. /* Disable HP driver bias circuits */
  695. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  696. 0x3 << 6, 0x0);
  697. /* Disable HP aux CMFB loop */
  698. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
  699. /* Disable HP aux feedback loop */
  700. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
  701. 0x3 << 4, 0x0);
  702. /* Disable HP aux output stage */
  703. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
  704. 0x3 << 2, 0x0);
  705. }
  706. static int mt_hp_event(struct snd_soc_dapm_widget *w,
  707. struct snd_kcontrol *kcontrol,
  708. int event)
  709. {
  710. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  711. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  712. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  713. int device = DEVICE_HP;
  714. dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
  715. __func__, event, priv->dev_counter[device], mux);
  716. switch (event) {
  717. case SND_SOC_DAPM_PRE_PMU:
  718. priv->dev_counter[device]++;
  719. if (mux == HP_MUX_HP)
  720. mtk_hp_enable(priv);
  721. break;
  722. case SND_SOC_DAPM_PRE_PMD:
  723. priv->dev_counter[device]--;
  724. if (mux == HP_MUX_HP)
  725. mtk_hp_disable(priv);
  726. break;
  727. default:
  728. break;
  729. }
  730. return 0;
  731. }
  732. static int mt_rcv_event(struct snd_soc_dapm_widget *w,
  733. struct snd_kcontrol *kcontrol,
  734. int event)
  735. {
  736. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  737. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  738. dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
  739. __func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
  740. switch (event) {
  741. case SND_SOC_DAPM_PRE_PMU:
  742. /* Disable handset short-circuit protection */
  743. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
  744. /* Set RCV DR bias current optimization, 010: 6uA */
  745. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
  746. DRBIAS_HS_MASK_SFT,
  747. DRBIAS_6UA << DRBIAS_HS_SFT);
  748. /* Set RCV & ZCD bias current optimization */
  749. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  750. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  751. IBIAS_ZCD_MASK_SFT,
  752. IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
  753. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  754. IBIAS_HS_MASK_SFT,
  755. IBIAS_5UA << IBIAS_HS_SFT);
  756. /* Set HS STB enhance circuits */
  757. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
  758. /* Set HS output stage (3'b111 = 8x) */
  759. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
  760. /* Enable HS driver bias circuits */
  761. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
  762. /* Enable HS driver core circuits */
  763. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
  764. /* Set HS gain to normal gain step by step */
  765. regmap_write(priv->regmap, MT6359_ZCD_CON3,
  766. priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
  767. /* Enable AUD_CLK */
  768. mt6359_set_decoder_clk(priv, true);
  769. /* Enable Audio DAC */
  770. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
  771. /* Enable low-noise mode of DAC */
  772. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
  773. /* Switch HS MUX to audio DAC */
  774. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
  775. break;
  776. case SND_SOC_DAPM_PRE_PMD:
  777. /* HS mux to open */
  778. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
  779. RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT,
  780. RCV_MUX_OPEN);
  781. /* Disable Audio DAC */
  782. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  783. 0x000f, 0x0000);
  784. /* Disable AUD_CLK */
  785. mt6359_set_decoder_clk(priv, false);
  786. /* decrease HS gain to minimum gain step by step */
  787. regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
  788. /* Disable HS driver core circuits */
  789. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
  790. RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0);
  791. /* Disable HS driver bias circuits */
  792. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
  793. RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
  794. break;
  795. default:
  796. break;
  797. }
  798. return 0;
  799. }
  800. static int mt_lo_event(struct snd_soc_dapm_widget *w,
  801. struct snd_kcontrol *kcontrol,
  802. int event)
  803. {
  804. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  805. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  806. dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
  807. __func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
  808. switch (event) {
  809. case SND_SOC_DAPM_PRE_PMU:
  810. /* Disable handset short-circuit protection */
  811. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
  812. /* Set LO DR bias current optimization, 010: 6uA */
  813. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
  814. DRBIAS_LO_MASK_SFT,
  815. DRBIAS_6UA << DRBIAS_LO_SFT);
  816. /* Set LO & ZCD bias current optimization */
  817. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  818. if (priv->dev_counter[DEVICE_HP] == 0)
  819. regmap_update_bits(priv->regmap,
  820. MT6359_AUDDEC_ANA_CON12,
  821. IBIAS_ZCD_MASK_SFT,
  822. IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
  823. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
  824. IBIAS_LO_MASK_SFT,
  825. IBIAS_5UA << IBIAS_LO_SFT);
  826. /* Set LO STB enhance circuits */
  827. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
  828. /* Enable LO driver bias circuits */
  829. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
  830. /* Enable LO driver core circuits */
  831. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
  832. /* Set LO gain to normal gain step by step */
  833. regmap_write(priv->regmap, MT6359_ZCD_CON1,
  834. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
  835. /* Enable AUD_CLK */
  836. mt6359_set_decoder_clk(priv, true);
  837. /* Enable Audio DAC (3rd DAC) */
  838. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
  839. /* Enable low-noise mode of DAC */
  840. if (priv->dev_counter[DEVICE_HP] == 0)
  841. regmap_write(priv->regmap,
  842. MT6359_AUDDEC_ANA_CON9, 0x0001);
  843. /* Switch LOL MUX to audio 3rd DAC */
  844. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
  845. break;
  846. case SND_SOC_DAPM_PRE_PMD:
  847. /* Switch LOL MUX to open */
  848. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
  849. RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT,
  850. LO_MUX_OPEN);
  851. /* Disable Audio DAC */
  852. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  853. 0x000f, 0x0000);
  854. /* Disable AUD_CLK */
  855. mt6359_set_decoder_clk(priv, false);
  856. /* decrease LO gain to minimum gain step by step */
  857. regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
  858. /* Disable LO driver core circuits */
  859. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
  860. RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0);
  861. /* Disable LO driver bias circuits */
  862. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
  863. RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
  864. break;
  865. default:
  866. break;
  867. }
  868. return 0;
  869. }
  870. static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w,
  871. struct snd_kcontrol *kcontrol,
  872. int event)
  873. {
  874. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  875. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  876. dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
  877. switch (event) {
  878. case SND_SOC_DAPM_POST_PMU:
  879. /* ADC CLK from CLKGEN (6.5MHz) */
  880. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  881. RG_AUDADCCLKRSTB_MASK_SFT,
  882. 0x1 << RG_AUDADCCLKRSTB_SFT);
  883. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  884. RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
  885. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  886. RG_AUDADCCLKSEL_MASK_SFT, 0x0);
  887. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  888. RG_AUDADCCLKGENMODE_MASK_SFT,
  889. 0x1 << RG_AUDADCCLKGENMODE_SFT);
  890. break;
  891. case SND_SOC_DAPM_PRE_PMD:
  892. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  893. RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
  894. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  895. RG_AUDADCCLKSEL_MASK_SFT, 0x0);
  896. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  897. RG_AUDADCCLKGENMODE_MASK_SFT, 0x0);
  898. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
  899. RG_AUDADCCLKRSTB_MASK_SFT, 0x0);
  900. break;
  901. default:
  902. break;
  903. }
  904. return 0;
  905. }
  906. static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w,
  907. struct snd_kcontrol *kcontrol,
  908. int event)
  909. {
  910. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  911. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  912. dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
  913. switch (event) {
  914. case SND_SOC_DAPM_PRE_PMU:
  915. /* DCC 50k CLK (from 26M) */
  916. /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */
  917. regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
  918. 0xfff7, 0x2062);
  919. regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
  920. 0xfff7, 0x2060);
  921. regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
  922. 0xfff7, 0x2061);
  923. regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
  924. break;
  925. case SND_SOC_DAPM_POST_PMD:
  926. regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
  927. 0xfff7, 0x2060);
  928. regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
  929. 0xfff7, 0x2062);
  930. break;
  931. default:
  932. break;
  933. }
  934. return 0;
  935. }
  936. static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
  937. struct snd_kcontrol *kcontrol,
  938. int event)
  939. {
  940. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  941. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  942. unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
  943. dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
  944. __func__, event, mic_type);
  945. switch (event) {
  946. case SND_SOC_DAPM_PRE_PMU:
  947. switch (mic_type) {
  948. case MIC_TYPE_MUX_DCC_ECM_DIFF:
  949. regmap_update_bits(priv->regmap,
  950. MT6359_AUDENC_ANA_CON15,
  951. 0xff00, 0x7700);
  952. break;
  953. case MIC_TYPE_MUX_DCC_ECM_SINGLE:
  954. regmap_update_bits(priv->regmap,
  955. MT6359_AUDENC_ANA_CON15,
  956. 0xff00, 0x1100);
  957. break;
  958. default:
  959. regmap_update_bits(priv->regmap,
  960. MT6359_AUDENC_ANA_CON15,
  961. 0xff00, 0x0000);
  962. break;
  963. }
  964. /* DMIC enable */
  965. regmap_write(priv->regmap,
  966. MT6359_AUDENC_ANA_CON14, 0x0004);
  967. /* MISBIAS0 = 1P9V */
  968. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
  969. RG_AUDMICBIAS0VREF_MASK_SFT,
  970. MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT);
  971. /* normal power select */
  972. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
  973. RG_AUDMICBIAS0LOWPEN_MASK_SFT,
  974. 0 << RG_AUDMICBIAS0LOWPEN_SFT);
  975. break;
  976. case SND_SOC_DAPM_POST_PMD:
  977. /* Disable MICBIAS0, MISBIAS0 = 1P7V */
  978. regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
  979. break;
  980. default:
  981. break;
  982. }
  983. return 0;
  984. }
  985. static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
  986. struct snd_kcontrol *kcontrol,
  987. int event)
  988. {
  989. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  990. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  991. unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
  992. dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
  993. __func__, event, mic_type);
  994. switch (event) {
  995. case SND_SOC_DAPM_PRE_PMU:
  996. /* MISBIAS1 = 2P6V */
  997. if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
  998. regmap_write(priv->regmap,
  999. MT6359_AUDENC_ANA_CON16, 0x0160);
  1000. else
  1001. regmap_write(priv->regmap,
  1002. MT6359_AUDENC_ANA_CON16, 0x0060);
  1003. /* normal power select */
  1004. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
  1005. RG_AUDMICBIAS1LOWPEN_MASK_SFT,
  1006. 0 << RG_AUDMICBIAS1LOWPEN_SFT);
  1007. break;
  1008. default:
  1009. break;
  1010. }
  1011. return 0;
  1012. }
  1013. static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
  1014. struct snd_kcontrol *kcontrol,
  1015. int event)
  1016. {
  1017. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1018. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1019. unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
  1020. dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
  1021. __func__, event, mic_type);
  1022. switch (event) {
  1023. case SND_SOC_DAPM_PRE_PMU:
  1024. switch (mic_type) {
  1025. case MIC_TYPE_MUX_DCC_ECM_DIFF:
  1026. regmap_update_bits(priv->regmap,
  1027. MT6359_AUDENC_ANA_CON17,
  1028. 0xff00, 0x7700);
  1029. break;
  1030. case MIC_TYPE_MUX_DCC_ECM_SINGLE:
  1031. regmap_update_bits(priv->regmap,
  1032. MT6359_AUDENC_ANA_CON17,
  1033. 0xff00, 0x1100);
  1034. break;
  1035. default:
  1036. regmap_update_bits(priv->regmap,
  1037. MT6359_AUDENC_ANA_CON17,
  1038. 0xff00, 0x0000);
  1039. break;
  1040. }
  1041. /* MISBIAS2 = 1P9V */
  1042. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
  1043. RG_AUDMICBIAS2VREF_MASK_SFT,
  1044. MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT);
  1045. /* normal power select */
  1046. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
  1047. RG_AUDMICBIAS2LOWPEN_MASK_SFT,
  1048. 0 << RG_AUDMICBIAS2LOWPEN_SFT);
  1049. break;
  1050. case SND_SOC_DAPM_POST_PMD:
  1051. /* Disable MICBIAS2, MISBIAS0 = 1P7V */
  1052. regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
  1053. break;
  1054. default:
  1055. break;
  1056. }
  1057. return 0;
  1058. }
  1059. static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w,
  1060. struct snd_kcontrol *kcontrol,
  1061. int event)
  1062. {
  1063. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1064. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1065. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1066. switch (event) {
  1067. case SND_SOC_DAPM_PRE_PMU:
  1068. mt6359_mtkaif_tx_enable(priv);
  1069. break;
  1070. case SND_SOC_DAPM_POST_PMD:
  1071. mt6359_mtkaif_tx_disable(priv);
  1072. break;
  1073. default:
  1074. break;
  1075. }
  1076. return 0;
  1077. }
  1078. static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w,
  1079. struct snd_kcontrol *kcontrol,
  1080. int event)
  1081. {
  1082. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1083. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1084. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1085. switch (event) {
  1086. case SND_SOC_DAPM_PRE_PMU:
  1087. /* UL dmic setting */
  1088. if (priv->dmic_one_wire_mode)
  1089. regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
  1090. 0x0400);
  1091. else
  1092. regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
  1093. 0x0080);
  1094. /* default one wire, 3.25M */
  1095. regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
  1096. 0xfffc, 0x0000);
  1097. break;
  1098. case SND_SOC_DAPM_POST_PMD:
  1099. regmap_write(priv->regmap,
  1100. MT6359_AFE_UL_SRC_CON0_H, 0x0000);
  1101. break;
  1102. default:
  1103. break;
  1104. }
  1105. return 0;
  1106. }
  1107. static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w,
  1108. struct snd_kcontrol *kcontrol,
  1109. int event)
  1110. {
  1111. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1112. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1113. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1114. switch (event) {
  1115. case SND_SOC_DAPM_PRE_PMU:
  1116. /* default two wire, 3.25M */
  1117. regmap_write(priv->regmap,
  1118. MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080);
  1119. regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
  1120. 0xfffc, 0x0000);
  1121. break;
  1122. case SND_SOC_DAPM_POST_PMD:
  1123. regmap_write(priv->regmap,
  1124. MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000);
  1125. break;
  1126. default:
  1127. break;
  1128. }
  1129. return 0;
  1130. }
  1131. static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
  1132. struct snd_kcontrol *kcontrol,
  1133. int event)
  1134. {
  1135. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1136. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1137. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1138. switch (event) {
  1139. case SND_SOC_DAPM_POST_PMU:
  1140. usleep_range(100, 120);
  1141. /* Audio L preamplifier DCC precharge off */
  1142. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
  1143. RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
  1144. 0x0);
  1145. break;
  1146. default:
  1147. break;
  1148. }
  1149. return 0;
  1150. }
  1151. static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
  1152. struct snd_kcontrol *kcontrol,
  1153. int event)
  1154. {
  1155. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1156. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1157. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1158. switch (event) {
  1159. case SND_SOC_DAPM_POST_PMU:
  1160. usleep_range(100, 120);
  1161. /* Audio R preamplifier DCC precharge off */
  1162. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
  1163. RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
  1164. 0x0);
  1165. break;
  1166. default:
  1167. break;
  1168. }
  1169. return 0;
  1170. }
  1171. static int mt_adc_3_event(struct snd_soc_dapm_widget *w,
  1172. struct snd_kcontrol *kcontrol,
  1173. int event)
  1174. {
  1175. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1176. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1177. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  1178. switch (event) {
  1179. case SND_SOC_DAPM_POST_PMU:
  1180. usleep_range(100, 120);
  1181. /* Audio R preamplifier DCC precharge off */
  1182. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
  1183. RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
  1184. 0x0);
  1185. break;
  1186. default:
  1187. break;
  1188. }
  1189. return 0;
  1190. }
  1191. static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w,
  1192. struct snd_kcontrol *kcontrol,
  1193. int event)
  1194. {
  1195. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1196. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1197. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1198. dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
  1199. priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
  1200. return 0;
  1201. }
  1202. static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w,
  1203. struct snd_kcontrol *kcontrol,
  1204. int event)
  1205. {
  1206. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1207. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1208. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1209. dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
  1210. priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
  1211. return 0;
  1212. }
  1213. static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w,
  1214. struct snd_kcontrol *kcontrol,
  1215. int event)
  1216. {
  1217. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1218. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1219. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1220. dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
  1221. priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
  1222. return 0;
  1223. }
  1224. static int mt_pga_l_event(struct snd_soc_dapm_widget *w,
  1225. struct snd_kcontrol *kcontrol,
  1226. int event)
  1227. {
  1228. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1229. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1230. int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
  1231. unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
  1232. unsigned int mic_type;
  1233. switch (mux_pga) {
  1234. case PGA_L_MUX_AIN0:
  1235. mic_type = priv->mux_select[MUX_MIC_TYPE_0];
  1236. break;
  1237. case PGA_L_MUX_AIN1:
  1238. mic_type = priv->mux_select[MUX_MIC_TYPE_1];
  1239. break;
  1240. default:
  1241. dev_err(priv->dev, "%s(), invalid pga mux %d\n",
  1242. __func__, mux_pga);
  1243. return -EINVAL;
  1244. }
  1245. switch (event) {
  1246. case SND_SOC_DAPM_PRE_PMU:
  1247. if (IS_DCC_BASE(mic_type)) {
  1248. /* Audio L preamplifier DCC precharge */
  1249. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
  1250. RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
  1251. 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT);
  1252. }
  1253. break;
  1254. case SND_SOC_DAPM_POST_PMU:
  1255. /* set mic pga gain */
  1256. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
  1257. RG_AUDPREAMPLGAIN_MASK_SFT,
  1258. mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
  1259. if (IS_DCC_BASE(mic_type)) {
  1260. /* L preamplifier DCCEN */
  1261. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
  1262. RG_AUDPREAMPLDCCEN_MASK_SFT,
  1263. 0x1 << RG_AUDPREAMPLDCCEN_SFT);
  1264. }
  1265. break;
  1266. case SND_SOC_DAPM_POST_PMD:
  1267. /* L preamplifier DCCEN */
  1268. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
  1269. RG_AUDPREAMPLDCCEN_MASK_SFT,
  1270. 0x0 << RG_AUDPREAMPLDCCEN_SFT);
  1271. break;
  1272. default:
  1273. break;
  1274. }
  1275. return 0;
  1276. }
  1277. static int mt_pga_r_event(struct snd_soc_dapm_widget *w,
  1278. struct snd_kcontrol *kcontrol,
  1279. int event)
  1280. {
  1281. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1282. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1283. int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
  1284. unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
  1285. unsigned int mic_type;
  1286. switch (mux_pga) {
  1287. case PGA_R_MUX_AIN0:
  1288. mic_type = priv->mux_select[MUX_MIC_TYPE_0];
  1289. break;
  1290. case PGA_R_MUX_AIN2:
  1291. case PGA_R_MUX_AIN3:
  1292. mic_type = priv->mux_select[MUX_MIC_TYPE_2];
  1293. break;
  1294. default:
  1295. dev_err(priv->dev, "%s(), invalid pga mux %d\n",
  1296. __func__, mux_pga);
  1297. return -EINVAL;
  1298. }
  1299. switch (event) {
  1300. case SND_SOC_DAPM_PRE_PMU:
  1301. if (IS_DCC_BASE(mic_type)) {
  1302. /* Audio R preamplifier DCC precharge */
  1303. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
  1304. RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
  1305. 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT);
  1306. }
  1307. break;
  1308. case SND_SOC_DAPM_POST_PMU:
  1309. /* set mic pga gain */
  1310. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
  1311. RG_AUDPREAMPRGAIN_MASK_SFT,
  1312. mic_gain_r << RG_AUDPREAMPRGAIN_SFT);
  1313. if (IS_DCC_BASE(mic_type)) {
  1314. /* R preamplifier DCCEN */
  1315. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
  1316. RG_AUDPREAMPRDCCEN_MASK_SFT,
  1317. 0x1 << RG_AUDPREAMPRDCCEN_SFT);
  1318. }
  1319. break;
  1320. case SND_SOC_DAPM_POST_PMD:
  1321. /* R preamplifier DCCEN */
  1322. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
  1323. RG_AUDPREAMPRDCCEN_MASK_SFT,
  1324. 0x0 << RG_AUDPREAMPRDCCEN_SFT);
  1325. break;
  1326. default:
  1327. break;
  1328. }
  1329. return 0;
  1330. }
  1331. static int mt_pga_3_event(struct snd_soc_dapm_widget *w,
  1332. struct snd_kcontrol *kcontrol,
  1333. int event)
  1334. {
  1335. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1336. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1337. int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
  1338. unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
  1339. unsigned int mic_type;
  1340. switch (mux_pga) {
  1341. case PGA_3_MUX_AIN2:
  1342. case PGA_3_MUX_AIN3:
  1343. mic_type = priv->mux_select[MUX_MIC_TYPE_2];
  1344. break;
  1345. default:
  1346. dev_err(priv->dev, "%s(), invalid pga mux %d\n",
  1347. __func__, mux_pga);
  1348. return -EINVAL;
  1349. }
  1350. switch (event) {
  1351. case SND_SOC_DAPM_PRE_PMU:
  1352. if (IS_DCC_BASE(mic_type)) {
  1353. /* Audio 3 preamplifier DCC precharge */
  1354. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
  1355. RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
  1356. 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT);
  1357. }
  1358. break;
  1359. case SND_SOC_DAPM_POST_PMU:
  1360. /* set mic pga gain */
  1361. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
  1362. RG_AUDPREAMP3GAIN_MASK_SFT,
  1363. mic_gain_3 << RG_AUDPREAMP3GAIN_SFT);
  1364. if (IS_DCC_BASE(mic_type)) {
  1365. /* 3 preamplifier DCCEN */
  1366. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
  1367. RG_AUDPREAMP3DCCEN_MASK_SFT,
  1368. 0x1 << RG_AUDPREAMP3DCCEN_SFT);
  1369. }
  1370. break;
  1371. case SND_SOC_DAPM_POST_PMD:
  1372. /* 3 preamplifier DCCEN */
  1373. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
  1374. RG_AUDPREAMP3DCCEN_MASK_SFT,
  1375. 0x0 << RG_AUDPREAMP3DCCEN_SFT);
  1376. break;
  1377. default:
  1378. break;
  1379. }
  1380. return 0;
  1381. }
  1382. /* It is based on hw's control sequenece to add some delay when PMU/PMD */
  1383. static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
  1384. struct snd_kcontrol *kcontrol,
  1385. int event)
  1386. {
  1387. switch (event) {
  1388. case SND_SOC_DAPM_POST_PMU:
  1389. case SND_SOC_DAPM_PRE_PMD:
  1390. usleep_range(250, 270);
  1391. break;
  1392. default:
  1393. break;
  1394. }
  1395. return 0;
  1396. }
  1397. static int mt_delay_100_event(struct snd_soc_dapm_widget *w,
  1398. struct snd_kcontrol *kcontrol,
  1399. int event)
  1400. {
  1401. switch (event) {
  1402. case SND_SOC_DAPM_POST_PMU:
  1403. case SND_SOC_DAPM_PRE_PMD:
  1404. usleep_range(100, 120);
  1405. break;
  1406. default:
  1407. break;
  1408. }
  1409. return 0;
  1410. }
  1411. static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w,
  1412. struct snd_kcontrol *kcontrol,
  1413. int event)
  1414. {
  1415. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1416. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1417. switch (event) {
  1418. case SND_SOC_DAPM_PRE_PMU:
  1419. hp_pull_down(priv, true);
  1420. break;
  1421. case SND_SOC_DAPM_POST_PMD:
  1422. hp_pull_down(priv, false);
  1423. break;
  1424. default:
  1425. break;
  1426. }
  1427. return 0;
  1428. }
  1429. static int mt_hp_mute_event(struct snd_soc_dapm_widget *w,
  1430. struct snd_kcontrol *kcontrol,
  1431. int event)
  1432. {
  1433. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1434. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1435. switch (event) {
  1436. case SND_SOC_DAPM_PRE_PMU:
  1437. /* Set HPR/HPL gain to -22dB */
  1438. regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
  1439. break;
  1440. case SND_SOC_DAPM_POST_PMD:
  1441. /* Set HPL/HPR gain to mute */
  1442. regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
  1443. break;
  1444. default:
  1445. break;
  1446. }
  1447. return 0;
  1448. }
  1449. static int mt_hp_damp_event(struct snd_soc_dapm_widget *w,
  1450. struct snd_kcontrol *kcontrol,
  1451. int event)
  1452. {
  1453. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1454. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1455. switch (event) {
  1456. case SND_SOC_DAPM_POST_PMD:
  1457. /* Disable HP damping circuit & HPN 4K load */
  1458. /* reset CMFB PW level */
  1459. regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
  1460. break;
  1461. default:
  1462. break;
  1463. }
  1464. return 0;
  1465. }
  1466. static int mt_esd_resist_event(struct snd_soc_dapm_widget *w,
  1467. struct snd_kcontrol *kcontrol,
  1468. int event)
  1469. {
  1470. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1471. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1472. switch (event) {
  1473. case SND_SOC_DAPM_PRE_PMU:
  1474. /* Reduce ESD resistance of AU_REFN */
  1475. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
  1476. RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT,
  1477. 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT);
  1478. usleep_range(250, 270);
  1479. break;
  1480. case SND_SOC_DAPM_POST_PMD:
  1481. /* Increase ESD resistance of AU_REFN */
  1482. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
  1483. RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0);
  1484. break;
  1485. default:
  1486. break;
  1487. }
  1488. return 0;
  1489. }
  1490. static int mt_sdm_event(struct snd_soc_dapm_widget *w,
  1491. struct snd_kcontrol *kcontrol,
  1492. int event)
  1493. {
  1494. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1495. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1496. switch (event) {
  1497. case SND_SOC_DAPM_PRE_PMU:
  1498. /* sdm audio fifo clock power on */
  1499. regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
  1500. 0xfffd, 0x0006);
  1501. /* scrambler clock on enable */
  1502. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
  1503. /* sdm power on */
  1504. regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
  1505. 0xfffd, 0x0003);
  1506. /* sdm fifo enable */
  1507. regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
  1508. 0xfffd, 0x000B);
  1509. break;
  1510. case SND_SOC_DAPM_POST_PMD:
  1511. /* DL scrambler disabling sequence */
  1512. regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
  1513. 0xfffd, 0x0000);
  1514. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
  1515. break;
  1516. default:
  1517. break;
  1518. }
  1519. return 0;
  1520. }
  1521. static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w,
  1522. struct snd_kcontrol *kcontrol,
  1523. int event)
  1524. {
  1525. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1526. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1527. switch (event) {
  1528. case SND_SOC_DAPM_PRE_PMU:
  1529. /* sdm audio fifo clock power on */
  1530. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
  1531. /* scrambler clock on enable */
  1532. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1);
  1533. /* sdm power on */
  1534. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
  1535. /* sdm fifo enable */
  1536. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b);
  1537. break;
  1538. case SND_SOC_DAPM_POST_PMD:
  1539. /* DL scrambler disabling sequence */
  1540. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
  1541. regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
  1542. break;
  1543. default:
  1544. break;
  1545. }
  1546. return 0;
  1547. }
  1548. static int mt_ncp_event(struct snd_soc_dapm_widget *w,
  1549. struct snd_kcontrol *kcontrol,
  1550. int event)
  1551. {
  1552. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1553. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1554. switch (event) {
  1555. case SND_SOC_DAPM_PRE_PMU:
  1556. regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
  1557. break;
  1558. default:
  1559. break;
  1560. }
  1561. return 0;
  1562. }
  1563. /* DAPM Widgets */
  1564. static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = {
  1565. /* Global Supply*/
  1566. SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
  1567. MT6359_DCXO_CW12,
  1568. RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
  1569. SND_SOC_DAPM_SUPPLY_S("LDO_VAUD18", SUPPLY_SEQ_LDO_VAUD18,
  1570. MT6359_LDO_VAUD18_CON0,
  1571. RG_LDO_VAUD18_EN_SFT, 0, NULL, 0),
  1572. SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
  1573. MT6359_AUDDEC_ANA_CON13,
  1574. RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
  1575. SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
  1576. MT6359_AUDENC_ANA_CON23,
  1577. RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU),
  1578. SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
  1579. MT6359_AUD_TOP_CKPDN_CON0,
  1580. RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
  1581. SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
  1582. MT6359_AUD_TOP_CKPDN_CON0,
  1583. RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
  1584. SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
  1585. MT6359_AUD_TOP_CKPDN_CON0,
  1586. RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event,
  1587. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1588. SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
  1589. MT6359_AUD_TOP_CKPDN_CON0,
  1590. RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
  1591. /* Digital Clock */
  1592. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
  1593. MT6359_AUDIO_TOP_CON0,
  1594. PDN_AFE_CTL_SFT, 1,
  1595. mt_delay_250_event,
  1596. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1597. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
  1598. MT6359_AUDIO_TOP_CON0,
  1599. PDN_DAC_CTL_SFT, 1, NULL, 0),
  1600. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
  1601. MT6359_AUDIO_TOP_CON0,
  1602. PDN_ADC_CTL_SFT, 1, NULL, 0),
  1603. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
  1604. MT6359_AUDIO_TOP_CON0,
  1605. PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
  1606. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
  1607. MT6359_AUDIO_TOP_CON0,
  1608. PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
  1609. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
  1610. MT6359_AUDIO_TOP_CON0,
  1611. PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
  1612. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
  1613. MT6359_AUDIO_TOP_CON0,
  1614. PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
  1615. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
  1616. MT6359_AUDIO_TOP_CON0,
  1617. PDN_RESERVED_SFT, 1, NULL, 0),
  1618. SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM,
  1619. SND_SOC_NOPM, 0, 0,
  1620. mt_sdm_event,
  1621. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1622. SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM,
  1623. SND_SOC_NOPM, 0, 0,
  1624. mt_sdm_3rd_event,
  1625. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1626. /* ch123 share SDM FIFO CLK */
  1627. SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK,
  1628. MT6359_AFUNC_AUD_CON2,
  1629. CCI_AFIFO_CLK_PWDB_SFT, 0,
  1630. NULL, 0),
  1631. SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP,
  1632. MT6359_AFE_NCP_CFG0,
  1633. RG_NCP_ON_SFT, 0,
  1634. mt_ncp_event,
  1635. SND_SOC_DAPM_PRE_PMU),
  1636. SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
  1637. 0, 0, NULL, 0),
  1638. SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM,
  1639. 0, 0, NULL, 0),
  1640. SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM,
  1641. 0, 0, NULL, 0),
  1642. /* AFE ON */
  1643. SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
  1644. MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
  1645. NULL, 0),
  1646. /* AIF Rx*/
  1647. SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
  1648. SND_SOC_NOPM, 0, 0),
  1649. SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
  1650. SND_SOC_NOPM, 0, 0),
  1651. SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC,
  1652. MT6359_AFE_DL_SRC2_CON0_L,
  1653. DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
  1654. NULL, 0),
  1655. /* DL Supply */
  1656. SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
  1657. 0, 0, NULL, 0),
  1658. SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST,
  1659. SND_SOC_NOPM,
  1660. 0, 0,
  1661. mt_esd_resist_event,
  1662. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1663. SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO,
  1664. MT6359_AUDDEC_ANA_CON14,
  1665. RG_LCLDO_DEC_EN_VA32_SFT, 0,
  1666. NULL, 0),
  1667. SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
  1668. MT6359_AUDDEC_ANA_CON14,
  1669. RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
  1670. NULL, 0),
  1671. SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV,
  1672. MT6359_AUDDEC_ANA_CON14,
  1673. RG_NVREG_EN_VAUDP32_SFT, 0,
  1674. mt_delay_100_event, SND_SOC_DAPM_POST_PMU),
  1675. SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST,
  1676. MT6359_AUDDEC_ANA_CON12,
  1677. RG_AUDIBIASPWRDN_VAUDP32_SFT, 1,
  1678. NULL, 0),
  1679. /* DAC */
  1680. SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
  1681. SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
  1682. SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
  1683. SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
  1684. /* Headphone */
  1685. SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0,
  1686. &hp_in_mux_control,
  1687. mt_hp_event,
  1688. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  1689. SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM,
  1690. 0, 0, NULL, 0),
  1691. SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN,
  1692. SND_SOC_NOPM,
  1693. 0, 0,
  1694. mt_hp_pull_down_event,
  1695. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1696. SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE,
  1697. SND_SOC_NOPM,
  1698. 0, 0,
  1699. mt_hp_mute_event,
  1700. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1701. SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
  1702. SND_SOC_NOPM,
  1703. 0, 0,
  1704. mt_hp_damp_event,
  1705. SND_SOC_DAPM_POST_PMD),
  1706. /* Receiver */
  1707. SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
  1708. &rcv_in_mux_control,
  1709. mt_rcv_event,
  1710. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  1711. /* LOL */
  1712. SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
  1713. &lo_in_mux_control,
  1714. mt_lo_event,
  1715. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  1716. /* Outputs */
  1717. SND_SOC_DAPM_OUTPUT("Receiver"),
  1718. SND_SOC_DAPM_OUTPUT("Headphone L"),
  1719. SND_SOC_DAPM_OUTPUT("Headphone R"),
  1720. SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
  1721. SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
  1722. SND_SOC_DAPM_OUTPUT("LINEOUT L"),
  1723. /* SGEN */
  1724. SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0,
  1725. SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
  1726. SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0,
  1727. SGEN_MUTE_SW_CTL_SFT, 1,
  1728. mt_sgen_event,
  1729. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1730. SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L,
  1731. DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
  1732. SND_SOC_DAPM_INPUT("SGEN DL"),
  1733. /* Uplinks */
  1734. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
  1735. SND_SOC_NOPM, 0, 0),
  1736. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
  1737. SND_SOC_NOPM, 0, 0),
  1738. SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN,
  1739. SND_SOC_NOPM, 0, 0,
  1740. mt_adc_clk_gen_event,
  1741. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1742. SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK,
  1743. SND_SOC_NOPM, 0, 0,
  1744. mt_dcc_clk_event,
  1745. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1746. /* Uplinks MUX */
  1747. SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
  1748. &aif_out_mux_control),
  1749. SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
  1750. &aif2_out_mux_control),
  1751. SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
  1752. SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF,
  1753. SND_SOC_NOPM, 0, 0,
  1754. mt_mtkaif_tx_event,
  1755. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1756. SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC,
  1757. MT6359_AFE_UL_SRC_CON0_L,
  1758. UL_SRC_ON_TMP_CTL_SFT, 0,
  1759. NULL, 0),
  1760. SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
  1761. SND_SOC_NOPM, 0, 0,
  1762. mt_ul_src_dmic_event,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1764. SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC,
  1765. MT6359_AFE_ADDA6_UL_SRC_CON0_L,
  1766. ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
  1767. NULL, 0),
  1768. SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
  1769. SND_SOC_NOPM, 0, 0,
  1770. mt_ul_src_34_dmic_event,
  1771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1772. SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
  1773. SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
  1774. SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
  1775. SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
  1776. &ul_src_mux_control),
  1777. SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
  1778. &ul2_src_mux_control),
  1779. SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
  1780. SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
  1781. SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
  1782. SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
  1783. &adc_left_mux_control, NULL, 0),
  1784. SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
  1785. &adc_right_mux_control, NULL, 0),
  1786. SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
  1787. &adc_3_mux_control, NULL, 0),
  1788. SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
  1789. SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
  1790. SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
  1791. SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC,
  1792. MT6359_AUDENC_ANA_CON0,
  1793. RG_AUDADCLPWRUP_SFT, 0,
  1794. mt_adc_l_event,
  1795. SND_SOC_DAPM_POST_PMU),
  1796. SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC,
  1797. MT6359_AUDENC_ANA_CON1,
  1798. RG_AUDADCRPWRUP_SFT, 0,
  1799. mt_adc_r_event,
  1800. SND_SOC_DAPM_POST_PMU),
  1801. SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC,
  1802. MT6359_AUDENC_ANA_CON2,
  1803. RG_AUDADC3PWRUP_SFT, 0,
  1804. mt_adc_3_event,
  1805. SND_SOC_DAPM_POST_PMU),
  1806. SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
  1807. &pga_left_mux_control,
  1808. mt_pga_l_mux_event,
  1809. SND_SOC_DAPM_WILL_PMU),
  1810. SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
  1811. &pga_right_mux_control,
  1812. mt_pga_r_mux_event,
  1813. SND_SOC_DAPM_WILL_PMU),
  1814. SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
  1815. &pga_3_mux_control,
  1816. mt_pga_3_mux_event,
  1817. SND_SOC_DAPM_WILL_PMU),
  1818. SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1819. SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1820. SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
  1821. SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA,
  1822. MT6359_AUDENC_ANA_CON0,
  1823. RG_AUDPREAMPLON_SFT, 0,
  1824. mt_pga_l_event,
  1825. SND_SOC_DAPM_PRE_PMU |
  1826. SND_SOC_DAPM_POST_PMU |
  1827. SND_SOC_DAPM_POST_PMD),
  1828. SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA,
  1829. MT6359_AUDENC_ANA_CON1,
  1830. RG_AUDPREAMPRON_SFT, 0,
  1831. mt_pga_r_event,
  1832. SND_SOC_DAPM_PRE_PMU |
  1833. SND_SOC_DAPM_POST_PMU |
  1834. SND_SOC_DAPM_POST_PMD),
  1835. SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA,
  1836. MT6359_AUDENC_ANA_CON2,
  1837. RG_AUDPREAMP3ON_SFT, 0,
  1838. mt_pga_3_event,
  1839. SND_SOC_DAPM_PRE_PMU |
  1840. SND_SOC_DAPM_POST_PMU |
  1841. SND_SOC_DAPM_POST_PMD),
  1842. /* UL input */
  1843. SND_SOC_DAPM_INPUT("AIN0"),
  1844. SND_SOC_DAPM_INPUT("AIN1"),
  1845. SND_SOC_DAPM_INPUT("AIN2"),
  1846. SND_SOC_DAPM_INPUT("AIN3"),
  1847. SND_SOC_DAPM_INPUT("AIN0_DMIC"),
  1848. SND_SOC_DAPM_INPUT("AIN2_DMIC"),
  1849. SND_SOC_DAPM_INPUT("AIN3_DMIC"),
  1850. /* mic bias */
  1851. SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS,
  1852. MT6359_AUDENC_ANA_CON15,
  1853. RG_AUDPWDBMICBIAS0_SFT, 0,
  1854. mt_mic_bias_0_event,
  1855. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1856. SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS,
  1857. MT6359_AUDENC_ANA_CON16,
  1858. RG_AUDPWDBMICBIAS1_SFT, 0,
  1859. mt_mic_bias_1_event,
  1860. SND_SOC_DAPM_PRE_PMU),
  1861. SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS,
  1862. MT6359_AUDENC_ANA_CON17,
  1863. RG_AUDPWDBMICBIAS2_SFT, 0,
  1864. mt_mic_bias_2_event,
  1865. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1866. /* dmic */
  1867. SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC,
  1868. MT6359_AUDENC_ANA_CON13,
  1869. RG_AUDDIGMICEN_SFT, 0,
  1870. NULL, 0),
  1871. SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC,
  1872. MT6359_AUDENC_ANA_CON14,
  1873. RG_AUDDIGMIC1EN_SFT, 0,
  1874. NULL, 0),
  1875. };
  1876. static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source,
  1877. struct snd_soc_dapm_widget *sink)
  1878. {
  1879. struct snd_soc_dapm_widget *w = sink;
  1880. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1881. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1882. if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
  1883. IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
  1884. IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
  1885. return 1;
  1886. else
  1887. return 0;
  1888. }
  1889. static const struct snd_soc_dapm_route mt6359_dapm_routes[] = {
  1890. /* Capture */
  1891. {"AIFTX_Supply", NULL, "CLK_BUF"},
  1892. {"AIFTX_Supply", NULL, "LDO_VAUD18"},
  1893. {"AIFTX_Supply", NULL, "AUDGLB"},
  1894. {"AIFTX_Supply", NULL, "CLKSQ Audio"},
  1895. {"AIFTX_Supply", NULL, "AUD_CK"},
  1896. {"AIFTX_Supply", NULL, "AUDIF_CK"},
  1897. {"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"},
  1898. {"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"},
  1899. {"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1900. {"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"},
  1901. /*
  1902. * *_ADC_CTL should enable only if UL_SRC in use,
  1903. * but dm ck may be needed even UL_SRC_x not in use
  1904. */
  1905. {"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"},
  1906. {"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"},
  1907. {"AIFTX_Supply", NULL, "AFE_ON"},
  1908. /* ul ch 12 */
  1909. {"AIF1TX", NULL, "AIF Out Mux"},
  1910. {"AIF1TX", NULL, "AIFTX_Supply"},
  1911. {"AIF1TX", NULL, "MTKAIF_TX"},
  1912. {"AIF2TX", NULL, "AIF2 Out Mux"},
  1913. {"AIF2TX", NULL, "AIFTX_Supply"},
  1914. {"AIF2TX", NULL, "MTKAIF_TX"},
  1915. {"AIF Out Mux", "Normal Path", "MISO0_MUX"},
  1916. {"AIF Out Mux", "Normal Path", "MISO1_MUX"},
  1917. {"AIF2 Out Mux", "Normal Path", "MISO2_MUX"},
  1918. {"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"},
  1919. {"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"},
  1920. {"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"},
  1921. {"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"},
  1922. {"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"},
  1923. {"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"},
  1924. {"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"},
  1925. {"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"},
  1926. {"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"},
  1927. {"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"},
  1928. {"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"},
  1929. {"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"},
  1930. {"UL_SRC_MUX", "AMIC", "ADC_L"},
  1931. {"UL_SRC_MUX", "AMIC", "ADC_R"},
  1932. {"UL_SRC_MUX", "DMIC", "DMIC0_MUX"},
  1933. {"UL_SRC_MUX", "DMIC", "DMIC1_MUX"},
  1934. {"UL_SRC_MUX", NULL, "UL_SRC"},
  1935. {"UL2_SRC_MUX", "AMIC", "ADC_3"},
  1936. {"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"},
  1937. {"UL2_SRC_MUX", NULL, "UL_SRC_34"},
  1938. {"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"},
  1939. {"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
  1940. {"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
  1941. {"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
  1942. {"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"},
  1943. {"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
  1944. {"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
  1945. {"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
  1946. {"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"},
  1947. {"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
  1948. {"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
  1949. {"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
  1950. {"DMIC0_MUX", NULL, "UL_SRC_DMIC"},
  1951. {"DMIC1_MUX", NULL, "UL_SRC_DMIC"},
  1952. {"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"},
  1953. {"AIN0_DMIC", NULL, "DMIC_0"},
  1954. {"AIN2_DMIC", NULL, "DMIC_1"},
  1955. {"AIN3_DMIC", NULL, "DMIC_1"},
  1956. {"AIN0_DMIC", NULL, "MIC_BIAS_0"},
  1957. {"AIN2_DMIC", NULL, "MIC_BIAS_2"},
  1958. {"AIN3_DMIC", NULL, "MIC_BIAS_2"},
  1959. /* adc */
  1960. {"ADC_L", NULL, "ADC_L_Mux"},
  1961. {"ADC_L", NULL, "ADC_CLKGEN"},
  1962. {"ADC_L", NULL, "ADC_L_EN"},
  1963. {"ADC_R", NULL, "ADC_R_Mux"},
  1964. {"ADC_R", NULL, "ADC_CLKGEN"},
  1965. {"ADC_R", NULL, "ADC_R_EN"},
  1966. /*
  1967. * amic fifo ch1/2 clk from ADC_L,
  1968. * enable ADC_L even use ADC_R only
  1969. */
  1970. {"ADC_R", NULL, "ADC_L_EN"},
  1971. {"ADC_3", NULL, "ADC_3_Mux"},
  1972. {"ADC_3", NULL, "ADC_CLKGEN"},
  1973. {"ADC_3", NULL, "ADC_3_EN"},
  1974. {"ADC_L_Mux", "Left Preamplifier", "PGA_L"},
  1975. {"ADC_R_Mux", "Right Preamplifier", "PGA_R"},
  1976. {"ADC_3_Mux", "Preamplifier", "PGA_3"},
  1977. {"PGA_L", NULL, "PGA_L_Mux"},
  1978. {"PGA_L", NULL, "PGA_L_EN"},
  1979. {"PGA_R", NULL, "PGA_R_Mux"},
  1980. {"PGA_R", NULL, "PGA_R_EN"},
  1981. {"PGA_3", NULL, "PGA_3_Mux"},
  1982. {"PGA_3", NULL, "PGA_3_EN"},
  1983. {"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect},
  1984. {"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect},
  1985. {"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect},
  1986. {"PGA_L_Mux", "AIN0", "AIN0"},
  1987. {"PGA_L_Mux", "AIN1", "AIN1"},
  1988. {"PGA_R_Mux", "AIN0", "AIN0"},
  1989. {"PGA_R_Mux", "AIN2", "AIN2"},
  1990. {"PGA_R_Mux", "AIN3", "AIN3"},
  1991. {"PGA_3_Mux", "AIN2", "AIN2"},
  1992. {"PGA_3_Mux", "AIN3", "AIN3"},
  1993. {"AIN0", NULL, "MIC_BIAS_0"},
  1994. {"AIN1", NULL, "MIC_BIAS_1"},
  1995. {"AIN2", NULL, "MIC_BIAS_0"},
  1996. {"AIN2", NULL, "MIC_BIAS_2"},
  1997. {"AIN3", NULL, "MIC_BIAS_2"},
  1998. /* DL Supply */
  1999. {"DL Power Supply", NULL, "CLK_BUF"},
  2000. {"DL Power Supply", NULL, "LDO_VAUD18"},
  2001. {"DL Power Supply", NULL, "AUDGLB"},
  2002. {"DL Power Supply", NULL, "CLKSQ Audio"},
  2003. {"DL Power Supply", NULL, "AUDNCP_CK"},
  2004. {"DL Power Supply", NULL, "ZCD13M_CK"},
  2005. {"DL Power Supply", NULL, "AUD_CK"},
  2006. {"DL Power Supply", NULL, "AUDIF_CK"},
  2007. {"DL Power Supply", NULL, "ESD_RESIST"},
  2008. {"DL Power Supply", NULL, "LDO"},
  2009. {"DL Power Supply", NULL, "LDO_REMOTE"},
  2010. {"DL Power Supply", NULL, "NV_REGULATOR"},
  2011. {"DL Power Supply", NULL, "IBIST"},
  2012. /* DL Digital Supply */
  2013. {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
  2014. {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
  2015. {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
  2016. {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
  2017. {"DL Digital Clock", NULL, "SDM_FIFO_CLK"},
  2018. {"DL Digital Clock", NULL, "NCP"},
  2019. {"DL Digital Clock", NULL, "AFE_ON"},
  2020. {"DL Digital Clock", NULL, "AFE_DL_SRC"},
  2021. {"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"},
  2022. {"DL Digital Clock CH_1_2", NULL, "SDM"},
  2023. {"DL Digital Clock CH_3", NULL, "DL Digital Clock"},
  2024. {"DL Digital Clock CH_3", NULL, "SDM_3RD"},
  2025. {"AIF_RX", NULL, "DL Digital Clock CH_1_2"},
  2026. {"AIF2_RX", NULL, "DL Digital Clock CH_3"},
  2027. /* DL Path */
  2028. {"DAC In Mux", "Normal Path", "AIF_RX"},
  2029. {"DAC In Mux", "Sgen", "SGEN DL"},
  2030. {"SGEN DL", NULL, "SGEN DL SRC"},
  2031. {"SGEN DL", NULL, "SGEN MUTE"},
  2032. {"SGEN DL", NULL, "SGEN DL Enable"},
  2033. {"SGEN DL", NULL, "DL Digital Clock CH_1_2"},
  2034. {"SGEN DL", NULL, "DL Digital Clock CH_3"},
  2035. {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
  2036. {"DACL", NULL, "DAC In Mux"},
  2037. {"DACL", NULL, "DL Power Supply"},
  2038. {"DACR", NULL, "DAC In Mux"},
  2039. {"DACR", NULL, "DL Power Supply"},
  2040. /* DAC 3RD */
  2041. {"DAC In Mux", "Normal Path", "AIF2_RX"},
  2042. {"DAC_3RD", NULL, "DAC In Mux"},
  2043. {"DAC_3RD", NULL, "DL Power Supply"},
  2044. /* Lineout Path */
  2045. {"LOL Mux", "Playback", "DAC_3RD"},
  2046. {"LINEOUT L", NULL, "LOL Mux"},
  2047. /* Headphone Path */
  2048. {"HP_Supply", NULL, "HP_PULL_DOWN"},
  2049. {"HP_Supply", NULL, "HP_MUTE"},
  2050. {"HP_Supply", NULL, "HP_DAMP"},
  2051. {"HP Mux", NULL, "HP_Supply"},
  2052. {"HP Mux", "Audio Playback", "DACL"},
  2053. {"HP Mux", "Audio Playback", "DACR"},
  2054. {"HP Mux", "HP Impedance", "DACL"},
  2055. {"HP Mux", "HP Impedance", "DACR"},
  2056. {"HP Mux", "LoudSPK Playback", "DACL"},
  2057. {"HP Mux", "LoudSPK Playback", "DACR"},
  2058. {"Headphone L", NULL, "HP Mux"},
  2059. {"Headphone R", NULL, "HP Mux"},
  2060. {"Headphone L Ext Spk Amp", NULL, "HP Mux"},
  2061. {"Headphone R Ext Spk Amp", NULL, "HP Mux"},
  2062. /* Receiver Path */
  2063. {"RCV Mux", "Voice Playback", "DACL"},
  2064. {"Receiver", NULL, "RCV Mux"},
  2065. };
  2066. static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream,
  2067. struct snd_pcm_hw_params *params,
  2068. struct snd_soc_dai *dai)
  2069. {
  2070. struct snd_soc_component *cmpnt = dai->component;
  2071. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2072. unsigned int rate = params_rate(params);
  2073. int id = dai->id;
  2074. dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
  2075. __func__, id, substream->stream, rate, substream->number);
  2076. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  2077. priv->dl_rate[id] = rate;
  2078. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  2079. priv->ul_rate[id] = rate;
  2080. return 0;
  2081. }
  2082. static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream,
  2083. struct snd_soc_dai *dai)
  2084. {
  2085. struct snd_soc_component *cmpnt = dai->component;
  2086. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2087. dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
  2088. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  2089. mt6359_set_playback_gpio(priv);
  2090. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  2091. mt6359_set_capture_gpio(priv);
  2092. return 0;
  2093. }
  2094. static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream,
  2095. struct snd_soc_dai *dai)
  2096. {
  2097. struct snd_soc_component *cmpnt = dai->component;
  2098. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2099. dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
  2100. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  2101. mt6359_reset_playback_gpio(priv);
  2102. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  2103. mt6359_reset_capture_gpio(priv);
  2104. }
  2105. static const struct snd_soc_dai_ops mt6359_codec_dai_ops = {
  2106. .hw_params = mt6359_codec_dai_hw_params,
  2107. .startup = mt6359_codec_dai_startup,
  2108. .shutdown = mt6359_codec_dai_shutdown,
  2109. };
  2110. #define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
  2111. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
  2112. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
  2113. SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
  2114. SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
  2115. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
  2116. static struct snd_soc_dai_driver mt6359_dai_driver[] = {
  2117. {
  2118. .id = MT6359_AIF_1,
  2119. .name = "mt6359-snd-codec-aif1",
  2120. .playback = {
  2121. .stream_name = "AIF1 Playback",
  2122. .channels_min = 1,
  2123. .channels_max = 2,
  2124. .rates = SNDRV_PCM_RATE_8000_48000 |
  2125. SNDRV_PCM_RATE_96000 |
  2126. SNDRV_PCM_RATE_192000,
  2127. .formats = MT6359_FORMATS,
  2128. },
  2129. .capture = {
  2130. .stream_name = "AIF1 Capture",
  2131. .channels_min = 1,
  2132. .channels_max = 2,
  2133. .rates = SNDRV_PCM_RATE_8000 |
  2134. SNDRV_PCM_RATE_16000 |
  2135. SNDRV_PCM_RATE_32000 |
  2136. SNDRV_PCM_RATE_48000 |
  2137. SNDRV_PCM_RATE_96000 |
  2138. SNDRV_PCM_RATE_192000,
  2139. .formats = MT6359_FORMATS,
  2140. },
  2141. .ops = &mt6359_codec_dai_ops,
  2142. },
  2143. {
  2144. .id = MT6359_AIF_2,
  2145. .name = "mt6359-snd-codec-aif2",
  2146. .playback = {
  2147. .stream_name = "AIF2 Playback",
  2148. .channels_min = 1,
  2149. .channels_max = 2,
  2150. .rates = SNDRV_PCM_RATE_8000_48000 |
  2151. SNDRV_PCM_RATE_96000 |
  2152. SNDRV_PCM_RATE_192000,
  2153. .formats = MT6359_FORMATS,
  2154. },
  2155. .capture = {
  2156. .stream_name = "AIF2 Capture",
  2157. .channels_min = 1,
  2158. .channels_max = 2,
  2159. .rates = SNDRV_PCM_RATE_8000 |
  2160. SNDRV_PCM_RATE_16000 |
  2161. SNDRV_PCM_RATE_32000 |
  2162. SNDRV_PCM_RATE_48000,
  2163. .formats = MT6359_FORMATS,
  2164. },
  2165. .ops = &mt6359_codec_dai_ops,
  2166. },
  2167. };
  2168. static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt)
  2169. {
  2170. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2171. /* enable clk buf */
  2172. regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
  2173. 0x1 << RG_XO_AUDIO_EN_M_SFT,
  2174. 0x1 << RG_XO_AUDIO_EN_M_SFT);
  2175. /* set those not controlled by dapm widget */
  2176. /* audio clk source from internal dcxo */
  2177. regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
  2178. RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
  2179. 0x0);
  2180. /* Disable HeadphoneL/HeadphoneR short circuit protection */
  2181. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  2182. RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT,
  2183. 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT);
  2184. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
  2185. RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT,
  2186. 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT);
  2187. /* Disable voice short circuit protection */
  2188. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
  2189. RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT,
  2190. 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT);
  2191. /* disable LO buffer left short circuit protection */
  2192. regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
  2193. RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT,
  2194. 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT);
  2195. /* set gpio */
  2196. mt6359_reset_playback_gpio(priv);
  2197. mt6359_reset_capture_gpio(priv);
  2198. /* hp hifi mode, default normal mode */
  2199. priv->hp_hifi_mode = 0;
  2200. /* Disable AUD_ZCD */
  2201. zcd_disable(priv);
  2202. /* disable clk buf */
  2203. regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
  2204. 0x1 << RG_XO_AUDIO_EN_M_SFT,
  2205. 0x0 << RG_XO_AUDIO_EN_M_SFT);
  2206. return 0;
  2207. }
  2208. static int mt6359_codec_probe(struct snd_soc_component *cmpnt)
  2209. {
  2210. struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2211. snd_soc_component_init_regmap(cmpnt, priv->regmap);
  2212. return mt6359_codec_init_reg(cmpnt);
  2213. }
  2214. static void mt6359_codec_remove(struct snd_soc_component *cmpnt)
  2215. {
  2216. snd_soc_component_exit_regmap(cmpnt);
  2217. }
  2218. static const DECLARE_TLV_DB_SCALE(hp_playback_tlv, -2200, 100, 0);
  2219. static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
  2220. static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
  2221. static const struct snd_kcontrol_new mt6359_snd_controls[] = {
  2222. /* dl pga gain */
  2223. SOC_DOUBLE_EXT_TLV("Headset Volume",
  2224. MT6359_ZCD_CON2, 0, 7, 0x1E, 0,
  2225. snd_soc_get_volsw, mt6359_put_volsw,
  2226. hp_playback_tlv),
  2227. SOC_DOUBLE_EXT_TLV("Lineout Volume",
  2228. MT6359_ZCD_CON1, 0, 7, 0x12, 0,
  2229. snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
  2230. SOC_SINGLE_EXT_TLV("Handset Volume",
  2231. MT6359_ZCD_CON3, 0, 0x12, 0,
  2232. snd_soc_get_volsw, mt6359_put_volsw, playback_tlv),
  2233. /* ul pga gain */
  2234. SOC_SINGLE_EXT_TLV("PGA1 Volume",
  2235. MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
  2236. snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
  2237. SOC_SINGLE_EXT_TLV("PGA2 Volume",
  2238. MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
  2239. snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
  2240. SOC_SINGLE_EXT_TLV("PGA3 Volume",
  2241. MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
  2242. snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
  2243. };
  2244. static const struct snd_soc_component_driver mt6359_soc_component_driver = {
  2245. .name = CODEC_MT6359_NAME,
  2246. .probe = mt6359_codec_probe,
  2247. .remove = mt6359_codec_remove,
  2248. .controls = mt6359_snd_controls,
  2249. .num_controls = ARRAY_SIZE(mt6359_snd_controls),
  2250. .dapm_widgets = mt6359_dapm_widgets,
  2251. .num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets),
  2252. .dapm_routes = mt6359_dapm_routes,
  2253. .num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes),
  2254. };
  2255. static int mt6359_parse_dt(struct mt6359_priv *priv)
  2256. {
  2257. int ret;
  2258. struct device *dev = priv->dev;
  2259. struct device_node *np;
  2260. np = of_get_child_by_name(dev->parent->of_node, "mt6359codec");
  2261. if (!np)
  2262. return -EINVAL;
  2263. ret = of_property_read_u32(np, "mediatek,dmic-mode",
  2264. &priv->dmic_one_wire_mode);
  2265. if (ret) {
  2266. dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
  2267. __func__);
  2268. priv->dmic_one_wire_mode = 0;
  2269. }
  2270. ret = of_property_read_u32(np, "mediatek,mic-type-0",
  2271. &priv->mux_select[MUX_MIC_TYPE_0]);
  2272. if (ret) {
  2273. dev_warn(priv->dev, "%s() failed to read mic-type-0\n",
  2274. __func__);
  2275. priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE;
  2276. }
  2277. ret = of_property_read_u32(np, "mediatek,mic-type-1",
  2278. &priv->mux_select[MUX_MIC_TYPE_1]);
  2279. if (ret) {
  2280. dev_warn(priv->dev, "%s() failed to read mic-type-1\n",
  2281. __func__);
  2282. priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE;
  2283. }
  2284. ret = of_property_read_u32(np, "mediatek,mic-type-2",
  2285. &priv->mux_select[MUX_MIC_TYPE_2]);
  2286. if (ret) {
  2287. dev_warn(priv->dev, "%s() failed to read mic-type-2\n",
  2288. __func__);
  2289. priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE;
  2290. }
  2291. return 0;
  2292. }
  2293. static int mt6359_platform_driver_probe(struct platform_device *pdev)
  2294. {
  2295. struct mt6359_priv *priv;
  2296. int ret;
  2297. struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
  2298. dev_dbg(&pdev->dev, "%s(), dev name %s\n",
  2299. __func__, dev_name(&pdev->dev));
  2300. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  2301. if (!priv)
  2302. return -ENOMEM;
  2303. priv->regmap = mt6397->regmap;
  2304. if (IS_ERR(priv->regmap))
  2305. return PTR_ERR(priv->regmap);
  2306. dev_set_drvdata(&pdev->dev, priv);
  2307. priv->dev = &pdev->dev;
  2308. priv->avdd_reg = devm_regulator_get(&pdev->dev, "vaud18");
  2309. if (IS_ERR(priv->avdd_reg)) {
  2310. dev_err(&pdev->dev, "%s(), have no vaud18 supply: %ld",
  2311. __func__, PTR_ERR(priv->avdd_reg));
  2312. return PTR_ERR(priv->avdd_reg);
  2313. }
  2314. ret = regulator_enable(priv->avdd_reg);
  2315. if (ret) {
  2316. dev_err(&pdev->dev, "%s(), failed to enable regulator!\n",
  2317. __func__);
  2318. return ret;
  2319. }
  2320. ret = mt6359_parse_dt(priv);
  2321. if (ret) {
  2322. dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__);
  2323. return ret;
  2324. }
  2325. return devm_snd_soc_register_component(&pdev->dev,
  2326. &mt6359_soc_component_driver,
  2327. mt6359_dai_driver,
  2328. ARRAY_SIZE(mt6359_dai_driver));
  2329. }
  2330. static int mt6359_platform_driver_remove(struct platform_device *pdev)
  2331. {
  2332. struct mt6359_priv *priv = dev_get_drvdata(&pdev->dev);
  2333. int ret;
  2334. dev_dbg(&pdev->dev, "%s(), dev name %s\n",
  2335. __func__, dev_name(&pdev->dev));
  2336. ret = regulator_disable(priv->avdd_reg);
  2337. if (ret) {
  2338. dev_err(&pdev->dev, "%s(), failed to disable regulator!\n",
  2339. __func__);
  2340. return ret;
  2341. }
  2342. return 0;
  2343. }
  2344. static struct platform_driver mt6359_platform_driver = {
  2345. .driver = {
  2346. .name = "mt6359-sound",
  2347. },
  2348. .probe = mt6359_platform_driver_probe,
  2349. .remove = mt6359_platform_driver_remove,
  2350. };
  2351. module_platform_driver(mt6359_platform_driver)
  2352. /* Module information */
  2353. MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver");
  2354. MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
  2355. MODULE_AUTHOR("Eason Yen <eason.yen@mediatek.com>");
  2356. MODULE_LICENSE("GPL v2");