mt6358.h 125 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mt6358.h -- mt6358 ALSA SoC audio codec driver
  4. *
  5. * Copyright (c) 2018 MediaTek Inc.
  6. * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
  7. */
  8. #ifndef __MT6358_H__
  9. #define __MT6358_H__
  10. /* Reg bit define */
  11. /* MT6358_DCXO_CW14 */
  12. #define RG_XO_AUDIO_EN_M_SFT 13
  13. /* MT6358_DCXO_CW13 */
  14. #define RG_XO_VOW_EN_SFT 8
  15. /* MT6358_AUD_TOP_CKPDN_CON0 */
  16. #define RG_VOW13M_CK_PDN_SFT 13
  17. #define RG_VOW13M_CK_PDN_MASK 0x1
  18. #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
  19. #define RG_VOW32K_CK_PDN_SFT 12
  20. #define RG_VOW32K_CK_PDN_MASK 0x1
  21. #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
  22. #define RG_AUD_INTRP_CK_PDN_SFT 8
  23. #define RG_AUD_INTRP_CK_PDN_MASK 0x1
  24. #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
  25. #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT 7
  26. #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
  27. #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
  28. #define RG_AUDNCP_CK_PDN_SFT 6
  29. #define RG_AUDNCP_CK_PDN_MASK 0x1
  30. #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
  31. #define RG_ZCD13M_CK_PDN_SFT 5
  32. #define RG_ZCD13M_CK_PDN_MASK 0x1
  33. #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
  34. #define RG_AUDIF_CK_PDN_SFT 2
  35. #define RG_AUDIF_CK_PDN_MASK 0x1
  36. #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
  37. #define RG_AUD_CK_PDN_SFT 1
  38. #define RG_AUD_CK_PDN_MASK 0x1
  39. #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
  40. #define RG_ACCDET_CK_PDN_SFT 0
  41. #define RG_ACCDET_CK_PDN_MASK 0x1
  42. #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
  43. /* MT6358_AUD_TOP_CKPDN_CON0_SET */
  44. #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0
  45. #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff
  46. #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)
  47. /* MT6358_AUD_TOP_CKPDN_CON0_CLR */
  48. #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0
  49. #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff
  50. #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)
  51. /* MT6358_AUD_TOP_CKSEL_CON0 */
  52. #define RG_AUDIF_CK_CKSEL_SFT 3
  53. #define RG_AUDIF_CK_CKSEL_MASK 0x1
  54. #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
  55. #define RG_AUD_CK_CKSEL_SFT 2
  56. #define RG_AUD_CK_CKSEL_MASK 0x1
  57. #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
  58. /* MT6358_AUD_TOP_CKSEL_CON0_SET */
  59. #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0
  60. #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf
  61. #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)
  62. /* MT6358_AUD_TOP_CKSEL_CON0_CLR */
  63. #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0
  64. #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf
  65. #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)
  66. /* MT6358_AUD_TOP_CKTST_CON0 */
  67. #define RG_VOW13M_CK_TSTSEL_SFT 9
  68. #define RG_VOW13M_CK_TSTSEL_MASK 0x1
  69. #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
  70. #define RG_VOW13M_CK_TST_DIS_SFT 8
  71. #define RG_VOW13M_CK_TST_DIS_MASK 0x1
  72. #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
  73. #define RG_AUD26M_CK_TSTSEL_SFT 4
  74. #define RG_AUD26M_CK_TSTSEL_MASK 0x1
  75. #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
  76. #define RG_AUDIF_CK_TSTSEL_SFT 3
  77. #define RG_AUDIF_CK_TSTSEL_MASK 0x1
  78. #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
  79. #define RG_AUD_CK_TSTSEL_SFT 2
  80. #define RG_AUD_CK_TSTSEL_MASK 0x1
  81. #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
  82. #define RG_AUD26M_CK_TST_DIS_SFT 0
  83. #define RG_AUD26M_CK_TST_DIS_MASK 0x1
  84. #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
  85. /* MT6358_AUD_TOP_CLK_HWEN_CON0 */
  86. #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0
  87. #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
  88. #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
  89. /* MT6358_AUD_TOP_CLK_HWEN_CON0_SET */
  90. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0
  91. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff
  92. #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)
  93. /* MT6358_AUD_TOP_CLK_HWEN_CON0_CLR */
  94. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0
  95. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff
  96. #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)
  97. /* MT6358_AUD_TOP_RST_CON0 */
  98. #define RG_AUDNCP_RST_SFT 3
  99. #define RG_AUDNCP_RST_MASK 0x1
  100. #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
  101. #define RG_ZCD_RST_SFT 2
  102. #define RG_ZCD_RST_MASK 0x1
  103. #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
  104. #define RG_ACCDET_RST_SFT 1
  105. #define RG_ACCDET_RST_MASK 0x1
  106. #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
  107. #define RG_AUDIO_RST_SFT 0
  108. #define RG_AUDIO_RST_MASK 0x1
  109. #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
  110. /* MT6358_AUD_TOP_RST_CON0_SET */
  111. #define RG_AUD_TOP_RST_CON0_SET_SFT 0
  112. #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf
  113. #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)
  114. /* MT6358_AUD_TOP_RST_CON0_CLR */
  115. #define RG_AUD_TOP_RST_CON0_CLR_SFT 0
  116. #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf
  117. #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)
  118. /* MT6358_AUD_TOP_RST_BANK_CON0 */
  119. #define BANK_AUDZCD_SWRST_SFT 2
  120. #define BANK_AUDZCD_SWRST_MASK 0x1
  121. #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
  122. #define BANK_AUDIO_SWRST_SFT 1
  123. #define BANK_AUDIO_SWRST_MASK 0x1
  124. #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
  125. #define BANK_ACCDET_SWRST_SFT 0
  126. #define BANK_ACCDET_SWRST_MASK 0x1
  127. #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
  128. /* MT6358_AUD_TOP_INT_CON0 */
  129. #define RG_INT_EN_AUDIO_SFT 0
  130. #define RG_INT_EN_AUDIO_MASK 0x1
  131. #define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0)
  132. #define RG_INT_EN_ACCDET_SFT 5
  133. #define RG_INT_EN_ACCDET_MASK 0x1
  134. #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
  135. #define RG_INT_EN_ACCDET_EINT0_SFT 6
  136. #define RG_INT_EN_ACCDET_EINT0_MASK 0x1
  137. #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
  138. #define RG_INT_EN_ACCDET_EINT1_SFT 7
  139. #define RG_INT_EN_ACCDET_EINT1_MASK 0x1
  140. #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
  141. /* MT6358_AUD_TOP_INT_CON0_SET */
  142. #define RG_AUD_INT_CON0_SET_SFT 0
  143. #define RG_AUD_INT_CON0_SET_MASK 0xffff
  144. #define RG_AUD_INT_CON0_SET_MASK_SFT (0xffff << 0)
  145. /* MT6358_AUD_TOP_INT_CON0_CLR */
  146. #define RG_AUD_INT_CON0_CLR_SFT 0
  147. #define RG_AUD_INT_CON0_CLR_MASK 0xffff
  148. #define RG_AUD_INT_CON0_CLR_MASK_SFT (0xffff << 0)
  149. /* MT6358_AUD_TOP_INT_MASK_CON0 */
  150. #define RG_INT_MASK_AUDIO_SFT 0
  151. #define RG_INT_MASK_AUDIO_MASK 0x1
  152. #define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0)
  153. #define RG_INT_MASK_ACCDET_SFT 5
  154. #define RG_INT_MASK_ACCDET_MASK 0x1
  155. #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
  156. #define RG_INT_MASK_ACCDET_EINT0_SFT 6
  157. #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
  158. #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
  159. #define RG_INT_MASK_ACCDET_EINT1_SFT 7
  160. #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
  161. #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
  162. /* MT6358_AUD_TOP_INT_MASK_CON0_SET */
  163. #define RG_AUD_INT_MASK_CON0_SET_SFT 0
  164. #define RG_AUD_INT_MASK_CON0_SET_MASK 0xff
  165. #define RG_AUD_INT_MASK_CON0_SET_MASK_SFT (0xff << 0)
  166. /* MT6358_AUD_TOP_INT_MASK_CON0_CLR */
  167. #define RG_AUD_INT_MASK_CON0_CLR_SFT 0
  168. #define RG_AUD_INT_MASK_CON0_CLR_MASK 0xff
  169. #define RG_AUD_INT_MASK_CON0_CLR_MASK_SFT (0xff << 0)
  170. /* MT6358_AUD_TOP_INT_STATUS0 */
  171. #define RG_INT_STATUS_AUDIO_SFT 0
  172. #define RG_INT_STATUS_AUDIO_MASK 0x1
  173. #define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0)
  174. #define RG_INT_STATUS_ACCDET_SFT 5
  175. #define RG_INT_STATUS_ACCDET_MASK 0x1
  176. #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
  177. #define RG_INT_STATUS_ACCDET_EINT0_SFT 6
  178. #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
  179. #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
  180. #define RG_INT_STATUS_ACCDET_EINT1_SFT 7
  181. #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
  182. #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
  183. /* MT6358_AUD_TOP_INT_RAW_STATUS0 */
  184. #define RG_INT_RAW_STATUS_AUDIO_SFT 0
  185. #define RG_INT_RAW_STATUS_AUDIO_MASK 0x1
  186. #define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0)
  187. #define RG_INT_RAW_STATUS_ACCDET_SFT 5
  188. #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
  189. #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
  190. #define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6
  191. #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
  192. #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
  193. #define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7
  194. #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
  195. #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
  196. /* MT6358_AUD_TOP_INT_MISC_CON0 */
  197. #define RG_AUD_TOP_INT_POLARITY_SFT 0
  198. #define RG_AUD_TOP_INT_POLARITY_MASK 0x1
  199. #define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0)
  200. /* MT6358_AUDNCP_CLKDIV_CON0 */
  201. #define RG_DIVCKS_CHG_SFT 0
  202. #define RG_DIVCKS_CHG_MASK 0x1
  203. #define RG_DIVCKS_CHG_MASK_SFT (0x1 << 0)
  204. /* MT6358_AUDNCP_CLKDIV_CON1 */
  205. #define RG_DIVCKS_ON_SFT 0
  206. #define RG_DIVCKS_ON_MASK 0x1
  207. #define RG_DIVCKS_ON_MASK_SFT (0x1 << 0)
  208. /* MT6358_AUDNCP_CLKDIV_CON2 */
  209. #define RG_DIVCKS_PRG_SFT 0
  210. #define RG_DIVCKS_PRG_MASK 0x1ff
  211. #define RG_DIVCKS_PRG_MASK_SFT (0x1ff << 0)
  212. /* MT6358_AUDNCP_CLKDIV_CON3 */
  213. #define RG_DIVCKS_PWD_NCP_SFT 0
  214. #define RG_DIVCKS_PWD_NCP_MASK 0x1
  215. #define RG_DIVCKS_PWD_NCP_MASK_SFT (0x1 << 0)
  216. /* MT6358_AUDNCP_CLKDIV_CON4 */
  217. #define RG_DIVCKS_PWD_NCP_ST_SEL_SFT 0
  218. #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
  219. #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT (0x3 << 0)
  220. /* MT6358_AUD_TOP_MON_CON0 */
  221. #define RG_AUD_TOP_MON_SEL_SFT 0
  222. #define RG_AUD_TOP_MON_SEL_MASK 0x7
  223. #define RG_AUD_TOP_MON_SEL_MASK_SFT (0x7 << 0)
  224. #define RG_AUD_CLK_INT_MON_FLAG_SEL_SFT 3
  225. #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xff
  226. #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT (0xff << 3)
  227. #define RG_AUD_CLK_INT_MON_FLAG_EN_SFT 11
  228. #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1
  229. #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 11)
  230. /* MT6358_AUDIO_DIG_DSN_ID */
  231. #define AUDIO_DIG_ANA_ID_SFT 0
  232. #define AUDIO_DIG_ANA_ID_MASK 0xff
  233. #define AUDIO_DIG_ANA_ID_MASK_SFT (0xff << 0)
  234. #define AUDIO_DIG_DIG_ID_SFT 8
  235. #define AUDIO_DIG_DIG_ID_MASK 0xff
  236. #define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 8)
  237. /* MT6358_AUDIO_DIG_DSN_REV0 */
  238. #define AUDIO_DIG_ANA_MINOR_REV_SFT 0
  239. #define AUDIO_DIG_ANA_MINOR_REV_MASK 0xf
  240. #define AUDIO_DIG_ANA_MINOR_REV_MASK_SFT (0xf << 0)
  241. #define AUDIO_DIG_ANA_MAJOR_REV_SFT 4
  242. #define AUDIO_DIG_ANA_MAJOR_REV_MASK 0xf
  243. #define AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
  244. #define AUDIO_DIG_DIG_MINOR_REV_SFT 8
  245. #define AUDIO_DIG_DIG_MINOR_REV_MASK 0xf
  246. #define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 8)
  247. #define AUDIO_DIG_DIG_MAJOR_REV_SFT 12
  248. #define AUDIO_DIG_DIG_MAJOR_REV_MASK 0xf
  249. #define AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
  250. /* MT6358_AUDIO_DIG_DSN_DBI */
  251. #define AUDIO_DIG_DSN_CBS_SFT 0
  252. #define AUDIO_DIG_DSN_CBS_MASK 0x3
  253. #define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0)
  254. #define AUDIO_DIG_DSN_BIX_SFT 2
  255. #define AUDIO_DIG_DSN_BIX_MASK 0x3
  256. #define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2)
  257. #define AUDIO_DIG_ESP_SFT 8
  258. #define AUDIO_DIG_ESP_MASK 0xff
  259. #define AUDIO_DIG_ESP_MASK_SFT (0xff << 8)
  260. /* MT6358_AUDIO_DIG_DSN_DXI */
  261. #define AUDIO_DIG_DSN_FPI_SFT 0
  262. #define AUDIO_DIG_DSN_FPI_MASK 0xff
  263. #define AUDIO_DIG_DSN_FPI_MASK_SFT (0xff << 0)
  264. /* MT6358_AFE_UL_DL_CON0 */
  265. #define AFE_UL_LR_SWAP_SFT 15
  266. #define AFE_UL_LR_SWAP_MASK 0x1
  267. #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
  268. #define AFE_DL_LR_SWAP_SFT 14
  269. #define AFE_DL_LR_SWAP_MASK 0x1
  270. #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
  271. #define AFE_ON_SFT 0
  272. #define AFE_ON_MASK 0x1
  273. #define AFE_ON_MASK_SFT (0x1 << 0)
  274. /* MT6358_AFE_DL_SRC2_CON0_L */
  275. #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
  276. #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
  277. #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
  278. /* MT6358_AFE_UL_SRC_CON0_H */
  279. #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11
  280. #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
  281. #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
  282. #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8
  283. #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
  284. #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
  285. #define C_TWO_DIGITAL_MIC_CTL_SFT 7
  286. #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
  287. #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
  288. /* MT6358_AFE_UL_SRC_CON0_L */
  289. #define DMIC_LOW_POWER_MODE_CTL_SFT 14
  290. #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
  291. #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
  292. #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
  293. #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
  294. #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
  295. #define UL_LOOP_BACK_MODE_CTL_SFT 2
  296. #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
  297. #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
  298. #define UL_SDM_3_LEVEL_CTL_SFT 1
  299. #define UL_SDM_3_LEVEL_CTL_MASK 0x1
  300. #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
  301. #define UL_SRC_ON_TMP_CTL_SFT 0
  302. #define UL_SRC_ON_TMP_CTL_MASK 0x1
  303. #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
  304. /* MT6358_AFE_TOP_CON0 */
  305. #define MTKAIF_SINE_ON_SFT 2
  306. #define MTKAIF_SINE_ON_MASK 0x1
  307. #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
  308. #define UL_SINE_ON_SFT 1
  309. #define UL_SINE_ON_MASK 0x1
  310. #define UL_SINE_ON_MASK_SFT (0x1 << 1)
  311. #define DL_SINE_ON_SFT 0
  312. #define DL_SINE_ON_MASK 0x1
  313. #define DL_SINE_ON_MASK_SFT (0x1 << 0)
  314. /* MT6358_AUDIO_TOP_CON0 */
  315. #define PDN_AFE_CTL_SFT 7
  316. #define PDN_AFE_CTL_MASK 0x1
  317. #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
  318. #define PDN_DAC_CTL_SFT 6
  319. #define PDN_DAC_CTL_MASK 0x1
  320. #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
  321. #define PDN_ADC_CTL_SFT 5
  322. #define PDN_ADC_CTL_MASK 0x1
  323. #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
  324. #define PDN_I2S_DL_CTL_SFT 3
  325. #define PDN_I2S_DL_CTL_MASK 0x1
  326. #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
  327. #define PWR_CLK_DIS_CTL_SFT 2
  328. #define PWR_CLK_DIS_CTL_MASK 0x1
  329. #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
  330. #define PDN_AFE_TESTMODEL_CTL_SFT 1
  331. #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
  332. #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
  333. #define PDN_RESERVED_SFT 0
  334. #define PDN_RESERVED_MASK 0x1
  335. #define PDN_RESERVED_MASK_SFT (0x1 << 0)
  336. /* MT6358_AFE_MON_DEBUG0 */
  337. #define AUDIO_SYS_TOP_MON_SWAP_SFT 14
  338. #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
  339. #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
  340. #define AUDIO_SYS_TOP_MON_SEL_SFT 8
  341. #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f
  342. #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)
  343. #define AFE_MON_SEL_SFT 0
  344. #define AFE_MON_SEL_MASK 0xff
  345. #define AFE_MON_SEL_MASK_SFT (0xff << 0)
  346. /* MT6358_AFUNC_AUD_CON0 */
  347. #define CCI_AUD_ANACK_SEL_SFT 15
  348. #define CCI_AUD_ANACK_SEL_MASK 0x1
  349. #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
  350. #define CCI_AUDIO_FIFO_WPTR_SFT 12
  351. #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
  352. #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
  353. #define CCI_SCRAMBLER_CG_EN_SFT 11
  354. #define CCI_SCRAMBLER_CG_EN_MASK 0x1
  355. #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
  356. #define CCI_LCH_INV_SFT 10
  357. #define CCI_LCH_INV_MASK 0x1
  358. #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
  359. #define CCI_RAND_EN_SFT 9
  360. #define CCI_RAND_EN_MASK 0x1
  361. #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
  362. #define CCI_SPLT_SCRMB_CLK_ON_SFT 8
  363. #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
  364. #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
  365. #define CCI_SPLT_SCRMB_ON_SFT 7
  366. #define CCI_SPLT_SCRMB_ON_MASK 0x1
  367. #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
  368. #define CCI_AUD_IDAC_TEST_EN_SFT 6
  369. #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
  370. #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
  371. #define CCI_ZERO_PAD_DISABLE_SFT 5
  372. #define CCI_ZERO_PAD_DISABLE_MASK 0x1
  373. #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
  374. #define CCI_AUD_SPLIT_TEST_EN_SFT 4
  375. #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
  376. #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
  377. #define CCI_AUD_SDM_MUTEL_SFT 3
  378. #define CCI_AUD_SDM_MUTEL_MASK 0x1
  379. #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
  380. #define CCI_AUD_SDM_MUTER_SFT 2
  381. #define CCI_AUD_SDM_MUTER_MASK 0x1
  382. #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
  383. #define CCI_AUD_SDM_7BIT_SEL_SFT 1
  384. #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
  385. #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
  386. #define CCI_SCRAMBLER_EN_SFT 0
  387. #define CCI_SCRAMBLER_EN_MASK 0x1
  388. #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
  389. /* MT6358_AFUNC_AUD_CON1 */
  390. #define AUD_SDM_TEST_L_SFT 8
  391. #define AUD_SDM_TEST_L_MASK 0xff
  392. #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)
  393. #define AUD_SDM_TEST_R_SFT 0
  394. #define AUD_SDM_TEST_R_MASK 0xff
  395. #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)
  396. /* MT6358_AFUNC_AUD_CON2 */
  397. #define CCI_AUD_DAC_ANA_MUTE_SFT 7
  398. #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
  399. #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
  400. #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6
  401. #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
  402. #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
  403. #define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4
  404. #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
  405. #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
  406. #define CCI_AUDIO_FIFO_ENABLE_SFT 3
  407. #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
  408. #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
  409. #define CCI_ACD_MODE_SFT 2
  410. #define CCI_ACD_MODE_MASK 0x1
  411. #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
  412. #define CCI_AFIFO_CLK_PWDB_SFT 1
  413. #define CCI_AFIFO_CLK_PWDB_MASK 0x1
  414. #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
  415. #define CCI_ACD_FUNC_RSTB_SFT 0
  416. #define CCI_ACD_FUNC_RSTB_MASK 0x1
  417. #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
  418. /* MT6358_AFUNC_AUD_CON3 */
  419. #define SDM_ANA13M_TESTCK_SEL_SFT 15
  420. #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
  421. #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
  422. #define SDM_ANA13M_TESTCK_SRC_SEL_SFT 12
  423. #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
  424. #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
  425. #define SDM_TESTCK_SRC_SEL_SFT 8
  426. #define SDM_TESTCK_SRC_SEL_MASK 0x7
  427. #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
  428. #define DIGMIC_TESTCK_SRC_SEL_SFT 4
  429. #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
  430. #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
  431. #define DIGMIC_TESTCK_SEL_SFT 0
  432. #define DIGMIC_TESTCK_SEL_MASK 0x1
  433. #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
  434. /* MT6358_AFUNC_AUD_CON4 */
  435. #define UL_FIFO_WCLK_INV_SFT 8
  436. #define UL_FIFO_WCLK_INV_MASK 0x1
  437. #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
  438. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6
  439. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
  440. #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
  441. #define UL_FIFO_WDATA_TESTEN_SFT 5
  442. #define UL_FIFO_WDATA_TESTEN_MASK 0x1
  443. #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
  444. #define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4
  445. #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
  446. #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
  447. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
  448. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
  449. #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
  450. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
  451. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
  452. #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
  453. /* MT6358_AFUNC_AUD_CON5 */
  454. #define R_AUD_DAC_POS_LARGE_MONO_SFT 8
  455. #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff
  456. #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)
  457. #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0
  458. #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff
  459. #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)
  460. /* MT6358_AFUNC_AUD_CON6 */
  461. #define R_AUD_DAC_POS_SMALL_MONO_SFT 12
  462. #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf
  463. #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)
  464. #define R_AUD_DAC_NEG_SMALL_MONO_SFT 8
  465. #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf
  466. #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)
  467. #define R_AUD_DAC_POS_TINY_MONO_SFT 6
  468. #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
  469. #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
  470. #define R_AUD_DAC_NEG_TINY_MONO_SFT 4
  471. #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
  472. #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
  473. #define R_AUD_DAC_MONO_SEL_SFT 3
  474. #define R_AUD_DAC_MONO_SEL_MASK 0x1
  475. #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
  476. #define R_AUD_DAC_SW_RSTB_SFT 0
  477. #define R_AUD_DAC_SW_RSTB_MASK 0x1
  478. #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
  479. /* MT6358_AFUNC_AUD_MON0 */
  480. #define AUD_SCR_OUT_L_SFT 8
  481. #define AUD_SCR_OUT_L_MASK 0xff
  482. #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)
  483. #define AUD_SCR_OUT_R_SFT 0
  484. #define AUD_SCR_OUT_R_MASK 0xff
  485. #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)
  486. /* MT6358_AUDRC_TUNE_MON0 */
  487. #define ASYNC_TEST_OUT_BCK_SFT 15
  488. #define ASYNC_TEST_OUT_BCK_MASK 0x1
  489. #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
  490. #define RGS_AUDRCTUNE1READ_SFT 8
  491. #define RGS_AUDRCTUNE1READ_MASK 0x1f
  492. #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)
  493. #define RGS_AUDRCTUNE0READ_SFT 0
  494. #define RGS_AUDRCTUNE0READ_MASK 0x1f
  495. #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)
  496. /* MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 */
  497. #define AFE_RESERVED_SFT 1
  498. #define AFE_RESERVED_MASK 0x7fff
  499. #define AFE_RESERVED_MASK_SFT (0x7fff << 1)
  500. #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0
  501. #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
  502. #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
  503. /* MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */
  504. #define MTKAIF_RXIF_WR_FULL_STATUS_SFT 1
  505. #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
  506. #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
  507. #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0
  508. #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
  509. #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
  510. /* MT6358_AFE_ADDA_MTKAIF_MON0 */
  511. #define MTKAIFTX_V3_SYNC_OUT_SFT 14
  512. #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
  513. #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 14)
  514. #define MTKAIFTX_V3_SDATA_OUT2_SFT 13
  515. #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
  516. #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
  517. #define MTKAIFTX_V3_SDATA_OUT1_SFT 12
  518. #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
  519. #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
  520. #define MTKAIF_RXIF_FIFO_STATUS_SFT 0
  521. #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff
  522. #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)
  523. /* MT6358_AFE_ADDA_MTKAIF_MON1 */
  524. #define MTKAIFRX_V3_SYNC_IN_SFT 14
  525. #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
  526. #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 14)
  527. #define MTKAIFRX_V3_SDATA_IN2_SFT 13
  528. #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
  529. #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
  530. #define MTKAIFRX_V3_SDATA_IN1_SFT 12
  531. #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
  532. #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
  533. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 11
  534. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
  535. #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
  536. #define MTKAIF_RXIF_INVALID_FLAG_SFT 8
  537. #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
  538. #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
  539. #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0
  540. #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff
  541. #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)
  542. /* MT6358_AFE_ADDA_MTKAIF_MON2 */
  543. #define MTKAIF_TXIF_IN_CH2_SFT 8
  544. #define MTKAIF_TXIF_IN_CH2_MASK 0xff
  545. #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
  546. #define MTKAIF_TXIF_IN_CH1_SFT 0
  547. #define MTKAIF_TXIF_IN_CH1_MASK 0xff
  548. #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
  549. /* MT6358_AFE_ADDA_MTKAIF_MON3 */
  550. #define MTKAIF_RXIF_OUT_CH2_SFT 8
  551. #define MTKAIF_RXIF_OUT_CH2_MASK 0xff
  552. #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
  553. #define MTKAIF_RXIF_OUT_CH1_SFT 0
  554. #define MTKAIF_RXIF_OUT_CH1_MASK 0xff
  555. #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
  556. /* MT6358_AFE_ADDA_MTKAIF_CFG0 */
  557. #define RG_MTKAIF_RXIF_CLKINV_SFT 15
  558. #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
  559. #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
  560. #define RG_MTKAIF_RXIF_PROTOCOL2_SFT 8
  561. #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
  562. #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
  563. #define RG_MTKAIF_BYPASS_SRC_MODE_SFT 6
  564. #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
  565. #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
  566. #define RG_MTKAIF_BYPASS_SRC_TEST_SFT 5
  567. #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
  568. #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
  569. #define RG_MTKAIF_TXIF_PROTOCOL2_SFT 4
  570. #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
  571. #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
  572. #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 2
  573. #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
  574. #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
  575. #define RG_MTKAIF_LOOPBACK_TEST2_SFT 1
  576. #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
  577. #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
  578. #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0
  579. #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
  580. #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
  581. /* MT6358_AFE_ADDA_MTKAIF_RX_CFG0 */
  582. #define RG_MTKAIF_RXIF_VOICE_MODE_SFT 12
  583. #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf
  584. #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)
  585. #define RG_MTKAIF_RXIF_DATA_BIT_SFT 8
  586. #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
  587. #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
  588. #define RG_MTKAIF_RXIF_FIFO_RSP_SFT 4
  589. #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
  590. #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
  591. #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3
  592. #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
  593. #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
  594. #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0
  595. #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
  596. #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
  597. /* MT6358_AFE_ADDA_MTKAIF_RX_CFG1 */
  598. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 12
  599. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
  600. #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
  601. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
  602. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
  603. #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
  604. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 4
  605. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf
  606. #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
  607. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0
  608. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf
  609. #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)
  610. /* MT6358_AFE_ADDA_MTKAIF_RX_CFG2 */
  611. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 12
  612. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
  613. #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
  614. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0
  615. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff
  616. #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)
  617. /* MT6358_AFE_ADDA_MTKAIF_RX_CFG3 */
  618. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT 7
  619. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
  620. #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
  621. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4
  622. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
  623. #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
  624. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3
  625. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
  626. #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
  627. /* MT6358_AFE_ADDA_MTKAIF_TX_CFG1 */
  628. #define RG_MTKAIF_SYNC_WORD2_SFT 4
  629. #define RG_MTKAIF_SYNC_WORD2_MASK 0x7
  630. #define RG_MTKAIF_SYNC_WORD2_MASK_SFT (0x7 << 4)
  631. #define RG_MTKAIF_SYNC_WORD1_SFT 0
  632. #define RG_MTKAIF_SYNC_WORD1_MASK 0x7
  633. #define RG_MTKAIF_SYNC_WORD1_MASK_SFT (0x7 << 0)
  634. /* MT6358_AFE_SGEN_CFG0 */
  635. #define SGEN_AMP_DIV_CH1_CTL_SFT 12
  636. #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf
  637. #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)
  638. #define SGEN_DAC_EN_CTL_SFT 7
  639. #define SGEN_DAC_EN_CTL_MASK 0x1
  640. #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
  641. #define SGEN_MUTE_SW_CTL_SFT 6
  642. #define SGEN_MUTE_SW_CTL_MASK 0x1
  643. #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
  644. #define R_AUD_SDM_MUTE_L_SFT 5
  645. #define R_AUD_SDM_MUTE_L_MASK 0x1
  646. #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
  647. #define R_AUD_SDM_MUTE_R_SFT 4
  648. #define R_AUD_SDM_MUTE_R_MASK 0x1
  649. #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
  650. /* MT6358_AFE_SGEN_CFG1 */
  651. #define C_SGEN_RCH_INV_5BIT_SFT 15
  652. #define C_SGEN_RCH_INV_5BIT_MASK 0x1
  653. #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
  654. #define C_SGEN_RCH_INV_8BIT_SFT 14
  655. #define C_SGEN_RCH_INV_8BIT_MASK 0x1
  656. #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
  657. #define SGEN_FREQ_DIV_CH1_CTL_SFT 0
  658. #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f
  659. #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)
  660. /* MT6358_AFE_ADC_ASYNC_FIFO_CFG */
  661. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5
  662. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
  663. #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
  664. #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4
  665. #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
  666. #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
  667. #define RG_AMIC_UL_ADC_CLK_SEL_SFT 1
  668. #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
  669. #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
  670. /* MT6358_AFE_DCCLK_CFG0 */
  671. #define DCCLK_DIV_SFT 5
  672. #define DCCLK_DIV_MASK 0x7ff
  673. #define DCCLK_DIV_MASK_SFT (0x7ff << 5)
  674. #define DCCLK_INV_SFT 4
  675. #define DCCLK_INV_MASK 0x1
  676. #define DCCLK_INV_MASK_SFT (0x1 << 4)
  677. #define DCCLK_PDN_SFT 1
  678. #define DCCLK_PDN_MASK 0x1
  679. #define DCCLK_PDN_MASK_SFT (0x1 << 1)
  680. #define DCCLK_GEN_ON_SFT 0
  681. #define DCCLK_GEN_ON_MASK 0x1
  682. #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
  683. /* MT6358_AFE_DCCLK_CFG1 */
  684. #define RESYNC_SRC_SEL_SFT 10
  685. #define RESYNC_SRC_SEL_MASK 0x3
  686. #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
  687. #define RESYNC_SRC_CK_INV_SFT 9
  688. #define RESYNC_SRC_CK_INV_MASK 0x1
  689. #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
  690. #define DCCLK_RESYNC_BYPASS_SFT 8
  691. #define DCCLK_RESYNC_BYPASS_MASK 0x1
  692. #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
  693. #define DCCLK_PHASE_SEL_SFT 4
  694. #define DCCLK_PHASE_SEL_MASK 0xf
  695. #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)
  696. /* MT6358_AUDIO_DIG_CFG */
  697. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 15
  698. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
  699. #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
  700. #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 8
  701. #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f
  702. #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)
  703. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7
  704. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
  705. #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
  706. #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0
  707. #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f
  708. #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)
  709. /* MT6358_AFE_AUD_PAD_TOP */
  710. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 12
  711. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
  712. #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
  713. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 11
  714. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
  715. #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
  716. #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 8
  717. #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
  718. #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
  719. /* MT6358_AFE_AUD_PAD_TOP_MON */
  720. #define ADDA_AUD_PAD_TOP_MON_SFT 0
  721. #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff
  722. #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
  723. /* MT6358_AFE_AUD_PAD_TOP_MON1 */
  724. #define ADDA_AUD_PAD_TOP_MON1_SFT 0
  725. #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff
  726. #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)
  727. /* MT6358_AFE_DL_NLE_CFG */
  728. #define NLE_RCH_HPGAIN_SEL_SFT 10
  729. #define NLE_RCH_HPGAIN_SEL_MASK 0x1
  730. #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
  731. #define NLE_RCH_CH_SEL_SFT 9
  732. #define NLE_RCH_CH_SEL_MASK 0x1
  733. #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
  734. #define NLE_RCH_ON_SFT 8
  735. #define NLE_RCH_ON_MASK 0x1
  736. #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
  737. #define NLE_LCH_HPGAIN_SEL_SFT 2
  738. #define NLE_LCH_HPGAIN_SEL_MASK 0x1
  739. #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
  740. #define NLE_LCH_CH_SEL_SFT 1
  741. #define NLE_LCH_CH_SEL_MASK 0x1
  742. #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
  743. #define NLE_LCH_ON_SFT 0
  744. #define NLE_LCH_ON_MASK 0x1
  745. #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
  746. /* MT6358_AFE_DL_NLE_MON */
  747. #define NLE_MONITOR_SFT 0
  748. #define NLE_MONITOR_MASK 0x3fff
  749. #define NLE_MONITOR_MASK_SFT (0x3fff << 0)
  750. /* MT6358_AFE_CG_EN_MON */
  751. #define CK_CG_EN_MON_SFT 0
  752. #define CK_CG_EN_MON_MASK 0x3f
  753. #define CK_CG_EN_MON_MASK_SFT (0x3f << 0)
  754. /* MT6358_AFE_VOW_TOP */
  755. #define PDN_VOW_SFT 15
  756. #define PDN_VOW_MASK 0x1
  757. #define PDN_VOW_MASK_SFT (0x1 << 15)
  758. #define VOW_1P6M_800K_SEL_SFT 14
  759. #define VOW_1P6M_800K_SEL_MASK 0x1
  760. #define VOW_1P6M_800K_SEL_MASK_SFT (0x1 << 14)
  761. #define VOW_DIGMIC_ON_SFT 13
  762. #define VOW_DIGMIC_ON_MASK 0x1
  763. #define VOW_DIGMIC_ON_MASK_SFT (0x1 << 13)
  764. #define VOW_CK_DIV_RST_SFT 12
  765. #define VOW_CK_DIV_RST_MASK 0x1
  766. #define VOW_CK_DIV_RST_MASK_SFT (0x1 << 12)
  767. #define VOW_ON_SFT 11
  768. #define VOW_ON_MASK 0x1
  769. #define VOW_ON_MASK_SFT (0x1 << 11)
  770. #define VOW_DIGMIC_CK_PHASE_SEL_SFT 8
  771. #define VOW_DIGMIC_CK_PHASE_SEL_MASK 0x7
  772. #define VOW_DIGMIC_CK_PHASE_SEL_MASK_SFT (0x7 << 8)
  773. #define MAIN_DMIC_CK_VOW_SEL_SFT 7
  774. #define MAIN_DMIC_CK_VOW_SEL_MASK 0x1
  775. #define MAIN_DMIC_CK_VOW_SEL_MASK_SFT (0x1 << 7)
  776. #define VOW_SDM_3_LEVEL_SFT 6
  777. #define VOW_SDM_3_LEVEL_MASK 0x1
  778. #define VOW_SDM_3_LEVEL_MASK_SFT (0x1 << 6)
  779. #define VOW_LOOP_BACK_MODE_SFT 5
  780. #define VOW_LOOP_BACK_MODE_MASK 0x1
  781. #define VOW_LOOP_BACK_MODE_MASK_SFT (0x1 << 5)
  782. #define VOW_INTR_SOURCE_SEL_SFT 4
  783. #define VOW_INTR_SOURCE_SEL_MASK 0x1
  784. #define VOW_INTR_SOURCE_SEL_MASK_SFT (0x1 << 4)
  785. #define VOW_INTR_CLR_SFT 3
  786. #define VOW_INTR_CLR_MASK 0x1
  787. #define VOW_INTR_CLR_MASK_SFT (0x1 << 3)
  788. #define S_N_VALUE_RST_SFT 2
  789. #define S_N_VALUE_RST_MASK 0x1
  790. #define S_N_VALUE_RST_MASK_SFT (0x1 << 2)
  791. #define SAMPLE_BASE_MODE_SFT 1
  792. #define SAMPLE_BASE_MODE_MASK 0x1
  793. #define SAMPLE_BASE_MODE_MASK_SFT (0x1 << 1)
  794. #define VOW_INTR_FLAG_SFT 0
  795. #define VOW_INTR_FLAG_MASK 0x1
  796. #define VOW_INTR_FLAG_MASK_SFT (0x1 << 0)
  797. /* MT6358_AFE_VOW_CFG0 */
  798. #define AMPREF_SFT 0
  799. #define AMPREF_MASK 0xffff
  800. #define AMPREF_MASK_SFT (0xffff << 0)
  801. /* MT6358_AFE_VOW_CFG1 */
  802. #define TIMERINI_SFT 0
  803. #define TIMERINI_MASK 0xffff
  804. #define TIMERINI_MASK_SFT (0xffff << 0)
  805. /* MT6358_AFE_VOW_CFG2 */
  806. #define B_DEFAULT_SFT 12
  807. #define B_DEFAULT_MASK 0x7
  808. #define B_DEFAULT_MASK_SFT (0x7 << 12)
  809. #define A_DEFAULT_SFT 8
  810. #define A_DEFAULT_MASK 0x7
  811. #define A_DEFAULT_MASK_SFT (0x7 << 8)
  812. #define B_INI_SFT 4
  813. #define B_INI_MASK 0x7
  814. #define B_INI_MASK_SFT (0x7 << 4)
  815. #define A_INI_SFT 0
  816. #define A_INI_MASK 0x7
  817. #define A_INI_MASK_SFT (0x7 << 0)
  818. /* MT6358_AFE_VOW_CFG3 */
  819. #define K_BETA_RISE_SFT 12
  820. #define K_BETA_RISE_MASK 0xf
  821. #define K_BETA_RISE_MASK_SFT (0xf << 12)
  822. #define K_BETA_FALL_SFT 8
  823. #define K_BETA_FALL_MASK 0xf
  824. #define K_BETA_FALL_MASK_SFT (0xf << 8)
  825. #define K_ALPHA_RISE_SFT 4
  826. #define K_ALPHA_RISE_MASK 0xf
  827. #define K_ALPHA_RISE_MASK_SFT (0xf << 4)
  828. #define K_ALPHA_FALL_SFT 0
  829. #define K_ALPHA_FALL_MASK 0xf
  830. #define K_ALPHA_FALL_MASK_SFT (0xf << 0)
  831. /* MT6358_AFE_VOW_CFG4 */
  832. #define VOW_TXIF_SCK_INV_SFT 15
  833. #define VOW_TXIF_SCK_INV_MASK 0x1
  834. #define VOW_TXIF_SCK_INV_MASK_SFT (0x1 << 15)
  835. #define VOW_ADC_TESTCK_SRC_SEL_SFT 12
  836. #define VOW_ADC_TESTCK_SRC_SEL_MASK 0x7
  837. #define VOW_ADC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
  838. #define VOW_ADC_TESTCK_SEL_SFT 11
  839. #define VOW_ADC_TESTCK_SEL_MASK 0x1
  840. #define VOW_ADC_TESTCK_SEL_MASK_SFT (0x1 << 11)
  841. #define VOW_ADC_CLK_INV_SFT 10
  842. #define VOW_ADC_CLK_INV_MASK 0x1
  843. #define VOW_ADC_CLK_INV_MASK_SFT (0x1 << 10)
  844. #define VOW_TXIF_MONO_SFT 9
  845. #define VOW_TXIF_MONO_MASK 0x1
  846. #define VOW_TXIF_MONO_MASK_SFT (0x1 << 9)
  847. #define VOW_TXIF_SCK_DIV_SFT 4
  848. #define VOW_TXIF_SCK_DIV_MASK 0x1f
  849. #define VOW_TXIF_SCK_DIV_MASK_SFT (0x1f << 4)
  850. #define K_GAMMA_SFT 0
  851. #define K_GAMMA_MASK 0xf
  852. #define K_GAMMA_MASK_SFT (0xf << 0)
  853. /* MT6358_AFE_VOW_CFG5 */
  854. #define N_MIN_SFT 0
  855. #define N_MIN_MASK 0xffff
  856. #define N_MIN_MASK_SFT (0xffff << 0)
  857. /* MT6358_AFE_VOW_CFG6 */
  858. #define RG_WINDOW_SIZE_SEL_SFT 12
  859. #define RG_WINDOW_SIZE_SEL_MASK 0x1
  860. #define RG_WINDOW_SIZE_SEL_MASK_SFT (0x1 << 12)
  861. #define RG_FLR_BYPASS_SFT 11
  862. #define RG_FLR_BYPASS_MASK 0x1
  863. #define RG_FLR_BYPASS_MASK_SFT (0x1 << 11)
  864. #define RG_FLR_RATIO_SFT 8
  865. #define RG_FLR_RATIO_MASK 0x7
  866. #define RG_FLR_RATIO_MASK_SFT (0x7 << 8)
  867. #define RG_BUCK_DVFS_DONE_SW_CTL_SFT 7
  868. #define RG_BUCK_DVFS_DONE_SW_CTL_MASK 0x1
  869. #define RG_BUCK_DVFS_DONE_SW_CTL_MASK_SFT (0x1 << 7)
  870. #define RG_BUCK_DVFS_DONE_HW_MODE_SFT 6
  871. #define RG_BUCK_DVFS_DONE_HW_MODE_MASK 0x1
  872. #define RG_BUCK_DVFS_DONE_HW_MODE_MASK_SFT (0x1 << 6)
  873. #define RG_BUCK_DVFS_HW_CNT_THR_SFT 0
  874. #define RG_BUCK_DVFS_HW_CNT_THR_MASK 0x3f
  875. #define RG_BUCK_DVFS_HW_CNT_THR_MASK_SFT (0x3f << 0)
  876. /* MT6358_AFE_VOW_MON0 */
  877. #define VOW_DOWNCNT_SFT 0
  878. #define VOW_DOWNCNT_MASK 0xffff
  879. #define VOW_DOWNCNT_MASK_SFT (0xffff << 0)
  880. /* MT6358_AFE_VOW_MON1 */
  881. #define K_TMP_MON_SFT 10
  882. #define K_TMP_MON_MASK 0xf
  883. #define K_TMP_MON_MASK_SFT (0xf << 10)
  884. #define SLT_COUNTER_MON_SFT 7
  885. #define SLT_COUNTER_MON_MASK 0x7
  886. #define SLT_COUNTER_MON_MASK_SFT (0x7 << 7)
  887. #define VOW_B_SFT 4
  888. #define VOW_B_MASK 0x7
  889. #define VOW_B_MASK_SFT (0x7 << 4)
  890. #define VOW_A_SFT 1
  891. #define VOW_A_MASK 0x7
  892. #define VOW_A_MASK_SFT (0x7 << 1)
  893. #define SECOND_CNT_START_SFT 0
  894. #define SECOND_CNT_START_MASK 0x1
  895. #define SECOND_CNT_START_MASK_SFT (0x1 << 0)
  896. /* MT6358_AFE_VOW_MON2 */
  897. #define VOW_S_L_SFT 0
  898. #define VOW_S_L_MASK 0xffff
  899. #define VOW_S_L_MASK_SFT (0xffff << 0)
  900. /* MT6358_AFE_VOW_MON3 */
  901. #define VOW_S_H_SFT 0
  902. #define VOW_S_H_MASK 0xffff
  903. #define VOW_S_H_MASK_SFT (0xffff << 0)
  904. /* MT6358_AFE_VOW_MON4 */
  905. #define VOW_N_L_SFT 0
  906. #define VOW_N_L_MASK 0xffff
  907. #define VOW_N_L_MASK_SFT (0xffff << 0)
  908. /* MT6358_AFE_VOW_MON5 */
  909. #define VOW_N_H_SFT 0
  910. #define VOW_N_H_MASK 0xffff
  911. #define VOW_N_H_MASK_SFT (0xffff << 0)
  912. /* MT6358_AFE_VOW_SN_INI_CFG */
  913. #define VOW_SN_INI_CFG_EN_SFT 15
  914. #define VOW_SN_INI_CFG_EN_MASK 0x1
  915. #define VOW_SN_INI_CFG_EN_MASK_SFT (0x1 << 15)
  916. #define VOW_SN_INI_CFG_VAL_SFT 0
  917. #define VOW_SN_INI_CFG_VAL_MASK 0x7fff
  918. #define VOW_SN_INI_CFG_VAL_MASK_SFT (0x7fff << 0)
  919. /* MT6358_AFE_VOW_TGEN_CFG0 */
  920. #define VOW_TGEN_EN_SFT 15
  921. #define VOW_TGEN_EN_MASK 0x1
  922. #define VOW_TGEN_EN_MASK_SFT (0x1 << 15)
  923. #define VOW_TGEN_MUTE_SW_SFT 14
  924. #define VOW_TGEN_MUTE_SW_MASK 0x1
  925. #define VOW_TGEN_MUTE_SW_MASK_SFT (0x1 << 14)
  926. #define VOW_TGEN_FREQ_DIV_SFT 0
  927. #define VOW_TGEN_FREQ_DIV_MASK 0x3fff
  928. #define VOW_TGEN_FREQ_DIV_MASK_SFT (0x3fff << 0)
  929. /* MT6358_AFE_VOW_POSDIV_CFG0 */
  930. #define BUCK_DVFS_DONE_SFT 15
  931. #define BUCK_DVFS_DONE_MASK 0x1
  932. #define BUCK_DVFS_DONE_MASK_SFT (0x1 << 15)
  933. #define VOW_32K_MODE_SFT 13
  934. #define VOW_32K_MODE_MASK 0x1
  935. #define VOW_32K_MODE_MASK_SFT (0x1 << 13)
  936. #define RG_BUCK_CLK_DIV_SFT 8
  937. #define RG_BUCK_CLK_DIV_MASK 0x1f
  938. #define RG_BUCK_CLK_DIV_MASK_SFT (0x1f << 8)
  939. #define RG_A1P6M_EN_SEL_SFT 7
  940. #define RG_A1P6M_EN_SEL_MASK 0x1
  941. #define RG_A1P6M_EN_SEL_MASK_SFT (0x1 << 7)
  942. #define VOW_CLK_SEL_SFT 6
  943. #define VOW_CLK_SEL_MASK 0x1
  944. #define VOW_CLK_SEL_MASK_SFT (0x1 << 6)
  945. #define VOW_INTR_SW_MODE_SFT 5
  946. #define VOW_INTR_SW_MODE_MASK 0x1
  947. #define VOW_INTR_SW_MODE_MASK_SFT (0x1 << 5)
  948. #define VOW_INTR_SW_VAL_SFT 4
  949. #define VOW_INTR_SW_VAL_MASK 0x1
  950. #define VOW_INTR_SW_VAL_MASK_SFT (0x1 << 4)
  951. #define VOW_CIC_MODE_SEL_SFT 2
  952. #define VOW_CIC_MODE_SEL_MASK 0x3
  953. #define VOW_CIC_MODE_SEL_MASK_SFT (0x3 << 2)
  954. #define RG_VOW_POSDIV_SFT 0
  955. #define RG_VOW_POSDIV_MASK 0x3
  956. #define RG_VOW_POSDIV_MASK_SFT (0x3 << 0)
  957. /* MT6358_AFE_VOW_HPF_CFG0 */
  958. #define VOW_HPF_DC_TEST_SFT 12
  959. #define VOW_HPF_DC_TEST_MASK 0xf
  960. #define VOW_HPF_DC_TEST_MASK_SFT (0xf << 12)
  961. #define VOW_IRQ_LATCH_SNR_EN_SFT 10
  962. #define VOW_IRQ_LATCH_SNR_EN_MASK 0x1
  963. #define VOW_IRQ_LATCH_SNR_EN_MASK_SFT (0x1 << 10)
  964. #define VOW_DMICCLK_PDN_SFT 9
  965. #define VOW_DMICCLK_PDN_MASK 0x1
  966. #define VOW_DMICCLK_PDN_MASK_SFT (0x1 << 9)
  967. #define VOW_POSDIVCLK_PDN_SFT 8
  968. #define VOW_POSDIVCLK_PDN_MASK 0x1
  969. #define VOW_POSDIVCLK_PDN_MASK_SFT (0x1 << 8)
  970. #define RG_BASELINE_ALPHA_ORDER_SFT 4
  971. #define RG_BASELINE_ALPHA_ORDER_MASK 0xf
  972. #define RG_BASELINE_ALPHA_ORDER_MASK_SFT (0xf << 4)
  973. #define RG_MTKAIF_HPF_BYPASS_SFT 2
  974. #define RG_MTKAIF_HPF_BYPASS_MASK 0x1
  975. #define RG_MTKAIF_HPF_BYPASS_MASK_SFT (0x1 << 2)
  976. #define RG_SNRDET_HPF_BYPASS_SFT 1
  977. #define RG_SNRDET_HPF_BYPASS_MASK 0x1
  978. #define RG_SNRDET_HPF_BYPASS_MASK_SFT (0x1 << 1)
  979. #define RG_HPF_ON_SFT 0
  980. #define RG_HPF_ON_MASK 0x1
  981. #define RG_HPF_ON_MASK_SFT (0x1 << 0)
  982. /* MT6358_AFE_VOW_PERIODIC_CFG0 */
  983. #define RG_PERIODIC_EN_SFT 15
  984. #define RG_PERIODIC_EN_MASK 0x1
  985. #define RG_PERIODIC_EN_MASK_SFT (0x1 << 15)
  986. #define RG_PERIODIC_CNT_CLR_SFT 14
  987. #define RG_PERIODIC_CNT_CLR_MASK 0x1
  988. #define RG_PERIODIC_CNT_CLR_MASK_SFT (0x1 << 14)
  989. #define RG_PERIODIC_CNT_PERIOD_SFT 0
  990. #define RG_PERIODIC_CNT_PERIOD_MASK 0x3fff
  991. #define RG_PERIODIC_CNT_PERIOD_MASK_SFT (0x3fff << 0)
  992. /* MT6358_AFE_VOW_PERIODIC_CFG1 */
  993. #define RG_PERIODIC_CNT_SET_SFT 15
  994. #define RG_PERIODIC_CNT_SET_MASK 0x1
  995. #define RG_PERIODIC_CNT_SET_MASK_SFT (0x1 << 15)
  996. #define RG_PERIODIC_CNT_PAUSE_SFT 14
  997. #define RG_PERIODIC_CNT_PAUSE_MASK 0x1
  998. #define RG_PERIODIC_CNT_PAUSE_MASK_SFT (0x1 << 14)
  999. #define RG_PERIODIC_CNT_SET_VALUE_SFT 0
  1000. #define RG_PERIODIC_CNT_SET_VALUE_MASK 0x3fff
  1001. #define RG_PERIODIC_CNT_SET_VALUE_MASK_SFT (0x3fff << 0)
  1002. /* MT6358_AFE_VOW_PERIODIC_CFG2 */
  1003. #define AUDPREAMPLON_PERIODIC_MODE_SFT 15
  1004. #define AUDPREAMPLON_PERIODIC_MODE_MASK 0x1
  1005. #define AUDPREAMPLON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1006. #define AUDPREAMPLON_PERIODIC_INVERSE_SFT 14
  1007. #define AUDPREAMPLON_PERIODIC_INVERSE_MASK 0x1
  1008. #define AUDPREAMPLON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1009. #define AUDPREAMPLON_PERIODIC_ON_CYCLE_SFT 0
  1010. #define AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK 0x3fff
  1011. #define AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1012. /* MT6358_AFE_VOW_PERIODIC_CFG3 */
  1013. #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_SFT 15
  1014. #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK 0x1
  1015. #define AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1016. #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_SFT 14
  1017. #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK 0x1
  1018. #define AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1019. #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_SFT 0
  1020. #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK 0x3fff
  1021. #define AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1022. /* MT6358_AFE_VOW_PERIODIC_CFG4 */
  1023. #define AUDADCLPWRUP_PERIODIC_MODE_SFT 15
  1024. #define AUDADCLPWRUP_PERIODIC_MODE_MASK 0x1
  1025. #define AUDADCLPWRUP_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1026. #define AUDADCLPWRUP_PERIODIC_INVERSE_SFT 14
  1027. #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK 0x1
  1028. #define AUDADCLPWRUP_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1029. #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_SFT 0
  1030. #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK 0x3fff
  1031. #define AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1032. /* MT6358_AFE_VOW_PERIODIC_CFG5 */
  1033. #define AUDGLBVOWLPWEN_PERIODIC_MODE_SFT 15
  1034. #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK 0x1
  1035. #define AUDGLBVOWLPWEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1036. #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_SFT 14
  1037. #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK 0x1
  1038. #define AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1039. #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_SFT 0
  1040. #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK 0x3fff
  1041. #define AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1042. /* MT6358_AFE_VOW_PERIODIC_CFG6 */
  1043. #define AUDDIGMICEN_PERIODIC_MODE_SFT 15
  1044. #define AUDDIGMICEN_PERIODIC_MODE_MASK 0x1
  1045. #define AUDDIGMICEN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1046. #define AUDDIGMICEN_PERIODIC_INVERSE_SFT 14
  1047. #define AUDDIGMICEN_PERIODIC_INVERSE_MASK 0x1
  1048. #define AUDDIGMICEN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1049. #define AUDDIGMICEN_PERIODIC_ON_CYCLE_SFT 0
  1050. #define AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK 0x3fff
  1051. #define AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1052. /* MT6358_AFE_VOW_PERIODIC_CFG7 */
  1053. #define AUDPWDBMICBIAS0_PERIODIC_MODE_SFT 15
  1054. #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK 0x1
  1055. #define AUDPWDBMICBIAS0_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1056. #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_SFT 14
  1057. #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK 0x1
  1058. #define AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1059. #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_SFT 0
  1060. #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK 0x3fff
  1061. #define AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1062. /* MT6358_AFE_VOW_PERIODIC_CFG8 */
  1063. #define AUDPWDBMICBIAS1_PERIODIC_MODE_SFT 15
  1064. #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK 0x1
  1065. #define AUDPWDBMICBIAS1_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1066. #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_SFT 14
  1067. #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK 0x1
  1068. #define AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1069. #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_SFT 0
  1070. #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK 0x3fff
  1071. #define AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1072. /* MT6358_AFE_VOW_PERIODIC_CFG9 */
  1073. #define XO_VOW_CK_EN_PERIODIC_MODE_SFT 15
  1074. #define XO_VOW_CK_EN_PERIODIC_MODE_MASK 0x1
  1075. #define XO_VOW_CK_EN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1076. #define XO_VOW_CK_EN_PERIODIC_INVERSE_SFT 14
  1077. #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK 0x1
  1078. #define XO_VOW_CK_EN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1079. #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_SFT 0
  1080. #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_MASK 0x3fff
  1081. #define XO_VOW_CK_EN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1082. /* MT6358_AFE_VOW_PERIODIC_CFG10 */
  1083. #define AUDGLB_PWRDN_PERIODIC_MODE_SFT 15
  1084. #define AUDGLB_PWRDN_PERIODIC_MODE_MASK 0x1
  1085. #define AUDGLB_PWRDN_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1086. #define AUDGLB_PWRDN_PERIODIC_INVERSE_SFT 14
  1087. #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK 0x1
  1088. #define AUDGLB_PWRDN_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1089. #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_SFT 0
  1090. #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK 0x3fff
  1091. #define AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1092. /* MT6358_AFE_VOW_PERIODIC_CFG11 */
  1093. #define VOW_ON_PERIODIC_MODE_SFT 15
  1094. #define VOW_ON_PERIODIC_MODE_MASK 0x1
  1095. #define VOW_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1096. #define VOW_ON_PERIODIC_INVERSE_SFT 14
  1097. #define VOW_ON_PERIODIC_INVERSE_MASK 0x1
  1098. #define VOW_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1099. #define VOW_ON_PERIODIC_ON_CYCLE_SFT 0
  1100. #define VOW_ON_PERIODIC_ON_CYCLE_MASK 0x3fff
  1101. #define VOW_ON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1102. /* MT6358_AFE_VOW_PERIODIC_CFG12 */
  1103. #define DMIC_ON_PERIODIC_MODE_SFT 15
  1104. #define DMIC_ON_PERIODIC_MODE_MASK 0x1
  1105. #define DMIC_ON_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1106. #define DMIC_ON_PERIODIC_INVERSE_SFT 14
  1107. #define DMIC_ON_PERIODIC_INVERSE_MASK 0x1
  1108. #define DMIC_ON_PERIODIC_INVERSE_MASK_SFT (0x1 << 14)
  1109. #define DMIC_ON_PERIODIC_ON_CYCLE_SFT 0
  1110. #define DMIC_ON_PERIODIC_ON_CYCLE_MASK 0x3fff
  1111. #define DMIC_ON_PERIODIC_ON_CYCLE_MASK_SFT (0x3fff << 0)
  1112. /* MT6358_AFE_VOW_PERIODIC_CFG13 */
  1113. #define PDN_VOW_F32K_CK_SFT 15
  1114. #define PDN_VOW_F32K_CK_MASK 0x1
  1115. #define PDN_VOW_F32K_CK_MASK_SFT (0x1 << 15)
  1116. #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_SFT 0
  1117. #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1118. #define AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1119. /* MT6358_AFE_VOW_PERIODIC_CFG14 */
  1120. #define VOW_SNRDET_PERIODIC_CFG_SFT 15
  1121. #define VOW_SNRDET_PERIODIC_CFG_MASK 0x1
  1122. #define VOW_SNRDET_PERIODIC_CFG_MASK_SFT (0x1 << 15)
  1123. #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_SFT 0
  1124. #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1125. #define AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1126. /* MT6358_AFE_VOW_PERIODIC_CFG15 */
  1127. #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_SFT 0
  1128. #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1129. #define AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1130. /* MT6358_AFE_VOW_PERIODIC_CFG16 */
  1131. #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_SFT 0
  1132. #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1133. #define AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1134. /* MT6358_AFE_VOW_PERIODIC_CFG17 */
  1135. #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_SFT 0
  1136. #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1137. #define AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1138. /* MT6358_AFE_VOW_PERIODIC_CFG18 */
  1139. #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_SFT 0
  1140. #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1141. #define AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1142. /* MT6358_AFE_VOW_PERIODIC_CFG19 */
  1143. #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_SFT 0
  1144. #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1145. #define AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1146. /* MT6358_AFE_VOW_PERIODIC_CFG20 */
  1147. #define CLKSQ_EN_VOW_PERIODIC_MODE_SFT 15
  1148. #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK 0x1
  1149. #define CLKSQ_EN_VOW_PERIODIC_MODE_MASK_SFT (0x1 << 15)
  1150. #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_SFT 0
  1151. #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1152. #define XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1153. /* MT6358_AFE_VOW_PERIODIC_CFG21 */
  1154. #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_SFT 0
  1155. #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1156. #define AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1157. /* MT6358_AFE_VOW_PERIODIC_CFG22 */
  1158. #define VOW_ON_PERIODIC_OFF_CYCLE_SFT 0
  1159. #define VOW_ON_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1160. #define VOW_ON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1161. /* MT6358_AFE_VOW_PERIODIC_CFG23 */
  1162. #define DMIC_ON_PERIODIC_OFF_CYCLE_SFT 0
  1163. #define DMIC_ON_PERIODIC_OFF_CYCLE_MASK 0x3fff
  1164. #define DMIC_ON_PERIODIC_OFF_CYCLE_MASK_SFT (0x3fff << 0)
  1165. /* MT6358_AFE_VOW_PERIODIC_MON0 */
  1166. #define VOW_PERIODIC_MON_SFT 0
  1167. #define VOW_PERIODIC_MON_MASK 0xffff
  1168. #define VOW_PERIODIC_MON_MASK_SFT (0xffff << 0)
  1169. /* MT6358_AFE_VOW_PERIODIC_MON1 */
  1170. #define VOW_PERIODIC_COUNT_MON_SFT 0
  1171. #define VOW_PERIODIC_COUNT_MON_MASK 0xffff
  1172. #define VOW_PERIODIC_COUNT_MON_MASK_SFT (0xffff << 0)
  1173. /* MT6358_AUDENC_DSN_ID */
  1174. #define AUDENC_ANA_ID_SFT 0
  1175. #define AUDENC_ANA_ID_MASK 0xff
  1176. #define AUDENC_ANA_ID_MASK_SFT (0xff << 0)
  1177. #define AUDENC_DIG_ID_SFT 8
  1178. #define AUDENC_DIG_ID_MASK 0xff
  1179. #define AUDENC_DIG_ID_MASK_SFT (0xff << 8)
  1180. /* MT6358_AUDENC_DSN_REV0 */
  1181. #define AUDENC_ANA_MINOR_REV_SFT 0
  1182. #define AUDENC_ANA_MINOR_REV_MASK 0xf
  1183. #define AUDENC_ANA_MINOR_REV_MASK_SFT (0xf << 0)
  1184. #define AUDENC_ANA_MAJOR_REV_SFT 4
  1185. #define AUDENC_ANA_MAJOR_REV_MASK 0xf
  1186. #define AUDENC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
  1187. #define AUDENC_DIG_MINOR_REV_SFT 8
  1188. #define AUDENC_DIG_MINOR_REV_MASK 0xf
  1189. #define AUDENC_DIG_MINOR_REV_MASK_SFT (0xf << 8)
  1190. #define AUDENC_DIG_MAJOR_REV_SFT 12
  1191. #define AUDENC_DIG_MAJOR_REV_MASK 0xf
  1192. #define AUDENC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
  1193. /* MT6358_AUDENC_DSN_DBI */
  1194. #define AUDENC_DSN_CBS_SFT 0
  1195. #define AUDENC_DSN_CBS_MASK 0x3
  1196. #define AUDENC_DSN_CBS_MASK_SFT (0x3 << 0)
  1197. #define AUDENC_DSN_BIX_SFT 2
  1198. #define AUDENC_DSN_BIX_MASK 0x3
  1199. #define AUDENC_DSN_BIX_MASK_SFT (0x3 << 2)
  1200. #define AUDENC_DSN_ESP_SFT 8
  1201. #define AUDENC_DSN_ESP_MASK 0xff
  1202. #define AUDENC_DSN_ESP_MASK_SFT (0xff << 8)
  1203. /* MT6358_AUDENC_DSN_FPI */
  1204. #define AUDENC_DSN_FPI_SFT 0
  1205. #define AUDENC_DSN_FPI_MASK 0xff
  1206. #define AUDENC_DSN_FPI_MASK_SFT (0xff << 0)
  1207. /* MT6358_AUDENC_ANA_CON0 */
  1208. #define RG_AUDPREAMPLON_SFT 0
  1209. #define RG_AUDPREAMPLON_MASK 0x1
  1210. #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
  1211. #define RG_AUDPREAMPLDCCEN_SFT 1
  1212. #define RG_AUDPREAMPLDCCEN_MASK 0x1
  1213. #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
  1214. #define RG_AUDPREAMPLDCPRECHARGE_SFT 2
  1215. #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
  1216. #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
  1217. #define RG_AUDPREAMPLPGATEST_SFT 3
  1218. #define RG_AUDPREAMPLPGATEST_MASK 0x1
  1219. #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
  1220. #define RG_AUDPREAMPLVSCALE_SFT 4
  1221. #define RG_AUDPREAMPLVSCALE_MASK 0x3
  1222. #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
  1223. #define RG_AUDPREAMPLINPUTSEL_SFT 6
  1224. #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
  1225. #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
  1226. #define RG_AUDPREAMPLGAIN_SFT 8
  1227. #define RG_AUDPREAMPLGAIN_MASK 0x7
  1228. #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
  1229. #define RG_AUDADCLPWRUP_SFT 12
  1230. #define RG_AUDADCLPWRUP_MASK 0x1
  1231. #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
  1232. #define RG_AUDADCLINPUTSEL_SFT 13
  1233. #define RG_AUDADCLINPUTSEL_MASK 0x3
  1234. #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
  1235. /* MT6358_AUDENC_ANA_CON1 */
  1236. #define RG_AUDPREAMPRON_SFT 0
  1237. #define RG_AUDPREAMPRON_MASK 0x1
  1238. #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
  1239. #define RG_AUDPREAMPRDCCEN_SFT 1
  1240. #define RG_AUDPREAMPRDCCEN_MASK 0x1
  1241. #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
  1242. #define RG_AUDPREAMPRDCPRECHARGE_SFT 2
  1243. #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
  1244. #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
  1245. #define RG_AUDPREAMPRPGATEST_SFT 3
  1246. #define RG_AUDPREAMPRPGATEST_MASK 0x1
  1247. #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
  1248. #define RG_AUDPREAMPRVSCALE_SFT 4
  1249. #define RG_AUDPREAMPRVSCALE_MASK 0x3
  1250. #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
  1251. #define RG_AUDPREAMPRINPUTSEL_SFT 6
  1252. #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
  1253. #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
  1254. #define RG_AUDPREAMPRGAIN_SFT 8
  1255. #define RG_AUDPREAMPRGAIN_MASK 0x7
  1256. #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
  1257. #define RG_AUDIO_VOW_EN_SFT 11
  1258. #define RG_AUDIO_VOW_EN_MASK 0x1
  1259. #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 11)
  1260. #define RG_AUDADCRPWRUP_SFT 12
  1261. #define RG_AUDADCRPWRUP_MASK 0x1
  1262. #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
  1263. #define RG_AUDADCRINPUTSEL_SFT 13
  1264. #define RG_AUDADCRINPUTSEL_MASK 0x3
  1265. #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
  1266. #define RG_CLKSQ_EN_VOW_SFT 15
  1267. #define RG_CLKSQ_EN_VOW_MASK 0x1
  1268. #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 15)
  1269. /* MT6358_AUDENC_ANA_CON2 */
  1270. #define RG_AUDULHALFBIAS_SFT 0
  1271. #define RG_AUDULHALFBIAS_MASK 0x1
  1272. #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
  1273. #define RG_AUDGLBVOWLPWEN_SFT 1
  1274. #define RG_AUDGLBVOWLPWEN_MASK 0x1
  1275. #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
  1276. #define RG_AUDPREAMPLPEN_SFT 2
  1277. #define RG_AUDPREAMPLPEN_MASK 0x1
  1278. #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
  1279. #define RG_AUDADC1STSTAGELPEN_SFT 3
  1280. #define RG_AUDADC1STSTAGELPEN_MASK 0x1
  1281. #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
  1282. #define RG_AUDADC2NDSTAGELPEN_SFT 4
  1283. #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
  1284. #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
  1285. #define RG_AUDADCFLASHLPEN_SFT 5
  1286. #define RG_AUDADCFLASHLPEN_MASK 0x1
  1287. #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
  1288. #define RG_AUDPREAMPIDDTEST_SFT 6
  1289. #define RG_AUDPREAMPIDDTEST_MASK 0x3
  1290. #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
  1291. #define RG_AUDADC1STSTAGEIDDTEST_SFT 8
  1292. #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
  1293. #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
  1294. #define RG_AUDADC2NDSTAGEIDDTEST_SFT 10
  1295. #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
  1296. #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
  1297. #define RG_AUDADCREFBUFIDDTEST_SFT 12
  1298. #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
  1299. #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
  1300. #define RG_AUDADCFLASHIDDTEST_SFT 14
  1301. #define RG_AUDADCFLASHIDDTEST_MASK 0x3
  1302. #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
  1303. /* MT6358_AUDENC_ANA_CON3 */
  1304. #define RG_AUDADCDAC0P25FS_SFT 0
  1305. #define RG_AUDADCDAC0P25FS_MASK 0x1
  1306. #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 0)
  1307. #define RG_AUDADCCLKSEL_SFT 1
  1308. #define RG_AUDADCCLKSEL_MASK 0x1
  1309. #define RG_AUDADCCLKSEL_MASK_SFT (0x1 << 1)
  1310. #define RG_AUDADCCLKSOURCE_SFT 2
  1311. #define RG_AUDADCCLKSOURCE_MASK 0x3
  1312. #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 2)
  1313. #define RG_AUDPREAMPAAFEN_SFT 8
  1314. #define RG_AUDPREAMPAAFEN_MASK 0x1
  1315. #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
  1316. #define RG_DCCVCMBUFLPMODSEL_SFT 9
  1317. #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
  1318. #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
  1319. #define RG_DCCVCMBUFLPSWEN_SFT 10
  1320. #define RG_DCCVCMBUFLPSWEN_MASK 0x1
  1321. #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
  1322. #define RG_CMSTBENH_SFT 11
  1323. #define RG_CMSTBENH_MASK 0x1
  1324. #define RG_CMSTBENH_MASK_SFT (0x1 << 11)
  1325. #define RG_PGABODYSW_SFT 12
  1326. #define RG_PGABODYSW_MASK 0x1
  1327. #define RG_PGABODYSW_MASK_SFT (0x1 << 12)
  1328. /* MT6358_AUDENC_ANA_CON4 */
  1329. #define RG_AUDADC1STSTAGESDENB_SFT 0
  1330. #define RG_AUDADC1STSTAGESDENB_MASK 0x1
  1331. #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
  1332. #define RG_AUDADC2NDSTAGERESET_SFT 1
  1333. #define RG_AUDADC2NDSTAGERESET_MASK 0x1
  1334. #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
  1335. #define RG_AUDADC3RDSTAGERESET_SFT 2
  1336. #define RG_AUDADC3RDSTAGERESET_MASK 0x1
  1337. #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
  1338. #define RG_AUDADCFSRESET_SFT 3
  1339. #define RG_AUDADCFSRESET_MASK 0x1
  1340. #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
  1341. #define RG_AUDADCWIDECM_SFT 4
  1342. #define RG_AUDADCWIDECM_MASK 0x1
  1343. #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
  1344. #define RG_AUDADCNOPATEST_SFT 5
  1345. #define RG_AUDADCNOPATEST_MASK 0x1
  1346. #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
  1347. #define RG_AUDADCBYPASS_SFT 6
  1348. #define RG_AUDADCBYPASS_MASK 0x1
  1349. #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
  1350. #define RG_AUDADCFFBYPASS_SFT 7
  1351. #define RG_AUDADCFFBYPASS_MASK 0x1
  1352. #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
  1353. #define RG_AUDADCDACFBCURRENT_SFT 8
  1354. #define RG_AUDADCDACFBCURRENT_MASK 0x1
  1355. #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
  1356. #define RG_AUDADCDACIDDTEST_SFT 9
  1357. #define RG_AUDADCDACIDDTEST_MASK 0x3
  1358. #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
  1359. #define RG_AUDADCDACNRZ_SFT 11
  1360. #define RG_AUDADCDACNRZ_MASK 0x1
  1361. #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
  1362. #define RG_AUDADCNODEM_SFT 12
  1363. #define RG_AUDADCNODEM_MASK 0x1
  1364. #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
  1365. #define RG_AUDADCDACTEST_SFT 13
  1366. #define RG_AUDADCDACTEST_MASK 0x1
  1367. #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
  1368. /* MT6358_AUDENC_ANA_CON5 */
  1369. #define RG_AUDRCTUNEL_SFT 0
  1370. #define RG_AUDRCTUNEL_MASK 0x1f
  1371. #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)
  1372. #define RG_AUDRCTUNELSEL_SFT 5
  1373. #define RG_AUDRCTUNELSEL_MASK 0x1
  1374. #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
  1375. #define RG_AUDRCTUNER_SFT 8
  1376. #define RG_AUDRCTUNER_MASK 0x1f
  1377. #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)
  1378. #define RG_AUDRCTUNERSEL_SFT 13
  1379. #define RG_AUDRCTUNERSEL_MASK 0x1
  1380. #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
  1381. /* MT6358_AUDENC_ANA_CON6 */
  1382. #define RG_CLKSQ_EN_SFT 0
  1383. #define RG_CLKSQ_EN_MASK 0x1
  1384. #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
  1385. #define RG_CLKSQ_IN_SEL_TEST_SFT 1
  1386. #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
  1387. #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
  1388. #define RG_CM_REFGENSEL_SFT 2
  1389. #define RG_CM_REFGENSEL_MASK 0x1
  1390. #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
  1391. #define RG_AUDSPARE_SFT 4
  1392. #define RG_AUDSPARE_MASK 0xf
  1393. #define RG_AUDSPARE_MASK_SFT (0xf << 4)
  1394. #define RG_AUDENCSPARE_SFT 8
  1395. #define RG_AUDENCSPARE_MASK 0x3f
  1396. #define RG_AUDENCSPARE_MASK_SFT (0x3f << 8)
  1397. /* MT6358_AUDENC_ANA_CON7 */
  1398. #define RG_AUDENCSPARE2_SFT 0
  1399. #define RG_AUDENCSPARE2_MASK 0xff
  1400. #define RG_AUDENCSPARE2_MASK_SFT (0xff << 0)
  1401. /* MT6358_AUDENC_ANA_CON8 */
  1402. #define RG_AUDDIGMICEN_SFT 0
  1403. #define RG_AUDDIGMICEN_MASK 0x1
  1404. #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
  1405. #define RG_AUDDIGMICBIAS_SFT 1
  1406. #define RG_AUDDIGMICBIAS_MASK 0x3
  1407. #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
  1408. #define RG_DMICHPCLKEN_SFT 3
  1409. #define RG_DMICHPCLKEN_MASK 0x1
  1410. #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
  1411. #define RG_AUDDIGMICPDUTY_SFT 4
  1412. #define RG_AUDDIGMICPDUTY_MASK 0x3
  1413. #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
  1414. #define RG_AUDDIGMICNDUTY_SFT 6
  1415. #define RG_AUDDIGMICNDUTY_MASK 0x3
  1416. #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
  1417. #define RG_DMICMONEN_SFT 8
  1418. #define RG_DMICMONEN_MASK 0x1
  1419. #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
  1420. #define RG_DMICMONSEL_SFT 9
  1421. #define RG_DMICMONSEL_MASK 0x7
  1422. #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
  1423. #define RG_AUDSPAREVMIC_SFT 12
  1424. #define RG_AUDSPAREVMIC_MASK 0xf
  1425. #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)
  1426. /* MT6358_AUDENC_ANA_CON9 */
  1427. #define RG_AUDPWDBMICBIAS0_SFT 0
  1428. #define RG_AUDPWDBMICBIAS0_MASK 0x1
  1429. #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
  1430. #define RG_AUDMICBIAS0BYPASSEN_SFT 1
  1431. #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
  1432. #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
  1433. #define RG_AUDMICBIAS0LOWPEN_SFT 2
  1434. #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
  1435. #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
  1436. #define RG_AUDMICBIAS0VREF_SFT 4
  1437. #define RG_AUDMICBIAS0VREF_MASK 0x7
  1438. #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
  1439. #define RG_AUDMICBIAS0DCSW0P1EN_SFT 8
  1440. #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
  1441. #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
  1442. #define RG_AUDMICBIAS0DCSW0P2EN_SFT 9
  1443. #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
  1444. #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
  1445. #define RG_AUDMICBIAS0DCSW0NEN_SFT 10
  1446. #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
  1447. #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
  1448. #define RG_AUDMICBIAS0DCSW2P1EN_SFT 12
  1449. #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
  1450. #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
  1451. #define RG_AUDMICBIAS0DCSW2P2EN_SFT 13
  1452. #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
  1453. #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
  1454. #define RG_AUDMICBIAS0DCSW2NEN_SFT 14
  1455. #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
  1456. #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
  1457. /* MT6358_AUDENC_ANA_CON10 */
  1458. #define RG_AUDPWDBMICBIAS1_SFT 0
  1459. #define RG_AUDPWDBMICBIAS1_MASK 0x1
  1460. #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
  1461. #define RG_AUDMICBIAS1BYPASSEN_SFT 1
  1462. #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
  1463. #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
  1464. #define RG_AUDMICBIAS1LOWPEN_SFT 2
  1465. #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
  1466. #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
  1467. #define RG_AUDMICBIAS1VREF_SFT 4
  1468. #define RG_AUDMICBIAS1VREF_MASK 0x7
  1469. #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
  1470. #define RG_AUDMICBIAS1DCSW1PEN_SFT 8
  1471. #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
  1472. #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
  1473. #define RG_AUDMICBIAS1DCSW1NEN_SFT 9
  1474. #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
  1475. #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
  1476. #define RG_BANDGAPGEN_SFT 12
  1477. #define RG_BANDGAPGEN_MASK 0x1
  1478. #define RG_BANDGAPGEN_MASK_SFT (0x1 << 12)
  1479. #define RG_MTEST_EN_SFT 13
  1480. #define RG_MTEST_EN_MASK 0x1
  1481. #define RG_MTEST_EN_MASK_SFT (0x1 << 13)
  1482. #define RG_MTEST_SEL_SFT 14
  1483. #define RG_MTEST_SEL_MASK 0x1
  1484. #define RG_MTEST_SEL_MASK_SFT (0x1 << 14)
  1485. #define RG_MTEST_CURRENT_SFT 15
  1486. #define RG_MTEST_CURRENT_MASK 0x1
  1487. #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 15)
  1488. /* MT6358_AUDENC_ANA_CON11 */
  1489. #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
  1490. #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
  1491. #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
  1492. #define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1
  1493. #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
  1494. #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
  1495. #define RG_AUDACCDETVIN1PULLLOW_SFT 2
  1496. #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
  1497. #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 2)
  1498. #define RG_AUDACCDETVTHACAL_SFT 4
  1499. #define RG_AUDACCDETVTHACAL_MASK 0x1
  1500. #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
  1501. #define RG_AUDACCDETVTHBCAL_SFT 5
  1502. #define RG_AUDACCDETVTHBCAL_MASK 0x1
  1503. #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
  1504. #define RG_AUDACCDETTVDET_SFT 6
  1505. #define RG_AUDACCDETTVDET_MASK 0x1
  1506. #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
  1507. #define RG_ACCDETSEL_SFT 7
  1508. #define RG_ACCDETSEL_MASK 0x1
  1509. #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
  1510. #define RG_SWBUFMODSEL_SFT 8
  1511. #define RG_SWBUFMODSEL_MASK 0x1
  1512. #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
  1513. #define RG_SWBUFSWEN_SFT 9
  1514. #define RG_SWBUFSWEN_MASK 0x1
  1515. #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
  1516. #define RG_EINTCOMPVTH_SFT 10
  1517. #define RG_EINTCOMPVTH_MASK 0x1
  1518. #define RG_EINTCOMPVTH_MASK_SFT (0x1 << 10)
  1519. #define RG_EINTCONFIGACCDET_SFT 11
  1520. #define RG_EINTCONFIGACCDET_MASK 0x1
  1521. #define RG_EINTCONFIGACCDET_MASK_SFT (0x1 << 11)
  1522. #define RG_EINTHIRENB_SFT 12
  1523. #define RG_EINTHIRENB_MASK 0x1
  1524. #define RG_EINTHIRENB_MASK_SFT (0x1 << 12)
  1525. #define RG_ACCDET2AUXRESBYPASS_SFT 13
  1526. #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
  1527. #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
  1528. #define RG_ACCDET2AUXBUFFERBYPASS_SFT 14
  1529. #define RG_ACCDET2AUXBUFFERBYPASS_MASK 0x1
  1530. #define RG_ACCDET2AUXBUFFERBYPASS_MASK_SFT (0x1 << 14)
  1531. #define RG_ACCDET2AUXSWEN_SFT 15
  1532. #define RG_ACCDET2AUXSWEN_MASK 0x1
  1533. #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 15)
  1534. /* MT6358_AUDENC_ANA_CON12 */
  1535. #define RGS_AUDRCTUNELREAD_SFT 0
  1536. #define RGS_AUDRCTUNELREAD_MASK 0x1f
  1537. #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)
  1538. #define RGS_AUDRCTUNERREAD_SFT 8
  1539. #define RGS_AUDRCTUNERREAD_MASK 0x1f
  1540. #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)
  1541. /* MT6358_AUDDEC_DSN_ID */
  1542. #define AUDDEC_ANA_ID_SFT 0
  1543. #define AUDDEC_ANA_ID_MASK 0xff
  1544. #define AUDDEC_ANA_ID_MASK_SFT (0xff << 0)
  1545. #define AUDDEC_DIG_ID_SFT 8
  1546. #define AUDDEC_DIG_ID_MASK 0xff
  1547. #define AUDDEC_DIG_ID_MASK_SFT (0xff << 8)
  1548. /* MT6358_AUDDEC_DSN_REV0 */
  1549. #define AUDDEC_ANA_MINOR_REV_SFT 0
  1550. #define AUDDEC_ANA_MINOR_REV_MASK 0xf
  1551. #define AUDDEC_ANA_MINOR_REV_MASK_SFT (0xf << 0)
  1552. #define AUDDEC_ANA_MAJOR_REV_SFT 4
  1553. #define AUDDEC_ANA_MAJOR_REV_MASK 0xf
  1554. #define AUDDEC_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
  1555. #define AUDDEC_DIG_MINOR_REV_SFT 8
  1556. #define AUDDEC_DIG_MINOR_REV_MASK 0xf
  1557. #define AUDDEC_DIG_MINOR_REV_MASK_SFT (0xf << 8)
  1558. #define AUDDEC_DIG_MAJOR_REV_SFT 12
  1559. #define AUDDEC_DIG_MAJOR_REV_MASK 0xf
  1560. #define AUDDEC_DIG_MAJOR_REV_MASK_SFT (0xf << 12)
  1561. /* MT6358_AUDDEC_DSN_DBI */
  1562. #define AUDDEC_DSN_CBS_SFT 0
  1563. #define AUDDEC_DSN_CBS_MASK 0x3
  1564. #define AUDDEC_DSN_CBS_MASK_SFT (0x3 << 0)
  1565. #define AUDDEC_DSN_BIX_SFT 2
  1566. #define AUDDEC_DSN_BIX_MASK 0x3
  1567. #define AUDDEC_DSN_BIX_MASK_SFT (0x3 << 2)
  1568. #define AUDDEC_DSN_ESP_SFT 8
  1569. #define AUDDEC_DSN_ESP_MASK 0xff
  1570. #define AUDDEC_DSN_ESP_MASK_SFT (0xff << 8)
  1571. /* MT6358_AUDDEC_DSN_FPI */
  1572. #define AUDDEC_DSN_FPI_SFT 0
  1573. #define AUDDEC_DSN_FPI_MASK 0xff
  1574. #define AUDDEC_DSN_FPI_MASK_SFT (0xff << 0)
  1575. /* MT6358_AUDDEC_ANA_CON0 */
  1576. #define RG_AUDDACLPWRUP_VAUDP15_SFT 0
  1577. #define RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
  1578. #define RG_AUDDACLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
  1579. #define RG_AUDDACRPWRUP_VAUDP15_SFT 1
  1580. #define RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
  1581. #define RG_AUDDACRPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
  1582. #define RG_AUD_DAC_PWR_UP_VA28_SFT 2
  1583. #define RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
  1584. #define RG_AUD_DAC_PWR_UP_VA28_MASK_SFT (0x1 << 2)
  1585. #define RG_AUD_DAC_PWL_UP_VA28_SFT 3
  1586. #define RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
  1587. #define RG_AUD_DAC_PWL_UP_VA28_MASK_SFT (0x1 << 3)
  1588. #define RG_AUDHPLPWRUP_VAUDP15_SFT 4
  1589. #define RG_AUDHPLPWRUP_VAUDP15_MASK 0x1
  1590. #define RG_AUDHPLPWRUP_VAUDP15_MASK_SFT (0x1 << 4)
  1591. #define RG_AUDHPRPWRUP_VAUDP15_SFT 5
  1592. #define RG_AUDHPRPWRUP_VAUDP15_MASK 0x1
  1593. #define RG_AUDHPRPWRUP_VAUDP15_MASK_SFT (0x1 << 5)
  1594. #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_SFT 6
  1595. #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK 0x1
  1596. #define RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 6)
  1597. #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_SFT 7
  1598. #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK 0x1
  1599. #define RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 7)
  1600. #define RG_AUDHPLMUXINPUTSEL_VAUDP15_SFT 8
  1601. #define RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK 0x3
  1602. #define RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 8)
  1603. #define RG_AUDHPRMUXINPUTSEL_VAUDP15_SFT 10
  1604. #define RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK 0x3
  1605. #define RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 10)
  1606. #define RG_AUDHPLSCDISABLE_VAUDP15_SFT 12
  1607. #define RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1
  1608. #define RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 12)
  1609. #define RG_AUDHPRSCDISABLE_VAUDP15_SFT 13
  1610. #define RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1
  1611. #define RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT (0x1 << 13)
  1612. #define RG_AUDHPLBSCCURRENT_VAUDP15_SFT 14
  1613. #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
  1614. #define RG_AUDHPLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 14)
  1615. #define RG_AUDHPRBSCCURRENT_VAUDP15_SFT 15
  1616. #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
  1617. #define RG_AUDHPRBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 15)
  1618. /* MT6358_AUDDEC_ANA_CON1 */
  1619. #define RG_AUDHPLOUTPWRUP_VAUDP15_SFT 0
  1620. #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK 0x1
  1621. #define RG_AUDHPLOUTPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
  1622. #define RG_AUDHPROUTPWRUP_VAUDP15_SFT 1
  1623. #define RG_AUDHPROUTPWRUP_VAUDP15_MASK 0x1
  1624. #define RG_AUDHPROUTPWRUP_VAUDP15_MASK_SFT (0x1 << 1)
  1625. #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_SFT 2
  1626. #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK 0x1
  1627. #define RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 2)
  1628. #define RG_AUDHPROUTAUXPWRUP_VAUDP15_SFT 3
  1629. #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK 0x1
  1630. #define RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK_SFT (0x1 << 3)
  1631. #define RG_HPLAUXFBRSW_EN_VAUDP15_SFT 4
  1632. #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK 0x1
  1633. #define RG_HPLAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 4)
  1634. #define RG_HPRAUXFBRSW_EN_VAUDP15_SFT 5
  1635. #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK 0x1
  1636. #define RG_HPRAUXFBRSW_EN_VAUDP15_MASK_SFT (0x1 << 5)
  1637. #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_SFT 6
  1638. #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK 0x1
  1639. #define RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK_SFT (0x1 << 6)
  1640. #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_SFT 7
  1641. #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK 0x1
  1642. #define RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK_SFT (0x1 << 7)
  1643. #define RG_HPLOUTSTGCTRL_VAUDP15_SFT 8
  1644. #define RG_HPLOUTSTGCTRL_VAUDP15_MASK 0x7
  1645. #define RG_HPLOUTSTGCTRL_VAUDP15_MASK_SFT (0x7 << 8)
  1646. #define RG_HPROUTSTGCTRL_VAUDP15_SFT 11
  1647. #define RG_HPROUTSTGCTRL_VAUDP15_MASK 0x7
  1648. #define RG_HPROUTSTGCTRL_VAUDP15_MASK_SFT (0x7 << 11)
  1649. /* MT6358_AUDDEC_ANA_CON2 */
  1650. #define RG_HPLOUTPUTSTBENH_VAUDP15_SFT 0
  1651. #define RG_HPLOUTPUTSTBENH_VAUDP15_MASK 0x7
  1652. #define RG_HPLOUTPUTSTBENH_VAUDP15_MASK_SFT (0x7 << 0)
  1653. #define RG_HPROUTPUTSTBENH_VAUDP15_SFT 4
  1654. #define RG_HPROUTPUTSTBENH_VAUDP15_MASK 0x7
  1655. #define RG_HPROUTPUTSTBENH_VAUDP15_MASK_SFT (0x7 << 4)
  1656. #define RG_AUDHPSTARTUP_VAUDP15_SFT 13
  1657. #define RG_AUDHPSTARTUP_VAUDP15_MASK 0x1
  1658. #define RG_AUDHPSTARTUP_VAUDP15_MASK_SFT (0x1 << 13)
  1659. #define RG_AUDREFN_DERES_EN_VAUDP15_SFT 14
  1660. #define RG_AUDREFN_DERES_EN_VAUDP15_MASK 0x1
  1661. #define RG_AUDREFN_DERES_EN_VAUDP15_MASK_SFT (0x1 << 14)
  1662. #define RG_HPPSHORT2VCM_VAUDP15_SFT 15
  1663. #define RG_HPPSHORT2VCM_VAUDP15_MASK 0x1
  1664. #define RG_HPPSHORT2VCM_VAUDP15_MASK_SFT (0x1 << 15)
  1665. /* MT6358_AUDDEC_ANA_CON3 */
  1666. #define RG_HPINPUTSTBENH_VAUDP15_SFT 13
  1667. #define RG_HPINPUTSTBENH_VAUDP15_MASK 0x1
  1668. #define RG_HPINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 13)
  1669. #define RG_HPINPUTRESET0_VAUDP15_SFT 14
  1670. #define RG_HPINPUTRESET0_VAUDP15_MASK 0x1
  1671. #define RG_HPINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 14)
  1672. #define RG_HPOUTPUTRESET0_VAUDP15_SFT 15
  1673. #define RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
  1674. #define RG_HPOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 15)
  1675. /* MT6358_AUDDEC_ANA_CON4 */
  1676. #define RG_ABIDEC_RSVD0_VAUDP28_SFT 0
  1677. #define RG_ABIDEC_RSVD0_VAUDP28_MASK 0xff
  1678. #define RG_ABIDEC_RSVD0_VAUDP28_MASK_SFT (0xff << 0)
  1679. /* MT6358_AUDDEC_ANA_CON5 */
  1680. #define RG_AUDHPDECMGAINADJ_VAUDP15_SFT 0
  1681. #define RG_AUDHPDECMGAINADJ_VAUDP15_MASK 0x7
  1682. #define RG_AUDHPDECMGAINADJ_VAUDP15_MASK_SFT (0x7 << 0)
  1683. #define RG_AUDHPDEDMGAINADJ_VAUDP15_SFT 4
  1684. #define RG_AUDHPDEDMGAINADJ_VAUDP15_MASK 0x7
  1685. #define RG_AUDHPDEDMGAINADJ_VAUDP15_MASK_SFT (0x7 << 4)
  1686. /* MT6358_AUDDEC_ANA_CON6 */
  1687. #define RG_AUDHSPWRUP_VAUDP15_SFT 0
  1688. #define RG_AUDHSPWRUP_VAUDP15_MASK 0x1
  1689. #define RG_AUDHSPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
  1690. #define RG_AUDHSPWRUP_IBIAS_VAUDP15_SFT 1
  1691. #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1
  1692. #define RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
  1693. #define RG_AUDHSMUXINPUTSEL_VAUDP15_SFT 2
  1694. #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
  1695. #define RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)
  1696. #define RG_AUDHSSCDISABLE_VAUDP15_SFT 4
  1697. #define RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
  1698. #define RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
  1699. #define RG_AUDHSBSCCURRENT_VAUDP15_SFT 5
  1700. #define RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
  1701. #define RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
  1702. #define RG_AUDHSSTARTUP_VAUDP15_SFT 6
  1703. #define RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
  1704. #define RG_AUDHSSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
  1705. #define RG_HSOUTPUTSTBENH_VAUDP15_SFT 7
  1706. #define RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
  1707. #define RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
  1708. #define RG_HSINPUTSTBENH_VAUDP15_SFT 8
  1709. #define RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
  1710. #define RG_HSINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
  1711. #define RG_HSINPUTRESET0_VAUDP15_SFT 9
  1712. #define RG_HSINPUTRESET0_VAUDP15_MASK 0x1
  1713. #define RG_HSINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
  1714. #define RG_HSOUTPUTRESET0_VAUDP15_SFT 10
  1715. #define RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
  1716. #define RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
  1717. #define RG_HSOUT_SHORTVCM_VAUDP15_SFT 11
  1718. #define RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
  1719. #define RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
  1720. /* MT6358_AUDDEC_ANA_CON7 */
  1721. #define RG_AUDLOLPWRUP_VAUDP15_SFT 0
  1722. #define RG_AUDLOLPWRUP_VAUDP15_MASK 0x1
  1723. #define RG_AUDLOLPWRUP_VAUDP15_MASK_SFT (0x1 << 0)
  1724. #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_SFT 1
  1725. #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK 0x1
  1726. #define RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT (0x1 << 1)
  1727. #define RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT 2
  1728. #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK 0x3
  1729. #define RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK_SFT (0x3 << 2)
  1730. #define RG_AUDLOLSCDISABLE_VAUDP15_SFT 4
  1731. #define RG_AUDLOLSCDISABLE_VAUDP15_MASK 0x1
  1732. #define RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT (0x1 << 4)
  1733. #define RG_AUDLOLBSCCURRENT_VAUDP15_SFT 5
  1734. #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1
  1735. #define RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT (0x1 << 5)
  1736. #define RG_AUDLOSTARTUP_VAUDP15_SFT 6
  1737. #define RG_AUDLOSTARTUP_VAUDP15_MASK 0x1
  1738. #define RG_AUDLOSTARTUP_VAUDP15_MASK_SFT (0x1 << 6)
  1739. #define RG_LOINPUTSTBENH_VAUDP15_SFT 7
  1740. #define RG_LOINPUTSTBENH_VAUDP15_MASK 0x1
  1741. #define RG_LOINPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 7)
  1742. #define RG_LOOUTPUTSTBENH_VAUDP15_SFT 8
  1743. #define RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1
  1744. #define RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT (0x1 << 8)
  1745. #define RG_LOINPUTRESET0_VAUDP15_SFT 9
  1746. #define RG_LOINPUTRESET0_VAUDP15_MASK 0x1
  1747. #define RG_LOINPUTRESET0_VAUDP15_MASK_SFT (0x1 << 9)
  1748. #define RG_LOOUTPUTRESET0_VAUDP15_SFT 10
  1749. #define RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1
  1750. #define RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT (0x1 << 10)
  1751. #define RG_LOOUT_SHORTVCM_VAUDP15_SFT 11
  1752. #define RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1
  1753. #define RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT (0x1 << 11)
  1754. /* MT6358_AUDDEC_ANA_CON8 */
  1755. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SFT 0
  1756. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xf
  1757. #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK_SFT (0xf << 0)
  1758. #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_SFT 4
  1759. #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3
  1760. #define RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK_SFT (0x3 << 4)
  1761. #define RG_AUDTRIMBUF_EN_VAUDP15_SFT 6
  1762. #define RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
  1763. #define RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT (0x1 << 6)
  1764. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SFT 8
  1765. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3
  1766. #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 8)
  1767. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SFT 10
  1768. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3
  1769. #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK_SFT (0x3 << 10)
  1770. #define RG_AUDHPSPKDET_EN_VAUDP15_SFT 12
  1771. #define RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
  1772. #define RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT (0x1 << 12)
  1773. /* MT6358_AUDDEC_ANA_CON9 */
  1774. #define RG_ABIDEC_RSVD0_VA28_SFT 0
  1775. #define RG_ABIDEC_RSVD0_VA28_MASK 0xff
  1776. #define RG_ABIDEC_RSVD0_VA28_MASK_SFT (0xff << 0)
  1777. #define RG_ABIDEC_RSVD0_VAUDP15_SFT 8
  1778. #define RG_ABIDEC_RSVD0_VAUDP15_MASK 0xff
  1779. #define RG_ABIDEC_RSVD0_VAUDP15_MASK_SFT (0xff << 8)
  1780. /* MT6358_AUDDEC_ANA_CON10 */
  1781. #define RG_ABIDEC_RSVD1_VAUDP15_SFT 0
  1782. #define RG_ABIDEC_RSVD1_VAUDP15_MASK 0xff
  1783. #define RG_ABIDEC_RSVD1_VAUDP15_MASK_SFT (0xff << 0)
  1784. #define RG_ABIDEC_RSVD2_VAUDP15_SFT 8
  1785. #define RG_ABIDEC_RSVD2_VAUDP15_MASK 0xff
  1786. #define RG_ABIDEC_RSVD2_VAUDP15_MASK_SFT (0xff << 8)
  1787. /* MT6358_AUDDEC_ANA_CON11 */
  1788. #define RG_AUDZCDMUXSEL_VAUDP15_SFT 0
  1789. #define RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7
  1790. #define RG_AUDZCDMUXSEL_VAUDP15_MASK_SFT (0x7 << 0)
  1791. #define RG_AUDZCDCLKSEL_VAUDP15_SFT 3
  1792. #define RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
  1793. #define RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT (0x1 << 3)
  1794. #define RG_AUDBIASADJ_0_VAUDP15_SFT 7
  1795. #define RG_AUDBIASADJ_0_VAUDP15_MASK 0x1ff
  1796. #define RG_AUDBIASADJ_0_VAUDP15_MASK_SFT (0x1ff << 7)
  1797. /* MT6358_AUDDEC_ANA_CON12 */
  1798. #define RG_AUDBIASADJ_1_VAUDP15_SFT 0
  1799. #define RG_AUDBIASADJ_1_VAUDP15_MASK 0xff
  1800. #define RG_AUDBIASADJ_1_VAUDP15_MASK_SFT (0xff << 0)
  1801. #define RG_AUDIBIASPWRDN_VAUDP15_SFT 8
  1802. #define RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
  1803. #define RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT (0x1 << 8)
  1804. /* MT6358_AUDDEC_ANA_CON13 */
  1805. #define RG_RSTB_DECODER_VA28_SFT 0
  1806. #define RG_RSTB_DECODER_VA28_MASK 0x1
  1807. #define RG_RSTB_DECODER_VA28_MASK_SFT (0x1 << 0)
  1808. #define RG_SEL_DECODER_96K_VA28_SFT 1
  1809. #define RG_SEL_DECODER_96K_VA28_MASK 0x1
  1810. #define RG_SEL_DECODER_96K_VA28_MASK_SFT (0x1 << 1)
  1811. #define RG_SEL_DELAY_VCORE_SFT 2
  1812. #define RG_SEL_DELAY_VCORE_MASK 0x1
  1813. #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
  1814. #define RG_AUDGLB_PWRDN_VA28_SFT 4
  1815. #define RG_AUDGLB_PWRDN_VA28_MASK 0x1
  1816. #define RG_AUDGLB_PWRDN_VA28_MASK_SFT (0x1 << 4)
  1817. #define RG_RSTB_ENCODER_VA28_SFT 5
  1818. #define RG_RSTB_ENCODER_VA28_MASK 0x1
  1819. #define RG_RSTB_ENCODER_VA28_MASK_SFT (0x1 << 5)
  1820. #define RG_SEL_ENCODER_96K_VA28_SFT 6
  1821. #define RG_SEL_ENCODER_96K_VA28_MASK 0x1
  1822. #define RG_SEL_ENCODER_96K_VA28_MASK_SFT (0x1 << 6)
  1823. /* MT6358_AUDDEC_ANA_CON14 */
  1824. #define RG_HCLDO_EN_VA18_SFT 0
  1825. #define RG_HCLDO_EN_VA18_MASK 0x1
  1826. #define RG_HCLDO_EN_VA18_MASK_SFT (0x1 << 0)
  1827. #define RG_HCLDO_PDDIS_EN_VA18_SFT 1
  1828. #define RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
  1829. #define RG_HCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
  1830. #define RG_HCLDO_REMOTE_SENSE_VA18_SFT 2
  1831. #define RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
  1832. #define RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
  1833. #define RG_LCLDO_EN_VA18_SFT 4
  1834. #define RG_LCLDO_EN_VA18_MASK 0x1
  1835. #define RG_LCLDO_EN_VA18_MASK_SFT (0x1 << 4)
  1836. #define RG_LCLDO_PDDIS_EN_VA18_SFT 5
  1837. #define RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
  1838. #define RG_LCLDO_PDDIS_EN_VA18_MASK_SFT (0x1 << 5)
  1839. #define RG_LCLDO_REMOTE_SENSE_VA18_SFT 6
  1840. #define RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
  1841. #define RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 6)
  1842. #define RG_LCLDO_ENC_EN_VA28_SFT 8
  1843. #define RG_LCLDO_ENC_EN_VA28_MASK 0x1
  1844. #define RG_LCLDO_ENC_EN_VA28_MASK_SFT (0x1 << 8)
  1845. #define RG_LCLDO_ENC_PDDIS_EN_VA28_SFT 9
  1846. #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
  1847. #define RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT (0x1 << 9)
  1848. #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_SFT 10
  1849. #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
  1850. #define RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT (0x1 << 10)
  1851. #define RG_VA33REFGEN_EN_VA18_SFT 12
  1852. #define RG_VA33REFGEN_EN_VA18_MASK 0x1
  1853. #define RG_VA33REFGEN_EN_VA18_MASK_SFT (0x1 << 12)
  1854. #define RG_VA28REFGEN_EN_VA28_SFT 13
  1855. #define RG_VA28REFGEN_EN_VA28_MASK 0x1
  1856. #define RG_VA28REFGEN_EN_VA28_MASK_SFT (0x1 << 13)
  1857. #define RG_HCLDO_VOSEL_VA18_SFT 14
  1858. #define RG_HCLDO_VOSEL_VA18_MASK 0x1
  1859. #define RG_HCLDO_VOSEL_VA18_MASK_SFT (0x1 << 14)
  1860. #define RG_LCLDO_VOSEL_VA18_SFT 15
  1861. #define RG_LCLDO_VOSEL_VA18_MASK 0x1
  1862. #define RG_LCLDO_VOSEL_VA18_MASK_SFT (0x1 << 15)
  1863. /* MT6358_AUDDEC_ANA_CON15 */
  1864. #define RG_NVREG_EN_VAUDP15_SFT 0
  1865. #define RG_NVREG_EN_VAUDP15_MASK 0x1
  1866. #define RG_NVREG_EN_VAUDP15_MASK_SFT (0x1 << 0)
  1867. #define RG_NVREG_PULL0V_VAUDP15_SFT 1
  1868. #define RG_NVREG_PULL0V_VAUDP15_MASK 0x1
  1869. #define RG_NVREG_PULL0V_VAUDP15_MASK_SFT (0x1 << 1)
  1870. #define RG_AUDPMU_RSD0_VAUDP15_SFT 4
  1871. #define RG_AUDPMU_RSD0_VAUDP15_MASK 0xf
  1872. #define RG_AUDPMU_RSD0_VAUDP15_MASK_SFT (0xf << 4)
  1873. #define RG_AUDPMU_RSD0_VA18_SFT 8
  1874. #define RG_AUDPMU_RSD0_VA18_MASK 0xf
  1875. #define RG_AUDPMU_RSD0_VA18_MASK_SFT (0xf << 8)
  1876. #define RG_AUDPMU_RSD0_VA28_SFT 12
  1877. #define RG_AUDPMU_RSD0_VA28_MASK 0xf
  1878. #define RG_AUDPMU_RSD0_VA28_MASK_SFT (0xf << 12)
  1879. /* MT6358_ZCD_CON0 */
  1880. #define RG_AUDZCDENABLE_SFT 0
  1881. #define RG_AUDZCDENABLE_MASK 0x1
  1882. #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
  1883. #define RG_AUDZCDGAINSTEPTIME_SFT 1
  1884. #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
  1885. #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
  1886. #define RG_AUDZCDGAINSTEPSIZE_SFT 4
  1887. #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
  1888. #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
  1889. #define RG_AUDZCDTIMEOUTMODESEL_SFT 6
  1890. #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
  1891. #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)
  1892. /* MT6358_ZCD_CON1 */
  1893. #define RG_AUDLOLGAIN_SFT 0
  1894. #define RG_AUDLOLGAIN_MASK 0x1f
  1895. #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)
  1896. #define RG_AUDLORGAIN_SFT 7
  1897. #define RG_AUDLORGAIN_MASK 0x1f
  1898. #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)
  1899. /* MT6358_ZCD_CON2 */
  1900. #define RG_AUDHPLGAIN_SFT 0
  1901. #define RG_AUDHPLGAIN_MASK 0x1f
  1902. #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)
  1903. #define RG_AUDHPRGAIN_SFT 7
  1904. #define RG_AUDHPRGAIN_MASK 0x1f
  1905. #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)
  1906. /* MT6358_ZCD_CON3 */
  1907. #define RG_AUDHSGAIN_SFT 0
  1908. #define RG_AUDHSGAIN_MASK 0x1f
  1909. #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)
  1910. /* MT6358_ZCD_CON4 */
  1911. #define RG_AUDIVLGAIN_SFT 0
  1912. #define RG_AUDIVLGAIN_MASK 0x7
  1913. #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
  1914. #define RG_AUDIVRGAIN_SFT 8
  1915. #define RG_AUDIVRGAIN_MASK 0x7
  1916. #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
  1917. /* MT6358_ZCD_CON5 */
  1918. #define RG_AUDINTGAIN1_SFT 0
  1919. #define RG_AUDINTGAIN1_MASK 0x3f
  1920. #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)
  1921. #define RG_AUDINTGAIN2_SFT 8
  1922. #define RG_AUDINTGAIN2_MASK 0x3f
  1923. #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)
  1924. /* audio register */
  1925. #define MT6358_DRV_CON3 0x3c
  1926. #define MT6358_GPIO_DIR0 0x88
  1927. #define MT6358_GPIO_MODE2 0xd8 /* mosi */
  1928. #define MT6358_GPIO_MODE2_SET 0xda
  1929. #define MT6358_GPIO_MODE2_CLR 0xdc
  1930. #define MT6358_GPIO_MODE3 0xde /* miso */
  1931. #define MT6358_GPIO_MODE3_SET 0xe0
  1932. #define MT6358_GPIO_MODE3_CLR 0xe2
  1933. #define MT6358_TOP_CKPDN_CON0 0x10c
  1934. #define MT6358_TOP_CKPDN_CON0_SET 0x10e
  1935. #define MT6358_TOP_CKPDN_CON0_CLR 0x110
  1936. #define MT6358_TOP_CKHWEN_CON0 0x12a
  1937. #define MT6358_TOP_CKHWEN_CON0_SET 0x12c
  1938. #define MT6358_TOP_CKHWEN_CON0_CLR 0x12e
  1939. #define MT6358_OTP_CON0 0x38a
  1940. #define MT6358_OTP_CON8 0x39a
  1941. #define MT6358_OTP_CON11 0x3a0
  1942. #define MT6358_OTP_CON12 0x3a2
  1943. #define MT6358_OTP_CON13 0x3a4
  1944. #define MT6358_DCXO_CW13 0x7aa
  1945. #define MT6358_DCXO_CW14 0x7ac
  1946. #define MT6358_AUXADC_CON10 0x11a0
  1947. /* audio register */
  1948. #define MT6358_AUD_TOP_ID 0x2200
  1949. #define MT6358_AUD_TOP_REV0 0x2202
  1950. #define MT6358_AUD_TOP_DBI 0x2204
  1951. #define MT6358_AUD_TOP_DXI 0x2206
  1952. #define MT6358_AUD_TOP_CKPDN_TPM0 0x2208
  1953. #define MT6358_AUD_TOP_CKPDN_TPM1 0x220a
  1954. #define MT6358_AUD_TOP_CKPDN_CON0 0x220c
  1955. #define MT6358_AUD_TOP_CKPDN_CON0_SET 0x220e
  1956. #define MT6358_AUD_TOP_CKPDN_CON0_CLR 0x2210
  1957. #define MT6358_AUD_TOP_CKSEL_CON0 0x2212
  1958. #define MT6358_AUD_TOP_CKSEL_CON0_SET 0x2214
  1959. #define MT6358_AUD_TOP_CKSEL_CON0_CLR 0x2216
  1960. #define MT6358_AUD_TOP_CKTST_CON0 0x2218
  1961. #define MT6358_AUD_TOP_CLK_HWEN_CON0 0x221a
  1962. #define MT6358_AUD_TOP_CLK_HWEN_CON0_SET 0x221c
  1963. #define MT6358_AUD_TOP_CLK_HWEN_CON0_CLR 0x221e
  1964. #define MT6358_AUD_TOP_RST_CON0 0x2220
  1965. #define MT6358_AUD_TOP_RST_CON0_SET 0x2222
  1966. #define MT6358_AUD_TOP_RST_CON0_CLR 0x2224
  1967. #define MT6358_AUD_TOP_RST_BANK_CON0 0x2226
  1968. #define MT6358_AUD_TOP_INT_CON0 0x2228
  1969. #define MT6358_AUD_TOP_INT_CON0_SET 0x222a
  1970. #define MT6358_AUD_TOP_INT_CON0_CLR 0x222c
  1971. #define MT6358_AUD_TOP_INT_MASK_CON0 0x222e
  1972. #define MT6358_AUD_TOP_INT_MASK_CON0_SET 0x2230
  1973. #define MT6358_AUD_TOP_INT_MASK_CON0_CLR 0x2232
  1974. #define MT6358_AUD_TOP_INT_STATUS0 0x2234
  1975. #define MT6358_AUD_TOP_INT_RAW_STATUS0 0x2236
  1976. #define MT6358_AUD_TOP_INT_MISC_CON0 0x2238
  1977. #define MT6358_AUDNCP_CLKDIV_CON0 0x223a
  1978. #define MT6358_AUDNCP_CLKDIV_CON1 0x223c
  1979. #define MT6358_AUDNCP_CLKDIV_CON2 0x223e
  1980. #define MT6358_AUDNCP_CLKDIV_CON3 0x2240
  1981. #define MT6358_AUDNCP_CLKDIV_CON4 0x2242
  1982. #define MT6358_AUD_TOP_MON_CON0 0x2244
  1983. #define MT6358_AUDIO_DIG_DSN_ID 0x2280
  1984. #define MT6358_AUDIO_DIG_DSN_REV0 0x2282
  1985. #define MT6358_AUDIO_DIG_DSN_DBI 0x2284
  1986. #define MT6358_AUDIO_DIG_DSN_DXI 0x2286
  1987. #define MT6358_AFE_UL_DL_CON0 0x2288
  1988. #define MT6358_AFE_DL_SRC2_CON0_L 0x228a
  1989. #define MT6358_AFE_UL_SRC_CON0_H 0x228c
  1990. #define MT6358_AFE_UL_SRC_CON0_L 0x228e
  1991. #define MT6358_AFE_TOP_CON0 0x2290
  1992. #define MT6358_AUDIO_TOP_CON0 0x2292
  1993. #define MT6358_AFE_MON_DEBUG0 0x2294
  1994. #define MT6358_AFUNC_AUD_CON0 0x2296
  1995. #define MT6358_AFUNC_AUD_CON1 0x2298
  1996. #define MT6358_AFUNC_AUD_CON2 0x229a
  1997. #define MT6358_AFUNC_AUD_CON3 0x229c
  1998. #define MT6358_AFUNC_AUD_CON4 0x229e
  1999. #define MT6358_AFUNC_AUD_CON5 0x22a0
  2000. #define MT6358_AFUNC_AUD_CON6 0x22a2
  2001. #define MT6358_AFUNC_AUD_MON0 0x22a4
  2002. #define MT6358_AUDRC_TUNE_MON0 0x22a6
  2003. #define MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 0x22a8
  2004. #define MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x22aa
  2005. #define MT6358_AFE_ADDA_MTKAIF_MON0 0x22ac
  2006. #define MT6358_AFE_ADDA_MTKAIF_MON1 0x22ae
  2007. #define MT6358_AFE_ADDA_MTKAIF_MON2 0x22b0
  2008. #define MT6358_AFE_ADDA_MTKAIF_MON3 0x22b2
  2009. #define MT6358_AFE_ADDA_MTKAIF_CFG0 0x22b4
  2010. #define MT6358_AFE_ADDA_MTKAIF_RX_CFG0 0x22b6
  2011. #define MT6358_AFE_ADDA_MTKAIF_RX_CFG1 0x22b8
  2012. #define MT6358_AFE_ADDA_MTKAIF_RX_CFG2 0x22ba
  2013. #define MT6358_AFE_ADDA_MTKAIF_RX_CFG3 0x22bc
  2014. #define MT6358_AFE_ADDA_MTKAIF_TX_CFG1 0x22be
  2015. #define MT6358_AFE_SGEN_CFG0 0x22c0
  2016. #define MT6358_AFE_SGEN_CFG1 0x22c2
  2017. #define MT6358_AFE_ADC_ASYNC_FIFO_CFG 0x22c4
  2018. #define MT6358_AFE_DCCLK_CFG0 0x22c6
  2019. #define MT6358_AFE_DCCLK_CFG1 0x22c8
  2020. #define MT6358_AUDIO_DIG_CFG 0x22ca
  2021. #define MT6358_AFE_AUD_PAD_TOP 0x22cc
  2022. #define MT6358_AFE_AUD_PAD_TOP_MON 0x22ce
  2023. #define MT6358_AFE_AUD_PAD_TOP_MON1 0x22d0
  2024. #define MT6358_AFE_DL_NLE_CFG 0x22d2
  2025. #define MT6358_AFE_DL_NLE_MON 0x22d4
  2026. #define MT6358_AFE_CG_EN_MON 0x22d6
  2027. #define MT6358_AUDIO_DIG_2ND_DSN_ID 0x2300
  2028. #define MT6358_AUDIO_DIG_2ND_DSN_REV0 0x2302
  2029. #define MT6358_AUDIO_DIG_2ND_DSN_DBI 0x2304
  2030. #define MT6358_AUDIO_DIG_2ND_DSN_DXI 0x2306
  2031. #define MT6358_AFE_PMIC_NEWIF_CFG3 0x2308
  2032. #define MT6358_AFE_VOW_TOP 0x230a
  2033. #define MT6358_AFE_VOW_CFG0 0x230c
  2034. #define MT6358_AFE_VOW_CFG1 0x230e
  2035. #define MT6358_AFE_VOW_CFG2 0x2310
  2036. #define MT6358_AFE_VOW_CFG3 0x2312
  2037. #define MT6358_AFE_VOW_CFG4 0x2314
  2038. #define MT6358_AFE_VOW_CFG5 0x2316
  2039. #define MT6358_AFE_VOW_CFG6 0x2318
  2040. #define MT6358_AFE_VOW_MON0 0x231a
  2041. #define MT6358_AFE_VOW_MON1 0x231c
  2042. #define MT6358_AFE_VOW_MON2 0x231e
  2043. #define MT6358_AFE_VOW_MON3 0x2320
  2044. #define MT6358_AFE_VOW_MON4 0x2322
  2045. #define MT6358_AFE_VOW_MON5 0x2324
  2046. #define MT6358_AFE_VOW_SN_INI_CFG 0x2326
  2047. #define MT6358_AFE_VOW_TGEN_CFG0 0x2328
  2048. #define MT6358_AFE_VOW_POSDIV_CFG0 0x232a
  2049. #define MT6358_AFE_VOW_HPF_CFG0 0x232c
  2050. #define MT6358_AFE_VOW_PERIODIC_CFG0 0x232e
  2051. #define MT6358_AFE_VOW_PERIODIC_CFG1 0x2330
  2052. #define MT6358_AFE_VOW_PERIODIC_CFG2 0x2332
  2053. #define MT6358_AFE_VOW_PERIODIC_CFG3 0x2334
  2054. #define MT6358_AFE_VOW_PERIODIC_CFG4 0x2336
  2055. #define MT6358_AFE_VOW_PERIODIC_CFG5 0x2338
  2056. #define MT6358_AFE_VOW_PERIODIC_CFG6 0x233a
  2057. #define MT6358_AFE_VOW_PERIODIC_CFG7 0x233c
  2058. #define MT6358_AFE_VOW_PERIODIC_CFG8 0x233e
  2059. #define MT6358_AFE_VOW_PERIODIC_CFG9 0x2340
  2060. #define MT6358_AFE_VOW_PERIODIC_CFG10 0x2342
  2061. #define MT6358_AFE_VOW_PERIODIC_CFG11 0x2344
  2062. #define MT6358_AFE_VOW_PERIODIC_CFG12 0x2346
  2063. #define MT6358_AFE_VOW_PERIODIC_CFG13 0x2348
  2064. #define MT6358_AFE_VOW_PERIODIC_CFG14 0x234a
  2065. #define MT6358_AFE_VOW_PERIODIC_CFG15 0x234c
  2066. #define MT6358_AFE_VOW_PERIODIC_CFG16 0x234e
  2067. #define MT6358_AFE_VOW_PERIODIC_CFG17 0x2350
  2068. #define MT6358_AFE_VOW_PERIODIC_CFG18 0x2352
  2069. #define MT6358_AFE_VOW_PERIODIC_CFG19 0x2354
  2070. #define MT6358_AFE_VOW_PERIODIC_CFG20 0x2356
  2071. #define MT6358_AFE_VOW_PERIODIC_CFG21 0x2358
  2072. #define MT6358_AFE_VOW_PERIODIC_CFG22 0x235a
  2073. #define MT6358_AFE_VOW_PERIODIC_CFG23 0x235c
  2074. #define MT6358_AFE_VOW_PERIODIC_MON0 0x235e
  2075. #define MT6358_AFE_VOW_PERIODIC_MON1 0x2360
  2076. #define MT6358_AUDENC_DSN_ID 0x2380
  2077. #define MT6358_AUDENC_DSN_REV0 0x2382
  2078. #define MT6358_AUDENC_DSN_DBI 0x2384
  2079. #define MT6358_AUDENC_DSN_FPI 0x2386
  2080. #define MT6358_AUDENC_ANA_CON0 0x2388
  2081. #define MT6358_AUDENC_ANA_CON1 0x238a
  2082. #define MT6358_AUDENC_ANA_CON2 0x238c
  2083. #define MT6358_AUDENC_ANA_CON3 0x238e
  2084. #define MT6358_AUDENC_ANA_CON4 0x2390
  2085. #define MT6358_AUDENC_ANA_CON5 0x2392
  2086. #define MT6358_AUDENC_ANA_CON6 0x2394
  2087. #define MT6358_AUDENC_ANA_CON7 0x2396
  2088. #define MT6358_AUDENC_ANA_CON8 0x2398
  2089. #define MT6358_AUDENC_ANA_CON9 0x239a
  2090. #define MT6358_AUDENC_ANA_CON10 0x239c
  2091. #define MT6358_AUDENC_ANA_CON11 0x239e
  2092. #define MT6358_AUDENC_ANA_CON12 0x23a0
  2093. #define MT6358_AUDDEC_DSN_ID 0x2400
  2094. #define MT6358_AUDDEC_DSN_REV0 0x2402
  2095. #define MT6358_AUDDEC_DSN_DBI 0x2404
  2096. #define MT6358_AUDDEC_DSN_FPI 0x2406
  2097. #define MT6358_AUDDEC_ANA_CON0 0x2408
  2098. #define MT6358_AUDDEC_ANA_CON1 0x240a
  2099. #define MT6358_AUDDEC_ANA_CON2 0x240c
  2100. #define MT6358_AUDDEC_ANA_CON3 0x240e
  2101. #define MT6358_AUDDEC_ANA_CON4 0x2410
  2102. #define MT6358_AUDDEC_ANA_CON5 0x2412
  2103. #define MT6358_AUDDEC_ANA_CON6 0x2414
  2104. #define MT6358_AUDDEC_ANA_CON7 0x2416
  2105. #define MT6358_AUDDEC_ANA_CON8 0x2418
  2106. #define MT6358_AUDDEC_ANA_CON9 0x241a
  2107. #define MT6358_AUDDEC_ANA_CON10 0x241c
  2108. #define MT6358_AUDDEC_ANA_CON11 0x241e
  2109. #define MT6358_AUDDEC_ANA_CON12 0x2420
  2110. #define MT6358_AUDDEC_ANA_CON13 0x2422
  2111. #define MT6358_AUDDEC_ANA_CON14 0x2424
  2112. #define MT6358_AUDDEC_ANA_CON15 0x2426
  2113. #define MT6358_AUDDEC_ELR_NUM 0x2428
  2114. #define MT6358_AUDDEC_ELR_0 0x242a
  2115. #define MT6358_AUDZCD_DSN_ID 0x2480
  2116. #define MT6358_AUDZCD_DSN_REV0 0x2482
  2117. #define MT6358_AUDZCD_DSN_DBI 0x2484
  2118. #define MT6358_AUDZCD_DSN_FPI 0x2486
  2119. #define MT6358_ZCD_CON0 0x2488
  2120. #define MT6358_ZCD_CON1 0x248a
  2121. #define MT6358_ZCD_CON2 0x248c
  2122. #define MT6358_ZCD_CON3 0x248e
  2123. #define MT6358_ZCD_CON4 0x2490
  2124. #define MT6358_ZCD_CON5 0x2492
  2125. #define MT6358_ACCDET_CON13 0x2522
  2126. #define MT6358_MAX_REGISTER MT6358_ZCD_CON5
  2127. enum {
  2128. MT6358_MTKAIF_PROTOCOL_1 = 0,
  2129. MT6358_MTKAIF_PROTOCOL_2,
  2130. MT6358_MTKAIF_PROTOCOL_2_CLK_P2,
  2131. };
  2132. /* set only during init */
  2133. int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
  2134. int mtkaif_protocol);
  2135. int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);
  2136. int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);
  2137. int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
  2138. int phase_1, int phase_2);
  2139. #endif /* __MT6358_H__ */