mt6358.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // mt6358.c -- mt6358 ALSA SoC audio codec driver
  4. //
  5. // Copyright (c) 2018 MediaTek Inc.
  6. // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
  7. #include <linux/platform_device.h>
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/sched.h>
  13. #include <linux/mfd/mt6397/core.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include "mt6358.h"
  18. enum {
  19. AUDIO_ANALOG_VOLUME_HSOUTL,
  20. AUDIO_ANALOG_VOLUME_HSOUTR,
  21. AUDIO_ANALOG_VOLUME_HPOUTL,
  22. AUDIO_ANALOG_VOLUME_HPOUTR,
  23. AUDIO_ANALOG_VOLUME_LINEOUTL,
  24. AUDIO_ANALOG_VOLUME_LINEOUTR,
  25. AUDIO_ANALOG_VOLUME_MICAMP1,
  26. AUDIO_ANALOG_VOLUME_MICAMP2,
  27. AUDIO_ANALOG_VOLUME_TYPE_MAX
  28. };
  29. enum {
  30. MUX_ADC_L,
  31. MUX_ADC_R,
  32. MUX_PGA_L,
  33. MUX_PGA_R,
  34. MUX_MIC_TYPE,
  35. MUX_HP_L,
  36. MUX_HP_R,
  37. MUX_NUM,
  38. };
  39. enum {
  40. DEVICE_HP,
  41. DEVICE_LO,
  42. DEVICE_RCV,
  43. DEVICE_MIC1,
  44. DEVICE_MIC2,
  45. DEVICE_NUM
  46. };
  47. /* Supply widget subseq */
  48. enum {
  49. /* common */
  50. SUPPLY_SEQ_CLK_BUF,
  51. SUPPLY_SEQ_AUD_GLB,
  52. SUPPLY_SEQ_CLKSQ,
  53. SUPPLY_SEQ_VOW_AUD_LPW,
  54. SUPPLY_SEQ_AUD_VOW,
  55. SUPPLY_SEQ_VOW_CLK,
  56. SUPPLY_SEQ_VOW_LDO,
  57. SUPPLY_SEQ_TOP_CK,
  58. SUPPLY_SEQ_TOP_CK_LAST,
  59. SUPPLY_SEQ_AUD_TOP,
  60. SUPPLY_SEQ_AUD_TOP_LAST,
  61. SUPPLY_SEQ_AFE,
  62. /* capture */
  63. SUPPLY_SEQ_ADC_SUPPLY,
  64. };
  65. enum {
  66. CH_L = 0,
  67. CH_R,
  68. NUM_CH,
  69. };
  70. #define REG_STRIDE 2
  71. struct mt6358_priv {
  72. struct device *dev;
  73. struct regmap *regmap;
  74. unsigned int dl_rate;
  75. unsigned int ul_rate;
  76. int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  77. unsigned int mux_select[MUX_NUM];
  78. int dev_counter[DEVICE_NUM];
  79. int mtkaif_protocol;
  80. struct regulator *avdd_reg;
  81. int wov_enabled;
  82. unsigned int dmic_one_wire_mode;
  83. };
  84. int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
  85. int mtkaif_protocol)
  86. {
  87. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  88. priv->mtkaif_protocol = mtkaif_protocol;
  89. return 0;
  90. }
  91. EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
  92. static void playback_gpio_set(struct mt6358_priv *priv)
  93. {
  94. /* set gpio mosi mode */
  95. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
  96. 0x01f8, 0x01f8);
  97. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
  98. 0xffff, 0x0249);
  99. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
  100. 0xffff, 0x0249);
  101. }
  102. static void playback_gpio_reset(struct mt6358_priv *priv)
  103. {
  104. /* set pad_aud_*_mosi to GPIO mode and dir input
  105. * reason:
  106. * pad_aud_dat_mosi*, because the pin is used as boot strap
  107. * don't clean clk/sync, for mtkaif protocol 2
  108. */
  109. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
  110. 0x01f8, 0x01f8);
  111. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
  112. 0x01f8, 0x0000);
  113. regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
  114. 0xf << 8, 0x0);
  115. }
  116. static void capture_gpio_set(struct mt6358_priv *priv)
  117. {
  118. /* set gpio miso mode */
  119. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
  120. 0xffff, 0xffff);
  121. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
  122. 0xffff, 0x0249);
  123. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
  124. 0xffff, 0x0249);
  125. }
  126. static void capture_gpio_reset(struct mt6358_priv *priv)
  127. {
  128. /* set pad_aud_*_miso to GPIO mode and dir input
  129. * reason:
  130. * pad_aud_clk_miso, because when playback only the miso_clk
  131. * will also have 26m, so will have power leak
  132. * pad_aud_dat_miso*, because the pin is used as boot strap
  133. */
  134. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
  135. 0xffff, 0xffff);
  136. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
  137. 0xffff, 0x0000);
  138. regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
  139. 0xf << 12, 0x0);
  140. }
  141. /* use only when not govern by DAPM */
  142. static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
  143. {
  144. regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
  145. 0x1 << RG_XO_AUDIO_EN_M_SFT,
  146. (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
  147. return 0;
  148. }
  149. /* use only when not govern by DAPM */
  150. static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
  151. {
  152. /* audio clk source from internal dcxo */
  153. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
  154. RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
  155. 0x0);
  156. /* Enable/disable CLKSQ 26MHz */
  157. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
  158. RG_CLKSQ_EN_MASK_SFT,
  159. (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
  160. return 0;
  161. }
  162. /* use only when not govern by DAPM */
  163. static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
  164. {
  165. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  166. RG_AUDGLB_PWRDN_VA28_MASK_SFT,
  167. (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
  168. return 0;
  169. }
  170. /* use only when not govern by DAPM */
  171. static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
  172. {
  173. regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
  174. 0x0066, enable ? 0x0 : 0x66);
  175. return 0;
  176. }
  177. static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
  178. {
  179. switch (priv->mtkaif_protocol) {
  180. case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
  181. /* MTKAIF TX format setting */
  182. regmap_update_bits(priv->regmap,
  183. MT6358_AFE_ADDA_MTKAIF_CFG0,
  184. 0xffff, 0x0010);
  185. /* enable aud_pad TX fifos */
  186. regmap_update_bits(priv->regmap,
  187. MT6358_AFE_AUD_PAD_TOP,
  188. 0xff00, 0x3800);
  189. regmap_update_bits(priv->regmap,
  190. MT6358_AFE_AUD_PAD_TOP,
  191. 0xff00, 0x3900);
  192. break;
  193. case MT6358_MTKAIF_PROTOCOL_2:
  194. /* MTKAIF TX format setting */
  195. regmap_update_bits(priv->regmap,
  196. MT6358_AFE_ADDA_MTKAIF_CFG0,
  197. 0xffff, 0x0010);
  198. /* enable aud_pad TX fifos */
  199. regmap_update_bits(priv->regmap,
  200. MT6358_AFE_AUD_PAD_TOP,
  201. 0xff00, 0x3100);
  202. break;
  203. case MT6358_MTKAIF_PROTOCOL_1:
  204. default:
  205. /* MTKAIF TX format setting */
  206. regmap_update_bits(priv->regmap,
  207. MT6358_AFE_ADDA_MTKAIF_CFG0,
  208. 0xffff, 0x0000);
  209. /* enable aud_pad TX fifos */
  210. regmap_update_bits(priv->regmap,
  211. MT6358_AFE_AUD_PAD_TOP,
  212. 0xff00, 0x3100);
  213. break;
  214. }
  215. return 0;
  216. }
  217. static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
  218. {
  219. /* disable aud_pad TX fifos */
  220. regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
  221. 0xff00, 0x3000);
  222. return 0;
  223. }
  224. int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
  225. {
  226. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  227. playback_gpio_set(priv);
  228. capture_gpio_set(priv);
  229. mt6358_mtkaif_tx_enable(priv);
  230. mt6358_set_dcxo(priv, true);
  231. mt6358_set_aud_global_bias(priv, true);
  232. mt6358_set_clksq(priv, true);
  233. mt6358_set_topck(priv, true);
  234. /* set dat_miso_loopback on */
  235. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  236. RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
  237. 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
  238. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  239. RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
  240. 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
  241. return 0;
  242. }
  243. EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable);
  244. int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
  245. {
  246. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  247. /* set dat_miso_loopback off */
  248. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  249. RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
  250. 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
  251. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  252. RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
  253. 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
  254. mt6358_set_topck(priv, false);
  255. mt6358_set_clksq(priv, false);
  256. mt6358_set_aud_global_bias(priv, false);
  257. mt6358_set_dcxo(priv, false);
  258. mt6358_mtkaif_tx_disable(priv);
  259. playback_gpio_reset(priv);
  260. capture_gpio_reset(priv);
  261. return 0;
  262. }
  263. EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable);
  264. int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
  265. int phase_1, int phase_2)
  266. {
  267. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  268. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  269. RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
  270. phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
  271. regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
  272. RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
  273. phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
  274. return 0;
  275. }
  276. EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase);
  277. /* dl pga gain */
  278. enum {
  279. DL_GAIN_8DB = 0,
  280. DL_GAIN_0DB = 8,
  281. DL_GAIN_N_1DB = 9,
  282. DL_GAIN_N_10DB = 18,
  283. DL_GAIN_N_40DB = 0x1f,
  284. };
  285. #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
  286. #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
  287. #define DL_GAIN_REG_MASK 0x0f9f
  288. static void hp_zcd_disable(struct mt6358_priv *priv)
  289. {
  290. regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
  291. }
  292. static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
  293. {
  294. int i = 0, stage = 0;
  295. int target = 7;
  296. /* Enable/Reduce HPL/R main output stage step by step */
  297. for (i = 0; i <= target; i++) {
  298. stage = up ? i : target - i;
  299. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
  300. 0x7 << 8, stage << 8);
  301. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
  302. 0x7 << 11, stage << 11);
  303. usleep_range(100, 150);
  304. }
  305. }
  306. static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
  307. {
  308. int i = 0, stage = 0;
  309. /* Reduce HP aux feedback loop gain step by step */
  310. for (i = 0; i <= 0xf; i++) {
  311. stage = up ? i : 0xf - i;
  312. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
  313. 0xf << 12, stage << 12);
  314. usleep_range(100, 150);
  315. }
  316. }
  317. static void hp_pull_down(struct mt6358_priv *priv, bool enable)
  318. {
  319. int i;
  320. if (enable) {
  321. for (i = 0x0; i <= 0x6; i++) {
  322. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  323. 0x7, i);
  324. usleep_range(600, 700);
  325. }
  326. } else {
  327. for (i = 0x6; i >= 0x1; i--) {
  328. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  329. 0x7, i);
  330. usleep_range(600, 700);
  331. }
  332. }
  333. }
  334. static bool is_valid_hp_pga_idx(int reg_idx)
  335. {
  336. return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
  337. reg_idx == DL_GAIN_N_40DB;
  338. }
  339. static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
  340. {
  341. int offset = 0, count = 0, reg_idx;
  342. if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
  343. dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
  344. __func__, from, to);
  345. dev_info(priv->dev, "%s(), from %d, to %d\n",
  346. __func__, from, to);
  347. if (to > from)
  348. offset = to - from;
  349. else
  350. offset = from - to;
  351. while (offset >= 0) {
  352. if (to > from)
  353. reg_idx = from + count;
  354. else
  355. reg_idx = from - count;
  356. if (is_valid_hp_pga_idx(reg_idx)) {
  357. regmap_update_bits(priv->regmap,
  358. MT6358_ZCD_CON2,
  359. DL_GAIN_REG_MASK,
  360. (reg_idx << 7) | reg_idx);
  361. usleep_range(200, 300);
  362. }
  363. offset--;
  364. count++;
  365. }
  366. }
  367. static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
  368. struct snd_ctl_elem_value *ucontrol)
  369. {
  370. struct snd_soc_component *component =
  371. snd_soc_kcontrol_component(kcontrol);
  372. struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
  373. struct soc_mixer_control *mc =
  374. (struct soc_mixer_control *)kcontrol->private_value;
  375. unsigned int reg;
  376. int ret;
  377. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  378. if (ret < 0)
  379. return ret;
  380. switch (mc->reg) {
  381. case MT6358_ZCD_CON2:
  382. regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
  383. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
  384. (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
  385. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
  386. (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
  387. break;
  388. case MT6358_ZCD_CON1:
  389. regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
  390. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
  391. (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
  392. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
  393. (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
  394. break;
  395. case MT6358_ZCD_CON3:
  396. regmap_read(priv->regmap, MT6358_ZCD_CON3, &reg);
  397. priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
  398. (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
  399. priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
  400. (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
  401. break;
  402. case MT6358_AUDENC_ANA_CON0:
  403. case MT6358_AUDENC_ANA_CON1:
  404. regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &reg);
  405. priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
  406. (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
  407. regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &reg);
  408. priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
  409. (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
  410. break;
  411. }
  412. return ret;
  413. }
  414. static void mt6358_restore_pga(struct mt6358_priv *priv);
  415. static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
  416. {
  417. /* analog */
  418. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  419. 0xffff, 0x0000);
  420. regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
  421. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  422. 0xffff, 0x0800);
  423. mt6358_restore_pga(priv);
  424. regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
  425. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  426. 0xffff, 0x0025);
  427. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
  428. 0xffff, 0x0005);
  429. /* digital */
  430. regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
  431. 0xffff, 0x0000);
  432. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
  433. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
  434. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
  435. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
  436. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
  437. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
  438. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
  439. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
  440. 0xffff, 0x0000);
  441. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
  442. 0xffff, 0x0451);
  443. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
  444. return 0;
  445. }
  446. static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
  447. {
  448. /* digital */
  449. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
  450. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
  451. 0xffff, 0x0450);
  452. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
  453. 0xffff, 0x0c00);
  454. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
  455. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
  456. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
  457. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
  458. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
  459. regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
  460. regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
  461. regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
  462. 0xffff, 0x0000);
  463. /* analog */
  464. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
  465. 0xffff, 0x0004);
  466. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  467. 0xffff, 0x0000);
  468. regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
  469. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  470. 0xffff, 0x0000);
  471. mt6358_restore_pga(priv);
  472. regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
  473. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  474. 0xffff, 0x0010);
  475. return 0;
  476. }
  477. static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
  478. struct snd_ctl_elem_value *ucontrol)
  479. {
  480. struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
  481. struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
  482. ucontrol->value.integer.value[0] = priv->wov_enabled;
  483. return 0;
  484. }
  485. static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
  486. struct snd_ctl_elem_value *ucontrol)
  487. {
  488. struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
  489. struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
  490. int enabled = ucontrol->value.integer.value[0];
  491. if (priv->wov_enabled != enabled) {
  492. if (enabled)
  493. mt6358_enable_wov_phase2(priv);
  494. else
  495. mt6358_disable_wov_phase2(priv);
  496. priv->wov_enabled = enabled;
  497. }
  498. return 0;
  499. }
  500. static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
  501. static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
  502. static const struct snd_kcontrol_new mt6358_snd_controls[] = {
  503. /* dl pga gain */
  504. SOC_DOUBLE_EXT_TLV("Headphone Volume",
  505. MT6358_ZCD_CON2, 0, 7, 0x12, 1,
  506. snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
  507. SOC_DOUBLE_EXT_TLV("Lineout Volume",
  508. MT6358_ZCD_CON1, 0, 7, 0x12, 1,
  509. snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
  510. SOC_SINGLE_EXT_TLV("Handset Volume",
  511. MT6358_ZCD_CON3, 0, 0x12, 1,
  512. snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
  513. /* ul pga gain */
  514. SOC_DOUBLE_R_EXT_TLV("PGA Volume",
  515. MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
  516. 8, 4, 0,
  517. snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
  518. SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
  519. mt6358_get_wov, mt6358_put_wov),
  520. };
  521. /* MUX */
  522. /* LOL MUX */
  523. static const char * const lo_in_mux_map[] = {
  524. "Open", "Mute", "Playback", "Test Mode"
  525. };
  526. static int lo_in_mux_map_value[] = {
  527. 0x0, 0x1, 0x2, 0x3,
  528. };
  529. static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
  530. MT6358_AUDDEC_ANA_CON7,
  531. RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
  532. RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
  533. lo_in_mux_map,
  534. lo_in_mux_map_value);
  535. static const struct snd_kcontrol_new lo_in_mux_control =
  536. SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
  537. /*HP MUX */
  538. enum {
  539. HP_MUX_OPEN = 0,
  540. HP_MUX_HPSPK,
  541. HP_MUX_HP,
  542. HP_MUX_TEST_MODE,
  543. HP_MUX_HP_IMPEDANCE,
  544. HP_MUX_MASK = 0x7,
  545. };
  546. static const char * const hp_in_mux_map[] = {
  547. "Open",
  548. "LoudSPK Playback",
  549. "Audio Playback",
  550. "Test Mode",
  551. "HP Impedance",
  552. "undefined1",
  553. "undefined2",
  554. "undefined3",
  555. };
  556. static int hp_in_mux_map_value[] = {
  557. HP_MUX_OPEN,
  558. HP_MUX_HPSPK,
  559. HP_MUX_HP,
  560. HP_MUX_TEST_MODE,
  561. HP_MUX_HP_IMPEDANCE,
  562. HP_MUX_OPEN,
  563. HP_MUX_OPEN,
  564. HP_MUX_OPEN,
  565. };
  566. static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
  567. SND_SOC_NOPM,
  568. 0,
  569. HP_MUX_MASK,
  570. hp_in_mux_map,
  571. hp_in_mux_map_value);
  572. static const struct snd_kcontrol_new hpl_in_mux_control =
  573. SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
  574. static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
  575. SND_SOC_NOPM,
  576. 0,
  577. HP_MUX_MASK,
  578. hp_in_mux_map,
  579. hp_in_mux_map_value);
  580. static const struct snd_kcontrol_new hpr_in_mux_control =
  581. SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
  582. /* RCV MUX */
  583. enum {
  584. RCV_MUX_OPEN = 0,
  585. RCV_MUX_MUTE,
  586. RCV_MUX_VOICE_PLAYBACK,
  587. RCV_MUX_TEST_MODE,
  588. RCV_MUX_MASK = 0x3,
  589. };
  590. static const char * const rcv_in_mux_map[] = {
  591. "Open", "Mute", "Voice Playback", "Test Mode"
  592. };
  593. static int rcv_in_mux_map_value[] = {
  594. RCV_MUX_OPEN,
  595. RCV_MUX_MUTE,
  596. RCV_MUX_VOICE_PLAYBACK,
  597. RCV_MUX_TEST_MODE,
  598. };
  599. static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
  600. SND_SOC_NOPM,
  601. 0,
  602. RCV_MUX_MASK,
  603. rcv_in_mux_map,
  604. rcv_in_mux_map_value);
  605. static const struct snd_kcontrol_new rcv_in_mux_control =
  606. SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
  607. /* DAC In MUX */
  608. static const char * const dac_in_mux_map[] = {
  609. "Normal Path", "Sgen"
  610. };
  611. static int dac_in_mux_map_value[] = {
  612. 0x0, 0x1,
  613. };
  614. static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
  615. MT6358_AFE_TOP_CON0,
  616. DL_SINE_ON_SFT,
  617. DL_SINE_ON_MASK,
  618. dac_in_mux_map,
  619. dac_in_mux_map_value);
  620. static const struct snd_kcontrol_new dac_in_mux_control =
  621. SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
  622. /* AIF Out MUX */
  623. static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
  624. MT6358_AFE_TOP_CON0,
  625. UL_SINE_ON_SFT,
  626. UL_SINE_ON_MASK,
  627. dac_in_mux_map,
  628. dac_in_mux_map_value);
  629. static const struct snd_kcontrol_new aif_out_mux_control =
  630. SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
  631. /* Mic Type MUX */
  632. enum {
  633. MIC_TYPE_MUX_IDLE = 0,
  634. MIC_TYPE_MUX_ACC,
  635. MIC_TYPE_MUX_DMIC,
  636. MIC_TYPE_MUX_DCC,
  637. MIC_TYPE_MUX_DCC_ECM_DIFF,
  638. MIC_TYPE_MUX_DCC_ECM_SINGLE,
  639. MIC_TYPE_MUX_MASK = 0x7,
  640. };
  641. #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
  642. (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
  643. (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
  644. static const char * const mic_type_mux_map[] = {
  645. "Idle",
  646. "ACC",
  647. "DMIC",
  648. "DCC",
  649. "DCC_ECM_DIFF",
  650. "DCC_ECM_SINGLE",
  651. };
  652. static int mic_type_mux_map_value[] = {
  653. MIC_TYPE_MUX_IDLE,
  654. MIC_TYPE_MUX_ACC,
  655. MIC_TYPE_MUX_DMIC,
  656. MIC_TYPE_MUX_DCC,
  657. MIC_TYPE_MUX_DCC_ECM_DIFF,
  658. MIC_TYPE_MUX_DCC_ECM_SINGLE,
  659. };
  660. static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
  661. SND_SOC_NOPM,
  662. 0,
  663. MIC_TYPE_MUX_MASK,
  664. mic_type_mux_map,
  665. mic_type_mux_map_value);
  666. static const struct snd_kcontrol_new mic_type_mux_control =
  667. SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
  668. /* ADC L MUX */
  669. enum {
  670. ADC_MUX_IDLE = 0,
  671. ADC_MUX_AIN0,
  672. ADC_MUX_PREAMPLIFIER,
  673. ADC_MUX_IDLE1,
  674. ADC_MUX_MASK = 0x3,
  675. };
  676. static const char * const adc_left_mux_map[] = {
  677. "Idle", "AIN0", "Left Preamplifier", "Idle_1"
  678. };
  679. static int adc_mux_map_value[] = {
  680. ADC_MUX_IDLE,
  681. ADC_MUX_AIN0,
  682. ADC_MUX_PREAMPLIFIER,
  683. ADC_MUX_IDLE1,
  684. };
  685. static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
  686. SND_SOC_NOPM,
  687. 0,
  688. ADC_MUX_MASK,
  689. adc_left_mux_map,
  690. adc_mux_map_value);
  691. static const struct snd_kcontrol_new adc_left_mux_control =
  692. SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
  693. /* ADC R MUX */
  694. static const char * const adc_right_mux_map[] = {
  695. "Idle", "AIN0", "Right Preamplifier", "Idle_1"
  696. };
  697. static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
  698. SND_SOC_NOPM,
  699. 0,
  700. ADC_MUX_MASK,
  701. adc_right_mux_map,
  702. adc_mux_map_value);
  703. static const struct snd_kcontrol_new adc_right_mux_control =
  704. SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
  705. /* PGA L MUX */
  706. enum {
  707. PGA_MUX_NONE = 0,
  708. PGA_MUX_AIN0,
  709. PGA_MUX_AIN1,
  710. PGA_MUX_AIN2,
  711. PGA_MUX_MASK = 0x3,
  712. };
  713. static const char * const pga_mux_map[] = {
  714. "None", "AIN0", "AIN1", "AIN2"
  715. };
  716. static int pga_mux_map_value[] = {
  717. PGA_MUX_NONE,
  718. PGA_MUX_AIN0,
  719. PGA_MUX_AIN1,
  720. PGA_MUX_AIN2,
  721. };
  722. static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
  723. SND_SOC_NOPM,
  724. 0,
  725. PGA_MUX_MASK,
  726. pga_mux_map,
  727. pga_mux_map_value);
  728. static const struct snd_kcontrol_new pga_left_mux_control =
  729. SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
  730. /* PGA R MUX */
  731. static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
  732. SND_SOC_NOPM,
  733. 0,
  734. PGA_MUX_MASK,
  735. pga_mux_map,
  736. pga_mux_map_value);
  737. static const struct snd_kcontrol_new pga_right_mux_control =
  738. SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
  739. static int mt_clksq_event(struct snd_soc_dapm_widget *w,
  740. struct snd_kcontrol *kcontrol,
  741. int event)
  742. {
  743. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  744. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  745. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  746. switch (event) {
  747. case SND_SOC_DAPM_PRE_PMU:
  748. /* audio clk source from internal dcxo */
  749. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
  750. RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
  751. 0x0);
  752. break;
  753. default:
  754. break;
  755. }
  756. return 0;
  757. }
  758. static int mt_sgen_event(struct snd_soc_dapm_widget *w,
  759. struct snd_kcontrol *kcontrol,
  760. int event)
  761. {
  762. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  763. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  764. dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
  765. switch (event) {
  766. case SND_SOC_DAPM_PRE_PMU:
  767. /* sdm audio fifo clock power on */
  768. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
  769. /* scrambler clock on enable */
  770. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
  771. /* sdm power on */
  772. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
  773. /* sdm fifo enable */
  774. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
  775. regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
  776. 0xff3f,
  777. 0x0000);
  778. regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
  779. 0xffff,
  780. 0x0001);
  781. break;
  782. case SND_SOC_DAPM_POST_PMD:
  783. /* DL scrambler disabling sequence */
  784. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
  785. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
  786. break;
  787. default:
  788. break;
  789. }
  790. return 0;
  791. }
  792. static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
  793. struct snd_kcontrol *kcontrol,
  794. int event)
  795. {
  796. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  797. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  798. dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
  799. __func__, event, priv->dl_rate);
  800. switch (event) {
  801. case SND_SOC_DAPM_PRE_PMU:
  802. playback_gpio_set(priv);
  803. /* sdm audio fifo clock power on */
  804. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
  805. /* scrambler clock on enable */
  806. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
  807. /* sdm power on */
  808. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
  809. /* sdm fifo enable */
  810. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
  811. break;
  812. case SND_SOC_DAPM_POST_PMD:
  813. /* DL scrambler disabling sequence */
  814. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
  815. regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
  816. playback_gpio_reset(priv);
  817. break;
  818. default:
  819. break;
  820. }
  821. return 0;
  822. }
  823. static int mtk_hp_enable(struct mt6358_priv *priv)
  824. {
  825. /* Pull-down HPL/R to AVSS28_AUD */
  826. hp_pull_down(priv, true);
  827. /* release HP CMFB gate rstb */
  828. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  829. 0x1 << 6, 0x1 << 6);
  830. /* Reduce ESD resistance of AU_REFN */
  831. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
  832. /* Set HPR/HPL gain as minimum (~ -40dB) */
  833. regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
  834. /* Turn on DA_600K_NCP_VA18 */
  835. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
  836. /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
  837. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
  838. /* Toggle RG_DIVCKS_CHG */
  839. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
  840. /* Set NCP soft start mode as default mode: 100us */
  841. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
  842. /* Enable NCP */
  843. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
  844. usleep_range(250, 270);
  845. /* Enable cap-less LDOs (1.5V) */
  846. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  847. 0x1055, 0x1055);
  848. /* Enable NV regulator (-1.2V) */
  849. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
  850. usleep_range(100, 120);
  851. /* Disable AUD_ZCD */
  852. hp_zcd_disable(priv);
  853. /* Disable headphone short-circuit protection */
  854. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
  855. /* Enable IBIST */
  856. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  857. /* Set HP DR bias current optimization, 010: 6uA */
  858. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
  859. /* Set HP & ZCD bias current optimization */
  860. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  861. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  862. /* Set HPP/N STB enhance circuits */
  863. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
  864. /* Enable HP aux output stage */
  865. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
  866. /* Enable HP aux feedback loop */
  867. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
  868. /* Enable HP aux CMFB loop */
  869. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
  870. /* Enable HP driver bias circuits */
  871. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
  872. /* Enable HP driver core circuits */
  873. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
  874. /* Short HP main output to HP aux output stage */
  875. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
  876. /* Enable HP main CMFB loop */
  877. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
  878. /* Disable HP aux CMFB loop */
  879. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
  880. /* Select CMFB resistor bulk to AC mode */
  881. /* Selec HS/LO cap size (6.5pF default) */
  882. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
  883. /* Enable HP main output stage */
  884. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
  885. /* Enable HPR/L main output stage step by step */
  886. hp_main_output_ramp(priv, true);
  887. /* Reduce HP aux feedback loop gain */
  888. hp_aux_feedback_loop_gain_ramp(priv, true);
  889. /* Disable HP aux feedback loop */
  890. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
  891. /* apply volume setting */
  892. headset_volume_ramp(priv,
  893. DL_GAIN_N_10DB,
  894. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
  895. /* Disable HP aux output stage */
  896. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
  897. /* Unshort HP main output to HP aux output stage */
  898. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
  899. usleep_range(100, 120);
  900. /* Enable AUD_CLK */
  901. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
  902. /* Enable Audio DAC */
  903. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
  904. /* Enable low-noise mode of DAC */
  905. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
  906. usleep_range(100, 120);
  907. /* Switch HPL MUX to audio DAC */
  908. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
  909. /* Switch HPR MUX to audio DAC */
  910. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
  911. /* Disable Pull-down HPL/R to AVSS28_AUD */
  912. hp_pull_down(priv, false);
  913. return 0;
  914. }
  915. static int mtk_hp_disable(struct mt6358_priv *priv)
  916. {
  917. /* Pull-down HPL/R to AVSS28_AUD */
  918. hp_pull_down(priv, true);
  919. /* HPR/HPL mux to open */
  920. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  921. 0x0f00, 0x0000);
  922. /* Disable low-noise mode of DAC */
  923. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
  924. 0x0001, 0x0000);
  925. /* Disable Audio DAC */
  926. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  927. 0x000f, 0x0000);
  928. /* Disable AUD_CLK */
  929. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
  930. /* Short HP main output to HP aux output stage */
  931. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
  932. /* Enable HP aux output stage */
  933. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
  934. /* decrease HPL/R gain to normal gain step by step */
  935. headset_volume_ramp(priv,
  936. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
  937. DL_GAIN_N_40DB);
  938. /* Enable HP aux feedback loop */
  939. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
  940. /* Reduce HP aux feedback loop gain */
  941. hp_aux_feedback_loop_gain_ramp(priv, false);
  942. /* decrease HPR/L main output stage step by step */
  943. hp_main_output_ramp(priv, false);
  944. /* Disable HP main output stage */
  945. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
  946. /* Enable HP aux CMFB loop */
  947. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
  948. /* Disable HP main CMFB loop */
  949. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
  950. /* Unshort HP main output to HP aux output stage */
  951. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
  952. 0x3 << 6, 0x0);
  953. /* Disable HP driver core circuits */
  954. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  955. 0x3 << 4, 0x0);
  956. /* Disable HP driver bias circuits */
  957. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  958. 0x3 << 6, 0x0);
  959. /* Disable HP aux CMFB loop */
  960. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
  961. /* Disable HP aux feedback loop */
  962. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
  963. 0x3 << 4, 0x0);
  964. /* Disable HP aux output stage */
  965. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
  966. 0x3 << 2, 0x0);
  967. /* Disable IBIST */
  968. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
  969. 0x1 << 8, 0x1 << 8);
  970. /* Disable NV regulator (-1.2V) */
  971. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
  972. /* Disable cap-less LDOs (1.5V) */
  973. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  974. 0x1055, 0x0);
  975. /* Disable NCP */
  976. regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
  977. 0x1, 0x1);
  978. /* Increase ESD resistance of AU_REFN */
  979. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
  980. 0x1 << 14, 0x0);
  981. /* Set HP CMFB gate rstb */
  982. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  983. 0x1 << 6, 0x0);
  984. /* disable Pull-down HPL/R to AVSS28_AUD */
  985. hp_pull_down(priv, false);
  986. return 0;
  987. }
  988. static int mtk_hp_spk_enable(struct mt6358_priv *priv)
  989. {
  990. /* Pull-down HPL/R to AVSS28_AUD */
  991. hp_pull_down(priv, true);
  992. /* release HP CMFB gate rstb */
  993. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  994. 0x1 << 6, 0x1 << 6);
  995. /* Reduce ESD resistance of AU_REFN */
  996. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
  997. /* Set HPR/HPL gain to -10dB */
  998. regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
  999. /* Turn on DA_600K_NCP_VA18 */
  1000. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
  1001. /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
  1002. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
  1003. /* Toggle RG_DIVCKS_CHG */
  1004. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
  1005. /* Set NCP soft start mode as default mode: 100us */
  1006. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
  1007. /* Enable NCP */
  1008. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
  1009. usleep_range(250, 270);
  1010. /* Enable cap-less LDOs (1.5V) */
  1011. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1012. 0x1055, 0x1055);
  1013. /* Enable NV regulator (-1.2V) */
  1014. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
  1015. usleep_range(100, 120);
  1016. /* Disable AUD_ZCD */
  1017. hp_zcd_disable(priv);
  1018. /* Disable headphone short-circuit protection */
  1019. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
  1020. /* Enable IBIST */
  1021. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  1022. /* Set HP DR bias current optimization, 010: 6uA */
  1023. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
  1024. /* Set HP & ZCD bias current optimization */
  1025. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  1026. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  1027. /* Set HPP/N STB enhance circuits */
  1028. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
  1029. /* Disable Pull-down HPL/R to AVSS28_AUD */
  1030. hp_pull_down(priv, false);
  1031. /* Enable HP driver bias circuits */
  1032. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
  1033. /* Enable HP driver core circuits */
  1034. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
  1035. /* Enable HP main CMFB loop */
  1036. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
  1037. /* Select CMFB resistor bulk to AC mode */
  1038. /* Selec HS/LO cap size (6.5pF default) */
  1039. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
  1040. /* Enable HP main output stage */
  1041. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
  1042. /* Enable HPR/L main output stage step by step */
  1043. hp_main_output_ramp(priv, true);
  1044. /* Set LO gain as minimum (~ -40dB) */
  1045. regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
  1046. /* apply volume setting */
  1047. headset_volume_ramp(priv,
  1048. DL_GAIN_N_10DB,
  1049. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
  1050. /* Set LO STB enhance circuits */
  1051. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
  1052. /* Enable LO driver bias circuits */
  1053. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
  1054. /* Enable LO driver core circuits */
  1055. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
  1056. /* Set LOL gain to normal gain step by step */
  1057. regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
  1058. RG_AUDLOLGAIN_MASK_SFT,
  1059. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
  1060. RG_AUDLOLGAIN_SFT);
  1061. regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
  1062. RG_AUDLORGAIN_MASK_SFT,
  1063. priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
  1064. RG_AUDLORGAIN_SFT);
  1065. /* Enable AUD_CLK */
  1066. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
  1067. /* Enable Audio DAC */
  1068. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
  1069. /* Enable low-noise mode of DAC */
  1070. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
  1071. /* Switch LOL MUX to audio DAC */
  1072. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
  1073. /* Switch HPL/R MUX to Line-out */
  1074. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
  1075. return 0;
  1076. }
  1077. static int mtk_hp_spk_disable(struct mt6358_priv *priv)
  1078. {
  1079. /* HPR/HPL mux to open */
  1080. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1081. 0x0f00, 0x0000);
  1082. /* LOL mux to open */
  1083. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
  1084. 0x3 << 2, 0x0000);
  1085. /* Disable Audio DAC */
  1086. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1087. 0x000f, 0x0000);
  1088. /* Disable AUD_CLK */
  1089. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
  1090. /* decrease HPL/R gain to normal gain step by step */
  1091. headset_volume_ramp(priv,
  1092. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
  1093. DL_GAIN_N_40DB);
  1094. /* decrease LOL gain to minimum gain step by step */
  1095. regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
  1096. DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
  1097. /* decrease HPR/L main output stage step by step */
  1098. hp_main_output_ramp(priv, false);
  1099. /* Disable HP main output stage */
  1100. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
  1101. /* Short HP main output to HP aux output stage */
  1102. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
  1103. /* Enable HP aux output stage */
  1104. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
  1105. /* Enable HP aux feedback loop */
  1106. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
  1107. /* Reduce HP aux feedback loop gain */
  1108. hp_aux_feedback_loop_gain_ramp(priv, false);
  1109. /* Disable HP driver core circuits */
  1110. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1111. 0x3 << 4, 0x0);
  1112. /* Disable LO driver core circuits */
  1113. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
  1114. 0x1, 0x0);
  1115. /* Disable HP driver bias circuits */
  1116. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1117. 0x3 << 6, 0x0);
  1118. /* Disable LO driver bias circuits */
  1119. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
  1120. 0x1 << 1, 0x0);
  1121. /* Disable HP aux CMFB loop */
  1122. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
  1123. 0xff << 8, 0x0000);
  1124. /* Disable IBIST */
  1125. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
  1126. 0x1 << 8, 0x1 << 8);
  1127. /* Disable NV regulator (-1.2V) */
  1128. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
  1129. /* Disable cap-less LDOs (1.5V) */
  1130. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
  1131. /* Disable NCP */
  1132. regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
  1133. /* Set HP CMFB gate rstb */
  1134. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
  1135. 0x1 << 6, 0x0);
  1136. /* disable Pull-down HPL/R to AVSS28_AUD */
  1137. hp_pull_down(priv, false);
  1138. return 0;
  1139. }
  1140. static int mt_hp_event(struct snd_soc_dapm_widget *w,
  1141. struct snd_kcontrol *kcontrol,
  1142. int event)
  1143. {
  1144. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1145. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1146. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1147. int device = DEVICE_HP;
  1148. dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
  1149. __func__,
  1150. event,
  1151. priv->dev_counter[device],
  1152. mux);
  1153. switch (event) {
  1154. case SND_SOC_DAPM_PRE_PMU:
  1155. priv->dev_counter[device]++;
  1156. if (priv->dev_counter[device] > 1)
  1157. break; /* already enabled, do nothing */
  1158. else if (priv->dev_counter[device] <= 0)
  1159. dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
  1160. __func__,
  1161. priv->dev_counter[device]);
  1162. priv->mux_select[MUX_HP_L] = mux;
  1163. if (mux == HP_MUX_HP)
  1164. mtk_hp_enable(priv);
  1165. else if (mux == HP_MUX_HPSPK)
  1166. mtk_hp_spk_enable(priv);
  1167. break;
  1168. case SND_SOC_DAPM_PRE_PMD:
  1169. priv->dev_counter[device]--;
  1170. if (priv->dev_counter[device] > 0) {
  1171. break; /* still being used, don't close */
  1172. } else if (priv->dev_counter[device] < 0) {
  1173. dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
  1174. __func__,
  1175. priv->dev_counter[device]);
  1176. priv->dev_counter[device] = 0;
  1177. break;
  1178. }
  1179. if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
  1180. mtk_hp_disable(priv);
  1181. else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
  1182. mtk_hp_spk_disable(priv);
  1183. priv->mux_select[MUX_HP_L] = mux;
  1184. break;
  1185. default:
  1186. break;
  1187. }
  1188. return 0;
  1189. }
  1190. static int mt_rcv_event(struct snd_soc_dapm_widget *w,
  1191. struct snd_kcontrol *kcontrol,
  1192. int event)
  1193. {
  1194. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1195. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1196. dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
  1197. __func__,
  1198. event,
  1199. dapm_kcontrol_get_value(w->kcontrols[0]));
  1200. switch (event) {
  1201. case SND_SOC_DAPM_PRE_PMU:
  1202. /* Reduce ESD resistance of AU_REFN */
  1203. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
  1204. /* Turn on DA_600K_NCP_VA18 */
  1205. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
  1206. /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
  1207. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
  1208. /* Toggle RG_DIVCKS_CHG */
  1209. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
  1210. /* Set NCP soft start mode as default mode: 100us */
  1211. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
  1212. /* Enable NCP */
  1213. regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
  1214. usleep_range(250, 270);
  1215. /* Enable cap-less LDOs (1.5V) */
  1216. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1217. 0x1055, 0x1055);
  1218. /* Enable NV regulator (-1.2V) */
  1219. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
  1220. usleep_range(100, 120);
  1221. /* Disable AUD_ZCD */
  1222. hp_zcd_disable(priv);
  1223. /* Disable handset short-circuit protection */
  1224. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
  1225. /* Enable IBIST */
  1226. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  1227. /* Set HP DR bias current optimization, 010: 6uA */
  1228. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
  1229. /* Set HP & ZCD bias current optimization */
  1230. /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
  1231. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
  1232. /* Set HS STB enhance circuits */
  1233. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
  1234. /* Disable HP main CMFB loop */
  1235. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
  1236. /* Select CMFB resistor bulk to AC mode */
  1237. /* Selec HS/LO cap size (6.5pF default) */
  1238. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
  1239. /* Enable HS driver bias circuits */
  1240. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
  1241. /* Enable HS driver core circuits */
  1242. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
  1243. /* Enable AUD_CLK */
  1244. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  1245. 0x1, 0x1);
  1246. /* Enable Audio DAC */
  1247. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
  1248. /* Enable low-noise mode of DAC */
  1249. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
  1250. /* Switch HS MUX to audio DAC */
  1251. regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
  1252. break;
  1253. case SND_SOC_DAPM_PRE_PMD:
  1254. /* HS mux to open */
  1255. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
  1256. RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
  1257. RCV_MUX_OPEN);
  1258. /* Disable Audio DAC */
  1259. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1260. 0x000f, 0x0000);
  1261. /* Disable AUD_CLK */
  1262. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  1263. 0x1, 0x0);
  1264. /* decrease HS gain to minimum gain step by step */
  1265. regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
  1266. /* Disable HS driver core circuits */
  1267. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
  1268. 0x1, 0x0);
  1269. /* Disable HS driver bias circuits */
  1270. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
  1271. 0x1 << 1, 0x0000);
  1272. /* Disable HP aux CMFB loop */
  1273. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
  1274. 0xff << 8, 0x0);
  1275. /* Enable HP main CMFB Switch */
  1276. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
  1277. 0xff << 8, 0x2 << 8);
  1278. /* Disable IBIST */
  1279. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
  1280. 0x1 << 8, 0x1 << 8);
  1281. /* Disable NV regulator (-1.2V) */
  1282. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
  1283. 0x1, 0x0);
  1284. /* Disable cap-less LDOs (1.5V) */
  1285. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1286. 0x1055, 0x0);
  1287. /* Disable NCP */
  1288. regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
  1289. 0x1, 0x1);
  1290. break;
  1291. default:
  1292. break;
  1293. }
  1294. return 0;
  1295. }
  1296. static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
  1297. struct snd_kcontrol *kcontrol,
  1298. int event)
  1299. {
  1300. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1301. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1302. dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
  1303. __func__, event, priv->ul_rate);
  1304. switch (event) {
  1305. case SND_SOC_DAPM_PRE_PMU:
  1306. capture_gpio_set(priv);
  1307. break;
  1308. case SND_SOC_DAPM_POST_PMD:
  1309. capture_gpio_reset(priv);
  1310. break;
  1311. default:
  1312. break;
  1313. }
  1314. return 0;
  1315. }
  1316. static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
  1317. struct snd_kcontrol *kcontrol,
  1318. int event)
  1319. {
  1320. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1321. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1322. dev_dbg(priv->dev, "%s(), event 0x%x\n",
  1323. __func__, event);
  1324. switch (event) {
  1325. case SND_SOC_DAPM_PRE_PMU:
  1326. /* Enable audio ADC CLKGEN */
  1327. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  1328. 0x1 << 5, 0x1 << 5);
  1329. /* ADC CLK from CLKGEN (13MHz) */
  1330. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
  1331. 0x0000);
  1332. /* Enable LCLDO_ENC 1P8V */
  1333. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1334. 0x2500, 0x0100);
  1335. /* LCLDO_ENC remote sense */
  1336. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1337. 0x2500, 0x2500);
  1338. break;
  1339. case SND_SOC_DAPM_POST_PMD:
  1340. /* LCLDO_ENC remote sense off */
  1341. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1342. 0x2500, 0x0100);
  1343. /* disable LCLDO_ENC 1P8V */
  1344. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
  1345. 0x2500, 0x0000);
  1346. /* ADC CLK from CLKGEN (13MHz) */
  1347. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
  1348. /* disable audio ADC CLKGEN */
  1349. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
  1350. 0x1 << 5, 0x0 << 5);
  1351. break;
  1352. default:
  1353. break;
  1354. }
  1355. return 0;
  1356. }
  1357. static int mt6358_amic_enable(struct mt6358_priv *priv)
  1358. {
  1359. unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
  1360. unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
  1361. unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
  1362. dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
  1363. __func__, mic_type, mux_pga_l, mux_pga_r);
  1364. if (IS_DCC_BASE(mic_type)) {
  1365. /* DCC 50k CLK (from 26M) */
  1366. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
  1367. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
  1368. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
  1369. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
  1370. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
  1371. }
  1372. /* mic bias 0 */
  1373. if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
  1374. mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
  1375. switch (mic_type) {
  1376. case MIC_TYPE_MUX_DCC_ECM_DIFF:
  1377. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  1378. 0xff00, 0x7700);
  1379. break;
  1380. case MIC_TYPE_MUX_DCC_ECM_SINGLE:
  1381. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  1382. 0xff00, 0x1100);
  1383. break;
  1384. default:
  1385. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  1386. 0xff00, 0x0000);
  1387. break;
  1388. }
  1389. /* Enable MICBIAS0, MISBIAS0 = 1P9V */
  1390. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
  1391. 0xff, 0x21);
  1392. }
  1393. /* mic bias 1 */
  1394. if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
  1395. /* Enable MICBIAS1, MISBIAS1 = 2P6V */
  1396. if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
  1397. regmap_write(priv->regmap,
  1398. MT6358_AUDENC_ANA_CON10, 0x0161);
  1399. else
  1400. regmap_write(priv->regmap,
  1401. MT6358_AUDENC_ANA_CON10, 0x0061);
  1402. }
  1403. if (IS_DCC_BASE(mic_type)) {
  1404. /* Audio L/R preamplifier DCC precharge */
  1405. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1406. 0xf8ff, 0x0004);
  1407. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1408. 0xf8ff, 0x0004);
  1409. } else {
  1410. /* reset reg */
  1411. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1412. 0xf8ff, 0x0000);
  1413. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1414. 0xf8ff, 0x0000);
  1415. }
  1416. if (mux_pga_l != PGA_MUX_NONE) {
  1417. /* L preamplifier input sel */
  1418. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1419. RG_AUDPREAMPLINPUTSEL_MASK_SFT,
  1420. mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
  1421. /* L preamplifier enable */
  1422. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1423. RG_AUDPREAMPLON_MASK_SFT,
  1424. 0x1 << RG_AUDPREAMPLON_SFT);
  1425. if (IS_DCC_BASE(mic_type)) {
  1426. /* L preamplifier DCCEN */
  1427. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1428. RG_AUDPREAMPLDCCEN_MASK_SFT,
  1429. 0x1 << RG_AUDPREAMPLDCCEN_SFT);
  1430. }
  1431. /* L ADC input sel : L PGA. Enable audio L ADC */
  1432. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1433. RG_AUDADCLINPUTSEL_MASK_SFT,
  1434. ADC_MUX_PREAMPLIFIER <<
  1435. RG_AUDADCLINPUTSEL_SFT);
  1436. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1437. RG_AUDADCLPWRUP_MASK_SFT,
  1438. 0x1 << RG_AUDADCLPWRUP_SFT);
  1439. }
  1440. if (mux_pga_r != PGA_MUX_NONE) {
  1441. /* R preamplifier input sel */
  1442. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1443. RG_AUDPREAMPRINPUTSEL_MASK_SFT,
  1444. mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
  1445. /* R preamplifier enable */
  1446. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1447. RG_AUDPREAMPRON_MASK_SFT,
  1448. 0x1 << RG_AUDPREAMPRON_SFT);
  1449. if (IS_DCC_BASE(mic_type)) {
  1450. /* R preamplifier DCCEN */
  1451. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1452. RG_AUDPREAMPRDCCEN_MASK_SFT,
  1453. 0x1 << RG_AUDPREAMPRDCCEN_SFT);
  1454. }
  1455. /* R ADC input sel : R PGA. Enable audio R ADC */
  1456. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1457. RG_AUDADCRINPUTSEL_MASK_SFT,
  1458. ADC_MUX_PREAMPLIFIER <<
  1459. RG_AUDADCRINPUTSEL_SFT);
  1460. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1461. RG_AUDADCRPWRUP_MASK_SFT,
  1462. 0x1 << RG_AUDADCRPWRUP_SFT);
  1463. }
  1464. if (IS_DCC_BASE(mic_type)) {
  1465. usleep_range(100, 150);
  1466. /* Audio L preamplifier DCC precharge off */
  1467. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1468. RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
  1469. /* Audio R preamplifier DCC precharge off */
  1470. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1471. RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
  1472. /* Short body to ground in PGA */
  1473. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
  1474. 0x1 << 12, 0x0);
  1475. }
  1476. /* here to set digital part */
  1477. mt6358_mtkaif_tx_enable(priv);
  1478. /* UL dmic setting off */
  1479. regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
  1480. /* UL turn on */
  1481. regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
  1482. return 0;
  1483. }
  1484. static void mt6358_amic_disable(struct mt6358_priv *priv)
  1485. {
  1486. unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
  1487. unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
  1488. unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
  1489. dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
  1490. __func__, mic_type, mux_pga_l, mux_pga_r);
  1491. /* UL turn off */
  1492. regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
  1493. 0x0001, 0x0000);
  1494. /* disable aud_pad TX fifos */
  1495. mt6358_mtkaif_tx_disable(priv);
  1496. /* L ADC input sel : off, disable L ADC */
  1497. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1498. 0xf000, 0x0000);
  1499. /* L preamplifier DCCEN */
  1500. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1501. 0x1 << 1, 0x0);
  1502. /* L preamplifier input sel : off, L PGA 0 dB gain */
  1503. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1504. 0xfffb, 0x0000);
  1505. /* disable L preamplifier DCC precharge */
  1506. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1507. 0x1 << 2, 0x0);
  1508. /* R ADC input sel : off, disable R ADC */
  1509. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1510. 0xf000, 0x0000);
  1511. /* R preamplifier DCCEN */
  1512. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1513. 0x1 << 1, 0x0);
  1514. /* R preamplifier input sel : off, R PGA 0 dB gain */
  1515. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1516. 0x0ffb, 0x0000);
  1517. /* disable R preamplifier DCC precharge */
  1518. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1519. 0x1 << 2, 0x0);
  1520. /* mic bias */
  1521. /* Disable MICBIAS0, MISBIAS0 = 1P7V */
  1522. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
  1523. /* Disable MICBIAS1 */
  1524. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
  1525. 0x0001, 0x0000);
  1526. if (IS_DCC_BASE(mic_type)) {
  1527. /* dcclk_gen_on=1'b0 */
  1528. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
  1529. /* dcclk_pdn=1'b1 */
  1530. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
  1531. /* dcclk_ref_ck_sel=2'b00 */
  1532. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
  1533. /* dcclk_div=11'b00100000011 */
  1534. regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
  1535. }
  1536. }
  1537. static int mt6358_dmic_enable(struct mt6358_priv *priv)
  1538. {
  1539. dev_info(priv->dev, "%s()\n", __func__);
  1540. /* mic bias */
  1541. /* Enable MICBIAS0, MISBIAS0 = 1P9V */
  1542. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
  1543. /* RG_BANDGAPGEN=1'b0 */
  1544. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
  1545. 0x1 << 12, 0x0);
  1546. /* DMIC enable */
  1547. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
  1548. /* here to set digital part */
  1549. mt6358_mtkaif_tx_enable(priv);
  1550. /* UL dmic setting */
  1551. if (priv->dmic_one_wire_mode)
  1552. regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
  1553. else
  1554. regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
  1555. /* UL turn on */
  1556. regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
  1557. /* Prevent pop noise form dmic hw */
  1558. msleep(100);
  1559. return 0;
  1560. }
  1561. static void mt6358_dmic_disable(struct mt6358_priv *priv)
  1562. {
  1563. dev_info(priv->dev, "%s()\n", __func__);
  1564. /* UL turn off */
  1565. regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
  1566. 0x0003, 0x0000);
  1567. /* disable aud_pad TX fifos */
  1568. mt6358_mtkaif_tx_disable(priv);
  1569. /* DMIC disable */
  1570. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
  1571. /* mic bias */
  1572. /* MISBIAS0 = 1P7V */
  1573. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
  1574. /* RG_BANDGAPGEN=1'b0 */
  1575. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
  1576. 0x1 << 12, 0x0);
  1577. /* MICBIA0 disable */
  1578. regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
  1579. }
  1580. static void mt6358_restore_pga(struct mt6358_priv *priv)
  1581. {
  1582. unsigned int gain_l, gain_r;
  1583. gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
  1584. gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
  1585. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
  1586. RG_AUDPREAMPLGAIN_MASK_SFT,
  1587. gain_l << RG_AUDPREAMPLGAIN_SFT);
  1588. regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
  1589. RG_AUDPREAMPRGAIN_MASK_SFT,
  1590. gain_r << RG_AUDPREAMPRGAIN_SFT);
  1591. }
  1592. static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
  1593. struct snd_kcontrol *kcontrol,
  1594. int event)
  1595. {
  1596. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1597. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1598. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1599. dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
  1600. __func__, event, mux);
  1601. switch (event) {
  1602. case SND_SOC_DAPM_WILL_PMU:
  1603. priv->mux_select[MUX_MIC_TYPE] = mux;
  1604. break;
  1605. case SND_SOC_DAPM_PRE_PMU:
  1606. switch (mux) {
  1607. case MIC_TYPE_MUX_DMIC:
  1608. mt6358_dmic_enable(priv);
  1609. break;
  1610. default:
  1611. mt6358_amic_enable(priv);
  1612. break;
  1613. }
  1614. mt6358_restore_pga(priv);
  1615. break;
  1616. case SND_SOC_DAPM_POST_PMD:
  1617. switch (priv->mux_select[MUX_MIC_TYPE]) {
  1618. case MIC_TYPE_MUX_DMIC:
  1619. mt6358_dmic_disable(priv);
  1620. break;
  1621. default:
  1622. mt6358_amic_disable(priv);
  1623. break;
  1624. }
  1625. priv->mux_select[MUX_MIC_TYPE] = mux;
  1626. break;
  1627. default:
  1628. break;
  1629. }
  1630. return 0;
  1631. }
  1632. static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
  1633. struct snd_kcontrol *kcontrol,
  1634. int event)
  1635. {
  1636. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1637. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1638. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1639. dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
  1640. __func__, event, mux);
  1641. priv->mux_select[MUX_ADC_L] = mux;
  1642. return 0;
  1643. }
  1644. static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
  1645. struct snd_kcontrol *kcontrol,
  1646. int event)
  1647. {
  1648. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1649. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1650. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1651. dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
  1652. __func__, event, mux);
  1653. priv->mux_select[MUX_ADC_R] = mux;
  1654. return 0;
  1655. }
  1656. static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
  1657. struct snd_kcontrol *kcontrol,
  1658. int event)
  1659. {
  1660. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1661. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1662. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1663. dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
  1664. __func__, event, mux);
  1665. priv->mux_select[MUX_PGA_L] = mux;
  1666. return 0;
  1667. }
  1668. static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
  1669. struct snd_kcontrol *kcontrol,
  1670. int event)
  1671. {
  1672. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  1673. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1674. unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
  1675. dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
  1676. __func__, event, mux);
  1677. priv->mux_select[MUX_PGA_R] = mux;
  1678. return 0;
  1679. }
  1680. static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
  1681. struct snd_kcontrol *kcontrol,
  1682. int event)
  1683. {
  1684. switch (event) {
  1685. case SND_SOC_DAPM_POST_PMU:
  1686. usleep_range(250, 270);
  1687. break;
  1688. case SND_SOC_DAPM_PRE_PMD:
  1689. usleep_range(250, 270);
  1690. break;
  1691. default:
  1692. break;
  1693. }
  1694. return 0;
  1695. }
  1696. /* DAPM Widgets */
  1697. static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
  1698. /* Global Supply*/
  1699. SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
  1700. MT6358_DCXO_CW14,
  1701. RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
  1702. SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
  1703. MT6358_AUDDEC_ANA_CON13,
  1704. RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
  1705. SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
  1706. MT6358_AUDENC_ANA_CON6,
  1707. RG_CLKSQ_EN_SFT, 0,
  1708. mt_clksq_event,
  1709. SND_SOC_DAPM_PRE_PMU),
  1710. SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
  1711. MT6358_AUD_TOP_CKPDN_CON0,
  1712. RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
  1713. SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
  1714. MT6358_AUD_TOP_CKPDN_CON0,
  1715. RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
  1716. SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
  1717. MT6358_AUD_TOP_CKPDN_CON0,
  1718. RG_AUD_CK_PDN_SFT, 1,
  1719. mt_delay_250_event,
  1720. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1721. SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
  1722. MT6358_AUD_TOP_CKPDN_CON0,
  1723. RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
  1724. /* Digital Clock */
  1725. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
  1726. MT6358_AUDIO_TOP_CON0,
  1727. PDN_AFE_CTL_SFT, 1,
  1728. mt_delay_250_event,
  1729. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1730. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
  1731. MT6358_AUDIO_TOP_CON0,
  1732. PDN_DAC_CTL_SFT, 1, NULL, 0),
  1733. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
  1734. MT6358_AUDIO_TOP_CON0,
  1735. PDN_ADC_CTL_SFT, 1, NULL, 0),
  1736. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
  1737. MT6358_AUDIO_TOP_CON0,
  1738. PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
  1739. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
  1740. MT6358_AUDIO_TOP_CON0,
  1741. PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
  1742. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
  1743. MT6358_AUDIO_TOP_CON0,
  1744. PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
  1745. SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
  1746. MT6358_AUDIO_TOP_CON0,
  1747. PDN_RESERVED_SFT, 1, NULL, 0),
  1748. SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
  1749. 0, 0, NULL, 0),
  1750. /* AFE ON */
  1751. SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
  1752. MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
  1753. NULL, 0),
  1754. /* AIF Rx*/
  1755. SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
  1756. MT6358_AFE_DL_SRC2_CON0_L,
  1757. DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
  1758. mt_aif_in_event,
  1759. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1760. /* DL Supply */
  1761. SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
  1762. 0, 0, NULL, 0),
  1763. /* DAC */
  1764. SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
  1765. SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
  1766. SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
  1767. /* LOL */
  1768. SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
  1769. SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
  1770. RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
  1771. SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
  1772. RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
  1773. /* Headphone */
  1774. SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
  1775. &hpl_in_mux_control,
  1776. mt_hp_event,
  1777. SND_SOC_DAPM_PRE_PMU |
  1778. SND_SOC_DAPM_PRE_PMD),
  1779. SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
  1780. &hpr_in_mux_control,
  1781. mt_hp_event,
  1782. SND_SOC_DAPM_PRE_PMU |
  1783. SND_SOC_DAPM_PRE_PMD),
  1784. /* Receiver */
  1785. SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
  1786. &rcv_in_mux_control,
  1787. mt_rcv_event,
  1788. SND_SOC_DAPM_PRE_PMU |
  1789. SND_SOC_DAPM_PRE_PMD),
  1790. /* Outputs */
  1791. SND_SOC_DAPM_OUTPUT("Receiver"),
  1792. SND_SOC_DAPM_OUTPUT("Headphone L"),
  1793. SND_SOC_DAPM_OUTPUT("Headphone R"),
  1794. SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
  1795. SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
  1796. SND_SOC_DAPM_OUTPUT("LINEOUT L"),
  1797. SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
  1798. /* SGEN */
  1799. SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
  1800. SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
  1801. SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
  1802. SGEN_MUTE_SW_CTL_SFT, 1,
  1803. mt_sgen_event,
  1804. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1805. SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
  1806. DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
  1807. SND_SOC_DAPM_INPUT("SGEN DL"),
  1808. /* Uplinks */
  1809. SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
  1810. SND_SOC_NOPM, 0, 0,
  1811. mt_aif_out_event,
  1812. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1813. SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
  1814. SND_SOC_NOPM, 0, 0,
  1815. mt_adc_supply_event,
  1816. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1817. /* Uplinks MUX */
  1818. SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
  1819. &aif_out_mux_control),
  1820. SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
  1821. &mic_type_mux_control,
  1822. mt_mic_type_event,
  1823. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
  1824. SND_SOC_DAPM_WILL_PMU),
  1825. SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
  1826. &adc_left_mux_control,
  1827. mt_adc_l_event,
  1828. SND_SOC_DAPM_WILL_PMU),
  1829. SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
  1830. &adc_right_mux_control,
  1831. mt_adc_r_event,
  1832. SND_SOC_DAPM_WILL_PMU),
  1833. SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
  1834. SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
  1835. SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
  1836. &pga_left_mux_control,
  1837. mt_pga_left_event,
  1838. SND_SOC_DAPM_WILL_PMU),
  1839. SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
  1840. &pga_right_mux_control,
  1841. mt_pga_right_event,
  1842. SND_SOC_DAPM_WILL_PMU),
  1843. SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1844. SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1845. /* UL input */
  1846. SND_SOC_DAPM_INPUT("AIN0"),
  1847. SND_SOC_DAPM_INPUT("AIN1"),
  1848. SND_SOC_DAPM_INPUT("AIN2"),
  1849. };
  1850. static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
  1851. /* Capture */
  1852. {"AIF1TX", NULL, "AIF Out Mux"},
  1853. {"AIF1TX", NULL, "CLK_BUF"},
  1854. {"AIF1TX", NULL, "AUDGLB"},
  1855. {"AIF1TX", NULL, "CLKSQ Audio"},
  1856. {"AIF1TX", NULL, "AUD_CK"},
  1857. {"AIF1TX", NULL, "AUDIF_CK"},
  1858. {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
  1859. {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
  1860. {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
  1861. {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1862. {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
  1863. {"AIF1TX", NULL, "AFE_ON"},
  1864. {"AIF Out Mux", NULL, "Mic Type Mux"},
  1865. {"Mic Type Mux", "ACC", "ADC L"},
  1866. {"Mic Type Mux", "ACC", "ADC R"},
  1867. {"Mic Type Mux", "DCC", "ADC L"},
  1868. {"Mic Type Mux", "DCC", "ADC R"},
  1869. {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
  1870. {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
  1871. {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
  1872. {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
  1873. {"Mic Type Mux", "DMIC", "AIN0"},
  1874. {"Mic Type Mux", "DMIC", "AIN2"},
  1875. {"ADC L", NULL, "ADC L Mux"},
  1876. {"ADC L", NULL, "ADC Supply"},
  1877. {"ADC R", NULL, "ADC R Mux"},
  1878. {"ADC R", NULL, "ADC Supply"},
  1879. {"ADC L Mux", "Left Preamplifier", "PGA L"},
  1880. {"ADC R Mux", "Right Preamplifier", "PGA R"},
  1881. {"PGA L", NULL, "PGA L Mux"},
  1882. {"PGA R", NULL, "PGA R Mux"},
  1883. {"PGA L Mux", "AIN0", "AIN0"},
  1884. {"PGA L Mux", "AIN1", "AIN1"},
  1885. {"PGA L Mux", "AIN2", "AIN2"},
  1886. {"PGA R Mux", "AIN0", "AIN0"},
  1887. {"PGA R Mux", "AIN1", "AIN1"},
  1888. {"PGA R Mux", "AIN2", "AIN2"},
  1889. /* DL Supply */
  1890. {"DL Power Supply", NULL, "CLK_BUF"},
  1891. {"DL Power Supply", NULL, "AUDGLB"},
  1892. {"DL Power Supply", NULL, "CLKSQ Audio"},
  1893. {"DL Power Supply", NULL, "AUDNCP_CK"},
  1894. {"DL Power Supply", NULL, "ZCD13M_CK"},
  1895. {"DL Power Supply", NULL, "AUD_CK"},
  1896. {"DL Power Supply", NULL, "AUDIF_CK"},
  1897. /* DL Digital Supply */
  1898. {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
  1899. {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
  1900. {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
  1901. {"DL Digital Clock", NULL, "AFE_ON"},
  1902. {"AIF_RX", NULL, "DL Digital Clock"},
  1903. /* DL Path */
  1904. {"DAC In Mux", "Normal Path", "AIF_RX"},
  1905. {"DAC In Mux", "Sgen", "SGEN DL"},
  1906. {"SGEN DL", NULL, "SGEN DL SRC"},
  1907. {"SGEN DL", NULL, "SGEN MUTE"},
  1908. {"SGEN DL", NULL, "SGEN DL Enable"},
  1909. {"SGEN DL", NULL, "DL Digital Clock"},
  1910. {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
  1911. {"DACL", NULL, "DAC In Mux"},
  1912. {"DACL", NULL, "DL Power Supply"},
  1913. {"DACR", NULL, "DAC In Mux"},
  1914. {"DACR", NULL, "DL Power Supply"},
  1915. /* Lineout Path */
  1916. {"LOL Mux", "Playback", "DACL"},
  1917. {"LOL Buffer", NULL, "LOL Mux"},
  1918. {"LOL Buffer", NULL, "LO Stability Enh"},
  1919. {"LINEOUT L", NULL, "LOL Buffer"},
  1920. /* Headphone Path */
  1921. {"HPL Mux", "Audio Playback", "DACL"},
  1922. {"HPR Mux", "Audio Playback", "DACR"},
  1923. {"HPL Mux", "HP Impedance", "DACL"},
  1924. {"HPR Mux", "HP Impedance", "DACR"},
  1925. {"HPL Mux", "LoudSPK Playback", "DACL"},
  1926. {"HPR Mux", "LoudSPK Playback", "DACR"},
  1927. {"Headphone L", NULL, "HPL Mux"},
  1928. {"Headphone R", NULL, "HPR Mux"},
  1929. {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
  1930. {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
  1931. {"LINEOUT L HSSPK", NULL, "HPL Mux"},
  1932. /* Receiver Path */
  1933. {"RCV Mux", "Voice Playback", "DACL"},
  1934. {"Receiver", NULL, "RCV Mux"},
  1935. };
  1936. static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
  1937. struct snd_pcm_hw_params *params,
  1938. struct snd_soc_dai *dai)
  1939. {
  1940. struct snd_soc_component *cmpnt = dai->component;
  1941. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1942. unsigned int rate = params_rate(params);
  1943. dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
  1944. __func__,
  1945. substream->stream,
  1946. rate,
  1947. substream->number);
  1948. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1949. priv->dl_rate = rate;
  1950. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  1951. priv->ul_rate = rate;
  1952. return 0;
  1953. }
  1954. static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
  1955. .hw_params = mt6358_codec_dai_hw_params,
  1956. };
  1957. #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
  1958. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
  1959. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
  1960. SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
  1961. SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
  1962. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
  1963. static struct snd_soc_dai_driver mt6358_dai_driver[] = {
  1964. {
  1965. .name = "mt6358-snd-codec-aif1",
  1966. .playback = {
  1967. .stream_name = "AIF1 Playback",
  1968. .channels_min = 1,
  1969. .channels_max = 2,
  1970. .rates = SNDRV_PCM_RATE_8000_48000 |
  1971. SNDRV_PCM_RATE_96000 |
  1972. SNDRV_PCM_RATE_192000,
  1973. .formats = MT6358_FORMATS,
  1974. },
  1975. .capture = {
  1976. .stream_name = "AIF1 Capture",
  1977. .channels_min = 1,
  1978. .channels_max = 2,
  1979. .rates = SNDRV_PCM_RATE_8000 |
  1980. SNDRV_PCM_RATE_16000 |
  1981. SNDRV_PCM_RATE_32000 |
  1982. SNDRV_PCM_RATE_48000,
  1983. .formats = MT6358_FORMATS,
  1984. },
  1985. .ops = &mt6358_codec_dai_ops,
  1986. },
  1987. };
  1988. static void mt6358_codec_init_reg(struct mt6358_priv *priv)
  1989. {
  1990. /* Disable HeadphoneL/HeadphoneR short circuit protection */
  1991. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1992. RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
  1993. 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
  1994. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
  1995. RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
  1996. 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
  1997. /* Disable voice short circuit protection */
  1998. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
  1999. RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
  2000. 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
  2001. /* disable LO buffer left short circuit protection */
  2002. regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
  2003. RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
  2004. 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
  2005. /* accdet s/w enable */
  2006. regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
  2007. 0xFFFF, 0x700E);
  2008. /* gpio miso driving set to 4mA */
  2009. regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
  2010. /* set gpio */
  2011. playback_gpio_reset(priv);
  2012. capture_gpio_reset(priv);
  2013. }
  2014. static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
  2015. {
  2016. struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  2017. int ret;
  2018. snd_soc_component_init_regmap(cmpnt, priv->regmap);
  2019. mt6358_codec_init_reg(priv);
  2020. priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
  2021. if (IS_ERR(priv->avdd_reg)) {
  2022. dev_err(priv->dev, "%s() have no Avdd supply", __func__);
  2023. return PTR_ERR(priv->avdd_reg);
  2024. }
  2025. ret = regulator_enable(priv->avdd_reg);
  2026. if (ret)
  2027. return ret;
  2028. return 0;
  2029. }
  2030. static const struct snd_soc_component_driver mt6358_soc_component_driver = {
  2031. .probe = mt6358_codec_probe,
  2032. .controls = mt6358_snd_controls,
  2033. .num_controls = ARRAY_SIZE(mt6358_snd_controls),
  2034. .dapm_widgets = mt6358_dapm_widgets,
  2035. .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
  2036. .dapm_routes = mt6358_dapm_routes,
  2037. .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
  2038. };
  2039. static void mt6358_parse_dt(struct mt6358_priv *priv)
  2040. {
  2041. int ret;
  2042. struct device *dev = priv->dev;
  2043. ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
  2044. &priv->dmic_one_wire_mode);
  2045. if (ret) {
  2046. dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
  2047. __func__);
  2048. priv->dmic_one_wire_mode = 0;
  2049. }
  2050. }
  2051. static int mt6358_platform_driver_probe(struct platform_device *pdev)
  2052. {
  2053. struct mt6358_priv *priv;
  2054. struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
  2055. priv = devm_kzalloc(&pdev->dev,
  2056. sizeof(struct mt6358_priv),
  2057. GFP_KERNEL);
  2058. if (!priv)
  2059. return -ENOMEM;
  2060. dev_set_drvdata(&pdev->dev, priv);
  2061. priv->dev = &pdev->dev;
  2062. priv->regmap = mt6397->regmap;
  2063. if (IS_ERR(priv->regmap))
  2064. return PTR_ERR(priv->regmap);
  2065. mt6358_parse_dt(priv);
  2066. dev_info(priv->dev, "%s(), dev name %s\n",
  2067. __func__, dev_name(&pdev->dev));
  2068. return devm_snd_soc_register_component(&pdev->dev,
  2069. &mt6358_soc_component_driver,
  2070. mt6358_dai_driver,
  2071. ARRAY_SIZE(mt6358_dai_driver));
  2072. }
  2073. static const struct of_device_id mt6358_of_match[] = {
  2074. {.compatible = "mediatek,mt6358-sound",},
  2075. {}
  2076. };
  2077. MODULE_DEVICE_TABLE(of, mt6358_of_match);
  2078. static struct platform_driver mt6358_platform_driver = {
  2079. .driver = {
  2080. .name = "mt6358-sound",
  2081. .of_match_table = mt6358_of_match,
  2082. },
  2083. .probe = mt6358_platform_driver_probe,
  2084. };
  2085. module_platform_driver(mt6358_platform_driver)
  2086. /* Module information */
  2087. MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
  2088. MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
  2089. MODULE_LICENSE("GPL v2");