mt6351.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // mt6351.c -- mt6351 ALSA SoC audio codec driver
  4. //
  5. // Copyright (c) 2018 MediaTek Inc.
  6. // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/delay.h>
  13. #include <sound/core.h>
  14. #include <sound/pcm.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include "mt6351.h"
  18. /* MT6351_TOP_CLKSQ */
  19. #define RG_CLKSQ_EN_AUD_BIT (0)
  20. /* MT6351_TOP_CKPDN_CON0 */
  21. #define RG_AUDNCP_CK_PDN_BIT (12)
  22. #define RG_AUDIF_CK_PDN_BIT (13)
  23. #define RG_AUD_CK_PDN_BIT (14)
  24. #define RG_ZCD13M_CK_PDN_BIT (15)
  25. /* MT6351_AUDDEC_ANA_CON0 */
  26. #define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
  27. #define RG_AUDDACRPWRUP_VAUDP32_BIT (1)
  28. #define RG_AUD_DAC_PWR_UP_VA32_BIT (2)
  29. #define RG_AUD_DAC_PWL_UP_VA32_BIT (3)
  30. #define RG_AUDHSPWRUP_VAUDP32_BIT (4)
  31. #define RG_AUDHPLPWRUP_VAUDP32_BIT (5)
  32. #define RG_AUDHPRPWRUP_VAUDP32_BIT (6)
  33. #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7)
  34. #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
  35. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9)
  36. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
  37. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11)
  38. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
  39. #define RG_AUDHSSCDISABLE_VAUDP32 (13)
  40. #define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14)
  41. #define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15)
  42. /* MT6351_AUDDEC_ANA_CON1 */
  43. #define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8)
  44. /* MT6351_AUDDEC_ANA_CON3 */
  45. #define RG_AUDLOLPWRUP_VAUDP32_BIT (2)
  46. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3)
  47. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
  48. #define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5)
  49. #define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9)
  50. /* MT6351_AUDDEC_ANA_CON6 */
  51. #define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8)
  52. #define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9)
  53. #define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10)
  54. #define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11)
  55. /* MT6351_AUDDEC_ANA_CON9 */
  56. #define RG_AUDIBIASPWRDN_VAUDP32_BIT (8)
  57. #define RG_RSTB_DECODER_VA32_BIT (9)
  58. #define RG_AUDGLB_PWRDN_VA32_BIT (12)
  59. #define RG_LCLDO_DEC_EN_VA32_BIT (13)
  60. #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15)
  61. /* MT6351_AUDDEC_ANA_CON10 */
  62. #define RG_NVREG_EN_VAUDP32_BIT (8)
  63. #define RG_AUDGLB_LP2_VOW_EN_VA32 10
  64. /* MT6351_AFE_UL_DL_CON0 */
  65. #define RG_AFE_ON_BIT (0)
  66. /* MT6351_AFE_DL_SRC2_CON0_L */
  67. #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
  68. /* MT6351_AFE_UL_SRC_CON0_L */
  69. #define UL_SRC_ON_TMP_CTL (0)
  70. /* MT6351_AFE_TOP_CON0 */
  71. #define RG_DL_SINE_ON_SFT (0)
  72. #define RG_DL_SINE_ON_MASK (0x1)
  73. #define RG_UL_SINE_ON_SFT (1)
  74. #define RG_UL_SINE_ON_MASK (0x1)
  75. /* MT6351_AUDIO_TOP_CON0 */
  76. #define AUD_TOP_PDN_RESERVED_BIT 0
  77. #define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2
  78. #define AUD_TOP_PDN_ADC_CTL_BIT 5
  79. #define AUD_TOP_PDN_DAC_CTL_BIT 6
  80. #define AUD_TOP_PDN_AFE_CTL_BIT 7
  81. /* MT6351_AFE_SGEN_CFG0 */
  82. #define SGEN_C_MUTE_SW_CTL_BIT 6
  83. #define SGEN_C_DAC_EN_CTL_BIT 7
  84. /* MT6351_AFE_NCP_CFG0 */
  85. #define RG_NCP_ON_BIT 0
  86. /* MT6351_LDO_VUSB33_CON0 */
  87. #define RG_VUSB33_EN 1
  88. #define RG_VUSB33_ON_CTRL 3
  89. /* MT6351_LDO_VA18_CON0 */
  90. #define RG_VA18_EN 1
  91. #define RG_VA18_ON_CTRL 3
  92. /* MT6351_AUDENC_ANA_CON0 */
  93. #define RG_AUDPREAMPLON 0
  94. #define RG_AUDPREAMPLDCCEN 1
  95. #define RG_AUDPREAMPLDCPRECHARGE 2
  96. #define RG_AUDPREAMPLINPUTSEL_SFT (4)
  97. #define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
  98. #define RG_AUDADCLPWRUP 12
  99. #define RG_AUDADCLINPUTSEL_SFT (13)
  100. #define RG_AUDADCLINPUTSEL_MASK (0x3)
  101. /* MT6351_AUDENC_ANA_CON1 */
  102. #define RG_AUDPREAMPRON 0
  103. #define RG_AUDPREAMPRDCCEN 1
  104. #define RG_AUDPREAMPRDCPRECHARGE 2
  105. #define RG_AUDPREAMPRINPUTSEL_SFT (4)
  106. #define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
  107. #define RG_AUDADCRPWRUP 12
  108. #define RG_AUDADCRINPUTSEL_SFT (13)
  109. #define RG_AUDADCRINPUTSEL_MASK (0x3)
  110. /* MT6351_AUDENC_ANA_CON3 */
  111. #define RG_AUDADCCLKRSTB 6
  112. /* MT6351_AUDENC_ANA_CON9 */
  113. #define RG_AUDPWDBMICBIAS0 0
  114. #define RG_AUDMICBIAS0VREF 4
  115. #define RG_AUDMICBIAS0LOWPEN 7
  116. #define RG_AUDPWDBMICBIAS2 8
  117. #define RG_AUDMICBIAS2VREF 12
  118. #define RG_AUDMICBIAS2LOWPEN 15
  119. /* MT6351_AUDENC_ANA_CON10 */
  120. #define RG_AUDPWDBMICBIAS1 0
  121. #define RG_AUDMICBIAS1DCSW1NEN 2
  122. #define RG_AUDMICBIAS1VREF 4
  123. #define RG_AUDMICBIAS1LOWPEN 7
  124. enum {
  125. AUDIO_ANALOG_VOLUME_HSOUTL,
  126. AUDIO_ANALOG_VOLUME_HSOUTR,
  127. AUDIO_ANALOG_VOLUME_HPOUTL,
  128. AUDIO_ANALOG_VOLUME_HPOUTR,
  129. AUDIO_ANALOG_VOLUME_LINEOUTL,
  130. AUDIO_ANALOG_VOLUME_LINEOUTR,
  131. AUDIO_ANALOG_VOLUME_MICAMP1,
  132. AUDIO_ANALOG_VOLUME_MICAMP2,
  133. AUDIO_ANALOG_VOLUME_TYPE_MAX
  134. };
  135. /* Supply subseq */
  136. enum {
  137. SUPPLY_SUBSEQ_SETTING,
  138. SUPPLY_SUBSEQ_ENABLE,
  139. SUPPLY_SUBSEQ_MICBIAS,
  140. };
  141. #define REG_STRIDE 2
  142. struct mt6351_priv {
  143. struct device *dev;
  144. struct regmap *regmap;
  145. unsigned int dl_rate;
  146. unsigned int ul_rate;
  147. int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  148. int hp_en_counter;
  149. };
  150. static void set_hp_gain_zero(struct snd_soc_component *cmpnt)
  151. {
  152. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
  153. 0x1f << 7, 0x8 << 7);
  154. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
  155. 0x1f << 0, 0x8 << 0);
  156. }
  157. static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt,
  158. unsigned int rate)
  159. {
  160. switch (rate) {
  161. case 8000:
  162. return 0;
  163. case 16000:
  164. return 1;
  165. case 32000:
  166. return 2;
  167. case 48000:
  168. return 3;
  169. case 96000:
  170. return 4;
  171. case 192000:
  172. return 5;
  173. default:
  174. dev_warn(cmpnt->dev, "%s(), error rate %d, return 3",
  175. __func__, rate);
  176. return 3;
  177. }
  178. }
  179. static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt,
  180. unsigned int rate)
  181. {
  182. switch (rate) {
  183. case 8000:
  184. return 0;
  185. case 11025:
  186. return 1;
  187. case 12000:
  188. return 2;
  189. case 16000:
  190. return 3;
  191. case 22050:
  192. return 4;
  193. case 24000:
  194. return 5;
  195. case 32000:
  196. return 6;
  197. case 44100:
  198. return 7;
  199. case 48000:
  200. case 96000:
  201. case 192000:
  202. return 8;
  203. default:
  204. dev_warn(cmpnt->dev, "%s(), error rate %d, return 8",
  205. __func__, rate);
  206. return 8;
  207. }
  208. }
  209. static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream,
  210. struct snd_pcm_hw_params *params,
  211. struct snd_soc_dai *dai)
  212. {
  213. struct snd_soc_component *cmpnt = dai->component;
  214. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  215. unsigned int rate = params_rate(params);
  216. dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n",
  217. __func__, substream->stream, rate);
  218. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  219. priv->dl_rate = rate;
  220. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  221. priv->ul_rate = rate;
  222. return 0;
  223. }
  224. static const struct snd_soc_dai_ops mt6351_codec_dai_ops = {
  225. .hw_params = mt6351_codec_dai_hw_params,
  226. };
  227. #define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
  228. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
  229. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
  230. SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
  231. SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
  232. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
  233. static struct snd_soc_dai_driver mt6351_dai_driver[] = {
  234. {
  235. .name = "mt6351-snd-codec-aif1",
  236. .playback = {
  237. .stream_name = "AIF1 Playback",
  238. .channels_min = 1,
  239. .channels_max = 2,
  240. .rates = SNDRV_PCM_RATE_8000_48000 |
  241. SNDRV_PCM_RATE_96000 |
  242. SNDRV_PCM_RATE_192000,
  243. .formats = MT6351_FORMATS,
  244. },
  245. .capture = {
  246. .stream_name = "AIF1 Capture",
  247. .channels_min = 1,
  248. .channels_max = 2,
  249. .rates = SNDRV_PCM_RATE_8000 |
  250. SNDRV_PCM_RATE_16000 |
  251. SNDRV_PCM_RATE_32000 |
  252. SNDRV_PCM_RATE_48000 |
  253. SNDRV_PCM_RATE_96000 |
  254. SNDRV_PCM_RATE_192000,
  255. .formats = MT6351_FORMATS,
  256. },
  257. .ops = &mt6351_codec_dai_ops,
  258. },
  259. };
  260. enum {
  261. HP_GAIN_SET_ZERO,
  262. HP_GAIN_RESTORE,
  263. };
  264. static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl)
  265. {
  266. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  267. int idx, old_idx, offset, reg_idx;
  268. if (hp_gain_ctl == HP_GAIN_SET_ZERO) {
  269. idx = 8; /* 0dB */
  270. old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
  271. } else {
  272. idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
  273. old_idx = 8; /* 0dB */
  274. }
  275. dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n",
  276. __func__, idx, old_idx);
  277. if (idx > old_idx)
  278. offset = idx - old_idx;
  279. else
  280. offset = old_idx - idx;
  281. reg_idx = old_idx;
  282. while (offset > 0) {
  283. reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
  284. /* check valid range, and set value */
  285. if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
  286. regmap_update_bits(cmpnt->regmap,
  287. MT6351_ZCD_CON2,
  288. 0xf9f,
  289. (reg_idx << 7) | reg_idx);
  290. usleep_range(100, 120);
  291. }
  292. offset--;
  293. }
  294. }
  295. static void hp_zcd_enable(struct snd_soc_component *cmpnt)
  296. {
  297. /* Enable ZCD, for minimize pop noise */
  298. /* when adjust gain during HP buffer on */
  299. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8);
  300. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7);
  301. /* timeout, 1=5ms, 0=30ms */
  302. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6);
  303. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4);
  304. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1);
  305. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0);
  306. }
  307. static void hp_zcd_disable(struct snd_soc_component *cmpnt)
  308. {
  309. regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000);
  310. }
  311. static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
  312. static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
  313. static const struct snd_kcontrol_new mt6351_snd_controls[] = {
  314. /* dl pga gain */
  315. SOC_DOUBLE_TLV("Headphone Volume",
  316. MT6351_ZCD_CON2, 0, 7, 0x12, 1,
  317. playback_tlv),
  318. SOC_DOUBLE_TLV("Lineout Volume",
  319. MT6351_ZCD_CON1, 0, 7, 0x12, 1,
  320. playback_tlv),
  321. SOC_SINGLE_TLV("Handset Volume",
  322. MT6351_ZCD_CON3, 0, 0x12, 1,
  323. playback_tlv),
  324. /* ul pga gain */
  325. SOC_DOUBLE_R_TLV("PGA Volume",
  326. MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1,
  327. 8, 4, 0,
  328. pga_tlv),
  329. };
  330. /* MUX */
  331. /* LOL MUX */
  332. static const char *const lo_in_mux_map[] = {
  333. "Open", "Mute", "Playback", "Test Mode",
  334. };
  335. static int lo_in_mux_map_value[] = {
  336. 0x0, 0x1, 0x2, 0x3,
  337. };
  338. static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
  339. MT6351_AUDDEC_ANA_CON3,
  340. RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT,
  341. RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK,
  342. lo_in_mux_map,
  343. lo_in_mux_map_value);
  344. static const struct snd_kcontrol_new lo_in_mux_control =
  345. SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
  346. /*HP MUX */
  347. static const char *const hp_in_mux_map[] = {
  348. "Open", "LoudSPK Playback", "Audio Playback", "Test Mode",
  349. };
  350. static int hp_in_mux_map_value[] = {
  351. 0x0, 0x1, 0x2, 0x3,
  352. };
  353. static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
  354. MT6351_AUDDEC_ANA_CON0,
  355. RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT,
  356. RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK,
  357. hp_in_mux_map,
  358. hp_in_mux_map_value);
  359. static const struct snd_kcontrol_new hpl_in_mux_control =
  360. SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
  361. static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
  362. MT6351_AUDDEC_ANA_CON0,
  363. RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT,
  364. RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK,
  365. hp_in_mux_map,
  366. hp_in_mux_map_value);
  367. static const struct snd_kcontrol_new hpr_in_mux_control =
  368. SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
  369. /* RCV MUX */
  370. static const char *const rcv_in_mux_map[] = {
  371. "Open", "Mute", "Voice Playback", "Test Mode",
  372. };
  373. static int rcv_in_mux_map_value[] = {
  374. 0x0, 0x1, 0x2, 0x3,
  375. };
  376. static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
  377. MT6351_AUDDEC_ANA_CON0,
  378. RG_AUDHSMUXINPUTSEL_VAUDP32_SFT,
  379. RG_AUDHSMUXINPUTSEL_VAUDP32_MASK,
  380. rcv_in_mux_map,
  381. rcv_in_mux_map_value);
  382. static const struct snd_kcontrol_new rcv_in_mux_control =
  383. SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
  384. /* DAC In MUX */
  385. static const char *const dac_in_mux_map[] = {
  386. "Normal Path", "Sgen",
  387. };
  388. static int dac_in_mux_map_value[] = {
  389. 0x0, 0x1,
  390. };
  391. static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
  392. MT6351_AFE_TOP_CON0,
  393. RG_DL_SINE_ON_SFT,
  394. RG_DL_SINE_ON_MASK,
  395. dac_in_mux_map,
  396. dac_in_mux_map_value);
  397. static const struct snd_kcontrol_new dac_in_mux_control =
  398. SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
  399. /* AIF Out MUX */
  400. static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
  401. MT6351_AFE_TOP_CON0,
  402. RG_UL_SINE_ON_SFT,
  403. RG_UL_SINE_ON_MASK,
  404. dac_in_mux_map,
  405. dac_in_mux_map_value);
  406. static const struct snd_kcontrol_new aif_out_mux_control =
  407. SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
  408. /* ADC L MUX */
  409. static const char *const adc_left_mux_map[] = {
  410. "Idle", "AIN0", "Left Preamplifier", "Idle_1",
  411. };
  412. static int adc_left_mux_map_value[] = {
  413. 0x0, 0x1, 0x2, 0x3,
  414. };
  415. static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
  416. MT6351_AUDENC_ANA_CON0,
  417. RG_AUDADCLINPUTSEL_SFT,
  418. RG_AUDADCLINPUTSEL_MASK,
  419. adc_left_mux_map,
  420. adc_left_mux_map_value);
  421. static const struct snd_kcontrol_new adc_left_mux_control =
  422. SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
  423. /* ADC R MUX */
  424. static const char *const adc_right_mux_map[] = {
  425. "Idle", "AIN0", "Right Preamplifier", "Idle_1",
  426. };
  427. static int adc_right_mux_map_value[] = {
  428. 0x0, 0x1, 0x2, 0x3,
  429. };
  430. static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
  431. MT6351_AUDENC_ANA_CON1,
  432. RG_AUDADCRINPUTSEL_SFT,
  433. RG_AUDADCRINPUTSEL_MASK,
  434. adc_right_mux_map,
  435. adc_right_mux_map_value);
  436. static const struct snd_kcontrol_new adc_right_mux_control =
  437. SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
  438. /* PGA L MUX */
  439. static const char *const pga_left_mux_map[] = {
  440. "None", "AIN0", "AIN1", "AIN2",
  441. };
  442. static int pga_left_mux_map_value[] = {
  443. 0x0, 0x1, 0x2, 0x3,
  444. };
  445. static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
  446. MT6351_AUDENC_ANA_CON0,
  447. RG_AUDPREAMPLINPUTSEL_SFT,
  448. RG_AUDPREAMPLINPUTSEL_MASK,
  449. pga_left_mux_map,
  450. pga_left_mux_map_value);
  451. static const struct snd_kcontrol_new pga_left_mux_control =
  452. SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
  453. /* PGA R MUX */
  454. static const char *const pga_right_mux_map[] = {
  455. "None", "AIN0", "AIN3", "AIN2",
  456. };
  457. static int pga_right_mux_map_value[] = {
  458. 0x0, 0x1, 0x2, 0x3,
  459. };
  460. static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
  461. MT6351_AUDENC_ANA_CON1,
  462. RG_AUDPREAMPRINPUTSEL_SFT,
  463. RG_AUDPREAMPRINPUTSEL_MASK,
  464. pga_right_mux_map,
  465. pga_right_mux_map_value);
  466. static const struct snd_kcontrol_new pga_right_mux_control =
  467. SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
  468. static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w,
  469. struct snd_kcontrol *kcontrol,
  470. int event)
  471. {
  472. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  473. switch (event) {
  474. case SND_SOC_DAPM_POST_PMU:
  475. if (w->on_val) {
  476. /* SET REG */
  477. regmap_update_bits(cmpnt->regmap,
  478. w->reg + REG_STRIDE,
  479. 0x1 << w->shift,
  480. 0x1 << w->shift);
  481. } else {
  482. /* CLR REG */
  483. regmap_update_bits(cmpnt->regmap,
  484. w->reg + REG_STRIDE * 2,
  485. 0x1 << w->shift,
  486. 0x1 << w->shift);
  487. }
  488. break;
  489. case SND_SOC_DAPM_PRE_PMD:
  490. if (w->off_val) {
  491. /* SET REG */
  492. regmap_update_bits(cmpnt->regmap,
  493. w->reg + REG_STRIDE,
  494. 0x1 << w->shift,
  495. 0x1 << w->shift);
  496. } else {
  497. /* CLR REG */
  498. regmap_update_bits(cmpnt->regmap,
  499. w->reg + REG_STRIDE * 2,
  500. 0x1 << w->shift,
  501. 0x1 << w->shift);
  502. }
  503. break;
  504. default:
  505. break;
  506. }
  507. return 0;
  508. }
  509. static int mt_ncp_event(struct snd_soc_dapm_widget *w,
  510. struct snd_kcontrol *kcontrol,
  511. int event)
  512. {
  513. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  514. switch (event) {
  515. case SND_SOC_DAPM_PRE_PMU:
  516. regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1,
  517. 0xffff, 0x1515);
  518. /* NCP: ck1 and ck2 clock frequecy adjust configure */
  519. regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0,
  520. 0xfffe, 0x8C00);
  521. break;
  522. case SND_SOC_DAPM_POST_PMU:
  523. usleep_range(250, 270);
  524. break;
  525. default:
  526. break;
  527. }
  528. return 0;
  529. }
  530. static int mt_sgen_event(struct snd_soc_dapm_widget *w,
  531. struct snd_kcontrol *kcontrol,
  532. int event)
  533. {
  534. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  535. switch (event) {
  536. case SND_SOC_DAPM_PRE_PMU:
  537. regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0,
  538. 0xffef, 0x0008);
  539. regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1,
  540. 0xffff, 0x0101);
  541. break;
  542. default:
  543. break;
  544. }
  545. return 0;
  546. }
  547. static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
  548. struct snd_kcontrol *kcontrol,
  549. int event)
  550. {
  551. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  552. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  553. dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
  554. __func__, event, priv->dl_rate);
  555. switch (event) {
  556. case SND_SOC_DAPM_PRE_PMU:
  557. /* sdm audio fifo clock power on */
  558. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  559. 0xffff, 0x0006);
  560. /* scrambler clock on enable */
  561. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0,
  562. 0xffff, 0xC3A1);
  563. /* sdm power on */
  564. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  565. 0xffff, 0x0003);
  566. /* sdm fifo enable */
  567. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  568. 0xffff, 0x000B);
  569. /* set attenuation gain */
  570. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1,
  571. 0xffff, 0x001E);
  572. regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0,
  573. (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
  574. 0x330);
  575. regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H,
  576. (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
  577. 0x300);
  578. regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
  579. 0x8000, 0x8000);
  580. break;
  581. default:
  582. break;
  583. }
  584. return 0;
  585. }
  586. static int mt_hp_event(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol,
  588. int event)
  589. {
  590. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  591. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  592. int reg;
  593. dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n",
  594. __func__, event, priv->hp_en_counter);
  595. switch (event) {
  596. case SND_SOC_DAPM_PRE_PMU:
  597. priv->hp_en_counter++;
  598. if (priv->hp_en_counter > 1)
  599. break; /* already enabled, do nothing */
  600. else if (priv->hp_en_counter <= 0)
  601. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  602. __func__,
  603. priv->hp_en_counter);
  604. hp_zcd_disable(cmpnt);
  605. /* from yoyo HQA script */
  606. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
  607. 0x0700, 0x0700);
  608. /* save target gain to restore after hardware open complete */
  609. regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, &reg);
  610. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f;
  611. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f;
  612. /* Set HPR/HPL gain as minimum (~ -40dB) */
  613. regmap_update_bits(cmpnt->regmap,
  614. MT6351_ZCD_CON2, 0xffff, 0x0F9F);
  615. /* Set HS gain as minimum (~ -40dB) */
  616. regmap_update_bits(cmpnt->regmap,
  617. MT6351_ZCD_CON3, 0xffff, 0x001F);
  618. /* De_OSC of HP */
  619. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2,
  620. 0x0001, 0x0001);
  621. /* enable output STBENH */
  622. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  623. 0xffff, 0x2000);
  624. /* De_OSC of voice, enable output STBENH */
  625. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  626. 0xffff, 0x2100);
  627. /* Enable voice driver */
  628. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  629. 0x0010, 0xE090);
  630. /* Enable pre-charge buffer */
  631. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  632. 0xffff, 0x2140);
  633. usleep_range(50, 60);
  634. /* Apply digital DC compensation value to DAC */
  635. set_hp_gain_zero(cmpnt);
  636. /* Enable HPR/HPL */
  637. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  638. 0xffff, 0x2100);
  639. /* Disable pre-charge buffer */
  640. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  641. 0xffff, 0x2000);
  642. /* Disable De_OSC of voice */
  643. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  644. 0x0010, 0xF4EF);
  645. /* Disable voice buffer */
  646. /* from yoyo HQ */
  647. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
  648. 0x0700, 0x0300);
  649. /* Enable ZCD, for minimize pop noise */
  650. /* when adjust gain during HP buffer on */
  651. hp_zcd_enable(cmpnt);
  652. /* apply volume setting */
  653. hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
  654. break;
  655. case SND_SOC_DAPM_PRE_PMD:
  656. priv->hp_en_counter--;
  657. if (priv->hp_en_counter > 0)
  658. break; /* still being used, don't close */
  659. else if (priv->hp_en_counter < 0)
  660. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  661. __func__,
  662. priv->hp_en_counter);
  663. /* Disable AUD_ZCD */
  664. hp_zcd_disable(cmpnt);
  665. /* Set HPR/HPL gain as -1dB, step by step */
  666. hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO);
  667. set_hp_gain_zero(cmpnt);
  668. break;
  669. case SND_SOC_DAPM_POST_PMD:
  670. if (priv->hp_en_counter > 0)
  671. break; /* still being used, don't close */
  672. else if (priv->hp_en_counter < 0)
  673. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  674. __func__,
  675. priv->hp_en_counter);
  676. /* reset*/
  677. regmap_update_bits(cmpnt->regmap,
  678. MT6351_AUDDEC_ANA_CON6,
  679. 0x0700,
  680. 0x0000);
  681. /* De_OSC of HP */
  682. regmap_update_bits(cmpnt->regmap,
  683. MT6351_AUDDEC_ANA_CON2,
  684. 0x0001,
  685. 0x0000);
  686. /* apply volume setting */
  687. hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
  688. break;
  689. default:
  690. break;
  691. }
  692. return 0;
  693. }
  694. static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
  695. struct snd_kcontrol *kcontrol,
  696. int event)
  697. {
  698. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  699. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  700. dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
  701. __func__, event, priv->ul_rate);
  702. switch (event) {
  703. case SND_SOC_DAPM_PRE_PMU:
  704. /* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */
  705. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  706. 0xffff, 0x2062);
  707. /* dcclk_pdn=1'b0 */
  708. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  709. 0xffff, 0x2060);
  710. /* dcclk_gen_on=1'b1 */
  711. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  712. 0xffff, 0x2061);
  713. /* UL sample rate and mode configure */
  714. regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H,
  715. 0x000E,
  716. get_cap_reg_val(cmpnt, priv->ul_rate) << 1);
  717. /* fixed 260k path for 8/16/32/48 */
  718. if (priv->ul_rate <= 48000) {
  719. /* anc ul path src on */
  720. regmap_update_bits(cmpnt->regmap,
  721. MT6351_AFE_HPANC_CFG0,
  722. 0x1 << 1,
  723. 0x1 << 1);
  724. /* ANC clk pdn release */
  725. regmap_update_bits(cmpnt->regmap,
  726. MT6351_AFE_HPANC_CFG0,
  727. 0x1 << 0,
  728. 0x0 << 0);
  729. }
  730. break;
  731. case SND_SOC_DAPM_PRE_PMD:
  732. /* fixed 260k path for 8/16/32/48 */
  733. if (priv->ul_rate <= 48000) {
  734. /* anc ul path src on */
  735. regmap_update_bits(cmpnt->regmap,
  736. MT6351_AFE_HPANC_CFG0,
  737. 0x1 << 1,
  738. 0x0 << 1);
  739. /* ANC clk pdn release */
  740. regmap_update_bits(cmpnt->regmap,
  741. MT6351_AFE_HPANC_CFG0,
  742. 0x1 << 0,
  743. 0x1 << 0);
  744. }
  745. break;
  746. default:
  747. break;
  748. }
  749. return 0;
  750. }
  751. static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w,
  752. struct snd_kcontrol *kcontrol,
  753. int event)
  754. {
  755. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  756. switch (event) {
  757. case SND_SOC_DAPM_PRE_PMU:
  758. /* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */
  759. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
  760. 0x3 << 4, 0x0);
  761. break;
  762. case SND_SOC_DAPM_POST_PMU:
  763. /* ADC CLK from: 00_13MHz from CLKSQ (Default) */
  764. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
  765. 0x3 << 2, 0x0);
  766. break;
  767. default:
  768. break;
  769. }
  770. return 0;
  771. }
  772. static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
  773. struct snd_kcontrol *kcontrol,
  774. int event)
  775. {
  776. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  777. switch (event) {
  778. case SND_SOC_DAPM_PRE_PMU:
  779. /* Audio L PGA precharge on */
  780. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  781. 0x3 << RG_AUDPREAMPLDCPRECHARGE,
  782. 0x1 << RG_AUDPREAMPLDCPRECHARGE);
  783. /* Audio L PGA mode: 1_DCC */
  784. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  785. 0x3 << RG_AUDPREAMPLDCCEN,
  786. 0x1 << RG_AUDPREAMPLDCCEN);
  787. break;
  788. case SND_SOC_DAPM_POST_PMU:
  789. usleep_range(100, 120);
  790. /* Audio L PGA precharge off */
  791. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  792. 0x3 << RG_AUDPREAMPLDCPRECHARGE,
  793. 0x0 << RG_AUDPREAMPLDCPRECHARGE);
  794. break;
  795. default:
  796. break;
  797. }
  798. return 0;
  799. }
  800. static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
  801. struct snd_kcontrol *kcontrol,
  802. int event)
  803. {
  804. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  805. switch (event) {
  806. case SND_SOC_DAPM_PRE_PMU:
  807. /* Audio R PGA precharge on */
  808. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  809. 0x3 << RG_AUDPREAMPRDCPRECHARGE,
  810. 0x1 << RG_AUDPREAMPRDCPRECHARGE);
  811. /* Audio R PGA mode: 1_DCC */
  812. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  813. 0x3 << RG_AUDPREAMPRDCCEN,
  814. 0x1 << RG_AUDPREAMPRDCCEN);
  815. break;
  816. case SND_SOC_DAPM_POST_PMU:
  817. usleep_range(100, 120);
  818. /* Audio R PGA precharge off */
  819. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  820. 0x3 << RG_AUDPREAMPRDCPRECHARGE,
  821. 0x0 << RG_AUDPREAMPRDCPRECHARGE);
  822. break;
  823. default:
  824. break;
  825. }
  826. return 0;
  827. }
  828. static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
  829. struct snd_kcontrol *kcontrol,
  830. int event)
  831. {
  832. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  833. switch (event) {
  834. case SND_SOC_DAPM_PRE_PMU:
  835. /* MIC Bias 0 LowPower: 0_Normal */
  836. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  837. 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0);
  838. /* MISBIAS0 = 1P9V */
  839. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  840. 0x7 << RG_AUDMICBIAS0VREF,
  841. 0x2 << RG_AUDMICBIAS0VREF);
  842. break;
  843. case SND_SOC_DAPM_POST_PMD:
  844. /* MISBIAS0 = 1P97 */
  845. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  846. 0x7 << RG_AUDMICBIAS0VREF,
  847. 0x0 << RG_AUDMICBIAS0VREF);
  848. break;
  849. default:
  850. break;
  851. }
  852. return 0;
  853. }
  854. static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
  855. struct snd_kcontrol *kcontrol,
  856. int event)
  857. {
  858. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  859. switch (event) {
  860. case SND_SOC_DAPM_PRE_PMU:
  861. /* MIC Bias 1 LowPower: 0_Normal */
  862. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  863. 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0);
  864. /* MISBIAS1 = 2P7V */
  865. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  866. 0x7 << RG_AUDMICBIAS1VREF,
  867. 0x7 << RG_AUDMICBIAS1VREF);
  868. break;
  869. case SND_SOC_DAPM_POST_PMD:
  870. /* MISBIAS1 = 1P7V */
  871. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  872. 0x7 << RG_AUDMICBIAS1VREF,
  873. 0x0 << RG_AUDMICBIAS1VREF);
  874. break;
  875. default:
  876. break;
  877. }
  878. return 0;
  879. }
  880. static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
  881. struct snd_kcontrol *kcontrol,
  882. int event)
  883. {
  884. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  885. switch (event) {
  886. case SND_SOC_DAPM_PRE_PMU:
  887. /* MIC Bias 2 LowPower: 0_Normal */
  888. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  889. 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0);
  890. /* MISBIAS2 = 1P9V */
  891. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  892. 0x7 << RG_AUDMICBIAS2VREF,
  893. 0x2 << RG_AUDMICBIAS2VREF);
  894. break;
  895. case SND_SOC_DAPM_POST_PMD:
  896. /* MISBIAS2 = 1P97 */
  897. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  898. 0x7 << RG_AUDMICBIAS2VREF,
  899. 0x0 << RG_AUDMICBIAS2VREF);
  900. break;
  901. default:
  902. break;
  903. }
  904. return 0;
  905. }
  906. /* DAPM Widgets */
  907. static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = {
  908. /* Digital Clock */
  909. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0,
  910. AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
  911. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0,
  912. AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
  913. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0,
  914. AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
  915. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0,
  916. AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
  917. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0,
  918. AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
  919. SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0,
  920. RG_NCP_ON_BIT, 0,
  921. mt_ncp_event,
  922. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  923. SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
  924. 0, 0, NULL, 0),
  925. /* Global Supply*/
  926. SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9,
  927. RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
  928. SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ,
  929. RG_CLKSQ_EN_AUD_BIT, 0,
  930. mt_reg_set_clr_event,
  931. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  932. SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0,
  933. RG_ZCD13M_CK_PDN_BIT, 1,
  934. mt_reg_set_clr_event,
  935. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  936. SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0,
  937. RG_AUD_CK_PDN_BIT, 1,
  938. mt_reg_set_clr_event,
  939. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  940. SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0,
  941. RG_AUDIF_CK_PDN_BIT, 1,
  942. mt_reg_set_clr_event,
  943. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  944. SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0,
  945. RG_AUDNCP_CK_PDN_BIT, 1,
  946. mt_reg_set_clr_event,
  947. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  948. SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
  949. NULL, 0),
  950. /* AIF Rx*/
  951. SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
  952. MT6351_AFE_DL_SRC2_CON0_L,
  953. RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
  954. mt_aif_in_event, SND_SOC_DAPM_PRE_PMU),
  955. /* DL Supply */
  956. SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
  957. 0, 0, NULL, 0),
  958. SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10,
  959. RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
  960. SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9,
  961. RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
  962. SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9,
  963. RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
  964. SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9,
  965. RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
  966. SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9,
  967. RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
  968. /* DAC */
  969. SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
  970. SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0,
  971. RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
  972. SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0,
  973. RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
  974. SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0,
  975. RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
  976. SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0,
  977. RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
  978. /* LOL */
  979. SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
  980. SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3,
  981. RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
  982. SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6,
  983. RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
  984. SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3,
  985. RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
  986. /* Headphone */
  987. SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
  988. SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
  989. SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0,
  990. RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
  991. mt_hp_event,
  992. SND_SOC_DAPM_PRE_PMU |
  993. SND_SOC_DAPM_PRE_PMD |
  994. SND_SOC_DAPM_POST_PMD),
  995. SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0,
  996. RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
  997. mt_hp_event,
  998. SND_SOC_DAPM_PRE_PMU |
  999. SND_SOC_DAPM_PRE_PMD |
  1000. SND_SOC_DAPM_POST_PMD),
  1001. /* Receiver */
  1002. SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
  1003. SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1,
  1004. RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
  1005. SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6,
  1006. RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
  1007. SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0,
  1008. RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
  1009. /* Outputs */
  1010. SND_SOC_DAPM_OUTPUT("Receiver"),
  1011. SND_SOC_DAPM_OUTPUT("Headphone L"),
  1012. SND_SOC_DAPM_OUTPUT("Headphone R"),
  1013. SND_SOC_DAPM_OUTPUT("LINEOUT L"),
  1014. /* SGEN */
  1015. SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
  1016. SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
  1017. SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
  1018. SGEN_C_MUTE_SW_CTL_BIT, 1,
  1019. mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
  1020. SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
  1021. RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
  1022. SND_SOC_DAPM_INPUT("SGEN DL"),
  1023. /* Uplinks */
  1024. SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
  1025. MT6351_AFE_UL_SRC_CON0_L,
  1026. UL_SRC_ON_TMP_CTL, 0,
  1027. mt_aif_out_event,
  1028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  1029. SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
  1030. MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
  1031. NULL, 0),
  1032. SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
  1033. MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
  1034. NULL, 0),
  1035. SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
  1036. MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
  1037. SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
  1038. MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
  1039. NULL, 0),
  1040. SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE,
  1041. MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
  1042. mt_adc_clkgen_event,
  1043. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1044. /* Uplinks MUX */
  1045. SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
  1046. &aif_out_mux_control),
  1047. SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
  1048. &adc_left_mux_control),
  1049. SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
  1050. &adc_right_mux_control),
  1051. SND_SOC_DAPM_ADC("ADC L", NULL,
  1052. MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
  1053. SND_SOC_DAPM_ADC("ADC R", NULL,
  1054. MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
  1055. SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
  1056. &pga_left_mux_control),
  1057. SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
  1058. &pga_right_mux_control),
  1059. SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
  1060. NULL, 0,
  1061. mt_pga_left_event,
  1062. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1063. SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
  1064. NULL, 0,
  1065. mt_pga_right_event,
  1066. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1067. /* main mic mic bias */
  1068. SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
  1069. MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
  1070. mt_mic_bias_0_event,
  1071. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1072. /* ref mic mic bias */
  1073. SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS,
  1074. MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
  1075. mt_mic_bias_2_event,
  1076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1077. /* headset mic1/2 mic bias */
  1078. SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS,
  1079. MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
  1080. mt_mic_bias_1_event,
  1081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1082. SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS,
  1083. MT6351_AUDENC_ANA_CON10,
  1084. RG_AUDMICBIAS1DCSW1NEN, 0,
  1085. NULL, 0),
  1086. /* UL input */
  1087. SND_SOC_DAPM_INPUT("AIN0"),
  1088. SND_SOC_DAPM_INPUT("AIN1"),
  1089. SND_SOC_DAPM_INPUT("AIN2"),
  1090. SND_SOC_DAPM_INPUT("AIN3"),
  1091. };
  1092. static const struct snd_soc_dapm_route mt6351_dapm_routes[] = {
  1093. /* Capture */
  1094. {"AIF1TX", NULL, "AIF Out Mux"},
  1095. {"AIF1TX", NULL, "VUSB33_LDO"},
  1096. {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"},
  1097. {"AIF1TX", NULL, "VA18_LDO"},
  1098. {"VA18_LDO", NULL, "VA18_LDO_CTRL"},
  1099. {"AIF1TX", NULL, "AUDGLB"},
  1100. {"AIF1TX", NULL, "CLKSQ Audio"},
  1101. {"AIF1TX", NULL, "AFE_ON"},
  1102. {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
  1103. {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
  1104. {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
  1105. {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1106. {"AIF Out Mux", "Normal Path", "ADC L"},
  1107. {"AIF Out Mux", "Normal Path", "ADC R"},
  1108. {"ADC L", NULL, "ADC L Mux"},
  1109. {"ADC L", NULL, "AUD_CK"},
  1110. {"ADC L", NULL, "AUDIF_CK"},
  1111. {"ADC L", NULL, "ADC CLKGEN"},
  1112. {"ADC R", NULL, "ADC R Mux"},
  1113. {"ADC R", NULL, "AUD_CK"},
  1114. {"ADC R", NULL, "AUDIF_CK"},
  1115. {"ADC R", NULL, "ADC CLKGEN"},
  1116. {"ADC L Mux", "AIN0", "AIN0"},
  1117. {"ADC L Mux", "Left Preamplifier", "PGA L"},
  1118. {"ADC R Mux", "AIN0", "AIN0"},
  1119. {"ADC R Mux", "Right Preamplifier", "PGA R"},
  1120. {"PGA L", NULL, "PGA L Mux"},
  1121. {"PGA R", NULL, "PGA R Mux"},
  1122. {"PGA L Mux", "AIN0", "AIN0"},
  1123. {"PGA L Mux", "AIN1", "AIN1"},
  1124. {"PGA L Mux", "AIN2", "AIN2"},
  1125. {"PGA R Mux", "AIN0", "AIN0"},
  1126. {"PGA R Mux", "AIN3", "AIN3"},
  1127. {"PGA R Mux", "AIN2", "AIN2"},
  1128. {"AIN0", NULL, "Mic Bias 0"},
  1129. {"AIN2", NULL, "Mic Bias 2"},
  1130. {"AIN1", NULL, "Mic Bias 1"},
  1131. {"AIN1", NULL, "Mic Bias 1 DCC pull high"},
  1132. /* DL Supply */
  1133. {"DL Power Supply", NULL, "AUDGLB"},
  1134. {"DL Power Supply", NULL, "CLKSQ Audio"},
  1135. {"DL Power Supply", NULL, "ZCD13M_CK"},
  1136. {"DL Power Supply", NULL, "AUD_CK"},
  1137. {"DL Power Supply", NULL, "AUDIF_CK"},
  1138. {"DL Power Supply", NULL, "AUDNCP_CK"},
  1139. {"DL Power Supply", NULL, "NV Regulator"},
  1140. {"DL Power Supply", NULL, "AUD_CLK"},
  1141. {"DL Power Supply", NULL, "IBIST"},
  1142. {"DL Power Supply", NULL, "LDO"},
  1143. {"LDO", NULL, "LDO_REMOTE_SENSE"},
  1144. /* DL Digital Supply */
  1145. {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
  1146. {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
  1147. {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
  1148. {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1149. {"DL Digital Clock", NULL, "NCP"},
  1150. {"DL Digital Clock", NULL, "AFE_ON"},
  1151. {"AIF_RX", NULL, "DL Digital Clock"},
  1152. /* DL Path */
  1153. {"DAC In Mux", "Normal Path", "AIF_RX"},
  1154. {"DAC In Mux", "Sgen", "SGEN DL"},
  1155. {"SGEN DL", NULL, "SGEN DL SRC"},
  1156. {"SGEN DL", NULL, "SGEN MUTE"},
  1157. {"SGEN DL", NULL, "SGEN DL Enable"},
  1158. {"SGEN DL", NULL, "DL Digital Clock"},
  1159. {"DACL", NULL, "DAC In Mux"},
  1160. {"DACL", NULL, "DL Power Supply"},
  1161. {"DACL", NULL, "DACL_BIASGEN"},
  1162. {"DACR", NULL, "DAC In Mux"},
  1163. {"DACR", NULL, "DL Power Supply"},
  1164. {"DACR", NULL, "DACR_BIASGEN"},
  1165. {"LOL Mux", "Playback", "DACL"},
  1166. {"LOL Buffer", NULL, "LOL Mux"},
  1167. {"LOL Buffer", NULL, "LO Stability Enh"},
  1168. {"LOL Buffer", NULL, "LOL Bias Gen"},
  1169. {"LINEOUT L", NULL, "LOL Buffer"},
  1170. /* Headphone Path */
  1171. {"HPL Mux", "Audio Playback", "DACL"},
  1172. {"HPR Mux", "Audio Playback", "DACR"},
  1173. {"HPL Mux", "LoudSPK Playback", "DACL"},
  1174. {"HPR Mux", "LoudSPK Playback", "DACR"},
  1175. {"HPL Power", NULL, "HPL Mux"},
  1176. {"HPR Power", NULL, "HPR Mux"},
  1177. {"Headphone L", NULL, "HPL Power"},
  1178. {"Headphone R", NULL, "HPR Power"},
  1179. /* Receiver Path */
  1180. {"RCV Mux", "Voice Playback", "DACL"},
  1181. {"RCV Buffer", NULL, "RCV Mux"},
  1182. {"RCV Buffer", NULL, "RCV Stability Enh"},
  1183. {"RCV Buffer", NULL, "RCV Bias Gen"},
  1184. {"Receiver", NULL, "RCV Buffer"},
  1185. };
  1186. static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt)
  1187. {
  1188. /* Disable CLKSQ 26MHz */
  1189. regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0);
  1190. /* disable AUDGLB */
  1191. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9,
  1192. 0x1000, 0x1000);
  1193. /* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */
  1194. regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET,
  1195. 0x3800, 0x3800);
  1196. /* Disable HeadphoneL/HeadphoneR/voice short circuit protection */
  1197. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  1198. 0xe000, 0xe000);
  1199. /* [5] = 1, disable LO buffer left short circuit protection */
  1200. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3,
  1201. 0x20, 0x20);
  1202. /* Reverse the PMIC clock*/
  1203. regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
  1204. 0x8000, 0x8000);
  1205. return 0;
  1206. }
  1207. static int mt6351_codec_probe(struct snd_soc_component *cmpnt)
  1208. {
  1209. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1210. snd_soc_component_init_regmap(cmpnt, priv->regmap);
  1211. mt6351_codec_init_reg(cmpnt);
  1212. return 0;
  1213. }
  1214. static const struct snd_soc_component_driver mt6351_soc_component_driver = {
  1215. .probe = mt6351_codec_probe,
  1216. .controls = mt6351_snd_controls,
  1217. .num_controls = ARRAY_SIZE(mt6351_snd_controls),
  1218. .dapm_widgets = mt6351_dapm_widgets,
  1219. .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets),
  1220. .dapm_routes = mt6351_dapm_routes,
  1221. .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes),
  1222. };
  1223. static int mt6351_codec_driver_probe(struct platform_device *pdev)
  1224. {
  1225. struct mt6351_priv *priv;
  1226. priv = devm_kzalloc(&pdev->dev,
  1227. sizeof(struct mt6351_priv),
  1228. GFP_KERNEL);
  1229. if (!priv)
  1230. return -ENOMEM;
  1231. dev_set_drvdata(&pdev->dev, priv);
  1232. priv->dev = &pdev->dev;
  1233. priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  1234. if (!priv->regmap)
  1235. return -ENODEV;
  1236. dev_dbg(priv->dev, "%s(), dev name %s\n",
  1237. __func__, dev_name(&pdev->dev));
  1238. return devm_snd_soc_register_component(&pdev->dev,
  1239. &mt6351_soc_component_driver,
  1240. mt6351_dai_driver,
  1241. ARRAY_SIZE(mt6351_dai_driver));
  1242. }
  1243. static const struct of_device_id mt6351_of_match[] = {
  1244. {.compatible = "mediatek,mt6351-sound",},
  1245. {}
  1246. };
  1247. static struct platform_driver mt6351_codec_driver = {
  1248. .driver = {
  1249. .name = "mt6351-sound",
  1250. .of_match_table = mt6351_of_match,
  1251. },
  1252. .probe = mt6351_codec_driver_probe,
  1253. };
  1254. module_platform_driver(mt6351_codec_driver)
  1255. /* Module information */
  1256. MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver");
  1257. MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
  1258. MODULE_LICENSE("GPL v2");